1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/types.h> 24 #include <linux/kernel.h> 25 #include <linux/gfp.h> 26 #include <linux/slab.h> 27 #include <linux/firmware.h> 28 #include <linux/reboot.h> 29 #include "amd_shared.h" 30 #include "power_state.h" 31 #include "amdgpu.h" 32 #include "hwmgr.h" 33 #include "amdgpu_dpm_internal.h" 34 35 static const struct amd_pm_funcs pp_dpm_funcs; 36 37 static int amd_powerplay_create(struct amdgpu_device *adev) 38 { 39 struct pp_hwmgr *hwmgr; 40 41 if (adev == NULL) 42 return -EINVAL; 43 44 hwmgr = kzalloc_obj(struct pp_hwmgr); 45 if (hwmgr == NULL) 46 return -ENOMEM; 47 48 hwmgr->adev = adev; 49 hwmgr->not_vf = !amdgpu_sriov_vf(adev); 50 hwmgr->device = amdgpu_cgs_create_device(adev); 51 if (!hwmgr->device) { 52 kfree(hwmgr); 53 return -ENOMEM; 54 } 55 56 mutex_init(&hwmgr->msg_lock); 57 hwmgr->chip_family = adev->family; 58 hwmgr->chip_id = adev->asic_type; 59 hwmgr->feature_mask = adev->pm.pp_feature; 60 hwmgr->display_config = &adev->pm.pm_display_cfg; 61 adev->powerplay.pp_handle = hwmgr; 62 adev->powerplay.pp_funcs = &pp_dpm_funcs; 63 return 0; 64 } 65 66 67 static void amd_powerplay_destroy(struct amdgpu_device *adev) 68 { 69 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 70 71 mutex_destroy(&hwmgr->msg_lock); 72 73 kfree(hwmgr->hardcode_pp_table); 74 hwmgr->hardcode_pp_table = NULL; 75 76 kfree(hwmgr); 77 hwmgr = NULL; 78 } 79 80 static int pp_early_init(struct amdgpu_ip_block *ip_block) 81 { 82 int ret; 83 struct amdgpu_device *adev = ip_block->adev; 84 ret = amd_powerplay_create(adev); 85 86 if (ret != 0) 87 return ret; 88 89 ret = hwmgr_early_init(adev->powerplay.pp_handle); 90 if (ret) 91 return -EINVAL; 92 93 return 0; 94 } 95 96 static void pp_swctf_delayed_work_handler(struct work_struct *work) 97 { 98 struct pp_hwmgr *hwmgr = 99 container_of(work, struct pp_hwmgr, swctf_delayed_work.work); 100 struct amdgpu_device *adev = hwmgr->adev; 101 struct amdgpu_dpm_thermal *range = 102 &adev->pm.dpm.thermal; 103 uint32_t gpu_temperature, size = sizeof(gpu_temperature); 104 int ret; 105 106 /* 107 * If the hotspot/edge temperature is confirmed as below SW CTF setting point 108 * after the delay enforced, nothing will be done. 109 * Otherwise, a graceful shutdown will be performed to prevent further damage. 110 */ 111 if (range->sw_ctf_threshold && 112 hwmgr->hwmgr_func->read_sensor) { 113 ret = hwmgr->hwmgr_func->read_sensor(hwmgr, 114 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 115 &gpu_temperature, 116 &size); 117 /* 118 * For some legacy ASICs, hotspot temperature retrieving might be not 119 * supported. Check the edge temperature instead then. 120 */ 121 if (ret == -EOPNOTSUPP) 122 ret = hwmgr->hwmgr_func->read_sensor(hwmgr, 123 AMDGPU_PP_SENSOR_EDGE_TEMP, 124 &gpu_temperature, 125 &size); 126 if (!ret && gpu_temperature / 1000 < range->sw_ctf_threshold) 127 return; 128 } 129 130 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 131 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 132 orderly_poweroff(true); 133 } 134 135 static int pp_sw_init(struct amdgpu_ip_block *ip_block) 136 { 137 struct amdgpu_device *adev = ip_block->adev; 138 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 139 int ret = 0; 140 141 ret = hwmgr_sw_init(hwmgr); 142 143 pr_debug("powerplay sw init %s\n", ret ? "failed" : "successfully"); 144 145 if (!ret) 146 INIT_DELAYED_WORK(&hwmgr->swctf_delayed_work, 147 pp_swctf_delayed_work_handler); 148 149 return ret; 150 } 151 152 static int pp_sw_fini(struct amdgpu_ip_block *ip_block) 153 { 154 struct amdgpu_device *adev = ip_block->adev; 155 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 156 157 hwmgr_sw_fini(hwmgr); 158 159 amdgpu_ucode_release(&adev->pm.fw); 160 161 return 0; 162 } 163 164 static int pp_hw_init(struct amdgpu_ip_block *ip_block) 165 { 166 int ret = 0; 167 struct amdgpu_device *adev = ip_block->adev; 168 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 169 170 ret = hwmgr_hw_init(hwmgr); 171 172 if (ret) 173 pr_err("powerplay hw init failed\n"); 174 175 return ret; 176 } 177 178 static int pp_hw_fini(struct amdgpu_ip_block *ip_block) 179 { 180 struct pp_hwmgr *hwmgr = ip_block->adev->powerplay.pp_handle; 181 182 cancel_delayed_work_sync(&hwmgr->swctf_delayed_work); 183 184 hwmgr_hw_fini(hwmgr); 185 186 return 0; 187 } 188 189 static void pp_reserve_vram_for_smu(struct amdgpu_device *adev) 190 { 191 int r = -EINVAL; 192 void *cpu_ptr = NULL; 193 uint64_t gpu_addr; 194 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 195 196 if (amdgpu_bo_create_kernel(adev, adev->pm.smu_prv_buffer_size, 197 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 198 &adev->pm.smu_prv_buffer, 199 &gpu_addr, 200 &cpu_ptr)) { 201 drm_err(adev_to_drm(adev), "failed to create smu prv buffer\n"); 202 return; 203 } 204 205 if (hwmgr->hwmgr_func->notify_cac_buffer_info) 206 r = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, 207 lower_32_bits((unsigned long)cpu_ptr), 208 upper_32_bits((unsigned long)cpu_ptr), 209 lower_32_bits(gpu_addr), 210 upper_32_bits(gpu_addr), 211 adev->pm.smu_prv_buffer_size); 212 213 if (r) { 214 amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL); 215 adev->pm.smu_prv_buffer = NULL; 216 drm_err(adev_to_drm(adev), "failed to notify SMU buffer address\n"); 217 } 218 } 219 220 static int pp_late_init(struct amdgpu_ip_block *ip_block) 221 { 222 struct amdgpu_device *adev = ip_block->adev; 223 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 224 225 if (hwmgr && hwmgr->pm_en) 226 hwmgr_handle_task(hwmgr, 227 AMD_PP_TASK_COMPLETE_INIT, NULL); 228 if (adev->pm.smu_prv_buffer_size != 0) 229 pp_reserve_vram_for_smu(adev); 230 231 return 0; 232 } 233 234 static void pp_late_fini(struct amdgpu_ip_block *ip_block) 235 { 236 struct amdgpu_device *adev = ip_block->adev; 237 238 if (adev->pm.smu_prv_buffer) 239 amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL); 240 amd_powerplay_destroy(adev); 241 } 242 243 244 static bool pp_is_idle(struct amdgpu_ip_block *ip_block) 245 { 246 return false; 247 } 248 249 static int pp_set_powergating_state(struct amdgpu_ip_block *ip_block, 250 enum amd_powergating_state state) 251 { 252 return 0; 253 } 254 255 static int pp_suspend(struct amdgpu_ip_block *ip_block) 256 { 257 struct amdgpu_device *adev = ip_block->adev; 258 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 259 260 cancel_delayed_work_sync(&hwmgr->swctf_delayed_work); 261 262 return hwmgr_suspend(hwmgr); 263 } 264 265 static int pp_resume(struct amdgpu_ip_block *ip_block) 266 { 267 struct pp_hwmgr *hwmgr = ip_block->adev->powerplay.pp_handle; 268 269 return hwmgr_resume(hwmgr); 270 } 271 272 static int pp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 273 enum amd_clockgating_state state) 274 { 275 return 0; 276 } 277 278 static const struct amd_ip_funcs pp_ip_funcs = { 279 .name = "powerplay", 280 .early_init = pp_early_init, 281 .late_init = pp_late_init, 282 .sw_init = pp_sw_init, 283 .sw_fini = pp_sw_fini, 284 .hw_init = pp_hw_init, 285 .hw_fini = pp_hw_fini, 286 .late_fini = pp_late_fini, 287 .suspend = pp_suspend, 288 .resume = pp_resume, 289 .is_idle = pp_is_idle, 290 .set_clockgating_state = pp_set_clockgating_state, 291 .set_powergating_state = pp_set_powergating_state, 292 }; 293 294 const struct amdgpu_ip_block_version pp_smu_ip_block = 295 { 296 .type = AMD_IP_BLOCK_TYPE_SMC, 297 .major = 1, 298 .minor = 0, 299 .rev = 0, 300 .funcs = &pp_ip_funcs, 301 }; 302 303 /* This interface only be supported On Vi, 304 * because only smu7/8 can help to load gfx/sdma fw, 305 * smu need to be enabled before load other ip's fw. 306 * so call start smu to load smu7 fw and other ip's fw 307 */ 308 static int pp_dpm_load_fw(void *handle) 309 { 310 struct pp_hwmgr *hwmgr = handle; 311 312 if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu) 313 return -EINVAL; 314 315 if (hwmgr->smumgr_funcs->start_smu(hwmgr)) { 316 pr_err("fw load failed\n"); 317 return -EINVAL; 318 } 319 320 return 0; 321 } 322 323 static int pp_dpm_fw_loading_complete(void *handle) 324 { 325 return 0; 326 } 327 328 static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id) 329 { 330 struct pp_hwmgr *hwmgr = handle; 331 332 if (!hwmgr || !hwmgr->pm_en) 333 return -EINVAL; 334 335 if (hwmgr->hwmgr_func->update_clock_gatings == NULL) { 336 pr_info_ratelimited("%s was not implemented.\n", __func__); 337 return 0; 338 } 339 340 return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); 341 } 342 343 static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, 344 enum amd_dpm_forced_level *level) 345 { 346 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 347 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 348 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 349 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 350 351 if (!(hwmgr->dpm_level & profile_mode_mask)) { 352 /* enter umd pstate, save current level, disable gfx cg*/ 353 if (*level & profile_mode_mask) { 354 hwmgr->saved_dpm_level = hwmgr->dpm_level; 355 hwmgr->en_umd_pstate = true; 356 } 357 } else { 358 /* exit umd pstate, restore level, enable gfx cg*/ 359 if (!(*level & profile_mode_mask)) { 360 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 361 *level = hwmgr->saved_dpm_level; 362 hwmgr->en_umd_pstate = false; 363 } 364 } 365 } 366 367 static int pp_dpm_force_performance_level(void *handle, 368 enum amd_dpm_forced_level level) 369 { 370 struct pp_hwmgr *hwmgr = handle; 371 372 if (!hwmgr || !hwmgr->pm_en) 373 return -EINVAL; 374 375 if (level == hwmgr->dpm_level) 376 return 0; 377 378 pp_dpm_en_umd_pstate(hwmgr, &level); 379 hwmgr->request_dpm_level = level; 380 hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL); 381 382 return 0; 383 } 384 385 static enum amd_dpm_forced_level pp_dpm_get_performance_level( 386 void *handle) 387 { 388 struct pp_hwmgr *hwmgr = handle; 389 390 if (!hwmgr || !hwmgr->pm_en) 391 return -EINVAL; 392 393 return hwmgr->dpm_level; 394 } 395 396 static uint32_t pp_dpm_get_sclk(void *handle, bool low) 397 { 398 struct pp_hwmgr *hwmgr = handle; 399 400 if (!hwmgr || !hwmgr->pm_en) 401 return 0; 402 403 if (hwmgr->hwmgr_func->get_sclk == NULL) { 404 pr_info_ratelimited("%s was not implemented.\n", __func__); 405 return 0; 406 } 407 return hwmgr->hwmgr_func->get_sclk(hwmgr, low); 408 } 409 410 static uint32_t pp_dpm_get_mclk(void *handle, bool low) 411 { 412 struct pp_hwmgr *hwmgr = handle; 413 414 if (!hwmgr || !hwmgr->pm_en) 415 return 0; 416 417 if (hwmgr->hwmgr_func->get_mclk == NULL) { 418 pr_info_ratelimited("%s was not implemented.\n", __func__); 419 return 0; 420 } 421 return hwmgr->hwmgr_func->get_mclk(hwmgr, low); 422 } 423 424 static void pp_dpm_powergate_vce(void *handle, bool gate) 425 { 426 struct pp_hwmgr *hwmgr = handle; 427 428 if (!hwmgr || !hwmgr->pm_en) 429 return; 430 431 if (hwmgr->hwmgr_func->powergate_vce == NULL) { 432 pr_info_ratelimited("%s was not implemented.\n", __func__); 433 return; 434 } 435 hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); 436 } 437 438 static void pp_dpm_powergate_uvd(void *handle, bool gate) 439 { 440 struct pp_hwmgr *hwmgr = handle; 441 442 if (!hwmgr || !hwmgr->pm_en) 443 return; 444 445 if (hwmgr->hwmgr_func->powergate_uvd == NULL) { 446 pr_info_ratelimited("%s was not implemented.\n", __func__); 447 return; 448 } 449 hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); 450 } 451 452 static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id, 453 enum amd_pm_state_type *user_state) 454 { 455 struct pp_hwmgr *hwmgr = handle; 456 457 if (!hwmgr || !hwmgr->pm_en) 458 return -EINVAL; 459 460 return hwmgr_handle_task(hwmgr, task_id, user_state); 461 } 462 463 static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) 464 { 465 struct pp_hwmgr *hwmgr = handle; 466 struct pp_power_state *state; 467 enum amd_pm_state_type pm_type; 468 469 if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps) 470 return -EINVAL; 471 472 state = hwmgr->current_ps; 473 474 switch (state->classification.ui_label) { 475 case PP_StateUILabel_Battery: 476 pm_type = POWER_STATE_TYPE_BATTERY; 477 break; 478 case PP_StateUILabel_Balanced: 479 pm_type = POWER_STATE_TYPE_BALANCED; 480 break; 481 case PP_StateUILabel_Performance: 482 pm_type = POWER_STATE_TYPE_PERFORMANCE; 483 break; 484 default: 485 if (state->classification.flags & PP_StateClassificationFlag_Boot) 486 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT; 487 else 488 pm_type = POWER_STATE_TYPE_DEFAULT; 489 break; 490 } 491 492 return pm_type; 493 } 494 495 static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) 496 { 497 struct pp_hwmgr *hwmgr = handle; 498 499 if (!hwmgr || !hwmgr->pm_en) 500 return -EOPNOTSUPP; 501 502 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) 503 return -EOPNOTSUPP; 504 505 if (mode == U32_MAX) 506 return -EINVAL; 507 508 hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); 509 510 return 0; 511 } 512 513 static int pp_dpm_get_fan_control_mode(void *handle, uint32_t *fan_mode) 514 { 515 struct pp_hwmgr *hwmgr = handle; 516 517 if (!hwmgr || !hwmgr->pm_en) 518 return -EOPNOTSUPP; 519 520 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) 521 return -EOPNOTSUPP; 522 523 if (!fan_mode) 524 return -EINVAL; 525 526 *fan_mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); 527 return 0; 528 } 529 530 static int pp_dpm_set_fan_speed_pwm(void *handle, uint32_t speed) 531 { 532 struct pp_hwmgr *hwmgr = handle; 533 534 if (!hwmgr || !hwmgr->pm_en) 535 return -EOPNOTSUPP; 536 537 if (hwmgr->hwmgr_func->set_fan_speed_pwm == NULL) 538 return -EOPNOTSUPP; 539 540 if (speed == U32_MAX) 541 return -EINVAL; 542 543 return hwmgr->hwmgr_func->set_fan_speed_pwm(hwmgr, speed); 544 } 545 546 static int pp_dpm_get_fan_speed_pwm(void *handle, uint32_t *speed) 547 { 548 struct pp_hwmgr *hwmgr = handle; 549 550 if (!hwmgr || !hwmgr->pm_en) 551 return -EOPNOTSUPP; 552 553 if (hwmgr->hwmgr_func->get_fan_speed_pwm == NULL) 554 return -EOPNOTSUPP; 555 556 if (!speed) 557 return -EINVAL; 558 559 return hwmgr->hwmgr_func->get_fan_speed_pwm(hwmgr, speed); 560 } 561 562 static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm) 563 { 564 struct pp_hwmgr *hwmgr = handle; 565 566 if (!hwmgr || !hwmgr->pm_en) 567 return -EOPNOTSUPP; 568 569 if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL) 570 return -EOPNOTSUPP; 571 572 if (!rpm) 573 return -EINVAL; 574 575 return hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm); 576 } 577 578 static int pp_dpm_set_fan_speed_rpm(void *handle, uint32_t rpm) 579 { 580 struct pp_hwmgr *hwmgr = handle; 581 582 if (!hwmgr || !hwmgr->pm_en) 583 return -EOPNOTSUPP; 584 585 if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL) 586 return -EOPNOTSUPP; 587 588 if (rpm == U32_MAX) 589 return -EINVAL; 590 591 return hwmgr->hwmgr_func->set_fan_speed_rpm(hwmgr, rpm); 592 } 593 594 static int pp_dpm_get_pp_num_states(void *handle, 595 struct pp_states_info *data) 596 { 597 struct pp_hwmgr *hwmgr = handle; 598 int i; 599 600 memset(data, 0, sizeof(*data)); 601 602 if (!hwmgr || !hwmgr->pm_en || !hwmgr->ps) 603 return -EINVAL; 604 605 data->nums = hwmgr->num_ps; 606 607 for (i = 0; i < hwmgr->num_ps; i++) { 608 struct pp_power_state *state = (struct pp_power_state *) 609 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size); 610 switch (state->classification.ui_label) { 611 case PP_StateUILabel_Battery: 612 data->states[i] = POWER_STATE_TYPE_BATTERY; 613 break; 614 case PP_StateUILabel_Balanced: 615 data->states[i] = POWER_STATE_TYPE_BALANCED; 616 break; 617 case PP_StateUILabel_Performance: 618 data->states[i] = POWER_STATE_TYPE_PERFORMANCE; 619 break; 620 default: 621 if (state->classification.flags & PP_StateClassificationFlag_Boot) 622 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT; 623 else 624 data->states[i] = POWER_STATE_TYPE_DEFAULT; 625 } 626 } 627 return 0; 628 } 629 630 static int pp_dpm_get_pp_table(void *handle, char **table) 631 { 632 struct pp_hwmgr *hwmgr = handle; 633 634 if (!hwmgr || !hwmgr->pm_en || !table) 635 return -EINVAL; 636 637 if (!hwmgr->soft_pp_table) 638 return -EOPNOTSUPP; 639 640 *table = (char *)hwmgr->soft_pp_table; 641 return hwmgr->soft_pp_table_size; 642 } 643 644 static int amd_powerplay_reset(void *handle) 645 { 646 struct pp_hwmgr *hwmgr = handle; 647 int ret; 648 649 ret = hwmgr_hw_fini(hwmgr); 650 if (ret) 651 return ret; 652 653 ret = hwmgr_hw_init(hwmgr); 654 if (ret) 655 return ret; 656 657 return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL); 658 } 659 660 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size) 661 { 662 struct pp_hwmgr *hwmgr = handle; 663 int ret = -ENOMEM; 664 665 if (!hwmgr || !hwmgr->pm_en) 666 return -EINVAL; 667 668 if (size > hwmgr->soft_pp_table_size) 669 return -EINVAL; 670 671 if (!hwmgr->hardcode_pp_table) { 672 hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table, 673 hwmgr->soft_pp_table_size, 674 GFP_KERNEL); 675 if (!hwmgr->hardcode_pp_table) 676 return ret; 677 } 678 679 memcpy(hwmgr->hardcode_pp_table, buf, size); 680 681 hwmgr->soft_pp_table = hwmgr->hardcode_pp_table; 682 683 ret = amd_powerplay_reset(handle); 684 if (ret) 685 return ret; 686 687 if (hwmgr->hwmgr_func->avfs_control) 688 ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false); 689 690 return ret; 691 } 692 693 static int pp_dpm_force_clock_level(void *handle, 694 enum pp_clock_type type, uint32_t mask) 695 { 696 struct pp_hwmgr *hwmgr = handle; 697 698 if (!hwmgr || !hwmgr->pm_en) 699 return -EINVAL; 700 701 if (hwmgr->hwmgr_func->force_clock_level == NULL) { 702 pr_info_ratelimited("%s was not implemented.\n", __func__); 703 return 0; 704 } 705 706 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 707 pr_debug("force clock level is for dpm manual mode only.\n"); 708 return -EINVAL; 709 } 710 711 return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask); 712 } 713 714 static int pp_dpm_emit_clock_levels(void *handle, 715 enum pp_clock_type type, 716 char *buf, 717 int *offset) 718 { 719 struct pp_hwmgr *hwmgr = handle; 720 721 if (!hwmgr || !hwmgr->pm_en) 722 return -EOPNOTSUPP; 723 724 if (!hwmgr->hwmgr_func->emit_clock_levels) 725 return -ENOENT; 726 727 return hwmgr->hwmgr_func->emit_clock_levels(hwmgr, type, buf, offset); 728 } 729 730 static int pp_dpm_get_sclk_od(void *handle) 731 { 732 struct pp_hwmgr *hwmgr = handle; 733 734 if (!hwmgr || !hwmgr->pm_en) 735 return -EINVAL; 736 737 if (hwmgr->hwmgr_func->get_sclk_od == NULL) { 738 pr_info_ratelimited("%s was not implemented.\n", __func__); 739 return 0; 740 } 741 return hwmgr->hwmgr_func->get_sclk_od(hwmgr); 742 } 743 744 static int pp_dpm_set_sclk_od(void *handle, uint32_t value) 745 { 746 struct pp_hwmgr *hwmgr = handle; 747 748 if (!hwmgr || !hwmgr->pm_en) 749 return -EINVAL; 750 751 if (hwmgr->hwmgr_func->set_sclk_od == NULL) { 752 pr_info_ratelimited("%s was not implemented.\n", __func__); 753 return 0; 754 } 755 756 return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value); 757 } 758 759 static int pp_dpm_get_mclk_od(void *handle) 760 { 761 struct pp_hwmgr *hwmgr = handle; 762 763 if (!hwmgr || !hwmgr->pm_en) 764 return -EINVAL; 765 766 if (hwmgr->hwmgr_func->get_mclk_od == NULL) { 767 pr_info_ratelimited("%s was not implemented.\n", __func__); 768 return 0; 769 } 770 return hwmgr->hwmgr_func->get_mclk_od(hwmgr); 771 } 772 773 static int pp_dpm_set_mclk_od(void *handle, uint32_t value) 774 { 775 struct pp_hwmgr *hwmgr = handle; 776 777 if (!hwmgr || !hwmgr->pm_en) 778 return -EINVAL; 779 780 if (hwmgr->hwmgr_func->set_mclk_od == NULL) { 781 pr_info_ratelimited("%s was not implemented.\n", __func__); 782 return 0; 783 } 784 return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value); 785 } 786 787 static int pp_dpm_read_sensor(void *handle, int idx, 788 void *value, int *size) 789 { 790 struct pp_hwmgr *hwmgr = handle; 791 792 if (!hwmgr || !hwmgr->pm_en || !value) 793 return -EINVAL; 794 795 switch (idx) { 796 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 797 *((uint32_t *)value) = hwmgr->pstate_sclk * 100; 798 return 0; 799 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 800 *((uint32_t *)value) = hwmgr->pstate_mclk * 100; 801 return 0; 802 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 803 *((uint32_t *)value) = hwmgr->pstate_sclk_peak * 100; 804 return 0; 805 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 806 *((uint32_t *)value) = hwmgr->pstate_mclk_peak * 100; 807 return 0; 808 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 809 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM; 810 return 0; 811 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 812 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMaxRPM; 813 return 0; 814 default: 815 return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size); 816 } 817 } 818 819 static struct amd_vce_state* 820 pp_dpm_get_vce_clock_state(void *handle, unsigned idx) 821 { 822 struct pp_hwmgr *hwmgr = handle; 823 824 if (!hwmgr || !hwmgr->pm_en) 825 return NULL; 826 827 if (idx < hwmgr->num_vce_state_tables) 828 return &hwmgr->vce_states[idx]; 829 return NULL; 830 } 831 832 static int pp_get_power_profile_mode(void *handle, char *buf) 833 { 834 struct pp_hwmgr *hwmgr = handle; 835 836 if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->get_power_profile_mode) 837 return -EOPNOTSUPP; 838 if (!buf) 839 return -EINVAL; 840 841 return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf); 842 } 843 844 static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size) 845 { 846 struct pp_hwmgr *hwmgr = handle; 847 848 if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->set_power_profile_mode) 849 return -EOPNOTSUPP; 850 851 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 852 pr_debug("power profile setting is for manual dpm mode only.\n"); 853 return -EINVAL; 854 } 855 856 return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size); 857 } 858 859 static int pp_set_fine_grain_clk_vol(void *handle, uint32_t type, long *input, uint32_t size) 860 { 861 struct pp_hwmgr *hwmgr = handle; 862 863 if (!hwmgr || !hwmgr->pm_en) 864 return -EINVAL; 865 866 if (hwmgr->hwmgr_func->set_fine_grain_clk_vol == NULL) 867 return 0; 868 869 return hwmgr->hwmgr_func->set_fine_grain_clk_vol(hwmgr, type, input, size); 870 } 871 872 static int pp_odn_edit_dpm_table(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 873 long *input, uint32_t size) 874 { 875 struct pp_hwmgr *hwmgr = handle; 876 877 if (!hwmgr || !hwmgr->pm_en) 878 return -EINVAL; 879 880 if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) { 881 pr_info_ratelimited("%s was not implemented.\n", __func__); 882 return 0; 883 } 884 885 return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size); 886 } 887 888 static int pp_dpm_set_mp1_state(void *handle, enum pp_mp1_state mp1_state) 889 { 890 struct pp_hwmgr *hwmgr = handle; 891 892 if (!hwmgr) 893 return -EINVAL; 894 895 if (!hwmgr->pm_en) 896 return 0; 897 898 if (hwmgr->hwmgr_func->set_mp1_state) 899 return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state); 900 901 return 0; 902 } 903 904 static int pp_dpm_switch_power_profile(void *handle, 905 enum PP_SMC_POWER_PROFILE type, bool en) 906 { 907 struct pp_hwmgr *hwmgr = handle; 908 long workload[1]; 909 uint32_t index; 910 911 if (!hwmgr || !hwmgr->pm_en) 912 return -EINVAL; 913 914 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) { 915 pr_info_ratelimited("%s was not implemented.\n", __func__); 916 return -EINVAL; 917 } 918 919 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 920 return -EINVAL; 921 922 if (!en) { 923 hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]); 924 index = fls(hwmgr->workload_mask); 925 index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0; 926 workload[0] = hwmgr->workload_setting[index]; 927 } else { 928 hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]); 929 index = fls(hwmgr->workload_mask); 930 index = index <= Workload_Policy_Max ? index - 1 : 0; 931 workload[0] = hwmgr->workload_setting[index]; 932 } 933 934 if (type == PP_SMC_POWER_PROFILE_COMPUTE && 935 hwmgr->hwmgr_func->disable_power_features_for_compute_performance) { 936 if (hwmgr->hwmgr_func->disable_power_features_for_compute_performance(hwmgr, en)) 937 return -EINVAL; 938 } 939 940 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 941 hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, workload, 0); 942 943 return 0; 944 } 945 946 static int pp_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit) 947 { 948 struct pp_hwmgr *hwmgr = handle; 949 uint32_t max_power_limit; 950 951 if (!hwmgr || !hwmgr->pm_en) 952 return -EINVAL; 953 954 if (hwmgr->hwmgr_func->set_power_limit == NULL) { 955 pr_info_ratelimited("%s was not implemented.\n", __func__); 956 return -EINVAL; 957 } 958 959 if (limit == 0) 960 limit = hwmgr->default_power_limit; 961 962 max_power_limit = hwmgr->default_power_limit; 963 if (hwmgr->od_enabled) { 964 max_power_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit); 965 max_power_limit /= 100; 966 } 967 968 if (limit > max_power_limit) 969 return -EINVAL; 970 971 hwmgr->hwmgr_func->set_power_limit(hwmgr, limit); 972 hwmgr->power_limit = limit; 973 return 0; 974 } 975 976 static int pp_get_power_limit(void *handle, uint32_t *limit, 977 enum pp_power_limit_level pp_limit_level, 978 enum pp_power_type power_type) 979 { 980 struct pp_hwmgr *hwmgr = handle; 981 int ret = 0; 982 983 if (!hwmgr || !hwmgr->pm_en || !limit) 984 return -EINVAL; 985 986 if (power_type != PP_PWR_TYPE_SUSTAINED) 987 return -EOPNOTSUPP; 988 989 switch (pp_limit_level) { 990 case PP_PWR_LIMIT_CURRENT: 991 *limit = hwmgr->power_limit; 992 break; 993 case PP_PWR_LIMIT_DEFAULT: 994 *limit = hwmgr->default_power_limit; 995 break; 996 case PP_PWR_LIMIT_MAX: 997 *limit = hwmgr->default_power_limit; 998 if (hwmgr->od_enabled) { 999 *limit *= (100 + hwmgr->platform_descriptor.TDPODLimit); 1000 *limit /= 100; 1001 } 1002 break; 1003 case PP_PWR_LIMIT_MIN: 1004 *limit = 0; 1005 break; 1006 default: 1007 ret = -EOPNOTSUPP; 1008 break; 1009 } 1010 1011 return ret; 1012 } 1013 1014 static int pp_display_configuration_change(void *handle, 1015 const struct amd_pp_display_configuration *display_config) 1016 { 1017 struct pp_hwmgr *hwmgr = handle; 1018 1019 if (!hwmgr || !hwmgr->pm_en) 1020 return -EINVAL; 1021 1022 phm_store_dal_configuration_data(hwmgr, display_config); 1023 return 0; 1024 } 1025 1026 static int pp_get_current_clocks(void *handle, 1027 struct amd_pp_clock_info *clocks) 1028 { 1029 struct pp_clock_info hw_clocks; 1030 struct pp_hwmgr *hwmgr = handle; 1031 int ret = 0; 1032 1033 if (!hwmgr || !hwmgr->pm_en) 1034 return -EINVAL; 1035 1036 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1037 PHM_PlatformCaps_PowerContainment)) 1038 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, 1039 &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment); 1040 else 1041 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, 1042 &hw_clocks, PHM_PerformanceLevelDesignation_Activity); 1043 1044 if (ret) { 1045 drm_err(adev_to_drm(hwmgr->adev), 1046 "Error in phm_get_clock_info\n"); 1047 return -EINVAL; 1048 } 1049 1050 clocks->min_engine_clock = hw_clocks.min_eng_clk; 1051 clocks->max_engine_clock = hw_clocks.max_eng_clk; 1052 clocks->min_memory_clock = hw_clocks.min_mem_clk; 1053 clocks->max_memory_clock = hw_clocks.max_mem_clk; 1054 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth; 1055 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth; 1056 1057 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; 1058 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; 1059 1060 if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) { 1061 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; 1062 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; 1063 } 1064 return 0; 1065 } 1066 1067 static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) 1068 { 1069 struct pp_hwmgr *hwmgr = handle; 1070 1071 if (!hwmgr || !hwmgr->pm_en) 1072 return -EINVAL; 1073 1074 if (clocks == NULL) 1075 return -EINVAL; 1076 1077 return phm_get_clock_by_type(hwmgr, type, clocks); 1078 } 1079 1080 static int pp_get_clock_by_type_with_latency(void *handle, 1081 enum amd_pp_clock_type type, 1082 struct pp_clock_levels_with_latency *clocks) 1083 { 1084 struct pp_hwmgr *hwmgr = handle; 1085 1086 if (!hwmgr || !hwmgr->pm_en || !clocks) 1087 return -EINVAL; 1088 1089 return phm_get_clock_by_type_with_latency(hwmgr, type, clocks); 1090 } 1091 1092 static int pp_get_clock_by_type_with_voltage(void *handle, 1093 enum amd_pp_clock_type type, 1094 struct pp_clock_levels_with_voltage *clocks) 1095 { 1096 struct pp_hwmgr *hwmgr = handle; 1097 1098 if (!hwmgr || !hwmgr->pm_en || !clocks) 1099 return -EINVAL; 1100 1101 return phm_get_clock_by_type_with_voltage(hwmgr, type, clocks); 1102 } 1103 1104 static int pp_set_watermarks_for_clocks_ranges(void *handle, 1105 void *clock_ranges) 1106 { 1107 struct pp_hwmgr *hwmgr = handle; 1108 1109 if (!hwmgr || !hwmgr->pm_en || !clock_ranges) 1110 return -EINVAL; 1111 1112 return phm_set_watermarks_for_clocks_ranges(hwmgr, 1113 clock_ranges); 1114 } 1115 1116 static int pp_display_clock_voltage_request(void *handle, 1117 struct pp_display_clock_request *clock) 1118 { 1119 struct pp_hwmgr *hwmgr = handle; 1120 1121 if (!hwmgr || !hwmgr->pm_en || !clock) 1122 return -EINVAL; 1123 1124 return phm_display_clock_voltage_request(hwmgr, clock); 1125 } 1126 1127 static int pp_get_display_mode_validation_clocks(void *handle, 1128 struct amd_pp_simple_clock_info *clocks) 1129 { 1130 struct pp_hwmgr *hwmgr = handle; 1131 int ret = 0; 1132 1133 if (!hwmgr || !hwmgr->pm_en || !clocks) 1134 return -EINVAL; 1135 1136 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState)) 1137 ret = phm_get_max_high_clocks(hwmgr, clocks); 1138 1139 return ret; 1140 } 1141 1142 static int pp_dpm_powergate_mmhub(void *handle) 1143 { 1144 struct pp_hwmgr *hwmgr = handle; 1145 1146 if (!hwmgr || !hwmgr->pm_en) 1147 return -EINVAL; 1148 1149 if (hwmgr->hwmgr_func->powergate_mmhub == NULL) { 1150 pr_info_ratelimited("%s was not implemented.\n", __func__); 1151 return 0; 1152 } 1153 1154 return hwmgr->hwmgr_func->powergate_mmhub(hwmgr); 1155 } 1156 1157 static int pp_dpm_powergate_gfx(void *handle, bool gate) 1158 { 1159 struct pp_hwmgr *hwmgr = handle; 1160 1161 if (!hwmgr || !hwmgr->pm_en) 1162 return 0; 1163 1164 if (hwmgr->hwmgr_func->powergate_gfx == NULL) { 1165 pr_info_ratelimited("%s was not implemented.\n", __func__); 1166 return 0; 1167 } 1168 1169 return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate); 1170 } 1171 1172 static void pp_dpm_powergate_acp(void *handle, bool gate) 1173 { 1174 struct pp_hwmgr *hwmgr = handle; 1175 1176 if (!hwmgr || !hwmgr->pm_en) 1177 return; 1178 1179 if (hwmgr->hwmgr_func->powergate_acp == NULL) { 1180 pr_info_ratelimited("%s was not implemented.\n", __func__); 1181 return; 1182 } 1183 1184 hwmgr->hwmgr_func->powergate_acp(hwmgr, gate); 1185 } 1186 1187 static void pp_dpm_powergate_sdma(void *handle, bool gate) 1188 { 1189 struct pp_hwmgr *hwmgr = handle; 1190 1191 if (!hwmgr) 1192 return; 1193 1194 if (hwmgr->hwmgr_func->powergate_sdma == NULL) { 1195 pr_info_ratelimited("%s was not implemented.\n", __func__); 1196 return; 1197 } 1198 1199 hwmgr->hwmgr_func->powergate_sdma(hwmgr, gate); 1200 } 1201 1202 static int pp_set_powergating_by_smu(void *handle, 1203 uint32_t block_type, 1204 bool gate, 1205 int inst) 1206 { 1207 int ret = 0; 1208 1209 switch (block_type) { 1210 case AMD_IP_BLOCK_TYPE_UVD: 1211 case AMD_IP_BLOCK_TYPE_VCN: 1212 pp_dpm_powergate_uvd(handle, gate); 1213 break; 1214 case AMD_IP_BLOCK_TYPE_VCE: 1215 pp_dpm_powergate_vce(handle, gate); 1216 break; 1217 case AMD_IP_BLOCK_TYPE_GMC: 1218 /* 1219 * For now, this is only used on PICASSO. 1220 * And only "gate" operation is supported. 1221 */ 1222 if (gate) 1223 pp_dpm_powergate_mmhub(handle); 1224 break; 1225 case AMD_IP_BLOCK_TYPE_GFX: 1226 ret = pp_dpm_powergate_gfx(handle, gate); 1227 break; 1228 case AMD_IP_BLOCK_TYPE_ACP: 1229 pp_dpm_powergate_acp(handle, gate); 1230 break; 1231 case AMD_IP_BLOCK_TYPE_SDMA: 1232 pp_dpm_powergate_sdma(handle, gate); 1233 break; 1234 default: 1235 break; 1236 } 1237 return ret; 1238 } 1239 1240 static int pp_notify_smu_enable_pwe(void *handle) 1241 { 1242 struct pp_hwmgr *hwmgr = handle; 1243 1244 if (!hwmgr || !hwmgr->pm_en) 1245 return -EINVAL; 1246 1247 if (hwmgr->hwmgr_func->smus_notify_pwe == NULL) { 1248 pr_info_ratelimited("%s was not implemented.\n", __func__); 1249 return -EINVAL; 1250 } 1251 1252 hwmgr->hwmgr_func->smus_notify_pwe(hwmgr); 1253 1254 return 0; 1255 } 1256 1257 static int pp_enable_mgpu_fan_boost(void *handle) 1258 { 1259 struct pp_hwmgr *hwmgr = handle; 1260 1261 if (!hwmgr) 1262 return -EINVAL; 1263 1264 if (!hwmgr->pm_en || 1265 hwmgr->hwmgr_func->enable_mgpu_fan_boost == NULL) 1266 return 0; 1267 1268 hwmgr->hwmgr_func->enable_mgpu_fan_boost(hwmgr); 1269 1270 return 0; 1271 } 1272 1273 static int pp_set_min_deep_sleep_dcefclk(void *handle, uint32_t clock) 1274 { 1275 struct pp_hwmgr *hwmgr = handle; 1276 1277 if (!hwmgr || !hwmgr->pm_en) 1278 return -EINVAL; 1279 1280 if (hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk == NULL) { 1281 pr_debug("%s was not implemented.\n", __func__); 1282 return -EINVAL; 1283 } 1284 1285 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock); 1286 1287 return 0; 1288 } 1289 1290 static int pp_set_hard_min_dcefclk_by_freq(void *handle, uint32_t clock) 1291 { 1292 struct pp_hwmgr *hwmgr = handle; 1293 1294 if (!hwmgr || !hwmgr->pm_en) 1295 return -EINVAL; 1296 1297 if (hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq == NULL) { 1298 pr_debug("%s was not implemented.\n", __func__); 1299 return -EINVAL; 1300 } 1301 1302 hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock); 1303 1304 return 0; 1305 } 1306 1307 static int pp_set_hard_min_fclk_by_freq(void *handle, uint32_t clock) 1308 { 1309 struct pp_hwmgr *hwmgr = handle; 1310 1311 if (!hwmgr || !hwmgr->pm_en) 1312 return -EINVAL; 1313 1314 if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL) { 1315 pr_debug("%s was not implemented.\n", __func__); 1316 return -EINVAL; 1317 } 1318 1319 hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock); 1320 1321 return 0; 1322 } 1323 1324 static int pp_set_active_display_count(void *handle, uint32_t count) 1325 { 1326 struct pp_hwmgr *hwmgr = handle; 1327 1328 if (!hwmgr || !hwmgr->pm_en) 1329 return -EINVAL; 1330 1331 return phm_set_active_display_count(hwmgr, count); 1332 } 1333 1334 static int pp_get_asic_baco_capability(void *handle) 1335 { 1336 struct pp_hwmgr *hwmgr = handle; 1337 1338 if (!hwmgr) 1339 return false; 1340 1341 if (!(hwmgr->not_vf && amdgpu_dpm) || 1342 !hwmgr->hwmgr_func->get_bamaco_support) 1343 return false; 1344 1345 return hwmgr->hwmgr_func->get_bamaco_support(hwmgr); 1346 } 1347 1348 static int pp_get_asic_baco_state(void *handle, int *state) 1349 { 1350 struct pp_hwmgr *hwmgr = handle; 1351 1352 if (!hwmgr) 1353 return -EINVAL; 1354 1355 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state) 1356 return 0; 1357 1358 hwmgr->hwmgr_func->get_asic_baco_state(hwmgr, (enum BACO_STATE *)state); 1359 1360 return 0; 1361 } 1362 1363 static int pp_set_asic_baco_state(void *handle, int state) 1364 { 1365 struct pp_hwmgr *hwmgr = handle; 1366 1367 if (!hwmgr) 1368 return -EINVAL; 1369 1370 if (!(hwmgr->not_vf && amdgpu_dpm) || 1371 !hwmgr->hwmgr_func->set_asic_baco_state) 1372 return 0; 1373 1374 hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum BACO_STATE)state); 1375 1376 return 0; 1377 } 1378 1379 static int pp_get_ppfeature_status(void *handle, char *buf) 1380 { 1381 struct pp_hwmgr *hwmgr = handle; 1382 1383 if (!hwmgr || !hwmgr->pm_en || !buf) 1384 return -EINVAL; 1385 1386 if (hwmgr->hwmgr_func->get_ppfeature_status == NULL) { 1387 pr_info_ratelimited("%s was not implemented.\n", __func__); 1388 return -EINVAL; 1389 } 1390 1391 return hwmgr->hwmgr_func->get_ppfeature_status(hwmgr, buf); 1392 } 1393 1394 static int pp_set_ppfeature_status(void *handle, uint64_t ppfeature_masks) 1395 { 1396 struct pp_hwmgr *hwmgr = handle; 1397 1398 if (!hwmgr || !hwmgr->pm_en) 1399 return -EINVAL; 1400 1401 if (hwmgr->hwmgr_func->set_ppfeature_status == NULL) { 1402 pr_info_ratelimited("%s was not implemented.\n", __func__); 1403 return -EINVAL; 1404 } 1405 1406 return hwmgr->hwmgr_func->set_ppfeature_status(hwmgr, ppfeature_masks); 1407 } 1408 1409 static int pp_asic_reset_mode_2(void *handle) 1410 { 1411 struct pp_hwmgr *hwmgr = handle; 1412 1413 if (!hwmgr || !hwmgr->pm_en) 1414 return -EINVAL; 1415 1416 if (hwmgr->hwmgr_func->asic_reset == NULL) { 1417 pr_info_ratelimited("%s was not implemented.\n", __func__); 1418 return -EINVAL; 1419 } 1420 1421 return hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASIC_RESET_MODE_2); 1422 } 1423 1424 static int pp_smu_i2c_bus_access(void *handle, bool acquire) 1425 { 1426 struct pp_hwmgr *hwmgr = handle; 1427 1428 if (!hwmgr || !hwmgr->pm_en) 1429 return -EINVAL; 1430 1431 if (hwmgr->hwmgr_func->smu_i2c_bus_access == NULL) { 1432 pr_info_ratelimited("%s was not implemented.\n", __func__); 1433 return -EINVAL; 1434 } 1435 1436 return hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire); 1437 } 1438 1439 static int pp_set_df_cstate(void *handle, enum pp_df_cstate state) 1440 { 1441 struct pp_hwmgr *hwmgr = handle; 1442 1443 if (!hwmgr) 1444 return -EINVAL; 1445 1446 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_df_cstate) 1447 return 0; 1448 1449 hwmgr->hwmgr_func->set_df_cstate(hwmgr, state); 1450 1451 return 0; 1452 } 1453 1454 static int pp_set_xgmi_pstate(void *handle, uint32_t pstate) 1455 { 1456 struct pp_hwmgr *hwmgr = handle; 1457 1458 if (!hwmgr) 1459 return -EINVAL; 1460 1461 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_xgmi_pstate) 1462 return 0; 1463 1464 hwmgr->hwmgr_func->set_xgmi_pstate(hwmgr, pstate); 1465 1466 return 0; 1467 } 1468 1469 static ssize_t pp_get_gpu_metrics(void *handle, void **table) 1470 { 1471 struct pp_hwmgr *hwmgr = handle; 1472 1473 if (!hwmgr) 1474 return -EINVAL; 1475 1476 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_gpu_metrics) 1477 return -EOPNOTSUPP; 1478 1479 return hwmgr->hwmgr_func->get_gpu_metrics(hwmgr, table); 1480 } 1481 1482 static int pp_gfx_state_change_set(void *handle, uint32_t state) 1483 { 1484 struct pp_hwmgr *hwmgr = handle; 1485 1486 if (!hwmgr || !hwmgr->pm_en) 1487 return -EINVAL; 1488 1489 if (hwmgr->hwmgr_func->gfx_state_change == NULL) { 1490 pr_info_ratelimited("%s was not implemented.\n", __func__); 1491 return -EINVAL; 1492 } 1493 1494 hwmgr->hwmgr_func->gfx_state_change(hwmgr, state); 1495 return 0; 1496 } 1497 1498 static int pp_get_prv_buffer_details(void *handle, void **addr, size_t *size) 1499 { 1500 struct pp_hwmgr *hwmgr = handle; 1501 struct amdgpu_device *adev = hwmgr->adev; 1502 int err; 1503 1504 if (!addr || !size) 1505 return -EINVAL; 1506 1507 *addr = NULL; 1508 *size = 0; 1509 if (adev->pm.smu_prv_buffer) { 1510 err = amdgpu_bo_kmap(adev->pm.smu_prv_buffer, addr); 1511 if (err) 1512 return err; 1513 *size = adev->pm.smu_prv_buffer_size; 1514 } 1515 1516 return 0; 1517 } 1518 1519 static void pp_pm_compute_clocks(void *handle) 1520 { 1521 struct pp_hwmgr *hwmgr = handle; 1522 struct amdgpu_device *adev = hwmgr->adev; 1523 1524 if (!adev->dc_enabled) { 1525 amdgpu_dpm_get_display_cfg(adev); 1526 pp_display_configuration_change(handle, 1527 &adev->pm.pm_display_cfg); 1528 } 1529 1530 pp_dpm_dispatch_tasks(handle, 1531 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 1532 NULL); 1533 } 1534 1535 static void pp_dpm_notify_ac_dc(void *handle) 1536 { 1537 struct pp_hwmgr *hwmgr = handle; 1538 1539 if (!hwmgr || !hwmgr->pm_en) 1540 return; 1541 1542 if (hwmgr->hwmgr_func->notify_ac_dc) 1543 hwmgr->hwmgr_func->notify_ac_dc(hwmgr); 1544 } 1545 1546 static const struct amd_pm_funcs pp_dpm_funcs = { 1547 .load_firmware = pp_dpm_load_fw, 1548 .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, 1549 .force_performance_level = pp_dpm_force_performance_level, 1550 .get_performance_level = pp_dpm_get_performance_level, 1551 .get_current_power_state = pp_dpm_get_current_power_state, 1552 .dispatch_tasks = pp_dpm_dispatch_tasks, 1553 .set_fan_control_mode = pp_dpm_set_fan_control_mode, 1554 .get_fan_control_mode = pp_dpm_get_fan_control_mode, 1555 .set_fan_speed_pwm = pp_dpm_set_fan_speed_pwm, 1556 .get_fan_speed_pwm = pp_dpm_get_fan_speed_pwm, 1557 .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm, 1558 .set_fan_speed_rpm = pp_dpm_set_fan_speed_rpm, 1559 .get_pp_num_states = pp_dpm_get_pp_num_states, 1560 .get_pp_table = pp_dpm_get_pp_table, 1561 .set_pp_table = pp_dpm_set_pp_table, 1562 .force_clock_level = pp_dpm_force_clock_level, 1563 .emit_clock_levels = pp_dpm_emit_clock_levels, 1564 .get_sclk_od = pp_dpm_get_sclk_od, 1565 .set_sclk_od = pp_dpm_set_sclk_od, 1566 .get_mclk_od = pp_dpm_get_mclk_od, 1567 .set_mclk_od = pp_dpm_set_mclk_od, 1568 .read_sensor = pp_dpm_read_sensor, 1569 .get_vce_clock_state = pp_dpm_get_vce_clock_state, 1570 .switch_power_profile = pp_dpm_switch_power_profile, 1571 .set_clockgating_by_smu = pp_set_clockgating_by_smu, 1572 .set_powergating_by_smu = pp_set_powergating_by_smu, 1573 .get_power_profile_mode = pp_get_power_profile_mode, 1574 .set_power_profile_mode = pp_set_power_profile_mode, 1575 .set_fine_grain_clk_vol = pp_set_fine_grain_clk_vol, 1576 .odn_edit_dpm_table = pp_odn_edit_dpm_table, 1577 .set_mp1_state = pp_dpm_set_mp1_state, 1578 .set_power_limit = pp_set_power_limit, 1579 .get_power_limit = pp_get_power_limit, 1580 /* export to DC */ 1581 .get_sclk = pp_dpm_get_sclk, 1582 .get_mclk = pp_dpm_get_mclk, 1583 .display_configuration_change = pp_display_configuration_change, 1584 .get_current_clocks = pp_get_current_clocks, 1585 .get_clock_by_type = pp_get_clock_by_type, 1586 .get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency, 1587 .get_clock_by_type_with_voltage = pp_get_clock_by_type_with_voltage, 1588 .set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges, 1589 .display_clock_voltage_request = pp_display_clock_voltage_request, 1590 .get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks, 1591 .notify_smu_enable_pwe = pp_notify_smu_enable_pwe, 1592 .enable_mgpu_fan_boost = pp_enable_mgpu_fan_boost, 1593 .set_active_display_count = pp_set_active_display_count, 1594 .set_min_deep_sleep_dcefclk = pp_set_min_deep_sleep_dcefclk, 1595 .set_hard_min_dcefclk_by_freq = pp_set_hard_min_dcefclk_by_freq, 1596 .set_hard_min_fclk_by_freq = pp_set_hard_min_fclk_by_freq, 1597 .get_asic_baco_capability = pp_get_asic_baco_capability, 1598 .get_asic_baco_state = pp_get_asic_baco_state, 1599 .set_asic_baco_state = pp_set_asic_baco_state, 1600 .get_ppfeature_status = pp_get_ppfeature_status, 1601 .set_ppfeature_status = pp_set_ppfeature_status, 1602 .asic_reset_mode_2 = pp_asic_reset_mode_2, 1603 .smu_i2c_bus_access = pp_smu_i2c_bus_access, 1604 .set_df_cstate = pp_set_df_cstate, 1605 .set_xgmi_pstate = pp_set_xgmi_pstate, 1606 .get_gpu_metrics = pp_get_gpu_metrics, 1607 .gfx_state_change_set = pp_gfx_state_change_set, 1608 .get_smu_prv_buf_details = pp_get_prv_buffer_details, 1609 .pm_compute_clocks = pp_pm_compute_clocks, 1610 .notify_ac_dc = pp_dpm_notify_ac_dc, 1611 }; 1612