1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Xilinx, Inc. 4 * CEVA AHCI SATA platform driver 5 * 6 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov 7 */ 8 9 #include <linux/ahci_platform.h> 10 #include <linux/kernel.h> 11 #include <linux/libata.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/reset.h> 17 #include "ahci.h" 18 19 /* Vendor Specific Register Offsets */ 20 #define AHCI_VEND_PCFG 0xA4 21 #define AHCI_VEND_PPCFG 0xA8 22 #define AHCI_VEND_PP2C 0xAC 23 #define AHCI_VEND_PP3C 0xB0 24 #define AHCI_VEND_PP4C 0xB4 25 #define AHCI_VEND_PP5C 0xB8 26 #define AHCI_VEND_AXICC 0xBC 27 #define AHCI_VEND_PAXIC 0xC0 28 #define AHCI_VEND_PTC 0xC8 29 30 /* Vendor Specific Register bit definitions */ 31 #define PAXIC_ADBW_BW64 0x1 32 #define PAXIC_MAWID(i) (((i) * 2) << 4) 33 #define PAXIC_MARID(i) (((i) * 2) << 12) 34 #define PAXIC_MARIDD(i) ((((i) * 2) + 1) << 16) 35 #define PAXIC_MAWIDD(i) ((((i) * 2) + 1) << 8) 36 #define PAXIC_OTL (0x4 << 20) 37 38 /* Register bit definitions for cache control */ 39 #define AXICC_ARCA_VAL (0xF << 0) 40 #define AXICC_ARCF_VAL (0xF << 4) 41 #define AXICC_ARCH_VAL (0xF << 8) 42 #define AXICC_ARCP_VAL (0xF << 12) 43 #define AXICC_AWCFD_VAL (0xF << 16) 44 #define AXICC_AWCD_VAL (0xF << 20) 45 #define AXICC_AWCF_VAL (0xF << 24) 46 47 #define PCFG_TPSS_VAL (0x32 << 16) 48 #define PCFG_TPRS_VAL (0x2 << 12) 49 #define PCFG_PAD_VAL 0x2 50 51 #define PPCFG_TTA 0x1FFFE 52 #define PPCFG_PSSO_EN (1 << 28) 53 #define PPCFG_PSS_EN (1 << 29) 54 #define PPCFG_ESDF_EN (1 << 31) 55 56 #define PP5C_RIT 0x60216 57 #define PP5C_RCT (0x7f0 << 20) 58 59 #define PTC_RX_WM_VAL 0x40 60 #define PTC_RSVD (1 << 27) 61 62 #define PORT0_BASE 0x100 63 #define PORT1_BASE 0x180 64 65 /* Port Control Register Bit Definitions */ 66 #define PORT_SCTL_SPD_GEN3 (0x3 << 4) 67 #define PORT_SCTL_SPD_GEN2 (0x2 << 4) 68 #define PORT_SCTL_SPD_GEN1 (0x1 << 4) 69 #define PORT_SCTL_IPM (0x3 << 8) 70 71 #define PORT_BASE 0x100 72 #define PORT_OFFSET 0x80 73 #define NR_PORTS 2 74 #define DRV_NAME "ahci-ceva" 75 #define CEVA_FLAG_BROKEN_GEN2 1 76 77 static unsigned int rx_watermark = PTC_RX_WM_VAL; 78 module_param(rx_watermark, uint, 0644); 79 MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)"); 80 81 struct ceva_ahci_priv { 82 struct platform_device *ahci_pdev; 83 /* Port Phy2Cfg Register */ 84 u32 pp2c[NR_PORTS]; 85 u32 pp3c[NR_PORTS]; 86 u32 pp4c[NR_PORTS]; 87 u32 pp5c[NR_PORTS]; 88 /* Axi Cache Control Register */ 89 u32 axicc; 90 bool is_cci_enabled; 91 int flags; 92 }; 93 94 static unsigned int ceva_ahci_read_id(struct ata_device *dev, 95 struct ata_taskfile *tf, __le16 *id) 96 { 97 u32 err_mask; 98 99 err_mask = ata_do_dev_read_id(dev, tf, id); 100 if (err_mask) 101 return err_mask; 102 /* 103 * Since CEVA controller does not support device sleep feature, we 104 * need to clear DEVSLP (bit 8) in word78 of the IDENTIFY DEVICE data. 105 */ 106 id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8)); 107 108 return 0; 109 } 110 111 static struct ata_port_operations ahci_ceva_ops = { 112 .inherits = &ahci_platform_ops, 113 .read_id = ceva_ahci_read_id, 114 }; 115 116 static const struct ata_port_info ahci_ceva_port_info = { 117 .flags = AHCI_FLAG_COMMON, 118 .pio_mask = ATA_PIO4, 119 .udma_mask = ATA_UDMA6, 120 .port_ops = &ahci_ceva_ops, 121 }; 122 123 static void ahci_ceva_setup(struct ahci_host_priv *hpriv) 124 { 125 void __iomem *mmio = hpriv->mmio; 126 struct ceva_ahci_priv *cevapriv = hpriv->plat_data; 127 u32 tmp; 128 int i; 129 130 /* Set AHCI Enable */ 131 tmp = readl(mmio + HOST_CTL); 132 tmp |= HOST_AHCI_EN; 133 writel(tmp, mmio + HOST_CTL); 134 135 for (i = 0; i < NR_PORTS; i++) { 136 /* TPSS TPRS scalars, CISE and Port Addr */ 137 tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i); 138 writel(tmp, mmio + AHCI_VEND_PCFG); 139 140 /* 141 * AXI Data bus width to 64 142 * Set Mem Addr Read, Write ID for data transfers 143 * Set Mem Addr Read ID, Write ID for non-data transfers 144 * Transfer limit to 72 DWord 145 */ 146 tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD(i) | PAXIC_MARIDD(i) | 147 PAXIC_MAWID(i) | PAXIC_MARID(i) | PAXIC_OTL; 148 writel(tmp, mmio + AHCI_VEND_PAXIC); 149 150 /* Set AXI cache control register if CCi is enabled */ 151 if (cevapriv->is_cci_enabled) { 152 tmp = readl(mmio + AHCI_VEND_AXICC); 153 tmp |= AXICC_ARCA_VAL | AXICC_ARCF_VAL | 154 AXICC_ARCH_VAL | AXICC_ARCP_VAL | 155 AXICC_AWCFD_VAL | AXICC_AWCD_VAL | 156 AXICC_AWCF_VAL; 157 writel(tmp, mmio + AHCI_VEND_AXICC); 158 } 159 160 /* Port Phy Cfg register enables */ 161 tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN; 162 writel(tmp, mmio + AHCI_VEND_PPCFG); 163 164 /* Phy Control OOB timing parameters COMINIT */ 165 writel(cevapriv->pp2c[i], mmio + AHCI_VEND_PP2C); 166 167 /* Phy Control OOB timing parameters COMWAKE */ 168 writel(cevapriv->pp3c[i], mmio + AHCI_VEND_PP3C); 169 170 /* Phy Control Burst timing setting */ 171 writel(cevapriv->pp4c[i], mmio + AHCI_VEND_PP4C); 172 173 /* Rate Change Timer and Retry Interval Timer setting */ 174 writel(cevapriv->pp5c[i], mmio + AHCI_VEND_PP5C); 175 176 /* Rx Watermark setting */ 177 tmp = rx_watermark | PTC_RSVD; 178 writel(tmp, mmio + AHCI_VEND_PTC); 179 180 /* Default to Gen 3 Speed and Gen 1 if Gen2 is broken */ 181 tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM; 182 if (cevapriv->flags & CEVA_FLAG_BROKEN_GEN2) 183 tmp = PORT_SCTL_SPD_GEN1 | PORT_SCTL_IPM; 184 writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); 185 } 186 } 187 188 static const struct scsi_host_template ahci_platform_sht = { 189 AHCI_SHT(DRV_NAME), 190 }; 191 192 static int ceva_ahci_platform_enable_resources(struct ahci_host_priv *hpriv) 193 { 194 int rc, i; 195 196 rc = ahci_platform_enable_regulators(hpriv); 197 if (rc) 198 return rc; 199 200 rc = ahci_platform_enable_clks(hpriv); 201 if (rc) 202 goto disable_regulator; 203 204 /* Assert the controller reset */ 205 rc = ahci_platform_assert_rsts(hpriv); 206 if (rc) 207 goto disable_clks; 208 209 for (i = 0; i < hpriv->nports; i++) { 210 if (ahci_ignore_port(hpriv, i)) 211 continue; 212 213 rc = phy_init(hpriv->phys[i]); 214 if (rc) 215 goto exit_phys; 216 } 217 218 /* De-assert the controller reset */ 219 ahci_platform_deassert_rsts(hpriv); 220 221 for (i = 0; i < hpriv->nports; i++) { 222 if (ahci_ignore_port(hpriv, i)) 223 continue; 224 225 rc = phy_power_on(hpriv->phys[i]); 226 if (rc) { 227 phy_exit(hpriv->phys[i]); 228 goto disable_phys; 229 } 230 } 231 232 return 0; 233 234 disable_phys: 235 while (--i >= 0) { 236 if (ahci_ignore_port(hpriv, i)) 237 continue; 238 239 phy_power_off(hpriv->phys[i]); 240 phy_exit(hpriv->phys[i]); 241 } 242 ahci_platform_assert_rsts(hpriv); 243 goto disable_clks; 244 245 exit_phys: 246 while (--i >= 0) { 247 if (ahci_ignore_port(hpriv, i)) 248 continue; 249 250 phy_exit(hpriv->phys[i]); 251 } 252 253 disable_clks: 254 ahci_platform_disable_clks(hpriv); 255 256 disable_regulator: 257 ahci_platform_disable_regulators(hpriv); 258 259 return rc; 260 } 261 262 static int ceva_ahci_probe(struct platform_device *pdev) 263 { 264 struct device_node *np = pdev->dev.of_node; 265 struct device *dev = &pdev->dev; 266 struct ahci_host_priv *hpriv; 267 struct ceva_ahci_priv *cevapriv; 268 enum dev_dma_attr attr; 269 int rc; 270 271 cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL); 272 if (!cevapriv) 273 return -ENOMEM; 274 275 cevapriv->ahci_pdev = pdev; 276 hpriv = ahci_platform_get_resources(pdev, 0); 277 if (IS_ERR(hpriv)) 278 return PTR_ERR(hpriv); 279 280 hpriv->rsts = devm_reset_control_get_optional_exclusive(&pdev->dev, 281 NULL); 282 if (IS_ERR(hpriv->rsts)) 283 return dev_err_probe(&pdev->dev, PTR_ERR(hpriv->rsts), 284 "failed to get reset\n"); 285 286 rc = ceva_ahci_platform_enable_resources(hpriv); 287 if (rc) 288 return rc; 289 290 if (of_property_read_bool(np, "ceva,broken-gen2")) 291 cevapriv->flags = CEVA_FLAG_BROKEN_GEN2; 292 293 /* Read OOB timing value for COMINIT from device-tree */ 294 if (of_property_read_u8_array(np, "ceva,p0-cominit-params", 295 (u8 *)&cevapriv->pp2c[0], 4) < 0) { 296 dev_warn(dev, "ceva,p0-cominit-params property not defined\n"); 297 rc = -EINVAL; 298 goto disable_resources; 299 } 300 301 if (of_property_read_u8_array(np, "ceva,p1-cominit-params", 302 (u8 *)&cevapriv->pp2c[1], 4) < 0) { 303 dev_warn(dev, "ceva,p1-cominit-params property not defined\n"); 304 rc = -EINVAL; 305 goto disable_resources; 306 } 307 308 /* Read OOB timing value for COMWAKE from device-tree*/ 309 if (of_property_read_u8_array(np, "ceva,p0-comwake-params", 310 (u8 *)&cevapriv->pp3c[0], 4) < 0) { 311 dev_warn(dev, "ceva,p0-comwake-params property not defined\n"); 312 rc = -EINVAL; 313 goto disable_resources; 314 } 315 316 if (of_property_read_u8_array(np, "ceva,p1-comwake-params", 317 (u8 *)&cevapriv->pp3c[1], 4) < 0) { 318 dev_warn(dev, "ceva,p1-comwake-params property not defined\n"); 319 rc = -EINVAL; 320 goto disable_resources; 321 } 322 323 /* Read phy BURST timing value from device-tree */ 324 if (of_property_read_u8_array(np, "ceva,p0-burst-params", 325 (u8 *)&cevapriv->pp4c[0], 4) < 0) { 326 dev_warn(dev, "ceva,p0-burst-params property not defined\n"); 327 rc = -EINVAL; 328 goto disable_resources; 329 } 330 331 if (of_property_read_u8_array(np, "ceva,p1-burst-params", 332 (u8 *)&cevapriv->pp4c[1], 4) < 0) { 333 dev_warn(dev, "ceva,p1-burst-params property not defined\n"); 334 rc = -EINVAL; 335 goto disable_resources; 336 } 337 338 /* Read phy RETRY interval timing value from device-tree */ 339 if (of_property_read_u16_array(np, "ceva,p0-retry-params", 340 (u16 *)&cevapriv->pp5c[0], 2) < 0) { 341 dev_warn(dev, "ceva,p0-retry-params property not defined\n"); 342 rc = -EINVAL; 343 goto disable_resources; 344 } 345 346 if (of_property_read_u16_array(np, "ceva,p1-retry-params", 347 (u16 *)&cevapriv->pp5c[1], 2) < 0) { 348 dev_warn(dev, "ceva,p1-retry-params property not defined\n"); 349 rc = -EINVAL; 350 goto disable_resources; 351 } 352 353 /* 354 * Check if CCI is enabled for SATA. The DEV_DMA_COHERENT is returned 355 * if CCI is enabled, so check for DEV_DMA_COHERENT. 356 */ 357 attr = device_get_dma_attr(dev); 358 cevapriv->is_cci_enabled = (attr == DEV_DMA_COHERENT); 359 360 hpriv->plat_data = cevapriv; 361 362 /* CEVA specific initialization */ 363 ahci_ceva_setup(hpriv); 364 365 rc = ahci_platform_init_host(pdev, hpriv, &ahci_ceva_port_info, 366 &ahci_platform_sht); 367 if (rc) 368 goto disable_resources; 369 370 return 0; 371 372 disable_resources: 373 ahci_platform_disable_resources(hpriv); 374 return rc; 375 } 376 377 static int __maybe_unused ceva_ahci_suspend(struct device *dev) 378 { 379 return ahci_platform_suspend(dev); 380 } 381 382 static int __maybe_unused ceva_ahci_resume(struct device *dev) 383 { 384 struct ata_host *host = dev_get_drvdata(dev); 385 struct ahci_host_priv *hpriv = host->private_data; 386 int rc; 387 388 rc = ceva_ahci_platform_enable_resources(hpriv); 389 if (rc) 390 return rc; 391 392 /* Configure CEVA specific config before resuming HBA */ 393 ahci_ceva_setup(hpriv); 394 395 rc = ahci_platform_resume_host(dev); 396 if (rc) 397 goto disable_resources; 398 399 /* We resumed so update PM runtime state */ 400 pm_runtime_disable(dev); 401 pm_runtime_set_active(dev); 402 pm_runtime_enable(dev); 403 404 return 0; 405 406 disable_resources: 407 ahci_platform_disable_resources(hpriv); 408 409 return rc; 410 } 411 412 static SIMPLE_DEV_PM_OPS(ahci_ceva_pm_ops, ceva_ahci_suspend, ceva_ahci_resume); 413 414 static const struct of_device_id ceva_ahci_of_match[] = { 415 { .compatible = "ceva,ahci-1v84" }, 416 { /* sentinel */ } 417 }; 418 MODULE_DEVICE_TABLE(of, ceva_ahci_of_match); 419 420 static struct platform_driver ceva_ahci_driver = { 421 .probe = ceva_ahci_probe, 422 .remove = ata_platform_remove_one, 423 .driver = { 424 .name = DRV_NAME, 425 .of_match_table = ceva_ahci_of_match, 426 .pm = &ahci_ceva_pm_ops, 427 }, 428 }; 429 module_platform_driver(ceva_ahci_driver); 430 431 MODULE_DESCRIPTION("CEVA AHCI SATA platform driver"); 432 MODULE_AUTHOR("Xilinx Inc."); 433 MODULE_LICENSE("GPL v2"); 434