1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/module.h>
26 #include <linux/slab.h>
27
28 #include "hwmgr.h"
29 #include "amd_powerplay.h"
30 #include "vega20_smumgr.h"
31 #include "hardwaremanager.h"
32 #include "ppatomfwctrl.h"
33 #include "atomfirmware.h"
34 #include "cgs_common.h"
35 #include "vega20_powertune.h"
36 #include "vega20_inc.h"
37 #include "pppcielanes.h"
38 #include "vega20_hwmgr.h"
39 #include "vega20_processpptables.h"
40 #include "vega20_pptable.h"
41 #include "vega20_thermal.h"
42 #include "vega20_ppsmc.h"
43 #include "pp_debug.h"
44 #include "amd_pcie_helpers.h"
45 #include "ppinterrupt.h"
46 #include "pp_overdriver.h"
47 #include "pp_thermal.h"
48 #include "soc15_common.h"
49 #include "vega20_baco.h"
50 #include "smuio/smuio_9_0_offset.h"
51 #include "smuio/smuio_9_0_sh_mask.h"
52 #include "nbio/nbio_7_4_sh_mask.h"
53
54 #define smnPCIE_LC_SPEED_CNTL 0x11140290
55 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
56
57 #define LINK_WIDTH_MAX 6
58 #define LINK_SPEED_MAX 3
59 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
60 static const int link_speed[] = {25, 50, 80, 160};
61
vega20_set_default_registry_data(struct pp_hwmgr * hwmgr)62 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
63 {
64 struct vega20_hwmgr *data =
65 (struct vega20_hwmgr *)(hwmgr->backend);
66
67 data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT;
68 data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT;
69 data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT;
70 data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT;
71 data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT;
72
73 data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT;
74 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
75 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
76 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
77 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
78 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
79 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
80 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
81 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
82 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
83 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
84 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
85 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
86
87 /*
88 * Disable the following features for now:
89 * GFXCLK DS
90 * SOCLK DS
91 * LCLK DS
92 * DCEFCLK DS
93 * FCLK DS
94 * MP1CLK DS
95 * MP0CLK DS
96 */
97 data->registry_data.disallowed_features = 0xE0041C00;
98 /* ECC feature should be disabled on old SMUs */
99 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion, &hwmgr->smu_version);
100 if (hwmgr->smu_version < 0x282100)
101 data->registry_data.disallowed_features |= FEATURE_ECC_MASK;
102
103 if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK))
104 data->registry_data.disallowed_features |= FEATURE_DPM_LINK_MASK;
105
106 if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK))
107 data->registry_data.disallowed_features |= FEATURE_DPM_GFXCLK_MASK;
108
109 if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK))
110 data->registry_data.disallowed_features |= FEATURE_DPM_SOCCLK_MASK;
111
112 if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK))
113 data->registry_data.disallowed_features |= FEATURE_DPM_UCLK_MASK;
114
115 if (!(hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK))
116 data->registry_data.disallowed_features |= FEATURE_DPM_DCEFCLK_MASK;
117
118 if (!(hwmgr->feature_mask & PP_ULV_MASK))
119 data->registry_data.disallowed_features |= FEATURE_ULV_MASK;
120
121 if (!(hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK))
122 data->registry_data.disallowed_features |= FEATURE_DS_GFXCLK_MASK;
123
124 data->registry_data.od_state_in_dc_support = 0;
125 data->registry_data.thermal_support = 1;
126 data->registry_data.skip_baco_hardware = 0;
127
128 data->registry_data.log_avfs_param = 0;
129 data->registry_data.sclk_throttle_low_notification = 1;
130 data->registry_data.force_dpm_high = 0;
131 data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
132
133 data->registry_data.didt_support = 0;
134 if (data->registry_data.didt_support) {
135 data->registry_data.didt_mode = 6;
136 data->registry_data.sq_ramping_support = 1;
137 data->registry_data.db_ramping_support = 0;
138 data->registry_data.td_ramping_support = 0;
139 data->registry_data.tcp_ramping_support = 0;
140 data->registry_data.dbr_ramping_support = 0;
141 data->registry_data.edc_didt_support = 1;
142 data->registry_data.gc_didt_support = 0;
143 data->registry_data.psm_didt_support = 0;
144 }
145
146 data->registry_data.pcie_lane_override = 0xff;
147 data->registry_data.pcie_speed_override = 0xff;
148 data->registry_data.pcie_clock_override = 0xffffffff;
149 data->registry_data.regulator_hot_gpio_support = 1;
150 data->registry_data.ac_dc_switch_gpio_support = 0;
151 data->registry_data.quick_transition_support = 0;
152 data->registry_data.zrpm_start_temp = 0xffff;
153 data->registry_data.zrpm_stop_temp = 0xffff;
154 data->registry_data.od8_feature_enable = 1;
155 data->registry_data.disable_water_mark = 0;
156 data->registry_data.disable_pp_tuning = 0;
157 data->registry_data.disable_xlpp_tuning = 0;
158 data->registry_data.disable_workload_policy = 0;
159 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
160 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
161 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
162 data->registry_data.force_workload_policy_mask = 0;
163 data->registry_data.disable_3d_fs_detection = 0;
164 data->registry_data.fps_support = 1;
165 data->registry_data.disable_auto_wattman = 1;
166 data->registry_data.auto_wattman_debug = 0;
167 data->registry_data.auto_wattman_sample_period = 100;
168 data->registry_data.fclk_gfxclk_ratio = 0;
169 data->registry_data.auto_wattman_threshold = 50;
170 data->registry_data.gfxoff_controlled_by_driver = 1;
171 data->gfxoff_allowed = false;
172 data->counter_gfxoff = 0;
173 data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
174 }
175
vega20_set_features_platform_caps(struct pp_hwmgr * hwmgr)176 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
177 {
178 struct vega20_hwmgr *data =
179 (struct vega20_hwmgr *)(hwmgr->backend);
180 struct amdgpu_device *adev = hwmgr->adev;
181
182 if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE)
183 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
184 PHM_PlatformCaps_ControlVDDCI);
185
186 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
187 PHM_PlatformCaps_TablelessHardwareInterface);
188
189 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
190 PHM_PlatformCaps_BACO);
191
192 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
193 PHM_PlatformCaps_EnableSMU7ThermalManagement);
194
195 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
196 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
197 PHM_PlatformCaps_UVDPowerGating);
198
199 if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
200 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
201 PHM_PlatformCaps_VCEPowerGating);
202
203 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
204 PHM_PlatformCaps_UnTabledHardwareInterface);
205
206 if (data->registry_data.od8_feature_enable)
207 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
208 PHM_PlatformCaps_OD8inACSupport);
209
210 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
211 PHM_PlatformCaps_ActivityReporting);
212 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
213 PHM_PlatformCaps_FanSpeedInTableIsRPM);
214
215 if (data->registry_data.od_state_in_dc_support) {
216 if (data->registry_data.od8_feature_enable)
217 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
218 PHM_PlatformCaps_OD8inDCSupport);
219 }
220
221 if (data->registry_data.thermal_support &&
222 data->registry_data.fuzzy_fan_control_support &&
223 hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
224 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
225 PHM_PlatformCaps_ODFuzzyFanControlSupport);
226
227 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
228 PHM_PlatformCaps_DynamicPowerManagement);
229 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
230 PHM_PlatformCaps_SMC);
231 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
232 PHM_PlatformCaps_ThermalPolicyDelay);
233
234 if (data->registry_data.force_dpm_high)
235 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
236 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
237
238 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
239 PHM_PlatformCaps_DynamicUVDState);
240
241 if (data->registry_data.sclk_throttle_low_notification)
242 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
243 PHM_PlatformCaps_SclkThrottleLowNotification);
244
245 /* power tune caps */
246 /* assume disabled */
247 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
248 PHM_PlatformCaps_PowerContainment);
249 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
250 PHM_PlatformCaps_DiDtSupport);
251 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
252 PHM_PlatformCaps_SQRamping);
253 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
254 PHM_PlatformCaps_DBRamping);
255 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
256 PHM_PlatformCaps_TDRamping);
257 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
258 PHM_PlatformCaps_TCPRamping);
259 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
260 PHM_PlatformCaps_DBRRamping);
261 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
262 PHM_PlatformCaps_DiDtEDCEnable);
263 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
264 PHM_PlatformCaps_GCEDC);
265 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
266 PHM_PlatformCaps_PSM);
267
268 if (data->registry_data.didt_support) {
269 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
270 PHM_PlatformCaps_DiDtSupport);
271 if (data->registry_data.sq_ramping_support)
272 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
273 PHM_PlatformCaps_SQRamping);
274 if (data->registry_data.db_ramping_support)
275 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
276 PHM_PlatformCaps_DBRamping);
277 if (data->registry_data.td_ramping_support)
278 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
279 PHM_PlatformCaps_TDRamping);
280 if (data->registry_data.tcp_ramping_support)
281 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
282 PHM_PlatformCaps_TCPRamping);
283 if (data->registry_data.dbr_ramping_support)
284 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
285 PHM_PlatformCaps_DBRRamping);
286 if (data->registry_data.edc_didt_support)
287 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
288 PHM_PlatformCaps_DiDtEDCEnable);
289 if (data->registry_data.gc_didt_support)
290 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
291 PHM_PlatformCaps_GCEDC);
292 if (data->registry_data.psm_didt_support)
293 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
294 PHM_PlatformCaps_PSM);
295 }
296
297 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
298 PHM_PlatformCaps_RegulatorHot);
299
300 if (data->registry_data.ac_dc_switch_gpio_support) {
301 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
302 PHM_PlatformCaps_AutomaticDCTransition);
303 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
304 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
305 }
306
307 if (data->registry_data.quick_transition_support) {
308 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
309 PHM_PlatformCaps_AutomaticDCTransition);
310 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
311 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
312 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
313 PHM_PlatformCaps_Falcon_QuickTransition);
314 }
315
316 if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) {
317 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
318 PHM_PlatformCaps_LowestUclkReservedForUlv);
319 if (data->lowest_uclk_reserved_for_ulv == 1)
320 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
321 PHM_PlatformCaps_LowestUclkReservedForUlv);
322 }
323
324 if (data->registry_data.custom_fan_support)
325 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
326 PHM_PlatformCaps_CustomFanControlSupport);
327
328 return 0;
329 }
330
vega20_init_dpm_defaults(struct pp_hwmgr * hwmgr)331 static int vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
332 {
333 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
334 struct amdgpu_device *adev = hwmgr->adev;
335 uint32_t top32, bottom32;
336 int i, ret;
337
338 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
339 FEATURE_DPM_PREFETCHER_BIT;
340 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
341 FEATURE_DPM_GFXCLK_BIT;
342 data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
343 FEATURE_DPM_UCLK_BIT;
344 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
345 FEATURE_DPM_SOCCLK_BIT;
346 data->smu_features[GNLD_DPM_UVD].smu_feature_id =
347 FEATURE_DPM_UVD_BIT;
348 data->smu_features[GNLD_DPM_VCE].smu_feature_id =
349 FEATURE_DPM_VCE_BIT;
350 data->smu_features[GNLD_ULV].smu_feature_id =
351 FEATURE_ULV_BIT;
352 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
353 FEATURE_DPM_MP0CLK_BIT;
354 data->smu_features[GNLD_DPM_LINK].smu_feature_id =
355 FEATURE_DPM_LINK_BIT;
356 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
357 FEATURE_DPM_DCEFCLK_BIT;
358 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
359 FEATURE_DS_GFXCLK_BIT;
360 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
361 FEATURE_DS_SOCCLK_BIT;
362 data->smu_features[GNLD_DS_LCLK].smu_feature_id =
363 FEATURE_DS_LCLK_BIT;
364 data->smu_features[GNLD_PPT].smu_feature_id =
365 FEATURE_PPT_BIT;
366 data->smu_features[GNLD_TDC].smu_feature_id =
367 FEATURE_TDC_BIT;
368 data->smu_features[GNLD_THERMAL].smu_feature_id =
369 FEATURE_THERMAL_BIT;
370 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
371 FEATURE_GFX_PER_CU_CG_BIT;
372 data->smu_features[GNLD_RM].smu_feature_id =
373 FEATURE_RM_BIT;
374 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
375 FEATURE_DS_DCEFCLK_BIT;
376 data->smu_features[GNLD_ACDC].smu_feature_id =
377 FEATURE_ACDC_BIT;
378 data->smu_features[GNLD_VR0HOT].smu_feature_id =
379 FEATURE_VR0HOT_BIT;
380 data->smu_features[GNLD_VR1HOT].smu_feature_id =
381 FEATURE_VR1HOT_BIT;
382 data->smu_features[GNLD_FW_CTF].smu_feature_id =
383 FEATURE_FW_CTF_BIT;
384 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
385 FEATURE_LED_DISPLAY_BIT;
386 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
387 FEATURE_FAN_CONTROL_BIT;
388 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
389 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
390 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
391 data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT;
392 data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT;
393 data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
394 data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
395 data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
396 data->smu_features[GNLD_ECC].smu_feature_id = FEATURE_ECC_BIT;
397
398 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
399 data->smu_features[i].smu_feature_bitmap =
400 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
401 data->smu_features[i].allowed =
402 ((data->registry_data.disallowed_features >> i) & 1) ?
403 false : true;
404 }
405
406 /* Get the SN to turn into a Unique ID */
407 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
408 if (ret)
409 return ret;
410
411 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
412 if (ret)
413 return ret;
414
415 adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
416
417 return 0;
418 }
419
vega20_set_private_data_based_on_pptable(struct pp_hwmgr * hwmgr)420 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
421 {
422 return 0;
423 }
424
vega20_hwmgr_backend_fini(struct pp_hwmgr * hwmgr)425 static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
426 {
427 kfree(hwmgr->backend);
428 hwmgr->backend = NULL;
429
430 return 0;
431 }
432
vega20_hwmgr_backend_init(struct pp_hwmgr * hwmgr)433 static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
434 {
435 struct vega20_hwmgr *data;
436 struct amdgpu_device *adev = hwmgr->adev;
437 int result;
438
439 data = kzalloc_obj(struct vega20_hwmgr);
440 if (data == NULL)
441 return -ENOMEM;
442
443 hwmgr->backend = data;
444
445 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
446 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
447 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
448
449 vega20_set_default_registry_data(hwmgr);
450
451 data->disable_dpm_mask = 0xff;
452
453 /* need to set voltage control types before EVV patching */
454 data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE;
455 data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE;
456 data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE;
457
458 data->water_marks_bitmap = 0;
459 data->avfs_exist = false;
460
461 vega20_set_features_platform_caps(hwmgr);
462
463 result = vega20_init_dpm_defaults(hwmgr);
464 if (result) {
465 pr_err("%s failed\n", __func__);
466 return result;
467 }
468 /* Parse pptable data read from VBIOS */
469 vega20_set_private_data_based_on_pptable(hwmgr);
470
471 data->is_tlu_enabled = false;
472
473 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
474 VEGA20_MAX_HARDWARE_POWERLEVELS;
475 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
476 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
477
478 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
479 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
480 hwmgr->platform_descriptor.clockStep.engineClock = 500;
481 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
482
483 data->total_active_cus = adev->gfx.cu_info.number;
484 data->is_custom_profile_set = false;
485
486 return 0;
487 }
488
vega20_init_sclk_threshold(struct pp_hwmgr * hwmgr)489 static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr)
490 {
491 struct vega20_hwmgr *data =
492 (struct vega20_hwmgr *)(hwmgr->backend);
493
494 data->low_sclk_interrupt_threshold = 0;
495
496 return 0;
497 }
498
vega20_setup_asic_task(struct pp_hwmgr * hwmgr)499 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
500 {
501 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
502 int ret = 0;
503 bool use_baco = (amdgpu_in_reset(adev) &&
504 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
505 (adev->in_runpm && amdgpu_asic_supports_baco(adev));
506
507 ret = vega20_init_sclk_threshold(hwmgr);
508 PP_ASSERT_WITH_CODE(!ret,
509 "Failed to init sclk threshold!",
510 return ret);
511
512 if (use_baco) {
513 ret = vega20_baco_apply_vdci_flush_workaround(hwmgr);
514 if (ret)
515 pr_err("Failed to apply vega20 baco workaround!\n");
516 }
517
518 return ret;
519 }
520
521 /*
522 * @fn vega20_init_dpm_state
523 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
524 *
525 * @param dpm_state - the address of the DPM Table to initiailize.
526 * @return None.
527 */
vega20_init_dpm_state(struct vega20_dpm_state * dpm_state)528 static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state)
529 {
530 dpm_state->soft_min_level = 0x0;
531 dpm_state->soft_max_level = VG20_CLOCK_MAX_DEFAULT;
532 dpm_state->hard_min_level = 0x0;
533 dpm_state->hard_max_level = VG20_CLOCK_MAX_DEFAULT;
534 }
535
vega20_get_number_of_dpm_level(struct pp_hwmgr * hwmgr,PPCLK_e clk_id,uint32_t * num_of_levels)536 static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
537 PPCLK_e clk_id, uint32_t *num_of_levels)
538 {
539 int ret = 0;
540
541 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
542 PPSMC_MSG_GetDpmFreqByIndex,
543 (clk_id << 16 | 0xFF),
544 num_of_levels);
545 PP_ASSERT_WITH_CODE(!ret,
546 "[GetNumOfDpmLevel] failed to get dpm levels!",
547 return ret);
548
549 return ret;
550 }
551
vega20_get_dpm_frequency_by_index(struct pp_hwmgr * hwmgr,PPCLK_e clk_id,uint32_t index,uint32_t * clk)552 static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
553 PPCLK_e clk_id, uint32_t index, uint32_t *clk)
554 {
555 int ret = 0;
556
557 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
558 PPSMC_MSG_GetDpmFreqByIndex,
559 (clk_id << 16 | index),
560 clk);
561 PP_ASSERT_WITH_CODE(!ret,
562 "[GetDpmFreqByIndex] failed to get dpm freq by index!",
563 return ret);
564
565 return ret;
566 }
567
vega20_setup_single_dpm_table(struct pp_hwmgr * hwmgr,struct vega20_single_dpm_table * dpm_table,PPCLK_e clk_id)568 static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
569 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id)
570 {
571 int ret = 0;
572 uint32_t i, num_of_levels, clk;
573
574 ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
575 PP_ASSERT_WITH_CODE(!ret,
576 "[SetupSingleDpmTable] failed to get clk levels!",
577 return ret);
578
579 dpm_table->count = num_of_levels;
580
581 for (i = 0; i < num_of_levels; i++) {
582 ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
583 PP_ASSERT_WITH_CODE(!ret,
584 "[SetupSingleDpmTable] failed to get clk of specific level!",
585 return ret);
586 dpm_table->dpm_levels[i].value = clk;
587 dpm_table->dpm_levels[i].enabled = true;
588 }
589
590 return ret;
591 }
592
vega20_setup_gfxclk_dpm_table(struct pp_hwmgr * hwmgr)593 static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr)
594 {
595 struct vega20_hwmgr *data =
596 (struct vega20_hwmgr *)(hwmgr->backend);
597 struct vega20_single_dpm_table *dpm_table;
598 int ret = 0;
599
600 dpm_table = &(data->dpm_table.gfx_table);
601 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
602 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
603 PP_ASSERT_WITH_CODE(!ret,
604 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
605 return ret);
606 } else {
607 dpm_table->count = 1;
608 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
609 }
610
611 return ret;
612 }
613
vega20_setup_memclk_dpm_table(struct pp_hwmgr * hwmgr)614 static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr)
615 {
616 struct vega20_hwmgr *data =
617 (struct vega20_hwmgr *)(hwmgr->backend);
618 struct vega20_single_dpm_table *dpm_table;
619 int ret = 0;
620
621 dpm_table = &(data->dpm_table.mem_table);
622 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
623 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
624 PP_ASSERT_WITH_CODE(!ret,
625 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
626 return ret);
627 } else {
628 dpm_table->count = 1;
629 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
630 }
631
632 return ret;
633 }
634
635 /*
636 * This function is to initialize all DPM state tables
637 * for SMU based on the dependency table.
638 * Dynamic state patching function will then trim these
639 * state tables to the allowed range based
640 * on the power policy or external client requests,
641 * such as UVD request, etc.
642 */
vega20_setup_default_dpm_tables(struct pp_hwmgr * hwmgr)643 static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
644 {
645 struct vega20_hwmgr *data =
646 (struct vega20_hwmgr *)(hwmgr->backend);
647 struct vega20_single_dpm_table *dpm_table;
648 int ret = 0;
649
650 memset(&data->dpm_table, 0, sizeof(data->dpm_table));
651
652 /* socclk */
653 dpm_table = &(data->dpm_table.soc_table);
654 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
655 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
656 PP_ASSERT_WITH_CODE(!ret,
657 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
658 return ret);
659 } else {
660 dpm_table->count = 1;
661 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
662 }
663 vega20_init_dpm_state(&(dpm_table->dpm_state));
664
665 /* gfxclk */
666 dpm_table = &(data->dpm_table.gfx_table);
667 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
668 if (ret)
669 return ret;
670 vega20_init_dpm_state(&(dpm_table->dpm_state));
671
672 /* memclk */
673 dpm_table = &(data->dpm_table.mem_table);
674 ret = vega20_setup_memclk_dpm_table(hwmgr);
675 if (ret)
676 return ret;
677 vega20_init_dpm_state(&(dpm_table->dpm_state));
678
679 /* eclk */
680 dpm_table = &(data->dpm_table.eclk_table);
681 if (data->smu_features[GNLD_DPM_VCE].enabled) {
682 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
683 PP_ASSERT_WITH_CODE(!ret,
684 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
685 return ret);
686 } else {
687 dpm_table->count = 1;
688 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
689 }
690 vega20_init_dpm_state(&(dpm_table->dpm_state));
691
692 /* vclk */
693 dpm_table = &(data->dpm_table.vclk_table);
694 if (data->smu_features[GNLD_DPM_UVD].enabled) {
695 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
696 PP_ASSERT_WITH_CODE(!ret,
697 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
698 return ret);
699 } else {
700 dpm_table->count = 1;
701 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
702 }
703 vega20_init_dpm_state(&(dpm_table->dpm_state));
704
705 /* dclk */
706 dpm_table = &(data->dpm_table.dclk_table);
707 if (data->smu_features[GNLD_DPM_UVD].enabled) {
708 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
709 PP_ASSERT_WITH_CODE(!ret,
710 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
711 return ret);
712 } else {
713 dpm_table->count = 1;
714 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
715 }
716 vega20_init_dpm_state(&(dpm_table->dpm_state));
717
718 /* dcefclk */
719 dpm_table = &(data->dpm_table.dcef_table);
720 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
721 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
722 PP_ASSERT_WITH_CODE(!ret,
723 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
724 return ret);
725 } else {
726 dpm_table->count = 1;
727 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
728 }
729 vega20_init_dpm_state(&(dpm_table->dpm_state));
730
731 /* pixclk */
732 dpm_table = &(data->dpm_table.pixel_table);
733 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
734 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
735 PP_ASSERT_WITH_CODE(!ret,
736 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
737 return ret);
738 } else
739 dpm_table->count = 0;
740 vega20_init_dpm_state(&(dpm_table->dpm_state));
741
742 /* dispclk */
743 dpm_table = &(data->dpm_table.display_table);
744 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
745 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
746 PP_ASSERT_WITH_CODE(!ret,
747 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
748 return ret);
749 } else
750 dpm_table->count = 0;
751 vega20_init_dpm_state(&(dpm_table->dpm_state));
752
753 /* phyclk */
754 dpm_table = &(data->dpm_table.phy_table);
755 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
756 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
757 PP_ASSERT_WITH_CODE(!ret,
758 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
759 return ret);
760 } else
761 dpm_table->count = 0;
762 vega20_init_dpm_state(&(dpm_table->dpm_state));
763
764 /* fclk */
765 dpm_table = &(data->dpm_table.fclk_table);
766 if (data->smu_features[GNLD_DPM_FCLK].enabled) {
767 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
768 PP_ASSERT_WITH_CODE(!ret,
769 "[SetupDefaultDpmTable] failed to get fclk dpm levels!",
770 return ret);
771 } else {
772 dpm_table->count = 1;
773 dpm_table->dpm_levels[0].value = data->vbios_boot_state.fclock / 100;
774 }
775 vega20_init_dpm_state(&(dpm_table->dpm_state));
776
777 /* save a copy of the default DPM table */
778 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
779 sizeof(struct vega20_dpm_table));
780
781 return 0;
782 }
783
784 /**
785 * vega20_init_smc_table - Initializes the SMC table and uploads it
786 *
787 * @hwmgr: the address of the powerplay hardware manager.
788 * return: always 0
789 */
vega20_init_smc_table(struct pp_hwmgr * hwmgr)790 static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
791 {
792 int result;
793 struct vega20_hwmgr *data =
794 (struct vega20_hwmgr *)(hwmgr->backend);
795 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
796 struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
797 struct phm_ppt_v3_information *pptable_information =
798 (struct phm_ppt_v3_information *)hwmgr->pptable;
799
800 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
801 PP_ASSERT_WITH_CODE(!result,
802 "[InitSMCTable] Failed to get vbios bootup values!",
803 return result);
804
805 data->vbios_boot_state.vddc = boot_up_values.usVddc;
806 data->vbios_boot_state.vddci = boot_up_values.usVddci;
807 data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
808 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
809 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
810 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
811 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
812 data->vbios_boot_state.eclock = boot_up_values.ulEClk;
813 data->vbios_boot_state.vclock = boot_up_values.ulVClk;
814 data->vbios_boot_state.dclock = boot_up_values.ulDClk;
815 data->vbios_boot_state.fclock = boot_up_values.ulFClk;
816 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
817
818 smum_send_msg_to_smc_with_parameter(hwmgr,
819 PPSMC_MSG_SetMinDeepSleepDcefclk,
820 (uint32_t)(data->vbios_boot_state.dcef_clock / 100),
821 NULL);
822
823 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
824
825 result = smum_smc_table_manager(hwmgr,
826 (uint8_t *)pp_table, TABLE_PPTABLE, false);
827 PP_ASSERT_WITH_CODE(!result,
828 "[InitSMCTable] Failed to upload PPtable!",
829 return result);
830
831 return 0;
832 }
833
834 /*
835 * Override PCIe link speed and link width for DPM Level 1. PPTable entries
836 * reflect the ASIC capabilities and not the system capabilities. For e.g.
837 * Vega20 board in a PCI Gen3 system. In this case, when SMU's tries to switch
838 * to DPM1, it fails as system doesn't support Gen4.
839 */
vega20_override_pcie_parameters(struct pp_hwmgr * hwmgr)840 static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr)
841 {
842 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
843 struct vega20_hwmgr *data =
844 (struct vega20_hwmgr *)(hwmgr->backend);
845 uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, pcie_width_arg;
846 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
847 int i;
848 int ret;
849
850 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
851 pcie_gen = 3;
852 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
853 pcie_gen = 2;
854 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
855 pcie_gen = 1;
856 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
857 pcie_gen = 0;
858
859 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
860 pcie_width = 6;
861 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
862 pcie_width = 5;
863 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
864 pcie_width = 4;
865 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
866 pcie_width = 3;
867 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
868 pcie_width = 2;
869 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
870 pcie_width = 1;
871
872 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
873 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
874 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
875 */
876 for (i = 0; i < NUM_LINK_LEVELS; i++) {
877 pcie_gen_arg = (pp_table->PcieGenSpeed[i] > pcie_gen) ? pcie_gen :
878 pp_table->PcieGenSpeed[i];
879 pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width :
880 pp_table->PcieLaneCount[i];
881
882 if (pcie_gen_arg != pp_table->PcieGenSpeed[i] || pcie_width_arg !=
883 pp_table->PcieLaneCount[i]) {
884 smu_pcie_arg = (i << 16) | (pcie_gen_arg << 8) | pcie_width_arg;
885 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
886 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,
887 NULL);
888 PP_ASSERT_WITH_CODE(!ret,
889 "[OverridePcieParameters] Attempt to override pcie params failed!",
890 return ret);
891 }
892
893 /* update the pptable */
894 pp_table->PcieGenSpeed[i] = pcie_gen_arg;
895 pp_table->PcieLaneCount[i] = pcie_width_arg;
896 }
897
898 /* override to the highest if it's disabled from ppfeaturmask */
899 if (data->registry_data.pcie_dpm_key_disabled) {
900 for (i = 0; i < NUM_LINK_LEVELS; i++) {
901 smu_pcie_arg = (i << 16) | (pcie_gen << 8) | pcie_width;
902 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
903 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,
904 NULL);
905 PP_ASSERT_WITH_CODE(!ret,
906 "[OverridePcieParameters] Attempt to override pcie params failed!",
907 return ret);
908
909 pp_table->PcieGenSpeed[i] = pcie_gen;
910 pp_table->PcieLaneCount[i] = pcie_width;
911 }
912 ret = vega20_enable_smc_features(hwmgr,
913 false,
914 data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap);
915 PP_ASSERT_WITH_CODE(!ret,
916 "Attempt to Disable DPM LINK Failed!",
917 return ret);
918 data->smu_features[GNLD_DPM_LINK].enabled = false;
919 data->smu_features[GNLD_DPM_LINK].supported = false;
920 }
921
922 return 0;
923 }
924
vega20_set_allowed_featuresmask(struct pp_hwmgr * hwmgr)925 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
926 {
927 struct vega20_hwmgr *data =
928 (struct vega20_hwmgr *)(hwmgr->backend);
929 uint32_t allowed_features_low = 0, allowed_features_high = 0;
930 int i;
931 int ret = 0;
932
933 for (i = 0; i < GNLD_FEATURES_MAX; i++)
934 if (data->smu_features[i].allowed)
935 data->smu_features[i].smu_feature_id > 31 ?
936 (allowed_features_high |=
937 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT)
938 & 0xFFFFFFFF)) :
939 (allowed_features_low |=
940 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT)
941 & 0xFFFFFFFF));
942
943 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
944 PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high, NULL);
945 PP_ASSERT_WITH_CODE(!ret,
946 "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!",
947 return ret);
948
949 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
950 PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low, NULL);
951 PP_ASSERT_WITH_CODE(!ret,
952 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
953 return ret);
954
955 return 0;
956 }
957
vega20_run_btc(struct pp_hwmgr * hwmgr)958 static int vega20_run_btc(struct pp_hwmgr *hwmgr)
959 {
960 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunBtc, NULL);
961 }
962
vega20_run_btc_afll(struct pp_hwmgr * hwmgr)963 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
964 {
965 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc, NULL);
966 }
967
vega20_enable_all_smu_features(struct pp_hwmgr * hwmgr)968 static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
969 {
970 struct vega20_hwmgr *data =
971 (struct vega20_hwmgr *)(hwmgr->backend);
972 uint64_t features_enabled;
973 int i;
974 bool enabled;
975 int ret = 0;
976
977 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
978 PPSMC_MSG_EnableAllSmuFeatures,
979 NULL)) == 0,
980 "[EnableAllSMUFeatures] Failed to enable all smu features!",
981 return ret);
982
983 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
984 PP_ASSERT_WITH_CODE(!ret,
985 "[EnableAllSmuFeatures] Failed to get enabled smc features!",
986 return ret);
987
988 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
989 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
990 true : false;
991 data->smu_features[i].enabled = enabled;
992 data->smu_features[i].supported = enabled;
993
994 #if 0
995 if (data->smu_features[i].allowed && !enabled)
996 pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);
997 else if (!data->smu_features[i].allowed && enabled)
998 pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);
999 #endif
1000 }
1001
1002 return 0;
1003 }
1004
vega20_notify_smc_display_change(struct pp_hwmgr * hwmgr)1005 static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
1006 {
1007 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1008
1009 if (data->smu_features[GNLD_DPM_UCLK].enabled)
1010 return smum_send_msg_to_smc_with_parameter(hwmgr,
1011 PPSMC_MSG_SetUclkFastSwitch,
1012 1,
1013 NULL);
1014
1015 return 0;
1016 }
1017
vega20_send_clock_ratio(struct pp_hwmgr * hwmgr)1018 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
1019 {
1020 struct vega20_hwmgr *data =
1021 (struct vega20_hwmgr *)(hwmgr->backend);
1022
1023 return smum_send_msg_to_smc_with_parameter(hwmgr,
1024 PPSMC_MSG_SetFclkGfxClkRatio,
1025 data->registry_data.fclk_gfxclk_ratio,
1026 NULL);
1027 }
1028
vega20_disable_all_smu_features(struct pp_hwmgr * hwmgr)1029 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
1030 {
1031 struct vega20_hwmgr *data =
1032 (struct vega20_hwmgr *)(hwmgr->backend);
1033 int i, ret = 0;
1034
1035 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
1036 PPSMC_MSG_DisableAllSmuFeatures,
1037 NULL)) == 0,
1038 "[DisableAllSMUFeatures] Failed to disable all smu features!",
1039 return ret);
1040
1041 for (i = 0; i < GNLD_FEATURES_MAX; i++)
1042 data->smu_features[i].enabled = 0;
1043
1044 return 0;
1045 }
1046
vega20_od8_set_feature_capabilities(struct pp_hwmgr * hwmgr)1047 static int vega20_od8_set_feature_capabilities(
1048 struct pp_hwmgr *hwmgr)
1049 {
1050 struct phm_ppt_v3_information *pptable_information =
1051 (struct phm_ppt_v3_information *)hwmgr->pptable;
1052 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1053 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1054 struct vega20_od8_settings *od_settings = &(data->od8_settings);
1055
1056 od_settings->overdrive8_capabilities = 0;
1057
1058 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1059 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
1060 pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
1061 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
1062 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
1063 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN]))
1064 od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS;
1065
1066 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
1067 (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
1068 pp_table->MinVoltageGfx / VOLTAGE_SCALE) &&
1069 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
1070 pp_table->MaxVoltageGfx / VOLTAGE_SCALE) &&
1071 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >=
1072 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1]))
1073 od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE;
1074 }
1075
1076 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1077 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] =
1078 data->dpm_table.mem_table.dpm_levels[data->dpm_table.mem_table.count - 2].value;
1079 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1080 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1081 pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1082 (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1083 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX]))
1084 od_settings->overdrive8_capabilities |= OD8_UCLK_MAX;
1085 }
1086
1087 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1088 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1089 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1090 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1091 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100)
1092 od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT;
1093
1094 if (data->smu_features[GNLD_FAN_CONTROL].enabled) {
1095 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1096 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1097 pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1098 (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1099 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT]))
1100 od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK;
1101
1102 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1103 (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >=
1104 (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) &&
1105 pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1106 (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1107 pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED]))
1108 od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN;
1109 }
1110
1111 if (data->smu_features[GNLD_THERMAL].enabled) {
1112 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1113 pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1114 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1115 (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1116 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP]))
1117 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN;
1118
1119 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1120 pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1121 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1122 (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1123 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX]))
1124 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM;
1125 }
1126
1127 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE])
1128 od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE;
1129
1130 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] &&
1131 pp_table->FanZeroRpmEnable)
1132 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
1133
1134 if (!od_settings->overdrive8_capabilities)
1135 hwmgr->od_enabled = false;
1136
1137 return 0;
1138 }
1139
vega20_od8_set_feature_id(struct pp_hwmgr * hwmgr)1140 static int vega20_od8_set_feature_id(
1141 struct pp_hwmgr *hwmgr)
1142 {
1143 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1144 struct vega20_od8_settings *od_settings = &(data->od8_settings);
1145
1146 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1147 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1148 OD8_GFXCLK_LIMITS;
1149 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1150 OD8_GFXCLK_LIMITS;
1151 } else {
1152 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1153 0;
1154 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1155 0;
1156 }
1157
1158 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1159 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1160 OD8_GFXCLK_CURVE;
1161 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1162 OD8_GFXCLK_CURVE;
1163 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1164 OD8_GFXCLK_CURVE;
1165 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1166 OD8_GFXCLK_CURVE;
1167 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1168 OD8_GFXCLK_CURVE;
1169 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1170 OD8_GFXCLK_CURVE;
1171 } else {
1172 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1173 0;
1174 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1175 0;
1176 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1177 0;
1178 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1179 0;
1180 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1181 0;
1182 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1183 0;
1184 }
1185
1186 if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1187 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX;
1188 else
1189 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0;
1190
1191 if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1192 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT;
1193 else
1194 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0;
1195
1196 if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1197 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1198 OD8_ACOUSTIC_LIMIT_SCLK;
1199 else
1200 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1201 0;
1202
1203 if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1204 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1205 OD8_FAN_SPEED_MIN;
1206 else
1207 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1208 0;
1209
1210 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1211 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1212 OD8_TEMPERATURE_FAN;
1213 else
1214 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1215 0;
1216
1217 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1218 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1219 OD8_TEMPERATURE_SYSTEM;
1220 else
1221 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1222 0;
1223
1224 return 0;
1225 }
1226
vega20_od8_get_gfx_clock_base_voltage(struct pp_hwmgr * hwmgr,uint32_t * voltage,uint32_t freq)1227 static int vega20_od8_get_gfx_clock_base_voltage(
1228 struct pp_hwmgr *hwmgr,
1229 uint32_t *voltage,
1230 uint32_t freq)
1231 {
1232 int ret = 0;
1233
1234 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1235 PPSMC_MSG_GetAVFSVoltageByDpm,
1236 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq),
1237 voltage);
1238 PP_ASSERT_WITH_CODE(!ret,
1239 "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!",
1240 return ret);
1241
1242 *voltage = *voltage / VOLTAGE_SCALE;
1243
1244 return 0;
1245 }
1246
vega20_od8_initialize_default_settings(struct pp_hwmgr * hwmgr)1247 static int vega20_od8_initialize_default_settings(
1248 struct pp_hwmgr *hwmgr)
1249 {
1250 struct phm_ppt_v3_information *pptable_information =
1251 (struct phm_ppt_v3_information *)hwmgr->pptable;
1252 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1253 struct vega20_od8_settings *od8_settings = &(data->od8_settings);
1254 OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1255 int i, ret = 0;
1256
1257 /* Set Feature Capabilities */
1258 vega20_od8_set_feature_capabilities(hwmgr);
1259
1260 /* Map FeatureID to individual settings */
1261 vega20_od8_set_feature_id(hwmgr);
1262
1263 /* Set default values */
1264 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
1265 PP_ASSERT_WITH_CODE(!ret,
1266 "Failed to export over drive table!",
1267 return ret);
1268
1269 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1270 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1271 od_table->GfxclkFmin;
1272 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1273 od_table->GfxclkFmax;
1274 } else {
1275 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1276 0;
1277 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1278 0;
1279 }
1280
1281 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1282 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1283 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1284 od_table->GfxclkFreq1;
1285
1286 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1287 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1288 od_table->GfxclkFreq3;
1289
1290 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2;
1291 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1292 od_table->GfxclkFreq2;
1293
1294 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1295 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value),
1296 od_table->GfxclkFreq1),
1297 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1298 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0);
1299 od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1300 * VOLTAGE_SCALE;
1301
1302 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1303 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value),
1304 od_table->GfxclkFreq2),
1305 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1306 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0);
1307 od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1308 * VOLTAGE_SCALE;
1309
1310 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1311 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value),
1312 od_table->GfxclkFreq3),
1313 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1314 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0);
1315 od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1316 * VOLTAGE_SCALE;
1317 } else {
1318 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1319 0;
1320 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value =
1321 0;
1322 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1323 0;
1324 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value =
1325 0;
1326 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1327 0;
1328 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value =
1329 0;
1330 }
1331
1332 if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1333 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1334 od_table->UclkFmax;
1335 else
1336 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1337 0;
1338
1339 if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1340 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1341 od_table->OverDrivePct;
1342 else
1343 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1344 0;
1345
1346 if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1347 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1348 od_table->FanMaximumRpm;
1349 else
1350 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1351 0;
1352
1353 if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1354 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1355 od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
1356 else
1357 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1358 0;
1359
1360 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1361 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1362 od_table->FanTargetTemperature;
1363 else
1364 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1365 0;
1366
1367 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1368 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1369 od_table->MaxOpTemp;
1370 else
1371 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1372 0;
1373
1374 for (i = 0; i < OD8_SETTING_COUNT; i++) {
1375 if (od8_settings->od8_settings_array[i].feature_id) {
1376 od8_settings->od8_settings_array[i].min_value =
1377 pptable_information->od_settings_min[i];
1378 od8_settings->od8_settings_array[i].max_value =
1379 pptable_information->od_settings_max[i];
1380 od8_settings->od8_settings_array[i].current_value =
1381 od8_settings->od8_settings_array[i].default_value;
1382 } else {
1383 od8_settings->od8_settings_array[i].min_value =
1384 0;
1385 od8_settings->od8_settings_array[i].max_value =
1386 0;
1387 od8_settings->od8_settings_array[i].current_value =
1388 0;
1389 }
1390 }
1391
1392 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
1393 PP_ASSERT_WITH_CODE(!ret,
1394 "Failed to import over drive table!",
1395 return ret);
1396
1397 return 0;
1398 }
1399
vega20_od8_set_settings(struct pp_hwmgr * hwmgr,uint32_t index,uint32_t value)1400 static int vega20_od8_set_settings(
1401 struct pp_hwmgr *hwmgr,
1402 uint32_t index,
1403 uint32_t value)
1404 {
1405 OverDriveTable_t od_table;
1406 int ret = 0;
1407 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1408 struct vega20_od8_single_setting *od8_settings =
1409 data->od8_settings.od8_settings_array;
1410
1411 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
1412 PP_ASSERT_WITH_CODE(!ret,
1413 "Failed to export over drive table!",
1414 return ret);
1415
1416 switch (index) {
1417 case OD8_SETTING_GFXCLK_FMIN:
1418 od_table.GfxclkFmin = (uint16_t)value;
1419 break;
1420 case OD8_SETTING_GFXCLK_FMAX:
1421 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
1422 value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value)
1423 return -EINVAL;
1424
1425 od_table.GfxclkFmax = (uint16_t)value;
1426 break;
1427 case OD8_SETTING_GFXCLK_FREQ1:
1428 od_table.GfxclkFreq1 = (uint16_t)value;
1429 break;
1430 case OD8_SETTING_GFXCLK_VOLTAGE1:
1431 od_table.GfxclkVolt1 = (uint16_t)value;
1432 break;
1433 case OD8_SETTING_GFXCLK_FREQ2:
1434 od_table.GfxclkFreq2 = (uint16_t)value;
1435 break;
1436 case OD8_SETTING_GFXCLK_VOLTAGE2:
1437 od_table.GfxclkVolt2 = (uint16_t)value;
1438 break;
1439 case OD8_SETTING_GFXCLK_FREQ3:
1440 od_table.GfxclkFreq3 = (uint16_t)value;
1441 break;
1442 case OD8_SETTING_GFXCLK_VOLTAGE3:
1443 od_table.GfxclkVolt3 = (uint16_t)value;
1444 break;
1445 case OD8_SETTING_UCLK_FMAX:
1446 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
1447 value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value)
1448 return -EINVAL;
1449 od_table.UclkFmax = (uint16_t)value;
1450 break;
1451 case OD8_SETTING_POWER_PERCENTAGE:
1452 od_table.OverDrivePct = (int16_t)value;
1453 break;
1454 case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
1455 od_table.FanMaximumRpm = (uint16_t)value;
1456 break;
1457 case OD8_SETTING_FAN_MIN_SPEED:
1458 od_table.FanMinimumPwm = (uint16_t)value;
1459 break;
1460 case OD8_SETTING_FAN_TARGET_TEMP:
1461 od_table.FanTargetTemperature = (uint16_t)value;
1462 break;
1463 case OD8_SETTING_OPERATING_TEMP_MAX:
1464 od_table.MaxOpTemp = (uint16_t)value;
1465 break;
1466 }
1467
1468 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
1469 PP_ASSERT_WITH_CODE(!ret,
1470 "Failed to import over drive table!",
1471 return ret);
1472
1473 return 0;
1474 }
1475
vega20_get_sclk_od(struct pp_hwmgr * hwmgr)1476 static int vega20_get_sclk_od(
1477 struct pp_hwmgr *hwmgr)
1478 {
1479 struct vega20_hwmgr *data = hwmgr->backend;
1480 struct vega20_single_dpm_table *sclk_table =
1481 &(data->dpm_table.gfx_table);
1482 struct vega20_single_dpm_table *golden_sclk_table =
1483 &(data->golden_dpm_table.gfx_table);
1484 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
1485 int golden_value = golden_sclk_table->dpm_levels
1486 [golden_sclk_table->count - 1].value;
1487
1488 /* od percentage */
1489 value -= golden_value;
1490 value = DIV_ROUND_UP(value * 100, golden_value);
1491
1492 return value;
1493 }
1494
vega20_set_sclk_od(struct pp_hwmgr * hwmgr,uint32_t value)1495 static int vega20_set_sclk_od(
1496 struct pp_hwmgr *hwmgr, uint32_t value)
1497 {
1498 struct vega20_hwmgr *data = hwmgr->backend;
1499 struct vega20_single_dpm_table *golden_sclk_table =
1500 &(data->golden_dpm_table.gfx_table);
1501 uint32_t od_sclk;
1502 int ret = 0;
1503
1504 od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
1505 od_sclk /= 100;
1506 od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
1507
1508 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
1509 PP_ASSERT_WITH_CODE(!ret,
1510 "[SetSclkOD] failed to set od gfxclk!",
1511 return ret);
1512
1513 /* retrieve updated gfxclk table */
1514 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
1515 PP_ASSERT_WITH_CODE(!ret,
1516 "[SetSclkOD] failed to refresh gfxclk table!",
1517 return ret);
1518
1519 return 0;
1520 }
1521
vega20_get_mclk_od(struct pp_hwmgr * hwmgr)1522 static int vega20_get_mclk_od(
1523 struct pp_hwmgr *hwmgr)
1524 {
1525 struct vega20_hwmgr *data = hwmgr->backend;
1526 struct vega20_single_dpm_table *mclk_table =
1527 &(data->dpm_table.mem_table);
1528 struct vega20_single_dpm_table *golden_mclk_table =
1529 &(data->golden_dpm_table.mem_table);
1530 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
1531 int golden_value = golden_mclk_table->dpm_levels
1532 [golden_mclk_table->count - 1].value;
1533
1534 /* od percentage */
1535 value -= golden_value;
1536 value = DIV_ROUND_UP(value * 100, golden_value);
1537
1538 return value;
1539 }
1540
vega20_set_mclk_od(struct pp_hwmgr * hwmgr,uint32_t value)1541 static int vega20_set_mclk_od(
1542 struct pp_hwmgr *hwmgr, uint32_t value)
1543 {
1544 struct vega20_hwmgr *data = hwmgr->backend;
1545 struct vega20_single_dpm_table *golden_mclk_table =
1546 &(data->golden_dpm_table.mem_table);
1547 uint32_t od_mclk;
1548 int ret = 0;
1549
1550 od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
1551 od_mclk /= 100;
1552 od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
1553
1554 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
1555 PP_ASSERT_WITH_CODE(!ret,
1556 "[SetMclkOD] failed to set od memclk!",
1557 return ret);
1558
1559 /* retrieve updated memclk table */
1560 ret = vega20_setup_memclk_dpm_table(hwmgr);
1561 PP_ASSERT_WITH_CODE(!ret,
1562 "[SetMclkOD] failed to refresh memclk table!",
1563 return ret);
1564
1565 return 0;
1566 }
1567
vega20_populate_umdpstate_clocks(struct pp_hwmgr * hwmgr)1568 static void vega20_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
1569 {
1570 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1571 struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
1572 struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
1573
1574 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1575 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
1576 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1577 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1578 } else {
1579 hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
1580 hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
1581 }
1582
1583 hwmgr->pstate_sclk_peak = gfx_table->dpm_levels[gfx_table->count - 1].value;
1584 hwmgr->pstate_mclk_peak = mem_table->dpm_levels[mem_table->count - 1].value;
1585 }
1586
vega20_get_max_sustainable_clock(struct pp_hwmgr * hwmgr,PP_Clock * clock,PPCLK_e clock_select)1587 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
1588 PP_Clock *clock, PPCLK_e clock_select)
1589 {
1590 int ret = 0;
1591
1592 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1593 PPSMC_MSG_GetDcModeMaxDpmFreq,
1594 (clock_select << 16),
1595 clock)) == 0,
1596 "[GetMaxSustainableClock] Failed to get max DC clock from SMC!",
1597 return ret);
1598
1599 /* if DC limit is zero, return AC limit */
1600 if (*clock == 0) {
1601 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1602 PPSMC_MSG_GetMaxDpmFreq,
1603 (clock_select << 16),
1604 clock)) == 0,
1605 "[GetMaxSustainableClock] failed to get max AC clock from SMC!",
1606 return ret);
1607 }
1608
1609 return 0;
1610 }
1611
vega20_init_max_sustainable_clocks(struct pp_hwmgr * hwmgr)1612 static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
1613 {
1614 struct vega20_hwmgr *data =
1615 (struct vega20_hwmgr *)(hwmgr->backend);
1616 struct vega20_max_sustainable_clocks *max_sustainable_clocks =
1617 &(data->max_sustainable_clocks);
1618 int ret = 0;
1619
1620 max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100;
1621 max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100;
1622 max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100;
1623 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
1624 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
1625 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
1626
1627 if (data->smu_features[GNLD_DPM_UCLK].enabled)
1628 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1629 &(max_sustainable_clocks->uclock),
1630 PPCLK_UCLK)) == 0,
1631 "[InitMaxSustainableClocks] failed to get max UCLK from SMC!",
1632 return ret);
1633
1634 if (data->smu_features[GNLD_DPM_SOCCLK].enabled)
1635 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1636 &(max_sustainable_clocks->soc_clock),
1637 PPCLK_SOCCLK)) == 0,
1638 "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!",
1639 return ret);
1640
1641 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1642 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1643 &(max_sustainable_clocks->dcef_clock),
1644 PPCLK_DCEFCLK)) == 0,
1645 "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!",
1646 return ret);
1647 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1648 &(max_sustainable_clocks->display_clock),
1649 PPCLK_DISPCLK)) == 0,
1650 "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!",
1651 return ret);
1652 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1653 &(max_sustainable_clocks->phy_clock),
1654 PPCLK_PHYCLK)) == 0,
1655 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!",
1656 return ret);
1657 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1658 &(max_sustainable_clocks->pixel_clock),
1659 PPCLK_PIXCLK)) == 0,
1660 "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!",
1661 return ret);
1662 }
1663
1664 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1665 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1666
1667 return 0;
1668 }
1669
vega20_enable_mgpu_fan_boost(struct pp_hwmgr * hwmgr)1670 static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
1671 {
1672 int result;
1673
1674 result = smum_send_msg_to_smc(hwmgr,
1675 PPSMC_MSG_SetMGpuFanBoostLimitRpm,
1676 NULL);
1677 PP_ASSERT_WITH_CODE(!result,
1678 "[EnableMgpuFan] Failed to enable mgpu fan boost!",
1679 return result);
1680
1681 return 0;
1682 }
1683
vega20_init_powergate_state(struct pp_hwmgr * hwmgr)1684 static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
1685 {
1686 struct vega20_hwmgr *data =
1687 (struct vega20_hwmgr *)(hwmgr->backend);
1688
1689 data->uvd_power_gated = true;
1690 data->vce_power_gated = true;
1691 }
1692
vega20_enable_dpm_tasks(struct pp_hwmgr * hwmgr)1693 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1694 {
1695 int result = 0;
1696
1697 smum_send_msg_to_smc_with_parameter(hwmgr,
1698 PPSMC_MSG_NumOfDisplays, 0, NULL);
1699
1700 result = vega20_set_allowed_featuresmask(hwmgr);
1701 PP_ASSERT_WITH_CODE(!result,
1702 "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1703 return result);
1704
1705 result = vega20_init_smc_table(hwmgr);
1706 PP_ASSERT_WITH_CODE(!result,
1707 "[EnableDPMTasks] Failed to initialize SMC table!",
1708 return result);
1709
1710 result = vega20_run_btc(hwmgr);
1711 PP_ASSERT_WITH_CODE(!result,
1712 "[EnableDPMTasks] Failed to run btc!",
1713 return result);
1714
1715 result = vega20_run_btc_afll(hwmgr);
1716 PP_ASSERT_WITH_CODE(!result,
1717 "[EnableDPMTasks] Failed to run btc afll!",
1718 return result);
1719
1720 result = vega20_enable_all_smu_features(hwmgr);
1721 PP_ASSERT_WITH_CODE(!result,
1722 "[EnableDPMTasks] Failed to enable all smu features!",
1723 return result);
1724
1725 result = vega20_override_pcie_parameters(hwmgr);
1726 PP_ASSERT_WITH_CODE(!result,
1727 "[EnableDPMTasks] Failed to override pcie parameters!",
1728 return result);
1729
1730 result = vega20_notify_smc_display_change(hwmgr);
1731 PP_ASSERT_WITH_CODE(!result,
1732 "[EnableDPMTasks] Failed to notify smc display change!",
1733 return result);
1734
1735 result = vega20_send_clock_ratio(hwmgr);
1736 PP_ASSERT_WITH_CODE(!result,
1737 "[EnableDPMTasks] Failed to send clock ratio!",
1738 return result);
1739
1740 /* Initialize UVD/VCE powergating state */
1741 vega20_init_powergate_state(hwmgr);
1742
1743 result = vega20_setup_default_dpm_tables(hwmgr);
1744 PP_ASSERT_WITH_CODE(!result,
1745 "[EnableDPMTasks] Failed to setup default DPM tables!",
1746 return result);
1747
1748 result = vega20_init_max_sustainable_clocks(hwmgr);
1749 PP_ASSERT_WITH_CODE(!result,
1750 "[EnableDPMTasks] Failed to get maximum sustainable clocks!",
1751 return result);
1752
1753 result = vega20_power_control_set_level(hwmgr);
1754 PP_ASSERT_WITH_CODE(!result,
1755 "[EnableDPMTasks] Failed to power control set level!",
1756 return result);
1757
1758 result = vega20_od8_initialize_default_settings(hwmgr);
1759 PP_ASSERT_WITH_CODE(!result,
1760 "[EnableDPMTasks] Failed to initialize odn settings!",
1761 return result);
1762
1763 vega20_populate_umdpstate_clocks(hwmgr);
1764
1765 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
1766 POWER_SOURCE_AC << 16, &hwmgr->default_power_limit);
1767 PP_ASSERT_WITH_CODE(!result,
1768 "[GetPptLimit] get default PPT limit failed!",
1769 return result);
1770 hwmgr->power_limit =
1771 hwmgr->default_power_limit;
1772
1773 return 0;
1774 }
1775
vega20_find_lowest_dpm_level(struct vega20_single_dpm_table * table)1776 static uint32_t vega20_find_lowest_dpm_level(
1777 struct vega20_single_dpm_table *table)
1778 {
1779 uint32_t i;
1780
1781 for (i = 0; i < table->count; i++) {
1782 if (table->dpm_levels[i].enabled)
1783 break;
1784 }
1785 if (i >= table->count) {
1786 i = 0;
1787 table->dpm_levels[i].enabled = true;
1788 }
1789
1790 return i;
1791 }
1792
vega20_find_highest_dpm_level(struct vega20_single_dpm_table * table)1793 static uint32_t vega20_find_highest_dpm_level(
1794 struct vega20_single_dpm_table *table)
1795 {
1796 int i = 0;
1797
1798 PP_ASSERT_WITH_CODE(table != NULL,
1799 "[FindHighestDPMLevel] DPM Table does not exist!",
1800 return 0);
1801 PP_ASSERT_WITH_CODE(table->count > 0,
1802 "[FindHighestDPMLevel] DPM Table has no entry!",
1803 return 0);
1804 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1805 "[FindHighestDPMLevel] DPM Table has too many entries!",
1806 return MAX_REGULAR_DPM_NUMBER - 1);
1807
1808 for (i = table->count - 1; i >= 0; i--) {
1809 if (table->dpm_levels[i].enabled)
1810 break;
1811 }
1812 if (i < 0) {
1813 i = 0;
1814 table->dpm_levels[i].enabled = true;
1815 }
1816
1817 return i;
1818 }
1819
vega20_upload_dpm_min_level(struct pp_hwmgr * hwmgr,uint32_t feature_mask)1820 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1821 {
1822 struct vega20_hwmgr *data =
1823 (struct vega20_hwmgr *)(hwmgr->backend);
1824 uint32_t min_freq;
1825 int ret = 0;
1826
1827 if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1828 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1829 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1830 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1831 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1832 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff),
1833 NULL)),
1834 "Failed to set soft min gfxclk !",
1835 return ret);
1836 }
1837
1838 if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1839 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1840 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1841 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1842 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1843 (PPCLK_UCLK << 16) | (min_freq & 0xffff),
1844 NULL)),
1845 "Failed to set soft min memclk !",
1846 return ret);
1847 }
1848
1849 if (data->smu_features[GNLD_DPM_UVD].enabled &&
1850 (feature_mask & FEATURE_DPM_UVD_MASK)) {
1851 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1852
1853 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1854 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1855 (PPCLK_VCLK << 16) | (min_freq & 0xffff),
1856 NULL)),
1857 "Failed to set soft min vclk!",
1858 return ret);
1859
1860 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1861
1862 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1863 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1864 (PPCLK_DCLK << 16) | (min_freq & 0xffff),
1865 NULL)),
1866 "Failed to set soft min dclk!",
1867 return ret);
1868 }
1869
1870 if (data->smu_features[GNLD_DPM_VCE].enabled &&
1871 (feature_mask & FEATURE_DPM_VCE_MASK)) {
1872 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1873
1874 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1875 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1876 (PPCLK_ECLK << 16) | (min_freq & 0xffff),
1877 NULL)),
1878 "Failed to set soft min eclk!",
1879 return ret);
1880 }
1881
1882 if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1883 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1884 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1885
1886 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1887 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1888 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff),
1889 NULL)),
1890 "Failed to set soft min socclk!",
1891 return ret);
1892 }
1893
1894 if (data->smu_features[GNLD_DPM_FCLK].enabled &&
1895 (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1896 min_freq = data->dpm_table.fclk_table.dpm_state.soft_min_level;
1897
1898 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1899 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1900 (PPCLK_FCLK << 16) | (min_freq & 0xffff),
1901 NULL)),
1902 "Failed to set soft min fclk!",
1903 return ret);
1904 }
1905
1906 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled &&
1907 (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1908 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level;
1909
1910 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1911 hwmgr, PPSMC_MSG_SetHardMinByFreq,
1912 (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff),
1913 NULL)),
1914 "Failed to set hard min dcefclk!",
1915 return ret);
1916 }
1917
1918 return ret;
1919 }
1920
vega20_upload_dpm_max_level(struct pp_hwmgr * hwmgr,uint32_t feature_mask)1921 static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1922 {
1923 struct vega20_hwmgr *data =
1924 (struct vega20_hwmgr *)(hwmgr->backend);
1925 uint32_t max_freq;
1926 int ret = 0;
1927
1928 if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1929 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1930 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1931
1932 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1933 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1934 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff),
1935 NULL)),
1936 "Failed to set soft max gfxclk!",
1937 return ret);
1938 }
1939
1940 if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1941 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1942 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1943
1944 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1945 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1946 (PPCLK_UCLK << 16) | (max_freq & 0xffff),
1947 NULL)),
1948 "Failed to set soft max memclk!",
1949 return ret);
1950 }
1951
1952 if (data->smu_features[GNLD_DPM_UVD].enabled &&
1953 (feature_mask & FEATURE_DPM_UVD_MASK)) {
1954 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1955
1956 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1957 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1958 (PPCLK_VCLK << 16) | (max_freq & 0xffff),
1959 NULL)),
1960 "Failed to set soft max vclk!",
1961 return ret);
1962
1963 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1964 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1965 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1966 (PPCLK_DCLK << 16) | (max_freq & 0xffff),
1967 NULL)),
1968 "Failed to set soft max dclk!",
1969 return ret);
1970 }
1971
1972 if (data->smu_features[GNLD_DPM_VCE].enabled &&
1973 (feature_mask & FEATURE_DPM_VCE_MASK)) {
1974 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1975
1976 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1977 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1978 (PPCLK_ECLK << 16) | (max_freq & 0xffff),
1979 NULL)),
1980 "Failed to set soft max eclk!",
1981 return ret);
1982 }
1983
1984 if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1985 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1986 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1987
1988 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1989 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1990 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff),
1991 NULL)),
1992 "Failed to set soft max socclk!",
1993 return ret);
1994 }
1995
1996 if (data->smu_features[GNLD_DPM_FCLK].enabled &&
1997 (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1998 max_freq = data->dpm_table.fclk_table.dpm_state.soft_max_level;
1999
2000 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
2001 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
2002 (PPCLK_FCLK << 16) | (max_freq & 0xffff),
2003 NULL)),
2004 "Failed to set soft max fclk!",
2005 return ret);
2006 }
2007
2008 return ret;
2009 }
2010
vega20_enable_disable_vce_dpm(struct pp_hwmgr * hwmgr,bool enable)2011 static int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
2012 {
2013 struct vega20_hwmgr *data =
2014 (struct vega20_hwmgr *)(hwmgr->backend);
2015 int ret = 0;
2016
2017 if (data->smu_features[GNLD_DPM_VCE].supported) {
2018 if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {
2019 if (enable)
2020 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n");
2021 else
2022 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n");
2023 }
2024
2025 ret = vega20_enable_smc_features(hwmgr,
2026 enable,
2027 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap);
2028 PP_ASSERT_WITH_CODE(!ret,
2029 "Attempt to Enable/Disable DPM VCE Failed!",
2030 return ret);
2031 data->smu_features[GNLD_DPM_VCE].enabled = enable;
2032 }
2033
2034 return 0;
2035 }
2036
vega20_get_clock_ranges(struct pp_hwmgr * hwmgr,uint32_t * clock,PPCLK_e clock_select,bool max)2037 static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr,
2038 uint32_t *clock,
2039 PPCLK_e clock_select,
2040 bool max)
2041 {
2042 int ret;
2043 *clock = 0;
2044
2045 if (max) {
2046 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2047 PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16),
2048 clock)) == 0,
2049 "[GetClockRanges] Failed to get max clock from SMC!",
2050 return ret);
2051 } else {
2052 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2053 PPSMC_MSG_GetMinDpmFreq,
2054 (clock_select << 16),
2055 clock)) == 0,
2056 "[GetClockRanges] Failed to get min clock from SMC!",
2057 return ret);
2058 }
2059
2060 return 0;
2061 }
2062
vega20_dpm_get_sclk(struct pp_hwmgr * hwmgr,bool low)2063 static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
2064 {
2065 struct vega20_hwmgr *data =
2066 (struct vega20_hwmgr *)(hwmgr->backend);
2067 uint32_t gfx_clk;
2068 int ret = 0;
2069
2070 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
2071 "[GetSclks]: gfxclk dpm not enabled!\n",
2072 return -EPERM);
2073
2074 if (low) {
2075 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
2076 PP_ASSERT_WITH_CODE(!ret,
2077 "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
2078 return ret);
2079 } else {
2080 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
2081 PP_ASSERT_WITH_CODE(!ret,
2082 "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
2083 return ret);
2084 }
2085
2086 return (gfx_clk * 100);
2087 }
2088
vega20_dpm_get_mclk(struct pp_hwmgr * hwmgr,bool low)2089 static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
2090 {
2091 struct vega20_hwmgr *data =
2092 (struct vega20_hwmgr *)(hwmgr->backend);
2093 uint32_t mem_clk;
2094 int ret = 0;
2095
2096 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
2097 "[MemMclks]: memclk dpm not enabled!\n",
2098 return -EPERM);
2099
2100 if (low) {
2101 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
2102 PP_ASSERT_WITH_CODE(!ret,
2103 "[GetMclks]: fail to get min PPCLK_UCLK\n",
2104 return ret);
2105 } else {
2106 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
2107 PP_ASSERT_WITH_CODE(!ret,
2108 "[GetMclks]: fail to get max PPCLK_UCLK\n",
2109 return ret);
2110 }
2111
2112 return (mem_clk * 100);
2113 }
2114
vega20_get_metrics_table(struct pp_hwmgr * hwmgr,SmuMetrics_t * metrics_table,bool bypass_cache)2115 static int vega20_get_metrics_table(struct pp_hwmgr *hwmgr,
2116 SmuMetrics_t *metrics_table,
2117 bool bypass_cache)
2118 {
2119 struct vega20_hwmgr *data =
2120 (struct vega20_hwmgr *)(hwmgr->backend);
2121 int ret = 0;
2122
2123 if (bypass_cache ||
2124 !data->metrics_time ||
2125 time_after(jiffies, data->metrics_time + msecs_to_jiffies(1))) {
2126 ret = smum_smc_table_manager(hwmgr,
2127 (uint8_t *)(&data->metrics_table),
2128 TABLE_SMU_METRICS,
2129 true);
2130 if (ret) {
2131 pr_info("Failed to export SMU metrics table!\n");
2132 return ret;
2133 }
2134 data->metrics_time = jiffies;
2135 }
2136
2137 if (metrics_table)
2138 memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t));
2139
2140 return ret;
2141 }
2142
vega20_get_gpu_power(struct pp_hwmgr * hwmgr,int idx,uint32_t * query)2143 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr, int idx,
2144 uint32_t *query)
2145 {
2146 int ret = 0;
2147 SmuMetrics_t metrics_table;
2148
2149 ret = vega20_get_metrics_table(hwmgr, &metrics_table, false);
2150 if (ret)
2151 return ret;
2152
2153 /* For the 40.46 release, they changed the value name */
2154 switch (idx) {
2155 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
2156 if (hwmgr->smu_version == 0x282e00)
2157 *query = metrics_table.AverageSocketPower *
2158 MILLIWATT_PER_WATT;
2159 else
2160 ret = -EOPNOTSUPP;
2161 break;
2162 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
2163 *query = metrics_table.CurrSocketPower * MILLIWATT_PER_WATT;
2164 break;
2165 }
2166
2167 return ret;
2168 }
2169
vega20_get_current_clk_freq(struct pp_hwmgr * hwmgr,PPCLK_e clk_id,uint32_t * clk_freq)2170 static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
2171 PPCLK_e clk_id, uint32_t *clk_freq)
2172 {
2173 int ret = 0;
2174
2175 *clk_freq = 0;
2176
2177 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2178 PPSMC_MSG_GetDpmClockFreq, (clk_id << 16),
2179 clk_freq)) == 0,
2180 "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!",
2181 return ret);
2182
2183 *clk_freq = *clk_freq * 100;
2184
2185 return 0;
2186 }
2187
vega20_get_current_activity_percent(struct pp_hwmgr * hwmgr,int idx,uint32_t * activity_percent)2188 static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
2189 int idx,
2190 uint32_t *activity_percent)
2191 {
2192 int ret = 0;
2193 SmuMetrics_t metrics_table;
2194
2195 ret = vega20_get_metrics_table(hwmgr, &metrics_table, false);
2196 if (ret)
2197 return ret;
2198
2199 switch (idx) {
2200 case AMDGPU_PP_SENSOR_GPU_LOAD:
2201 *activity_percent = metrics_table.AverageGfxActivity;
2202 break;
2203 case AMDGPU_PP_SENSOR_MEM_LOAD:
2204 *activity_percent = metrics_table.AverageUclkActivity;
2205 break;
2206 default:
2207 pr_err("Invalid index for retrieving clock activity\n");
2208 return -EINVAL;
2209 }
2210
2211 return ret;
2212 }
2213
vega20_read_sensor(struct pp_hwmgr * hwmgr,int idx,void * value,int * size)2214 static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
2215 void *value, int *size)
2216 {
2217 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2218 struct amdgpu_device *adev = hwmgr->adev;
2219 SmuMetrics_t metrics_table;
2220 uint32_t val_vid;
2221 int ret = 0;
2222
2223 switch (idx) {
2224 case AMDGPU_PP_SENSOR_GFX_SCLK:
2225 ret = vega20_get_metrics_table(hwmgr, &metrics_table, false);
2226 if (ret)
2227 return ret;
2228
2229 *((uint32_t *)value) = metrics_table.AverageGfxclkFrequency * 100;
2230 *size = 4;
2231 break;
2232 case AMDGPU_PP_SENSOR_GFX_MCLK:
2233 ret = vega20_get_current_clk_freq(hwmgr,
2234 PPCLK_UCLK,
2235 (uint32_t *)value);
2236 if (!ret)
2237 *size = 4;
2238 break;
2239 case AMDGPU_PP_SENSOR_GPU_LOAD:
2240 case AMDGPU_PP_SENSOR_MEM_LOAD:
2241 ret = vega20_get_current_activity_percent(hwmgr, idx, (uint32_t *)value);
2242 if (!ret)
2243 *size = 4;
2244 break;
2245 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
2246 *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);
2247 *size = 4;
2248 break;
2249 case AMDGPU_PP_SENSOR_EDGE_TEMP:
2250 ret = vega20_get_metrics_table(hwmgr, &metrics_table, false);
2251 if (ret)
2252 return ret;
2253
2254 *((uint32_t *)value) = metrics_table.TemperatureEdge *
2255 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2256 *size = 4;
2257 break;
2258 case AMDGPU_PP_SENSOR_MEM_TEMP:
2259 ret = vega20_get_metrics_table(hwmgr, &metrics_table, false);
2260 if (ret)
2261 return ret;
2262
2263 *((uint32_t *)value) = metrics_table.TemperatureHBM *
2264 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2265 *size = 4;
2266 break;
2267 case AMDGPU_PP_SENSOR_UVD_POWER:
2268 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
2269 *size = 4;
2270 break;
2271 case AMDGPU_PP_SENSOR_VCE_POWER:
2272 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
2273 *size = 4;
2274 break;
2275 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
2276 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
2277 *size = 16;
2278 ret = vega20_get_gpu_power(hwmgr, idx, (uint32_t *)value);
2279 break;
2280 case AMDGPU_PP_SENSOR_VDDGFX:
2281 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
2282 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
2283 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
2284 *((uint32_t *)value) =
2285 (uint32_t)convert_to_vddc((uint8_t)val_vid);
2286 break;
2287 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2288 ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
2289 if (!ret)
2290 *size = 8;
2291 break;
2292 default:
2293 ret = -EOPNOTSUPP;
2294 break;
2295 }
2296 return ret;
2297 }
2298
vega20_display_clock_voltage_request(struct pp_hwmgr * hwmgr,struct pp_display_clock_request * clock_req)2299 static int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
2300 struct pp_display_clock_request *clock_req)
2301 {
2302 int result = 0;
2303 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2304 enum amd_pp_clock_type clk_type = clock_req->clock_type;
2305 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
2306 PPCLK_e clk_select = 0;
2307 uint32_t clk_request = 0;
2308
2309 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
2310 switch (clk_type) {
2311 case amd_pp_dcef_clock:
2312 clk_select = PPCLK_DCEFCLK;
2313 break;
2314 case amd_pp_disp_clock:
2315 clk_select = PPCLK_DISPCLK;
2316 break;
2317 case amd_pp_pixel_clock:
2318 clk_select = PPCLK_PIXCLK;
2319 break;
2320 case amd_pp_phy_clock:
2321 clk_select = PPCLK_PHYCLK;
2322 break;
2323 default:
2324 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
2325 result = -EINVAL;
2326 break;
2327 }
2328
2329 if (!result) {
2330 clk_request = (clk_select << 16) | clk_freq;
2331 result = smum_send_msg_to_smc_with_parameter(hwmgr,
2332 PPSMC_MSG_SetHardMinByFreq,
2333 clk_request,
2334 NULL);
2335 }
2336 }
2337
2338 return result;
2339 }
2340
vega20_get_performance_level(struct pp_hwmgr * hwmgr,const struct pp_hw_power_state * state,PHM_PerformanceLevelDesignation designation,uint32_t index,PHM_PerformanceLevel * level)2341 static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2342 PHM_PerformanceLevelDesignation designation, uint32_t index,
2343 PHM_PerformanceLevel *level)
2344 {
2345 return 0;
2346 }
2347
vega20_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr * hwmgr)2348 static int vega20_notify_smc_display_config_after_ps_adjustment(
2349 struct pp_hwmgr *hwmgr)
2350 {
2351 struct vega20_hwmgr *data =
2352 (struct vega20_hwmgr *)(hwmgr->backend);
2353 struct vega20_single_dpm_table *dpm_table =
2354 &data->dpm_table.mem_table;
2355 struct PP_Clocks min_clocks = {0};
2356 struct pp_display_clock_request clock_req;
2357 int ret = 0;
2358
2359 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2360 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2361 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2362
2363 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
2364 clock_req.clock_type = amd_pp_dcef_clock;
2365 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2366 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
2367 if (data->smu_features[GNLD_DS_DCEFCLK].supported)
2368 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
2369 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
2370 min_clocks.dcefClockInSR / 100,
2371 NULL)) == 0,
2372 "Attempt to set divider for DCEFCLK Failed!",
2373 return ret);
2374 } else {
2375 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2376 }
2377 }
2378
2379 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2380 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
2381 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2382 PPSMC_MSG_SetHardMinByFreq,
2383 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level,
2384 NULL)),
2385 "[SetHardMinFreq] Set hard min uclk failed!",
2386 return ret);
2387 }
2388
2389 return 0;
2390 }
2391
vega20_force_dpm_highest(struct pp_hwmgr * hwmgr)2392 static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
2393 {
2394 struct vega20_hwmgr *data =
2395 (struct vega20_hwmgr *)(hwmgr->backend);
2396 uint32_t soft_level;
2397 int ret = 0;
2398
2399 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2400
2401 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2402 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2403 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2404
2405 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2406
2407 data->dpm_table.mem_table.dpm_state.soft_min_level =
2408 data->dpm_table.mem_table.dpm_state.soft_max_level =
2409 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2410
2411 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
2412
2413 data->dpm_table.soc_table.dpm_state.soft_min_level =
2414 data->dpm_table.soc_table.dpm_state.soft_max_level =
2415 data->dpm_table.soc_table.dpm_levels[soft_level].value;
2416
2417 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2418 FEATURE_DPM_UCLK_MASK |
2419 FEATURE_DPM_SOCCLK_MASK);
2420 PP_ASSERT_WITH_CODE(!ret,
2421 "Failed to upload boot level to highest!",
2422 return ret);
2423
2424 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2425 FEATURE_DPM_UCLK_MASK |
2426 FEATURE_DPM_SOCCLK_MASK);
2427 PP_ASSERT_WITH_CODE(!ret,
2428 "Failed to upload dpm max level to highest!",
2429 return ret);
2430
2431 return 0;
2432 }
2433
vega20_force_dpm_lowest(struct pp_hwmgr * hwmgr)2434 static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2435 {
2436 struct vega20_hwmgr *data =
2437 (struct vega20_hwmgr *)(hwmgr->backend);
2438 uint32_t soft_level;
2439 int ret = 0;
2440
2441 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2442
2443 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2444 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2445 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2446
2447 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2448
2449 data->dpm_table.mem_table.dpm_state.soft_min_level =
2450 data->dpm_table.mem_table.dpm_state.soft_max_level =
2451 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2452
2453 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
2454
2455 data->dpm_table.soc_table.dpm_state.soft_min_level =
2456 data->dpm_table.soc_table.dpm_state.soft_max_level =
2457 data->dpm_table.soc_table.dpm_levels[soft_level].value;
2458
2459 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2460 FEATURE_DPM_UCLK_MASK |
2461 FEATURE_DPM_SOCCLK_MASK);
2462 PP_ASSERT_WITH_CODE(!ret,
2463 "Failed to upload boot level to highest!",
2464 return ret);
2465
2466 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2467 FEATURE_DPM_UCLK_MASK |
2468 FEATURE_DPM_SOCCLK_MASK);
2469 PP_ASSERT_WITH_CODE(!ret,
2470 "Failed to upload dpm max level to highest!",
2471 return ret);
2472
2473 return 0;
2474
2475 }
2476
vega20_unforce_dpm_levels(struct pp_hwmgr * hwmgr)2477 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2478 {
2479 struct vega20_hwmgr *data =
2480 (struct vega20_hwmgr *)(hwmgr->backend);
2481 uint32_t soft_min_level, soft_max_level;
2482 int ret = 0;
2483
2484 /* gfxclk soft min/max settings */
2485 soft_min_level =
2486 vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2487 soft_max_level =
2488 vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2489
2490 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2491 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2492 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2493 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2494
2495 /* uclk soft min/max settings */
2496 soft_min_level =
2497 vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2498 soft_max_level =
2499 vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2500
2501 data->dpm_table.mem_table.dpm_state.soft_min_level =
2502 data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2503 data->dpm_table.mem_table.dpm_state.soft_max_level =
2504 data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2505
2506 /* socclk soft min/max settings */
2507 soft_min_level =
2508 vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
2509 soft_max_level =
2510 vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
2511
2512 data->dpm_table.soc_table.dpm_state.soft_min_level =
2513 data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2514 data->dpm_table.soc_table.dpm_state.soft_max_level =
2515 data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2516
2517 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2518 FEATURE_DPM_UCLK_MASK |
2519 FEATURE_DPM_SOCCLK_MASK);
2520 PP_ASSERT_WITH_CODE(!ret,
2521 "Failed to upload DPM Bootup Levels!",
2522 return ret);
2523
2524 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2525 FEATURE_DPM_UCLK_MASK |
2526 FEATURE_DPM_SOCCLK_MASK);
2527 PP_ASSERT_WITH_CODE(!ret,
2528 "Failed to upload DPM Max Levels!",
2529 return ret);
2530
2531 return 0;
2532 }
2533
vega20_get_profiling_clk_mask(struct pp_hwmgr * hwmgr,enum amd_dpm_forced_level level,uint32_t * sclk_mask,uint32_t * mclk_mask,uint32_t * soc_mask)2534 static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2535 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2536 {
2537 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2538 struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
2539 struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
2540 struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
2541
2542 *sclk_mask = 0;
2543 *mclk_mask = 0;
2544 *soc_mask = 0;
2545
2546 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2547 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2548 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2549 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2550 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2551 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2552 }
2553
2554 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2555 *sclk_mask = 0;
2556 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2557 *mclk_mask = 0;
2558 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2559 *sclk_mask = gfx_dpm_table->count - 1;
2560 *mclk_mask = mem_dpm_table->count - 1;
2561 *soc_mask = soc_dpm_table->count - 1;
2562 }
2563
2564 return 0;
2565 }
2566
vega20_force_clock_level(struct pp_hwmgr * hwmgr,enum pp_clock_type type,uint32_t mask)2567 static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2568 enum pp_clock_type type, uint32_t mask)
2569 {
2570 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2571 uint32_t soft_min_level, soft_max_level, hard_min_level;
2572 int ret = 0;
2573
2574 switch (type) {
2575 case PP_SCLK:
2576 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2577 soft_max_level = mask ? (fls(mask) - 1) : 0;
2578
2579 if (soft_max_level >= data->dpm_table.gfx_table.count) {
2580 pr_err("Clock level specified %d is over max allowed %d\n",
2581 soft_max_level,
2582 data->dpm_table.gfx_table.count - 1);
2583 return -EINVAL;
2584 }
2585
2586 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2587 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2588 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2589 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2590
2591 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2592 PP_ASSERT_WITH_CODE(!ret,
2593 "Failed to upload boot level to lowest!",
2594 return ret);
2595
2596 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2597 PP_ASSERT_WITH_CODE(!ret,
2598 "Failed to upload dpm max level to highest!",
2599 return ret);
2600 break;
2601
2602 case PP_MCLK:
2603 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2604 soft_max_level = mask ? (fls(mask) - 1) : 0;
2605
2606 if (soft_max_level >= data->dpm_table.mem_table.count) {
2607 pr_err("Clock level specified %d is over max allowed %d\n",
2608 soft_max_level,
2609 data->dpm_table.mem_table.count - 1);
2610 return -EINVAL;
2611 }
2612
2613 data->dpm_table.mem_table.dpm_state.soft_min_level =
2614 data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2615 data->dpm_table.mem_table.dpm_state.soft_max_level =
2616 data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2617
2618 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2619 PP_ASSERT_WITH_CODE(!ret,
2620 "Failed to upload boot level to lowest!",
2621 return ret);
2622
2623 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2624 PP_ASSERT_WITH_CODE(!ret,
2625 "Failed to upload dpm max level to highest!",
2626 return ret);
2627
2628 break;
2629
2630 case PP_SOCCLK:
2631 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2632 soft_max_level = mask ? (fls(mask) - 1) : 0;
2633
2634 if (soft_max_level >= data->dpm_table.soc_table.count) {
2635 pr_err("Clock level specified %d is over max allowed %d\n",
2636 soft_max_level,
2637 data->dpm_table.soc_table.count - 1);
2638 return -EINVAL;
2639 }
2640
2641 data->dpm_table.soc_table.dpm_state.soft_min_level =
2642 data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2643 data->dpm_table.soc_table.dpm_state.soft_max_level =
2644 data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2645
2646 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
2647 PP_ASSERT_WITH_CODE(!ret,
2648 "Failed to upload boot level to lowest!",
2649 return ret);
2650
2651 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
2652 PP_ASSERT_WITH_CODE(!ret,
2653 "Failed to upload dpm max level to highest!",
2654 return ret);
2655
2656 break;
2657
2658 case PP_FCLK:
2659 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2660 soft_max_level = mask ? (fls(mask) - 1) : 0;
2661
2662 if (soft_max_level >= data->dpm_table.fclk_table.count) {
2663 pr_err("Clock level specified %d is over max allowed %d\n",
2664 soft_max_level,
2665 data->dpm_table.fclk_table.count - 1);
2666 return -EINVAL;
2667 }
2668
2669 data->dpm_table.fclk_table.dpm_state.soft_min_level =
2670 data->dpm_table.fclk_table.dpm_levels[soft_min_level].value;
2671 data->dpm_table.fclk_table.dpm_state.soft_max_level =
2672 data->dpm_table.fclk_table.dpm_levels[soft_max_level].value;
2673
2674 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_FCLK_MASK);
2675 PP_ASSERT_WITH_CODE(!ret,
2676 "Failed to upload boot level to lowest!",
2677 return ret);
2678
2679 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_FCLK_MASK);
2680 PP_ASSERT_WITH_CODE(!ret,
2681 "Failed to upload dpm max level to highest!",
2682 return ret);
2683
2684 break;
2685
2686 case PP_DCEFCLK:
2687 hard_min_level = mask ? (ffs(mask) - 1) : 0;
2688
2689 if (hard_min_level >= data->dpm_table.dcef_table.count) {
2690 pr_err("Clock level specified %d is over max allowed %d\n",
2691 hard_min_level,
2692 data->dpm_table.dcef_table.count - 1);
2693 return -EINVAL;
2694 }
2695
2696 data->dpm_table.dcef_table.dpm_state.hard_min_level =
2697 data->dpm_table.dcef_table.dpm_levels[hard_min_level].value;
2698
2699 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_DCEFCLK_MASK);
2700 PP_ASSERT_WITH_CODE(!ret,
2701 "Failed to upload boot level to lowest!",
2702 return ret);
2703
2704 //TODO: Setting DCEFCLK max dpm level is not supported
2705
2706 break;
2707
2708 case PP_PCIE:
2709 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2710 soft_max_level = mask ? (fls(mask) - 1) : 0;
2711 if (soft_min_level >= NUM_LINK_LEVELS ||
2712 soft_max_level >= NUM_LINK_LEVELS)
2713 return -EINVAL;
2714
2715 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2716 PPSMC_MSG_SetMinLinkDpmByIndex, soft_min_level,
2717 NULL);
2718 PP_ASSERT_WITH_CODE(!ret,
2719 "Failed to set min link dpm level!",
2720 return ret);
2721
2722 break;
2723
2724 default:
2725 break;
2726 }
2727
2728 return 0;
2729 }
2730
vega20_dpm_force_dpm_level(struct pp_hwmgr * hwmgr,enum amd_dpm_forced_level level)2731 static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
2732 enum amd_dpm_forced_level level)
2733 {
2734 int ret = 0;
2735 uint32_t sclk_mask, mclk_mask, soc_mask;
2736
2737 switch (level) {
2738 case AMD_DPM_FORCED_LEVEL_HIGH:
2739 ret = vega20_force_dpm_highest(hwmgr);
2740 break;
2741
2742 case AMD_DPM_FORCED_LEVEL_LOW:
2743 ret = vega20_force_dpm_lowest(hwmgr);
2744 break;
2745
2746 case AMD_DPM_FORCED_LEVEL_AUTO:
2747 ret = vega20_unforce_dpm_levels(hwmgr);
2748 break;
2749
2750 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2751 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2752 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2753 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2754 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2755 if (ret)
2756 return ret;
2757 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
2758 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
2759 vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask);
2760 break;
2761
2762 case AMD_DPM_FORCED_LEVEL_MANUAL:
2763 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2764 default:
2765 break;
2766 }
2767
2768 return ret;
2769 }
2770
vega20_get_fan_control_mode(struct pp_hwmgr * hwmgr)2771 static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
2772 {
2773 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2774
2775 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
2776 return AMD_FAN_CTRL_MANUAL;
2777 else
2778 return AMD_FAN_CTRL_AUTO;
2779 }
2780
vega20_set_fan_control_mode(struct pp_hwmgr * hwmgr,uint32_t mode)2781 static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
2782 {
2783 switch (mode) {
2784 case AMD_FAN_CTRL_NONE:
2785 vega20_fan_ctrl_set_fan_speed_pwm(hwmgr, 255);
2786 break;
2787 case AMD_FAN_CTRL_MANUAL:
2788 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2789 vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
2790 break;
2791 case AMD_FAN_CTRL_AUTO:
2792 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2793 vega20_fan_ctrl_start_smc_fan_control(hwmgr);
2794 break;
2795 default:
2796 break;
2797 }
2798 }
2799
vega20_get_sclks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)2800 static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
2801 struct pp_clock_levels_with_latency *clocks)
2802 {
2803 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2804 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
2805 int i, count;
2806
2807 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
2808 return -1;
2809
2810 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2811 clocks->num_levels = count;
2812
2813 for (i = 0; i < count; i++) {
2814 clocks->data[i].clocks_in_khz =
2815 dpm_table->dpm_levels[i].value * 1000;
2816 clocks->data[i].latency_in_us = 0;
2817 }
2818
2819 return 0;
2820 }
2821
vega20_get_mem_latency(struct pp_hwmgr * hwmgr,uint32_t clock)2822 static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,
2823 uint32_t clock)
2824 {
2825 return 25;
2826 }
2827
vega20_get_memclocks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)2828 static int vega20_get_memclocks(struct pp_hwmgr *hwmgr,
2829 struct pp_clock_levels_with_latency *clocks)
2830 {
2831 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2832 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table);
2833 int i, count;
2834
2835 if (!data->smu_features[GNLD_DPM_UCLK].enabled)
2836 return -1;
2837
2838 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2839 clocks->num_levels = data->mclk_latency_table.count = count;
2840
2841 for (i = 0; i < count; i++) {
2842 clocks->data[i].clocks_in_khz =
2843 data->mclk_latency_table.entries[i].frequency =
2844 dpm_table->dpm_levels[i].value * 1000;
2845 clocks->data[i].latency_in_us =
2846 data->mclk_latency_table.entries[i].latency =
2847 vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
2848 }
2849
2850 return 0;
2851 }
2852
vega20_get_dcefclocks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)2853 static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr,
2854 struct pp_clock_levels_with_latency *clocks)
2855 {
2856 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2857 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table);
2858 int i, count;
2859
2860 if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled)
2861 return -1;
2862
2863 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2864 clocks->num_levels = count;
2865
2866 for (i = 0; i < count; i++) {
2867 clocks->data[i].clocks_in_khz =
2868 dpm_table->dpm_levels[i].value * 1000;
2869 clocks->data[i].latency_in_us = 0;
2870 }
2871
2872 return 0;
2873 }
2874
vega20_get_socclocks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)2875 static int vega20_get_socclocks(struct pp_hwmgr *hwmgr,
2876 struct pp_clock_levels_with_latency *clocks)
2877 {
2878 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2879 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table);
2880 int i, count;
2881
2882 if (!data->smu_features[GNLD_DPM_SOCCLK].enabled)
2883 return -1;
2884
2885 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2886 clocks->num_levels = count;
2887
2888 for (i = 0; i < count; i++) {
2889 clocks->data[i].clocks_in_khz =
2890 dpm_table->dpm_levels[i].value * 1000;
2891 clocks->data[i].latency_in_us = 0;
2892 }
2893
2894 return 0;
2895
2896 }
2897
vega20_get_clock_by_type_with_latency(struct pp_hwmgr * hwmgr,enum amd_pp_clock_type type,struct pp_clock_levels_with_latency * clocks)2898 static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
2899 enum amd_pp_clock_type type,
2900 struct pp_clock_levels_with_latency *clocks)
2901 {
2902 int ret;
2903
2904 switch (type) {
2905 case amd_pp_sys_clock:
2906 ret = vega20_get_sclks(hwmgr, clocks);
2907 break;
2908 case amd_pp_mem_clock:
2909 ret = vega20_get_memclocks(hwmgr, clocks);
2910 break;
2911 case amd_pp_dcef_clock:
2912 ret = vega20_get_dcefclocks(hwmgr, clocks);
2913 break;
2914 case amd_pp_soc_clock:
2915 ret = vega20_get_socclocks(hwmgr, clocks);
2916 break;
2917 default:
2918 return -EINVAL;
2919 }
2920
2921 return ret;
2922 }
2923
vega20_get_clock_by_type_with_voltage(struct pp_hwmgr * hwmgr,enum amd_pp_clock_type type,struct pp_clock_levels_with_voltage * clocks)2924 static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
2925 enum amd_pp_clock_type type,
2926 struct pp_clock_levels_with_voltage *clocks)
2927 {
2928 clocks->num_levels = 0;
2929
2930 return 0;
2931 }
2932
vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr * hwmgr,void * clock_ranges)2933 static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
2934 void *clock_ranges)
2935 {
2936 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2937 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2938 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
2939
2940 if (!data->registry_data.disable_water_mark &&
2941 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2942 data->smu_features[GNLD_DPM_SOCCLK].supported) {
2943 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
2944 data->water_marks_bitmap |= WaterMarksExist;
2945 data->water_marks_bitmap &= ~WaterMarksLoaded;
2946 }
2947
2948 return 0;
2949 }
2950
vega20_odn_edit_dpm_table(struct pp_hwmgr * hwmgr,enum PP_OD_DPM_TABLE_COMMAND type,long * input,uint32_t size)2951 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
2952 enum PP_OD_DPM_TABLE_COMMAND type,
2953 long *input, uint32_t size)
2954 {
2955 struct vega20_hwmgr *data =
2956 (struct vega20_hwmgr *)(hwmgr->backend);
2957 struct vega20_od8_single_setting *od8_settings =
2958 data->od8_settings.od8_settings_array;
2959 OverDriveTable_t *od_table =
2960 &(data->smc_state_table.overdrive_table);
2961 int32_t input_clk, input_vol, i;
2962 uint32_t input_index;
2963 int od8_id;
2964 int ret;
2965
2966 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
2967 return -EINVAL);
2968
2969 switch (type) {
2970 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2971 if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2972 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2973 pr_info("Sclk min/max frequency overdrive not supported\n");
2974 return -EOPNOTSUPP;
2975 }
2976
2977 for (i = 0; i < size; i += 2) {
2978 if (i + 2 > size) {
2979 pr_info("invalid number of input parameters %d\n",
2980 size);
2981 return -EINVAL;
2982 }
2983
2984 input_index = input[i];
2985 input_clk = input[i + 1];
2986
2987 if (input_index != 0 && input_index != 1) {
2988 pr_info("Invalid index %d\n", input_index);
2989 pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
2990 return -EINVAL;
2991 }
2992
2993 if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
2994 input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
2995 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2996 input_clk,
2997 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2998 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2999 return -EINVAL;
3000 }
3001
3002 if ((input_index == 0 && od_table->GfxclkFmin != input_clk) ||
3003 (input_index == 1 && od_table->GfxclkFmax != input_clk))
3004 data->gfxclk_overdrive = true;
3005
3006 if (input_index == 0)
3007 od_table->GfxclkFmin = input_clk;
3008 else
3009 od_table->GfxclkFmax = input_clk;
3010 }
3011
3012 break;
3013
3014 case PP_OD_EDIT_MCLK_VDDC_TABLE:
3015 if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
3016 pr_info("Mclk max frequency overdrive not supported\n");
3017 return -EOPNOTSUPP;
3018 }
3019
3020 for (i = 0; i < size; i += 2) {
3021 if (i + 2 > size) {
3022 pr_info("invalid number of input parameters %d\n",
3023 size);
3024 return -EINVAL;
3025 }
3026
3027 input_index = input[i];
3028 input_clk = input[i + 1];
3029
3030 if (input_index != 1) {
3031 pr_info("Invalid index %d\n", input_index);
3032 pr_info("Support max Mclk frequency setting only which index by 1\n");
3033 return -EINVAL;
3034 }
3035
3036 if (input_clk < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
3037 input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
3038 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
3039 input_clk,
3040 od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
3041 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
3042 return -EINVAL;
3043 }
3044
3045 if (input_index == 1 && od_table->UclkFmax != input_clk)
3046 data->memclk_overdrive = true;
3047
3048 od_table->UclkFmax = input_clk;
3049 }
3050
3051 break;
3052
3053 case PP_OD_EDIT_VDDC_CURVE:
3054 if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3055 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3056 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3057 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3058 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3059 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
3060 pr_info("Voltage curve calibrate not supported\n");
3061 return -EOPNOTSUPP;
3062 }
3063
3064 for (i = 0; i < size; i += 3) {
3065 if (i + 3 > size) {
3066 pr_info("invalid number of input parameters %d\n",
3067 size);
3068 return -EINVAL;
3069 }
3070
3071 input_index = input[i];
3072 input_clk = input[i + 1];
3073 input_vol = input[i + 2];
3074
3075 if (input_index > 2) {
3076 pr_info("Setting for point %d is not supported\n",
3077 input_index + 1);
3078 pr_info("Three supported points index by 0, 1, 2\n");
3079 return -EINVAL;
3080 }
3081
3082 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
3083 if (input_clk < od8_settings[od8_id].min_value ||
3084 input_clk > od8_settings[od8_id].max_value) {
3085 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
3086 input_clk,
3087 od8_settings[od8_id].min_value,
3088 od8_settings[od8_id].max_value);
3089 return -EINVAL;
3090 }
3091
3092 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
3093 if (input_vol < od8_settings[od8_id].min_value ||
3094 input_vol > od8_settings[od8_id].max_value) {
3095 pr_info("clock voltage %d is not within allowed range [%d - %d]\n",
3096 input_vol,
3097 od8_settings[od8_id].min_value,
3098 od8_settings[od8_id].max_value);
3099 return -EINVAL;
3100 }
3101
3102 switch (input_index) {
3103 case 0:
3104 od_table->GfxclkFreq1 = input_clk;
3105 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
3106 break;
3107 case 1:
3108 od_table->GfxclkFreq2 = input_clk;
3109 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
3110 break;
3111 case 2:
3112 od_table->GfxclkFreq3 = input_clk;
3113 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
3114 break;
3115 }
3116 }
3117 break;
3118
3119 case PP_OD_RESTORE_DEFAULT_TABLE:
3120 data->gfxclk_overdrive = false;
3121 data->memclk_overdrive = false;
3122
3123 ret = smum_smc_table_manager(hwmgr,
3124 (uint8_t *)od_table,
3125 TABLE_OVERDRIVE, true);
3126 PP_ASSERT_WITH_CODE(!ret,
3127 "Failed to export overdrive table!",
3128 return ret);
3129 break;
3130
3131 case PP_OD_COMMIT_DPM_TABLE:
3132 ret = smum_smc_table_manager(hwmgr,
3133 (uint8_t *)od_table,
3134 TABLE_OVERDRIVE, false);
3135 PP_ASSERT_WITH_CODE(!ret,
3136 "Failed to import overdrive table!",
3137 return ret);
3138
3139 /* retrieve updated gfxclk table */
3140 if (data->gfxclk_overdrive) {
3141 data->gfxclk_overdrive = false;
3142
3143 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
3144 if (ret)
3145 return ret;
3146 }
3147
3148 /* retrieve updated memclk table */
3149 if (data->memclk_overdrive) {
3150 data->memclk_overdrive = false;
3151
3152 ret = vega20_setup_memclk_dpm_table(hwmgr);
3153 if (ret)
3154 return ret;
3155 }
3156 break;
3157
3158 default:
3159 return -EINVAL;
3160 }
3161
3162 return 0;
3163 }
3164
vega20_set_mp1_state(struct pp_hwmgr * hwmgr,enum pp_mp1_state mp1_state)3165 static int vega20_set_mp1_state(struct pp_hwmgr *hwmgr,
3166 enum pp_mp1_state mp1_state)
3167 {
3168 uint16_t msg;
3169 int ret;
3170
3171 switch (mp1_state) {
3172 case PP_MP1_STATE_SHUTDOWN:
3173 msg = PPSMC_MSG_PrepareMp1ForShutdown;
3174 break;
3175 case PP_MP1_STATE_UNLOAD:
3176 msg = PPSMC_MSG_PrepareMp1ForUnload;
3177 break;
3178 case PP_MP1_STATE_RESET:
3179 msg = PPSMC_MSG_PrepareMp1ForReset;
3180 break;
3181 case PP_MP1_STATE_NONE:
3182 default:
3183 return 0;
3184 }
3185
3186 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,
3187 "[PrepareMp1] Failed!",
3188 return ret);
3189
3190 return 0;
3191 }
3192
vega20_get_ppfeature_status(struct pp_hwmgr * hwmgr,char * buf)3193 static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
3194 {
3195 static const char *ppfeature_name[] = {
3196 "DPM_PREFETCHER",
3197 "GFXCLK_DPM",
3198 "UCLK_DPM",
3199 "SOCCLK_DPM",
3200 "UVD_DPM",
3201 "VCE_DPM",
3202 "ULV",
3203 "MP0CLK_DPM",
3204 "LINK_DPM",
3205 "DCEFCLK_DPM",
3206 "GFXCLK_DS",
3207 "SOCCLK_DS",
3208 "LCLK_DS",
3209 "PPT",
3210 "TDC",
3211 "THERMAL",
3212 "GFX_PER_CU_CG",
3213 "RM",
3214 "DCEFCLK_DS",
3215 "ACDC",
3216 "VR0HOT",
3217 "VR1HOT",
3218 "FW_CTF",
3219 "LED_DISPLAY",
3220 "FAN_CONTROL",
3221 "GFX_EDC",
3222 "GFXOFF",
3223 "CG",
3224 "FCLK_DPM",
3225 "FCLK_DS",
3226 "MP1CLK_DS",
3227 "MP0CLK_DS",
3228 "XGMI",
3229 "ECC"};
3230 static const char *output_title[] = {
3231 "FEATURES",
3232 "BITMASK",
3233 "ENABLEMENT"};
3234 uint64_t features_enabled;
3235 int i;
3236 int ret = 0;
3237 int size = 0;
3238
3239 phm_get_sysfs_buf(&buf, &size);
3240
3241 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3242 PP_ASSERT_WITH_CODE(!ret,
3243 "[EnableAllSmuFeatures] Failed to get enabled smc features!",
3244 return ret);
3245
3246 size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled);
3247 size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n",
3248 output_title[0],
3249 output_title[1],
3250 output_title[2]);
3251 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
3252 size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n",
3253 ppfeature_name[i],
3254 1ULL << i,
3255 (features_enabled & (1ULL << i)) ? "Y" : "N");
3256 }
3257
3258 return size;
3259 }
3260
vega20_set_ppfeature_status(struct pp_hwmgr * hwmgr,uint64_t new_ppfeature_masks)3261 static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
3262 {
3263 struct vega20_hwmgr *data =
3264 (struct vega20_hwmgr *)(hwmgr->backend);
3265 uint64_t features_enabled, features_to_enable, features_to_disable;
3266 int i, ret = 0;
3267 bool enabled;
3268
3269 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
3270 return -EINVAL;
3271
3272 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3273 if (ret)
3274 return ret;
3275
3276 features_to_disable =
3277 features_enabled & ~new_ppfeature_masks;
3278 features_to_enable =
3279 ~features_enabled & new_ppfeature_masks;
3280
3281 pr_debug("features_to_disable 0x%llx\n", features_to_disable);
3282 pr_debug("features_to_enable 0x%llx\n", features_to_enable);
3283
3284 if (features_to_disable) {
3285 ret = vega20_enable_smc_features(hwmgr, false, features_to_disable);
3286 if (ret)
3287 return ret;
3288 }
3289
3290 if (features_to_enable) {
3291 ret = vega20_enable_smc_features(hwmgr, true, features_to_enable);
3292 if (ret)
3293 return ret;
3294 }
3295
3296 /* Update the cached feature enablement state */
3297 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3298 if (ret)
3299 return ret;
3300
3301 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
3302 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
3303 true : false;
3304 data->smu_features[i].enabled = enabled;
3305 }
3306
3307 return 0;
3308 }
3309
vega20_get_current_pcie_link_width_level(struct pp_hwmgr * hwmgr)3310 static int vega20_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr)
3311 {
3312 struct amdgpu_device *adev = hwmgr->adev;
3313
3314 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
3315 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
3316 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
3317 }
3318
vega20_get_current_pcie_link_width(struct pp_hwmgr * hwmgr)3319 static int vega20_get_current_pcie_link_width(struct pp_hwmgr *hwmgr)
3320 {
3321 uint32_t width_level;
3322
3323 width_level = vega20_get_current_pcie_link_width_level(hwmgr);
3324 if (width_level > LINK_WIDTH_MAX)
3325 width_level = 0;
3326
3327 return link_width[width_level];
3328 }
3329
vega20_get_current_pcie_link_speed_level(struct pp_hwmgr * hwmgr)3330 static int vega20_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr)
3331 {
3332 struct amdgpu_device *adev = hwmgr->adev;
3333
3334 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
3335 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
3336 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
3337 }
3338
vega20_get_current_pcie_link_speed(struct pp_hwmgr * hwmgr)3339 static int vega20_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr)
3340 {
3341 uint32_t speed_level;
3342
3343 speed_level = vega20_get_current_pcie_link_speed_level(hwmgr);
3344 if (speed_level > LINK_SPEED_MAX)
3345 speed_level = 0;
3346
3347 return link_speed[speed_level];
3348 }
3349
vega20_emit_clock_levels(struct pp_hwmgr * hwmgr,enum pp_clock_type type,char * buf,int * offset)3350 static int vega20_emit_clock_levels(struct pp_hwmgr *hwmgr,
3351 enum pp_clock_type type, char *buf,
3352 int *offset)
3353 {
3354 struct vega20_hwmgr *data =
3355 (struct vega20_hwmgr *)(hwmgr->backend);
3356 struct vega20_od8_single_setting *od8_settings =
3357 data->od8_settings.od8_settings_array;
3358 OverDriveTable_t *od_table =
3359 &(data->smc_state_table.overdrive_table);
3360 PPTable_t *pptable = &(data->smc_state_table.pp_table);
3361 struct pp_clock_levels_with_latency clocks;
3362 struct vega20_single_dpm_table *fclk_dpm_table =
3363 &(data->dpm_table.fclk_table);
3364 int i, now, size = *offset;
3365 int ret = 0;
3366 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
3367
3368 switch (type) {
3369 case PP_SCLK:
3370 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
3371 PP_ASSERT_WITH_CODE(!ret,
3372 "Attempt to get current gfx clk Failed!",
3373 return ret);
3374
3375 if (vega20_get_sclks(hwmgr, &clocks)) {
3376 size += sysfs_emit_at(buf, size,
3377 "0: %uMhz * (DPM disabled)\n",
3378 now / 100);
3379 break;
3380 }
3381
3382 for (i = 0; i < clocks.num_levels; i++)
3383 size += sysfs_emit_at(
3384 buf, size, "%d: %uMhz %s\n", i,
3385 clocks.data[i].clocks_in_khz / 1000,
3386 (clocks.data[i].clocks_in_khz == now * 10) ?
3387 "*" :
3388 "");
3389 break;
3390
3391 case PP_MCLK:
3392 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
3393 PP_ASSERT_WITH_CODE(!ret,
3394 "Attempt to get current mclk freq Failed!",
3395 return ret);
3396
3397 if (vega20_get_memclocks(hwmgr, &clocks)) {
3398 size += sysfs_emit_at(buf, size,
3399 "0: %uMhz * (DPM disabled)\n",
3400 now / 100);
3401 break;
3402 }
3403
3404 for (i = 0; i < clocks.num_levels; i++)
3405 size += sysfs_emit_at(
3406 buf, size, "%d: %uMhz %s\n", i,
3407 clocks.data[i].clocks_in_khz / 1000,
3408 (clocks.data[i].clocks_in_khz == now * 10) ?
3409 "*" :
3410 "");
3411 break;
3412
3413 case PP_SOCCLK:
3414 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_SOCCLK, &now);
3415 PP_ASSERT_WITH_CODE(!ret,
3416 "Attempt to get current socclk freq Failed!",
3417 return ret);
3418
3419 if (vega20_get_socclocks(hwmgr, &clocks)) {
3420 size += sysfs_emit_at(buf, size,
3421 "0: %uMhz * (DPM disabled)\n",
3422 now / 100);
3423 break;
3424 }
3425
3426 for (i = 0; i < clocks.num_levels; i++)
3427 size += sysfs_emit_at(
3428 buf, size, "%d: %uMhz %s\n", i,
3429 clocks.data[i].clocks_in_khz / 1000,
3430 (clocks.data[i].clocks_in_khz == now * 10) ?
3431 "*" :
3432 "");
3433 break;
3434
3435 case PP_FCLK:
3436 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_FCLK, &now);
3437 PP_ASSERT_WITH_CODE(!ret,
3438 "Attempt to get current fclk freq Failed!",
3439 return ret);
3440
3441 for (i = 0; i < fclk_dpm_table->count; i++)
3442 size += sysfs_emit_at(
3443 buf, size, "%d: %uMhz %s\n", i,
3444 fclk_dpm_table->dpm_levels[i].value,
3445 fclk_dpm_table->dpm_levels[i].value ==
3446 (now / 100) ?
3447 "*" :
3448 "");
3449 break;
3450
3451 case PP_DCEFCLK:
3452 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_DCEFCLK, &now);
3453 PP_ASSERT_WITH_CODE(!ret,
3454 "Attempt to get current dcefclk freq Failed!",
3455 return ret);
3456
3457 if (vega20_get_dcefclocks(hwmgr, &clocks)) {
3458 size += sysfs_emit_at(buf, size,
3459 "0: %uMhz * (DPM disabled)\n",
3460 now / 100);
3461 break;
3462 }
3463
3464 for (i = 0; i < clocks.num_levels; i++)
3465 size += sysfs_emit_at(
3466 buf, size, "%d: %uMhz %s\n", i,
3467 clocks.data[i].clocks_in_khz / 1000,
3468 (clocks.data[i].clocks_in_khz == now * 10) ?
3469 "*" :
3470 "");
3471 break;
3472
3473 case PP_PCIE:
3474 current_gen_speed =
3475 vega20_get_current_pcie_link_speed_level(hwmgr);
3476 current_lane_width =
3477 vega20_get_current_pcie_link_width_level(hwmgr);
3478 for (i = 0; i < NUM_LINK_LEVELS; i++) {
3479 gen_speed = pptable->PcieGenSpeed[i];
3480 lane_width = pptable->PcieLaneCount[i];
3481
3482 size += sysfs_emit_at(
3483 buf, size, "%d: %s %s %dMhz %s\n", i,
3484 (gen_speed == 0) ? "2.5GT/s," :
3485 (gen_speed == 1) ? "5.0GT/s," :
3486 (gen_speed == 2) ? "8.0GT/s," :
3487 (gen_speed == 3) ? "16.0GT/s," :
3488 "",
3489 (lane_width == 1) ? "x1" :
3490 (lane_width == 2) ? "x2" :
3491 (lane_width == 3) ? "x4" :
3492 (lane_width == 4) ? "x8" :
3493 (lane_width == 5) ? "x12" :
3494 (lane_width == 6) ? "x16" :
3495 "",
3496 pptable->LclkFreq[i],
3497 (current_gen_speed == gen_speed) &&
3498 (current_lane_width ==
3499 lane_width) ?
3500 "*" :
3501 "");
3502 }
3503 break;
3504
3505 case OD_SCLK:
3506 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
3507 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
3508 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
3509 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
3510 od_table->GfxclkFmin);
3511 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
3512 od_table->GfxclkFmax);
3513 }
3514 break;
3515
3516 case OD_MCLK:
3517 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
3518 size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK");
3519 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
3520 od_table->UclkFmax);
3521 }
3522
3523 break;
3524
3525 case OD_VDDC_CURVE:
3526 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3527 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3528 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3529 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3530 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3531 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
3532 size += sysfs_emit_at(buf, size, "%s:\n",
3533 "OD_VDDC_CURVE");
3534 size += sysfs_emit_at(buf, size, "0: %10uMhz %10dmV\n",
3535 od_table->GfxclkFreq1,
3536 od_table->GfxclkVolt1 /
3537 VOLTAGE_SCALE);
3538 size += sysfs_emit_at(buf, size, "1: %10uMhz %10dmV\n",
3539 od_table->GfxclkFreq2,
3540 od_table->GfxclkVolt2 /
3541 VOLTAGE_SCALE);
3542 size += sysfs_emit_at(buf, size, "2: %10uMhz %10dmV\n",
3543 od_table->GfxclkFreq3,
3544 od_table->GfxclkVolt3 /
3545 VOLTAGE_SCALE);
3546 }
3547
3548 break;
3549
3550 case OD_RANGE:
3551 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
3552
3553 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
3554 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
3555 size += sysfs_emit_at(
3556 buf, size, "SCLK: %7uMhz %10uMhz\n",
3557 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
3558 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
3559 }
3560
3561 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
3562 size += sysfs_emit_at(
3563 buf, size, "MCLK: %7uMhz %10uMhz\n",
3564 od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
3565 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
3566 }
3567
3568 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3569 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3570 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3571 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3572 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3573 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
3574 size += sysfs_emit_at(
3575 buf, size,
3576 "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
3577 od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
3578 od8_settings[OD8_SETTING_GFXCLK_FREQ1]
3579 .max_value);
3580 size += sysfs_emit_at(
3581 buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
3582 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1]
3583 .min_value,
3584 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1]
3585 .max_value);
3586 size += sysfs_emit_at(
3587 buf, size,
3588 "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
3589 od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
3590 od8_settings[OD8_SETTING_GFXCLK_FREQ2]
3591 .max_value);
3592 size += sysfs_emit_at(
3593 buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
3594 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2]
3595 .min_value,
3596 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2]
3597 .max_value);
3598 size += sysfs_emit_at(
3599 buf, size,
3600 "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
3601 od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
3602 od8_settings[OD8_SETTING_GFXCLK_FREQ3]
3603 .max_value);
3604 size += sysfs_emit_at(
3605 buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
3606 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3]
3607 .min_value,
3608 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3]
3609 .max_value);
3610 }
3611
3612 break;
3613 default:
3614 break;
3615 }
3616
3617 *offset = size;
3618
3619 return 0;
3620 }
3621
vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr * hwmgr,struct vega20_single_dpm_table * dpm_table)3622 static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
3623 struct vega20_single_dpm_table *dpm_table)
3624 {
3625 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3626 int ret = 0;
3627
3628 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
3629 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
3630 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
3631 return -EINVAL);
3632 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
3633 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
3634 return -EINVAL);
3635
3636 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3637 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
3638 PPSMC_MSG_SetHardMinByFreq,
3639 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level,
3640 NULL)),
3641 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
3642 return ret);
3643 }
3644
3645 return ret;
3646 }
3647
vega20_set_fclk_to_highest_dpm_level(struct pp_hwmgr * hwmgr)3648 static int vega20_set_fclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr)
3649 {
3650 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3651 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.fclk_table);
3652 int ret = 0;
3653
3654 if (data->smu_features[GNLD_DPM_FCLK].enabled) {
3655 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
3656 "[SetFclkToHightestDpmLevel] Dpm table has no entry!",
3657 return -EINVAL);
3658 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_FCLK_DPM_LEVELS,
3659 "[SetFclkToHightestDpmLevel] Dpm table has too many entries!",
3660 return -EINVAL);
3661
3662 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3663 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
3664 PPSMC_MSG_SetSoftMinByFreq,
3665 (PPCLK_FCLK << 16) | dpm_table->dpm_state.soft_min_level,
3666 NULL)),
3667 "[SetFclkToHightestDpmLevel] Set soft min fclk failed!",
3668 return ret);
3669 }
3670
3671 return ret;
3672 }
3673
vega20_pre_display_configuration_changed_task(struct pp_hwmgr * hwmgr)3674 static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
3675 {
3676 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3677 int ret = 0;
3678
3679 smum_send_msg_to_smc_with_parameter(hwmgr,
3680 PPSMC_MSG_NumOfDisplays, 0, NULL);
3681
3682 ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
3683 &data->dpm_table.mem_table);
3684 if (ret)
3685 return ret;
3686
3687 return vega20_set_fclk_to_highest_dpm_level(hwmgr);
3688 }
3689
vega20_display_configuration_changed_task(struct pp_hwmgr * hwmgr)3690 static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
3691 {
3692 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3693 int result = 0;
3694 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
3695
3696 if ((data->water_marks_bitmap & WaterMarksExist) &&
3697 !(data->water_marks_bitmap & WaterMarksLoaded)) {
3698 result = smum_smc_table_manager(hwmgr,
3699 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
3700 PP_ASSERT_WITH_CODE(!result,
3701 "Failed to update WMTABLE!",
3702 return result);
3703 data->water_marks_bitmap |= WaterMarksLoaded;
3704 }
3705
3706 if ((data->water_marks_bitmap & WaterMarksExist) &&
3707 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
3708 data->smu_features[GNLD_DPM_SOCCLK].supported) {
3709 result = smum_send_msg_to_smc_with_parameter(hwmgr,
3710 PPSMC_MSG_NumOfDisplays,
3711 hwmgr->display_config->num_display,
3712 NULL);
3713 }
3714
3715 return result;
3716 }
3717
vega20_enable_disable_uvd_dpm(struct pp_hwmgr * hwmgr,bool enable)3718 static int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
3719 {
3720 struct vega20_hwmgr *data =
3721 (struct vega20_hwmgr *)(hwmgr->backend);
3722 int ret = 0;
3723
3724 if (data->smu_features[GNLD_DPM_UVD].supported) {
3725 if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {
3726 if (enable)
3727 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n");
3728 else
3729 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n");
3730 }
3731
3732 ret = vega20_enable_smc_features(hwmgr,
3733 enable,
3734 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap);
3735 PP_ASSERT_WITH_CODE(!ret,
3736 "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!",
3737 return ret);
3738 data->smu_features[GNLD_DPM_UVD].enabled = enable;
3739 }
3740
3741 return 0;
3742 }
3743
vega20_power_gate_vce(struct pp_hwmgr * hwmgr,bool bgate)3744 static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
3745 {
3746 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3747
3748 if (data->vce_power_gated == bgate)
3749 return ;
3750
3751 data->vce_power_gated = bgate;
3752 if (bgate) {
3753 vega20_enable_disable_vce_dpm(hwmgr, !bgate);
3754 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
3755 AMD_IP_BLOCK_TYPE_VCE,
3756 AMD_PG_STATE_GATE);
3757 } else {
3758 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
3759 AMD_IP_BLOCK_TYPE_VCE,
3760 AMD_PG_STATE_UNGATE);
3761 vega20_enable_disable_vce_dpm(hwmgr, !bgate);
3762 }
3763
3764 }
3765
vega20_power_gate_uvd(struct pp_hwmgr * hwmgr,bool bgate)3766 static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
3767 {
3768 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3769
3770 if (data->uvd_power_gated == bgate)
3771 return ;
3772
3773 data->uvd_power_gated = bgate;
3774 vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
3775 }
3776
vega20_apply_clocks_adjust_rules(struct pp_hwmgr * hwmgr)3777 static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
3778 {
3779 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3780 struct vega20_single_dpm_table *dpm_table;
3781 bool vblank_too_short = false;
3782 bool disable_mclk_switching;
3783 bool disable_fclk_switching;
3784 uint32_t i, latency;
3785
3786 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3787 !hwmgr->display_config->multi_monitor_in_sync) ||
3788 vblank_too_short;
3789 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3790
3791 /* gfxclk */
3792 dpm_table = &(data->dpm_table.gfx_table);
3793 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3794 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3795 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3796 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3797
3798 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3799 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
3800 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3801 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3802 }
3803
3804 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3805 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3806 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3807 }
3808
3809 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3810 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3811 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3812 }
3813 }
3814
3815 /* memclk */
3816 dpm_table = &(data->dpm_table.mem_table);
3817 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3818 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3819 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3820 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3821
3822 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3823 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
3824 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3825 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3826 }
3827
3828 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3829 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3830 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3831 }
3832
3833 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3834 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3835 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3836 }
3837 }
3838
3839 /* honour DAL's UCLK Hardmin */
3840 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
3841 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
3842
3843 /* Hardmin is dependent on displayconfig */
3844 if (disable_mclk_switching) {
3845 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3846 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
3847 if (data->mclk_latency_table.entries[i].latency <= latency) {
3848 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
3849 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
3850 break;
3851 }
3852 }
3853 }
3854 }
3855
3856 if (hwmgr->display_config->nb_pstate_switch_disable)
3857 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3858
3859 if ((disable_mclk_switching &&
3860 (dpm_table->dpm_state.hard_min_level == dpm_table->dpm_levels[dpm_table->count - 1].value)) ||
3861 hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].value)
3862 disable_fclk_switching = true;
3863 else
3864 disable_fclk_switching = false;
3865
3866 /* fclk */
3867 dpm_table = &(data->dpm_table.fclk_table);
3868 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3869 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3870 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3871 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3872 if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching)
3873 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3874
3875 /* vclk */
3876 dpm_table = &(data->dpm_table.vclk_table);
3877 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3878 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3879 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3880 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3881
3882 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3883 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3884 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3885 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3886 }
3887
3888 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3889 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3890 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3891 }
3892 }
3893
3894 /* dclk */
3895 dpm_table = &(data->dpm_table.dclk_table);
3896 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3897 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3898 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3899 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3900
3901 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3902 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3903 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3904 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3905 }
3906
3907 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3908 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3909 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3910 }
3911 }
3912
3913 /* socclk */
3914 dpm_table = &(data->dpm_table.soc_table);
3915 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3916 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3917 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3918 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3919
3920 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3921 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
3922 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3923 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3924 }
3925
3926 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3927 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3928 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3929 }
3930 }
3931
3932 /* eclk */
3933 dpm_table = &(data->dpm_table.eclk_table);
3934 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3935 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3936 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3937 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3938
3939 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3940 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
3941 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3942 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3943 }
3944
3945 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3946 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3947 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3948 }
3949 }
3950
3951 return 0;
3952 }
3953
3954 static bool
vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr * hwmgr)3955 vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3956 {
3957 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3958 bool is_update_required = false;
3959
3960 if (data->display_timing.num_existing_displays !=
3961 hwmgr->display_config->num_display)
3962 is_update_required = true;
3963
3964 if (data->registry_data.gfx_clk_deep_sleep_support &&
3965 (data->display_timing.min_clock_in_sr !=
3966 hwmgr->display_config->min_core_set_clock_in_sr))
3967 is_update_required = true;
3968
3969 return is_update_required;
3970 }
3971
vega20_disable_dpm_tasks(struct pp_hwmgr * hwmgr)3972 static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
3973 {
3974 int ret = 0;
3975
3976 ret = vega20_disable_all_smu_features(hwmgr);
3977 PP_ASSERT_WITH_CODE(!ret,
3978 "[DisableDpmTasks] Failed to disable all smu features!",
3979 return ret);
3980
3981 return 0;
3982 }
3983
vega20_power_off_asic(struct pp_hwmgr * hwmgr)3984 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
3985 {
3986 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3987 int result;
3988
3989 result = vega20_disable_dpm_tasks(hwmgr);
3990 PP_ASSERT_WITH_CODE((0 == result),
3991 "[PowerOffAsic] Failed to disable DPM!",
3992 );
3993 data->water_marks_bitmap &= ~(WaterMarksLoaded);
3994
3995 return result;
3996 }
3997
conv_power_profile_to_pplib_workload(int power_profile)3998 static int conv_power_profile_to_pplib_workload(int power_profile)
3999 {
4000 int pplib_workload = 0;
4001
4002 switch (power_profile) {
4003 case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
4004 pplib_workload = WORKLOAD_DEFAULT_BIT;
4005 break;
4006 case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
4007 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
4008 break;
4009 case PP_SMC_POWER_PROFILE_POWERSAVING:
4010 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
4011 break;
4012 case PP_SMC_POWER_PROFILE_VIDEO:
4013 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
4014 break;
4015 case PP_SMC_POWER_PROFILE_VR:
4016 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
4017 break;
4018 case PP_SMC_POWER_PROFILE_COMPUTE:
4019 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
4020 break;
4021 case PP_SMC_POWER_PROFILE_CUSTOM:
4022 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
4023 break;
4024 }
4025
4026 return pplib_workload;
4027 }
4028
vega20_get_power_profile_mode(struct pp_hwmgr * hwmgr,char * buf)4029 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
4030 {
4031 DpmActivityMonitorCoeffInt_t activity_monitor;
4032 uint32_t i, size = 0;
4033 uint16_t workload_type = 0;
4034 static const char *title[] = {
4035 "PROFILE_INDEX(NAME)",
4036 "CLOCK_TYPE(NAME)",
4037 "FPS",
4038 "UseRlcBusy",
4039 "MinActiveFreqType",
4040 "MinActiveFreq",
4041 "BoosterFreqType",
4042 "BoosterFreq",
4043 "PD_Data_limit_c",
4044 "PD_Data_error_coeff",
4045 "PD_Data_error_rate_coeff"};
4046 int result = 0;
4047
4048 if (!buf)
4049 return -EINVAL;
4050
4051 phm_get_sysfs_buf(&buf, &size);
4052
4053 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
4054 title[0], title[1], title[2], title[3], title[4], title[5],
4055 title[6], title[7], title[8], title[9], title[10]);
4056
4057 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
4058 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
4059 workload_type = conv_power_profile_to_pplib_workload(i);
4060 result = vega20_get_activity_monitor_coeff(hwmgr,
4061 (uint8_t *)(&activity_monitor), workload_type);
4062 PP_ASSERT_WITH_CODE(!result,
4063 "[GetPowerProfile] Failed to get activity monitor!",
4064 return result);
4065
4066 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
4067 i, amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");
4068
4069 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
4070 " ",
4071 0,
4072 "GFXCLK",
4073 activity_monitor.Gfx_FPS,
4074 activity_monitor.Gfx_UseRlcBusy,
4075 activity_monitor.Gfx_MinActiveFreqType,
4076 activity_monitor.Gfx_MinActiveFreq,
4077 activity_monitor.Gfx_BoosterFreqType,
4078 activity_monitor.Gfx_BoosterFreq,
4079 activity_monitor.Gfx_PD_Data_limit_c,
4080 activity_monitor.Gfx_PD_Data_error_coeff,
4081 activity_monitor.Gfx_PD_Data_error_rate_coeff);
4082
4083 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
4084 " ",
4085 1,
4086 "SOCCLK",
4087 activity_monitor.Soc_FPS,
4088 activity_monitor.Soc_UseRlcBusy,
4089 activity_monitor.Soc_MinActiveFreqType,
4090 activity_monitor.Soc_MinActiveFreq,
4091 activity_monitor.Soc_BoosterFreqType,
4092 activity_monitor.Soc_BoosterFreq,
4093 activity_monitor.Soc_PD_Data_limit_c,
4094 activity_monitor.Soc_PD_Data_error_coeff,
4095 activity_monitor.Soc_PD_Data_error_rate_coeff);
4096
4097 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
4098 " ",
4099 2,
4100 "UCLK",
4101 activity_monitor.Mem_FPS,
4102 activity_monitor.Mem_UseRlcBusy,
4103 activity_monitor.Mem_MinActiveFreqType,
4104 activity_monitor.Mem_MinActiveFreq,
4105 activity_monitor.Mem_BoosterFreqType,
4106 activity_monitor.Mem_BoosterFreq,
4107 activity_monitor.Mem_PD_Data_limit_c,
4108 activity_monitor.Mem_PD_Data_error_coeff,
4109 activity_monitor.Mem_PD_Data_error_rate_coeff);
4110
4111 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
4112 " ",
4113 3,
4114 "FCLK",
4115 activity_monitor.Fclk_FPS,
4116 activity_monitor.Fclk_UseRlcBusy,
4117 activity_monitor.Fclk_MinActiveFreqType,
4118 activity_monitor.Fclk_MinActiveFreq,
4119 activity_monitor.Fclk_BoosterFreqType,
4120 activity_monitor.Fclk_BoosterFreq,
4121 activity_monitor.Fclk_PD_Data_limit_c,
4122 activity_monitor.Fclk_PD_Data_error_coeff,
4123 activity_monitor.Fclk_PD_Data_error_rate_coeff);
4124 }
4125
4126 return size;
4127 }
4128
vega20_set_power_profile_mode(struct pp_hwmgr * hwmgr,long * input,uint32_t size)4129 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
4130 {
4131 DpmActivityMonitorCoeffInt_t activity_monitor;
4132 int workload_type, result = 0;
4133 uint32_t power_profile_mode = input[size];
4134
4135 if (power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
4136 pr_err("Invalid power profile mode %d\n", power_profile_mode);
4137 return -EINVAL;
4138 }
4139
4140 if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
4141 struct vega20_hwmgr *data =
4142 (struct vega20_hwmgr *)(hwmgr->backend);
4143
4144 if (size != 10 && size != 0)
4145 return -EINVAL;
4146
4147 if (size == 0 && !data->is_custom_profile_set)
4148 return -EINVAL;
4149
4150 result = vega20_get_activity_monitor_coeff(hwmgr,
4151 (uint8_t *)(&activity_monitor),
4152 WORKLOAD_PPLIB_CUSTOM_BIT);
4153 PP_ASSERT_WITH_CODE(!result,
4154 "[SetPowerProfile] Failed to get activity monitor!",
4155 return result);
4156
4157 /* If size==0, then we want to apply the already-configured
4158 * CUSTOM profile again. Just apply it, since we checked its
4159 * validity above
4160 */
4161 if (size == 0)
4162 goto out;
4163
4164 switch (input[0]) {
4165 case 0: /* Gfxclk */
4166 activity_monitor.Gfx_FPS = input[1];
4167 activity_monitor.Gfx_UseRlcBusy = input[2];
4168 activity_monitor.Gfx_MinActiveFreqType = input[3];
4169 activity_monitor.Gfx_MinActiveFreq = input[4];
4170 activity_monitor.Gfx_BoosterFreqType = input[5];
4171 activity_monitor.Gfx_BoosterFreq = input[6];
4172 activity_monitor.Gfx_PD_Data_limit_c = input[7];
4173 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
4174 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
4175 break;
4176 case 1: /* Socclk */
4177 activity_monitor.Soc_FPS = input[1];
4178 activity_monitor.Soc_UseRlcBusy = input[2];
4179 activity_monitor.Soc_MinActiveFreqType = input[3];
4180 activity_monitor.Soc_MinActiveFreq = input[4];
4181 activity_monitor.Soc_BoosterFreqType = input[5];
4182 activity_monitor.Soc_BoosterFreq = input[6];
4183 activity_monitor.Soc_PD_Data_limit_c = input[7];
4184 activity_monitor.Soc_PD_Data_error_coeff = input[8];
4185 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
4186 break;
4187 case 2: /* Uclk */
4188 activity_monitor.Mem_FPS = input[1];
4189 activity_monitor.Mem_UseRlcBusy = input[2];
4190 activity_monitor.Mem_MinActiveFreqType = input[3];
4191 activity_monitor.Mem_MinActiveFreq = input[4];
4192 activity_monitor.Mem_BoosterFreqType = input[5];
4193 activity_monitor.Mem_BoosterFreq = input[6];
4194 activity_monitor.Mem_PD_Data_limit_c = input[7];
4195 activity_monitor.Mem_PD_Data_error_coeff = input[8];
4196 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
4197 break;
4198 case 3: /* Fclk */
4199 activity_monitor.Fclk_FPS = input[1];
4200 activity_monitor.Fclk_UseRlcBusy = input[2];
4201 activity_monitor.Fclk_MinActiveFreqType = input[3];
4202 activity_monitor.Fclk_MinActiveFreq = input[4];
4203 activity_monitor.Fclk_BoosterFreqType = input[5];
4204 activity_monitor.Fclk_BoosterFreq = input[6];
4205 activity_monitor.Fclk_PD_Data_limit_c = input[7];
4206 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
4207 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
4208 break;
4209 default:
4210 return -EINVAL;
4211 }
4212
4213 result = vega20_set_activity_monitor_coeff(hwmgr,
4214 (uint8_t *)(&activity_monitor),
4215 WORKLOAD_PPLIB_CUSTOM_BIT);
4216 data->is_custom_profile_set = true;
4217 PP_ASSERT_WITH_CODE(!result,
4218 "[SetPowerProfile] Failed to set activity monitor!",
4219 return result);
4220 }
4221
4222 out:
4223 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
4224 workload_type =
4225 conv_power_profile_to_pplib_workload(power_profile_mode);
4226 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
4227 1 << workload_type,
4228 NULL);
4229
4230 hwmgr->power_profile_mode = power_profile_mode;
4231
4232 return 0;
4233 }
4234
vega20_notify_cac_buffer_info(struct pp_hwmgr * hwmgr,uint32_t virtual_addr_low,uint32_t virtual_addr_hi,uint32_t mc_addr_low,uint32_t mc_addr_hi,uint32_t size)4235 static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
4236 uint32_t virtual_addr_low,
4237 uint32_t virtual_addr_hi,
4238 uint32_t mc_addr_low,
4239 uint32_t mc_addr_hi,
4240 uint32_t size)
4241 {
4242 smum_send_msg_to_smc_with_parameter(hwmgr,
4243 PPSMC_MSG_SetSystemVirtualDramAddrHigh,
4244 virtual_addr_hi,
4245 NULL);
4246 smum_send_msg_to_smc_with_parameter(hwmgr,
4247 PPSMC_MSG_SetSystemVirtualDramAddrLow,
4248 virtual_addr_low,
4249 NULL);
4250 smum_send_msg_to_smc_with_parameter(hwmgr,
4251 PPSMC_MSG_DramLogSetDramAddrHigh,
4252 mc_addr_hi,
4253 NULL);
4254
4255 smum_send_msg_to_smc_with_parameter(hwmgr,
4256 PPSMC_MSG_DramLogSetDramAddrLow,
4257 mc_addr_low,
4258 NULL);
4259
4260 smum_send_msg_to_smc_with_parameter(hwmgr,
4261 PPSMC_MSG_DramLogSetDramSize,
4262 size,
4263 NULL);
4264 return 0;
4265 }
4266
vega20_get_thermal_temperature_range(struct pp_hwmgr * hwmgr,struct PP_TemperatureRange * thermal_data)4267 static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
4268 struct PP_TemperatureRange *thermal_data)
4269 {
4270 struct phm_ppt_v3_information *pptable_information =
4271 (struct phm_ppt_v3_information *)hwmgr->pptable;
4272 struct vega20_hwmgr *data =
4273 (struct vega20_hwmgr *)(hwmgr->backend);
4274 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
4275
4276 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
4277
4278 thermal_data->max = pp_table->TedgeLimit *
4279 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4280 thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) *
4281 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4282 thermal_data->hotspot_crit_max = pp_table->ThotspotLimit *
4283 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4284 thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
4285 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4286 thermal_data->mem_crit_max = pp_table->ThbmLimit *
4287 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4288 thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)*
4289 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4290 thermal_data->sw_ctf_threshold = pptable_information->us_software_shutdown_temp *
4291 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4292
4293 return 0;
4294 }
4295
vega20_smu_i2c_bus_access(struct pp_hwmgr * hwmgr,bool acquire)4296 static int vega20_smu_i2c_bus_access(struct pp_hwmgr *hwmgr, bool acquire)
4297 {
4298 int res;
4299
4300 /* I2C bus access can happen very early, when SMU not loaded yet */
4301 if (!vega20_is_smc_ram_running(hwmgr))
4302 return 0;
4303
4304 res = smum_send_msg_to_smc_with_parameter(hwmgr,
4305 (acquire ?
4306 PPSMC_MSG_RequestI2CBus :
4307 PPSMC_MSG_ReleaseI2CBus),
4308 0,
4309 NULL);
4310
4311 PP_ASSERT_WITH_CODE(!res, "[SmuI2CAccessBus] Failed to access bus!", return res);
4312 return res;
4313 }
4314
vega20_set_df_cstate(struct pp_hwmgr * hwmgr,enum pp_df_cstate state)4315 static int vega20_set_df_cstate(struct pp_hwmgr *hwmgr,
4316 enum pp_df_cstate state)
4317 {
4318 int ret;
4319
4320 /* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */
4321 if (hwmgr->smu_version < 0x283200) {
4322 pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n");
4323 return -EINVAL;
4324 }
4325
4326 ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DFCstateControl, state,
4327 NULL);
4328 if (ret)
4329 pr_err("SetDfCstate failed!\n");
4330
4331 return ret;
4332 }
4333
vega20_set_xgmi_pstate(struct pp_hwmgr * hwmgr,uint32_t pstate)4334 static int vega20_set_xgmi_pstate(struct pp_hwmgr *hwmgr,
4335 uint32_t pstate)
4336 {
4337 int ret;
4338
4339 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
4340 PPSMC_MSG_SetXgmiMode,
4341 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
4342 NULL);
4343 if (ret)
4344 pr_err("SetXgmiPstate failed!\n");
4345
4346 return ret;
4347 }
4348
vega20_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 * gpu_metrics)4349 static void vega20_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
4350 {
4351 memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0));
4352
4353 gpu_metrics->common_header.structure_size =
4354 sizeof(struct gpu_metrics_v1_0);
4355 gpu_metrics->common_header.format_revision = 1;
4356 gpu_metrics->common_header.content_revision = 0;
4357
4358 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
4359 }
4360
vega20_get_gpu_metrics(struct pp_hwmgr * hwmgr,void ** table)4361 static ssize_t vega20_get_gpu_metrics(struct pp_hwmgr *hwmgr,
4362 void **table)
4363 {
4364 struct vega20_hwmgr *data =
4365 (struct vega20_hwmgr *)(hwmgr->backend);
4366 struct gpu_metrics_v1_0 *gpu_metrics =
4367 &data->gpu_metrics_table;
4368 SmuMetrics_t metrics;
4369 uint32_t fan_speed_rpm;
4370 int ret;
4371
4372 ret = vega20_get_metrics_table(hwmgr, &metrics, true);
4373 if (ret)
4374 return ret;
4375
4376 vega20_init_gpu_metrics_v1_0(gpu_metrics);
4377
4378 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
4379 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
4380 gpu_metrics->temperature_mem = metrics.TemperatureHBM;
4381 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
4382 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
4383 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
4384
4385 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
4386 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
4387
4388 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
4389
4390 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
4391 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
4392 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
4393
4394 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
4395 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
4396 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
4397 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
4398 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
4399
4400 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
4401
4402 vega20_fan_ctrl_get_fan_speed_rpm(hwmgr, &fan_speed_rpm);
4403 gpu_metrics->current_fan_speed = (uint16_t)fan_speed_rpm;
4404
4405 gpu_metrics->pcie_link_width =
4406 vega20_get_current_pcie_link_width(hwmgr);
4407 gpu_metrics->pcie_link_speed =
4408 vega20_get_current_pcie_link_speed(hwmgr);
4409
4410 *table = (void *)gpu_metrics;
4411
4412 return sizeof(struct gpu_metrics_v1_0);
4413 }
4414
4415 static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
4416 /* init/fini related */
4417 .backend_init = vega20_hwmgr_backend_init,
4418 .backend_fini = vega20_hwmgr_backend_fini,
4419 .asic_setup = vega20_setup_asic_task,
4420 .power_off_asic = vega20_power_off_asic,
4421 .dynamic_state_management_enable = vega20_enable_dpm_tasks,
4422 .dynamic_state_management_disable = vega20_disable_dpm_tasks,
4423 /* power state related */
4424 .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
4425 .pre_display_config_changed = vega20_pre_display_configuration_changed_task,
4426 .display_config_changed = vega20_display_configuration_changed_task,
4427 .check_smc_update_required_for_display_configuration =
4428 vega20_check_smc_update_required_for_display_configuration,
4429 .notify_smc_display_config_after_ps_adjustment =
4430 vega20_notify_smc_display_config_after_ps_adjustment,
4431 /* export to DAL */
4432 .get_sclk = vega20_dpm_get_sclk,
4433 .get_mclk = vega20_dpm_get_mclk,
4434 .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
4435 .get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage,
4436 .set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges,
4437 .display_clock_voltage_request = vega20_display_clock_voltage_request,
4438 .get_performance_level = vega20_get_performance_level,
4439 /* UMD pstate, profile related */
4440 .force_dpm_level = vega20_dpm_force_dpm_level,
4441 .get_power_profile_mode = vega20_get_power_profile_mode,
4442 .set_power_profile_mode = vega20_set_power_profile_mode,
4443 /* od related */
4444 .set_power_limit = vega20_set_power_limit,
4445 .get_sclk_od = vega20_get_sclk_od,
4446 .set_sclk_od = vega20_set_sclk_od,
4447 .get_mclk_od = vega20_get_mclk_od,
4448 .set_mclk_od = vega20_set_mclk_od,
4449 .odn_edit_dpm_table = vega20_odn_edit_dpm_table,
4450 /* for sysfs to retrive/set gfxclk/memclk */
4451 .force_clock_level = vega20_force_clock_level,
4452 .emit_clock_levels = vega20_emit_clock_levels,
4453 .read_sensor = vega20_read_sensor,
4454 .get_ppfeature_status = vega20_get_ppfeature_status,
4455 .set_ppfeature_status = vega20_set_ppfeature_status,
4456 /* powergate related */
4457 .powergate_uvd = vega20_power_gate_uvd,
4458 .powergate_vce = vega20_power_gate_vce,
4459 /* thermal related */
4460 .start_thermal_controller = vega20_start_thermal_controller,
4461 .stop_thermal_controller = vega20_thermal_stop_thermal_controller,
4462 .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
4463 .register_irq_handlers = smu9_register_irq_handlers,
4464 .disable_smc_firmware_ctf = vega20_thermal_disable_alert,
4465 /* fan control related */
4466 .get_fan_speed_pwm = vega20_fan_ctrl_get_fan_speed_pwm,
4467 .set_fan_speed_pwm = vega20_fan_ctrl_set_fan_speed_pwm,
4468 .get_fan_speed_info = vega20_fan_ctrl_get_fan_speed_info,
4469 .get_fan_speed_rpm = vega20_fan_ctrl_get_fan_speed_rpm,
4470 .set_fan_speed_rpm = vega20_fan_ctrl_set_fan_speed_rpm,
4471 .get_fan_control_mode = vega20_get_fan_control_mode,
4472 .set_fan_control_mode = vega20_set_fan_control_mode,
4473 /* smu memory related */
4474 .notify_cac_buffer_info = vega20_notify_cac_buffer_info,
4475 .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost,
4476 /* BACO related */
4477 .get_bamaco_support = vega20_get_bamaco_support,
4478 .get_asic_baco_state = vega20_baco_get_state,
4479 .set_asic_baco_state = vega20_baco_set_state,
4480 .set_mp1_state = vega20_set_mp1_state,
4481 .smu_i2c_bus_access = vega20_smu_i2c_bus_access,
4482 .set_df_cstate = vega20_set_df_cstate,
4483 .set_xgmi_pstate = vega20_set_xgmi_pstate,
4484 .get_gpu_metrics = vega20_get_gpu_metrics,
4485 };
4486
vega20_hwmgr_init(struct pp_hwmgr * hwmgr)4487 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
4488 {
4489 hwmgr->hwmgr_func = &vega20_hwmgr_funcs;
4490 hwmgr->pptable_func = &vega20_pptable_funcs;
4491
4492 return 0;
4493 }
4494