1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Texas Instruments N-Port Ethernet Switch Address Lookup Engine 4 * 5 * Copyright (C) 2012 Texas Instruments 6 * 7 */ 8 #include <linux/bitmap.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/seq_file.h> 15 #include <linux/slab.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/stat.h> 19 #include <linux/sysfs.h> 20 #include <linux/etherdevice.h> 21 22 #include "cpsw_ale.h" 23 24 #define BITMASK(bits) (BIT(bits) - 1) 25 26 /* ALE Registers */ 27 #define ALE_IDVER 0x00 28 #define ALE_STATUS 0x04 29 #define ALE_CONTROL 0x08 30 #define ALE_PRESCALE 0x10 31 #define ALE_AGING_TIMER 0x14 32 #define ALE_UNKNOWNVLAN 0x18 33 #define ALE_TABLE_CONTROL 0x20 34 #define ALE_TABLE 0x34 35 #define ALE_PORTCTL 0x40 36 37 /* ALE NetCP NU switch specific Registers */ 38 #define ALE_UNKNOWNVLAN_MEMBER 0x90 39 #define ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD 0x94 40 #define ALE_UNKNOWNVLAN_REG_MCAST_FLOOD 0x98 41 #define ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS 0x9C 42 #define ALE_VLAN_MASK_MUX(reg) (0xc0 + (0x4 * (reg))) 43 44 #define ALE_POLICER_PORT_OUI 0x100 45 #define ALE_POLICER_DA_SA 0x104 46 #define ALE_POLICER_VLAN 0x108 47 #define ALE_POLICER_ETHERTYPE_IPSA 0x10c 48 #define ALE_POLICER_IPDA 0x110 49 #define ALE_POLICER_PIR 0x118 50 #define ALE_POLICER_CIR 0x11c 51 #define ALE_POLICER_TBL_CTL 0x120 52 #define ALE_POLICER_CTL 0x124 53 #define ALE_POLICER_TEST_CTL 0x128 54 #define ALE_POLICER_HIT_STATUS 0x12c 55 #define ALE_THREAD_DEF 0x134 56 #define ALE_THREAD_CTL 0x138 57 #define ALE_THREAD_VAL 0x13c 58 59 #define ALE_POLICER_TBL_WRITE_ENABLE BIT(31) 60 #define ALE_POLICER_TBL_INDEX_MASK GENMASK(4, 0) 61 62 #define AM65_CPSW_ALE_THREAD_DEF_REG 0x134 63 64 /* ALE_AGING_TIMER */ 65 #define ALE_AGING_TIMER_MASK GENMASK(23, 0) 66 67 #define ALE_RATE_LIMIT_MIN_PPS 1000 68 69 /** 70 * struct ale_entry_fld - The ALE tbl entry field description 71 * @start_bit: field start bit 72 * @num_bits: field bit length 73 * @flags: field flags 74 */ 75 struct ale_entry_fld { 76 u8 start_bit; 77 u8 num_bits; 78 u8 flags; 79 }; 80 81 enum { 82 CPSW_ALE_F_STATUS_REG = BIT(0), /* Status register present */ 83 CPSW_ALE_F_HW_AUTOAGING = BIT(1), /* HW auto aging */ 84 85 CPSW_ALE_F_COUNT 86 }; 87 88 /** 89 * struct cpsw_ale_dev_id - The ALE version/SoC specific configuration 90 * @dev_id: ALE version/SoC id 91 * @features: features supported by ALE 92 * @tbl_entries: number of ALE entries 93 * @reg_fields: pointer to array of register field configuration 94 * @num_fields: number of fields in the reg_fields array 95 * @nu_switch_ale: NU Switch ALE 96 * @vlan_entry_tbl: ALE vlan entry fields description tbl 97 */ 98 struct cpsw_ale_dev_id { 99 const char *dev_id; 100 u32 features; 101 u32 tbl_entries; 102 const struct reg_field *reg_fields; 103 int num_fields; 104 bool nu_switch_ale; 105 const struct ale_entry_fld *vlan_entry_tbl; 106 }; 107 108 #define ALE_TABLE_WRITE BIT(31) 109 110 #define ALE_TYPE_FREE 0 111 #define ALE_TYPE_ADDR 1 112 #define ALE_TYPE_VLAN 2 113 #define ALE_TYPE_VLAN_ADDR 3 114 115 #define ALE_UCAST_PERSISTANT 0 116 #define ALE_UCAST_UNTOUCHED 1 117 #define ALE_UCAST_OUI 2 118 #define ALE_UCAST_TOUCHED 3 119 120 #define ALE_TABLE_SIZE_MULTIPLIER 1024 121 #define ALE_POLICER_SIZE_MULTIPLIER 8 122 123 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) 124 { 125 int idx, idx2, index; 126 u32 hi_val = 0; 127 128 idx = start / 32; 129 idx2 = (start + bits - 1) / 32; 130 /* Check if bits to be fetched exceed a word */ 131 if (idx != idx2) { 132 index = 2 - idx2; /* flip */ 133 hi_val = ale_entry[index] << ((idx2 * 32) - start); 134 } 135 start -= idx * 32; 136 idx = 2 - idx; /* flip */ 137 return (hi_val + (ale_entry[idx] >> start)) & BITMASK(bits); 138 } 139 140 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, 141 u32 value) 142 { 143 int idx, idx2, index; 144 145 value &= BITMASK(bits); 146 idx = start / 32; 147 idx2 = (start + bits - 1) / 32; 148 /* Check if bits to be set exceed a word */ 149 if (idx != idx2) { 150 index = 2 - idx2; /* flip */ 151 ale_entry[index] &= ~(BITMASK(bits + start - (idx2 * 32))); 152 ale_entry[index] |= (value >> ((idx2 * 32) - start)); 153 } 154 start -= idx * 32; 155 idx = 2 - idx; /* flip */ 156 ale_entry[idx] &= ~(BITMASK(bits) << start); 157 ale_entry[idx] |= (value << start); 158 } 159 160 #define DEFINE_ALE_FIELD_GET(name, start, bits) \ 161 static inline int cpsw_ale_get_##name(u32 *ale_entry) \ 162 { \ 163 return cpsw_ale_get_field(ale_entry, start, bits); \ 164 } 165 166 #define DEFINE_ALE_FIELD_SET(name, start, bits) \ 167 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \ 168 { \ 169 cpsw_ale_set_field(ale_entry, start, bits, value); \ 170 } 171 172 #define DEFINE_ALE_FIELD(name, start, bits) \ 173 DEFINE_ALE_FIELD_GET(name, start, bits) \ 174 DEFINE_ALE_FIELD_SET(name, start, bits) 175 176 #define DEFINE_ALE_FIELD1_GET(name, start) \ 177 static inline int cpsw_ale_get_##name(u32 *ale_entry, u32 bits) \ 178 { \ 179 return cpsw_ale_get_field(ale_entry, start, bits); \ 180 } 181 182 #define DEFINE_ALE_FIELD1_SET(name, start) \ 183 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value, \ 184 u32 bits) \ 185 { \ 186 cpsw_ale_set_field(ale_entry, start, bits, value); \ 187 } 188 189 #define DEFINE_ALE_FIELD1(name, start) \ 190 DEFINE_ALE_FIELD1_GET(name, start) \ 191 DEFINE_ALE_FIELD1_SET(name, start) 192 193 enum { 194 ALE_ENT_VID_MEMBER_LIST = 0, 195 ALE_ENT_VID_UNREG_MCAST_MSK, 196 ALE_ENT_VID_REG_MCAST_MSK, 197 ALE_ENT_VID_FORCE_UNTAGGED_MSK, 198 ALE_ENT_VID_UNREG_MCAST_IDX, 199 ALE_ENT_VID_REG_MCAST_IDX, 200 ALE_ENT_VID_LAST, 201 }; 202 203 #define ALE_FLD_ALLOWED BIT(0) 204 #define ALE_FLD_SIZE_PORT_MASK_BITS BIT(1) 205 #define ALE_FLD_SIZE_PORT_NUM_BITS BIT(2) 206 207 #define ALE_ENTRY_FLD(id, start, bits) \ 208 [id] = { \ 209 .start_bit = start, \ 210 .num_bits = bits, \ 211 .flags = ALE_FLD_ALLOWED, \ 212 } 213 214 #define ALE_ENTRY_FLD_DYN_MSK_SIZE(id, start) \ 215 [id] = { \ 216 .start_bit = start, \ 217 .num_bits = 0, \ 218 .flags = ALE_FLD_ALLOWED | \ 219 ALE_FLD_SIZE_PORT_MASK_BITS, \ 220 } 221 222 /* dm814x, am3/am4/am5, k2hk */ 223 static const struct ale_entry_fld vlan_entry_cpsw[ALE_ENT_VID_LAST] = { 224 ALE_ENTRY_FLD(ALE_ENT_VID_MEMBER_LIST, 0, 3), 225 ALE_ENTRY_FLD(ALE_ENT_VID_UNREG_MCAST_MSK, 8, 3), 226 ALE_ENTRY_FLD(ALE_ENT_VID_REG_MCAST_MSK, 16, 3), 227 ALE_ENTRY_FLD(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24, 3), 228 }; 229 230 /* k2e/k2l, k3 am65/j721e cpsw2g */ 231 static const struct ale_entry_fld vlan_entry_nu[ALE_ENT_VID_LAST] = { 232 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_MEMBER_LIST, 0), 233 ALE_ENTRY_FLD(ALE_ENT_VID_UNREG_MCAST_IDX, 20, 3), 234 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24), 235 ALE_ENTRY_FLD(ALE_ENT_VID_REG_MCAST_IDX, 44, 3), 236 }; 237 238 /* K3 j721e/j7200 cpsw9g/5g, am64x cpsw3g */ 239 static const struct ale_entry_fld vlan_entry_k3_cpswxg[] = { 240 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_MEMBER_LIST, 0), 241 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_UNREG_MCAST_MSK, 12), 242 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24), 243 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_REG_MCAST_MSK, 36), 244 }; 245 246 DEFINE_ALE_FIELD(entry_type, 60, 2) 247 DEFINE_ALE_FIELD(vlan_id, 48, 12) 248 DEFINE_ALE_FIELD_SET(mcast_state, 62, 2) 249 DEFINE_ALE_FIELD1(port_mask, 66) 250 DEFINE_ALE_FIELD(super, 65, 1) 251 DEFINE_ALE_FIELD(ucast_type, 62, 2) 252 DEFINE_ALE_FIELD1_SET(port_num, 66) 253 DEFINE_ALE_FIELD_SET(blocked, 65, 1) 254 DEFINE_ALE_FIELD_SET(secure, 64, 1) 255 DEFINE_ALE_FIELD_GET(mcast, 40, 1) 256 257 #define NU_VLAN_UNREG_MCAST_IDX 1 258 259 static int cpsw_ale_entry_get_fld(struct cpsw_ale *ale, 260 u32 *ale_entry, 261 const struct ale_entry_fld *entry_tbl, 262 int fld_id) 263 { 264 const struct ale_entry_fld *entry_fld; 265 u32 bits; 266 267 if (!ale || !ale_entry) 268 return -EINVAL; 269 270 entry_fld = &entry_tbl[fld_id]; 271 if (!(entry_fld->flags & ALE_FLD_ALLOWED)) { 272 dev_err(ale->params.dev, "get: wrong ale fld id %d\n", fld_id); 273 return -ENOENT; 274 } 275 276 bits = entry_fld->num_bits; 277 if (entry_fld->flags & ALE_FLD_SIZE_PORT_MASK_BITS) 278 bits = ale->port_mask_bits; 279 280 return cpsw_ale_get_field(ale_entry, entry_fld->start_bit, bits); 281 } 282 283 static void cpsw_ale_entry_set_fld(struct cpsw_ale *ale, 284 u32 *ale_entry, 285 const struct ale_entry_fld *entry_tbl, 286 int fld_id, 287 u32 value) 288 { 289 const struct ale_entry_fld *entry_fld; 290 u32 bits; 291 292 if (!ale || !ale_entry) 293 return; 294 295 entry_fld = &entry_tbl[fld_id]; 296 if (!(entry_fld->flags & ALE_FLD_ALLOWED)) { 297 dev_err(ale->params.dev, "set: wrong ale fld id %d\n", fld_id); 298 return; 299 } 300 301 bits = entry_fld->num_bits; 302 if (entry_fld->flags & ALE_FLD_SIZE_PORT_MASK_BITS) 303 bits = ale->port_mask_bits; 304 305 cpsw_ale_set_field(ale_entry, entry_fld->start_bit, bits, value); 306 } 307 308 static int cpsw_ale_vlan_get_fld(struct cpsw_ale *ale, 309 u32 *ale_entry, 310 int fld_id) 311 { 312 return cpsw_ale_entry_get_fld(ale, ale_entry, 313 ale->vlan_entry_tbl, fld_id); 314 } 315 316 static void cpsw_ale_vlan_set_fld(struct cpsw_ale *ale, 317 u32 *ale_entry, 318 int fld_id, 319 u32 value) 320 { 321 cpsw_ale_entry_set_fld(ale, ale_entry, 322 ale->vlan_entry_tbl, fld_id, value); 323 } 324 325 /* The MAC address field in the ALE entry cannot be macroized as above */ 326 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr) 327 { 328 int i; 329 330 for (i = 0; i < 6; i++) 331 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8); 332 } 333 334 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr) 335 { 336 int i; 337 338 for (i = 0; i < 6; i++) 339 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]); 340 } 341 342 static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry) 343 { 344 int i; 345 346 WARN_ON(idx > ale->params.ale_entries); 347 348 writel_relaxed(idx, ale->params.ale_regs + ALE_TABLE_CONTROL); 349 350 for (i = 0; i < ALE_ENTRY_WORDS; i++) 351 ale_entry[i] = readl_relaxed(ale->params.ale_regs + 352 ALE_TABLE + 4 * i); 353 354 return idx; 355 } 356 357 static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry) 358 { 359 int i; 360 361 WARN_ON(idx > ale->params.ale_entries); 362 363 for (i = 0; i < ALE_ENTRY_WORDS; i++) 364 writel_relaxed(ale_entry[i], ale->params.ale_regs + 365 ALE_TABLE + 4 * i); 366 367 writel_relaxed(idx | ALE_TABLE_WRITE, ale->params.ale_regs + 368 ALE_TABLE_CONTROL); 369 370 return idx; 371 } 372 373 static int cpsw_ale_match_addr(struct cpsw_ale *ale, const u8 *addr, u16 vid) 374 { 375 u32 ale_entry[ALE_ENTRY_WORDS]; 376 int type, idx; 377 378 for (idx = 0; idx < ale->params.ale_entries; idx++) { 379 u8 entry_addr[6]; 380 381 cpsw_ale_read(ale, idx, ale_entry); 382 type = cpsw_ale_get_entry_type(ale_entry); 383 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 384 continue; 385 if (cpsw_ale_get_vlan_id(ale_entry) != vid) 386 continue; 387 cpsw_ale_get_addr(ale_entry, entry_addr); 388 if (ether_addr_equal(entry_addr, addr)) 389 return idx; 390 } 391 return -ENOENT; 392 } 393 394 static int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid) 395 { 396 u32 ale_entry[ALE_ENTRY_WORDS]; 397 int type, idx; 398 399 for (idx = 0; idx < ale->params.ale_entries; idx++) { 400 cpsw_ale_read(ale, idx, ale_entry); 401 type = cpsw_ale_get_entry_type(ale_entry); 402 if (type != ALE_TYPE_VLAN) 403 continue; 404 if (cpsw_ale_get_vlan_id(ale_entry) == vid) 405 return idx; 406 } 407 return -ENOENT; 408 } 409 410 static int cpsw_ale_match_free(struct cpsw_ale *ale) 411 { 412 u32 ale_entry[ALE_ENTRY_WORDS]; 413 int type, idx; 414 415 for (idx = 0; idx < ale->params.ale_entries; idx++) { 416 cpsw_ale_read(ale, idx, ale_entry); 417 type = cpsw_ale_get_entry_type(ale_entry); 418 if (type == ALE_TYPE_FREE) 419 return idx; 420 } 421 return -ENOENT; 422 } 423 424 static int cpsw_ale_find_ageable(struct cpsw_ale *ale) 425 { 426 u32 ale_entry[ALE_ENTRY_WORDS]; 427 int type, idx; 428 429 for (idx = 0; idx < ale->params.ale_entries; idx++) { 430 cpsw_ale_read(ale, idx, ale_entry); 431 type = cpsw_ale_get_entry_type(ale_entry); 432 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 433 continue; 434 if (cpsw_ale_get_mcast(ale_entry)) 435 continue; 436 type = cpsw_ale_get_ucast_type(ale_entry); 437 if (type != ALE_UCAST_PERSISTANT && 438 type != ALE_UCAST_OUI) 439 return idx; 440 } 441 return -ENOENT; 442 } 443 444 static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry, 445 int port_mask) 446 { 447 int mask; 448 449 mask = cpsw_ale_get_port_mask(ale_entry, 450 ale->port_mask_bits); 451 if ((mask & port_mask) == 0) 452 return; /* ports dont intersect, not interested */ 453 mask &= ~port_mask; 454 455 /* free if only remaining port is host port */ 456 if (mask) 457 cpsw_ale_set_port_mask(ale_entry, mask, 458 ale->port_mask_bits); 459 else 460 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 461 } 462 463 int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid) 464 { 465 u32 ale_entry[ALE_ENTRY_WORDS]; 466 int ret, idx; 467 468 for (idx = 0; idx < ale->params.ale_entries; idx++) { 469 cpsw_ale_read(ale, idx, ale_entry); 470 ret = cpsw_ale_get_entry_type(ale_entry); 471 if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR) 472 continue; 473 474 /* if vid passed is -1 then remove all multicast entry from 475 * the table irrespective of vlan id, if a valid vlan id is 476 * passed then remove only multicast added to that vlan id. 477 * if vlan id doesn't match then move on to next entry. 478 */ 479 if (vid != -1 && cpsw_ale_get_vlan_id(ale_entry) != vid) 480 continue; 481 482 if (cpsw_ale_get_mcast(ale_entry)) { 483 u8 addr[6]; 484 485 if (cpsw_ale_get_super(ale_entry)) 486 continue; 487 488 cpsw_ale_get_addr(ale_entry, addr); 489 if (!is_broadcast_ether_addr(addr)) 490 cpsw_ale_flush_mcast(ale, ale_entry, port_mask); 491 } 492 493 cpsw_ale_write(ale, idx, ale_entry); 494 } 495 return 0; 496 } 497 498 static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry, 499 int flags, u16 vid) 500 { 501 if (flags & ALE_VLAN) { 502 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR); 503 cpsw_ale_set_vlan_id(ale_entry, vid); 504 } else { 505 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 506 } 507 } 508 509 int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port, 510 int flags, u16 vid) 511 { 512 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 513 int idx; 514 515 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid); 516 517 cpsw_ale_set_addr(ale_entry, addr); 518 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT); 519 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0); 520 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0); 521 cpsw_ale_set_port_num(ale_entry, port, ale->port_num_bits); 522 523 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 524 if (idx < 0) 525 idx = cpsw_ale_match_free(ale); 526 if (idx < 0) 527 idx = cpsw_ale_find_ageable(ale); 528 if (idx < 0) 529 return -ENOMEM; 530 531 cpsw_ale_write(ale, idx, ale_entry); 532 return 0; 533 } 534 535 int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port, 536 int flags, u16 vid) 537 { 538 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 539 int idx; 540 541 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 542 if (idx < 0) 543 return -ENOENT; 544 545 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 546 cpsw_ale_write(ale, idx, ale_entry); 547 return 0; 548 } 549 550 int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, 551 int flags, u16 vid, int mcast_state) 552 { 553 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 554 int idx, mask; 555 556 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 557 if (idx >= 0) 558 cpsw_ale_read(ale, idx, ale_entry); 559 560 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid); 561 562 cpsw_ale_set_addr(ale_entry, addr); 563 cpsw_ale_set_super(ale_entry, (flags & ALE_SUPER) ? 1 : 0); 564 cpsw_ale_set_mcast_state(ale_entry, mcast_state); 565 566 mask = cpsw_ale_get_port_mask(ale_entry, 567 ale->port_mask_bits); 568 port_mask |= mask; 569 cpsw_ale_set_port_mask(ale_entry, port_mask, 570 ale->port_mask_bits); 571 572 if (idx < 0) 573 idx = cpsw_ale_match_free(ale); 574 if (idx < 0) 575 idx = cpsw_ale_find_ageable(ale); 576 if (idx < 0) 577 return -ENOMEM; 578 579 cpsw_ale_write(ale, idx, ale_entry); 580 return 0; 581 } 582 583 int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, 584 int flags, u16 vid) 585 { 586 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 587 int mcast_members = 0; 588 int idx; 589 590 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 591 if (idx < 0) 592 return -ENOENT; 593 594 cpsw_ale_read(ale, idx, ale_entry); 595 596 if (port_mask) { 597 mcast_members = cpsw_ale_get_port_mask(ale_entry, 598 ale->port_mask_bits); 599 mcast_members &= ~port_mask; 600 } 601 602 if (mcast_members) 603 cpsw_ale_set_port_mask(ale_entry, mcast_members, 604 ale->port_mask_bits); 605 else 606 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 607 608 cpsw_ale_write(ale, idx, ale_entry); 609 return 0; 610 } 611 612 /* ALE NetCP NU switch specific vlan functions */ 613 static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry, 614 int reg_mcast, int unreg_mcast) 615 { 616 int idx; 617 618 /* Set VLAN registered multicast flood mask */ 619 idx = cpsw_ale_vlan_get_fld(ale, ale_entry, 620 ALE_ENT_VID_REG_MCAST_IDX); 621 writel(reg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 622 623 /* Set VLAN unregistered multicast flood mask */ 624 idx = cpsw_ale_vlan_get_fld(ale, ale_entry, 625 ALE_ENT_VID_UNREG_MCAST_IDX); 626 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 627 } 628 629 static void cpsw_ale_set_vlan_untag(struct cpsw_ale *ale, u32 *ale_entry, 630 u16 vid, int untag_mask) 631 { 632 cpsw_ale_vlan_set_fld(ale, ale_entry, 633 ALE_ENT_VID_FORCE_UNTAGGED_MSK, 634 untag_mask); 635 if (untag_mask & ALE_PORT_HOST) 636 bitmap_set(ale->p0_untag_vid_mask, vid, 1); 637 else 638 bitmap_clear(ale->p0_untag_vid_mask, vid, 1); 639 } 640 641 int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag, 642 int reg_mcast, int unreg_mcast) 643 { 644 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 645 int idx; 646 647 idx = cpsw_ale_match_vlan(ale, vid); 648 if (idx >= 0) 649 cpsw_ale_read(ale, idx, ale_entry); 650 651 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN); 652 cpsw_ale_set_vlan_id(ale_entry, vid); 653 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag); 654 655 if (!ale->params.nu_switch_ale) { 656 cpsw_ale_vlan_set_fld(ale, ale_entry, 657 ALE_ENT_VID_REG_MCAST_MSK, reg_mcast); 658 cpsw_ale_vlan_set_fld(ale, ale_entry, 659 ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast); 660 } else { 661 cpsw_ale_vlan_set_fld(ale, ale_entry, 662 ALE_ENT_VID_UNREG_MCAST_IDX, 663 NU_VLAN_UNREG_MCAST_IDX); 664 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, unreg_mcast); 665 } 666 667 cpsw_ale_vlan_set_fld(ale, ale_entry, 668 ALE_ENT_VID_MEMBER_LIST, port_mask); 669 670 if (idx < 0) 671 idx = cpsw_ale_match_free(ale); 672 if (idx < 0) 673 idx = cpsw_ale_find_ageable(ale); 674 if (idx < 0) 675 return -ENOMEM; 676 677 cpsw_ale_write(ale, idx, ale_entry); 678 return 0; 679 } 680 681 static void cpsw_ale_vlan_del_modify_int(struct cpsw_ale *ale, u32 *ale_entry, 682 u16 vid, int port_mask) 683 { 684 int reg_mcast, unreg_mcast; 685 int members, untag; 686 687 members = cpsw_ale_vlan_get_fld(ale, ale_entry, 688 ALE_ENT_VID_MEMBER_LIST); 689 members &= ~port_mask; 690 if (!members) { 691 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0); 692 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 693 return; 694 } 695 696 untag = cpsw_ale_vlan_get_fld(ale, ale_entry, 697 ALE_ENT_VID_FORCE_UNTAGGED_MSK); 698 reg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry, 699 ALE_ENT_VID_REG_MCAST_MSK); 700 unreg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry, 701 ALE_ENT_VID_UNREG_MCAST_MSK); 702 untag &= members; 703 reg_mcast &= members; 704 unreg_mcast &= members; 705 706 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag); 707 708 if (!ale->params.nu_switch_ale) { 709 cpsw_ale_vlan_set_fld(ale, ale_entry, 710 ALE_ENT_VID_REG_MCAST_MSK, reg_mcast); 711 cpsw_ale_vlan_set_fld(ale, ale_entry, 712 ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast); 713 } else { 714 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, 715 unreg_mcast); 716 } 717 cpsw_ale_vlan_set_fld(ale, ale_entry, 718 ALE_ENT_VID_MEMBER_LIST, members); 719 } 720 721 int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask) 722 { 723 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 724 int idx; 725 726 idx = cpsw_ale_match_vlan(ale, vid); 727 if (idx < 0) 728 return -ENOENT; 729 730 cpsw_ale_read(ale, idx, ale_entry); 731 732 cpsw_ale_vlan_del_modify_int(ale, ale_entry, vid, port_mask); 733 cpsw_ale_write(ale, idx, ale_entry); 734 735 return 0; 736 } 737 738 int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask) 739 { 740 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 741 int members, idx; 742 743 idx = cpsw_ale_match_vlan(ale, vid); 744 if (idx < 0) 745 return -ENOENT; 746 747 cpsw_ale_read(ale, idx, ale_entry); 748 749 /* if !port_mask - force remove VLAN (legacy). 750 * Check if there are other VLAN members ports 751 * if no - remove VLAN. 752 * if yes it means same VLAN was added to >1 port in multi port mode, so 753 * remove port_mask ports from VLAN ALE entry excluding Host port. 754 */ 755 members = cpsw_ale_vlan_get_fld(ale, ale_entry, ALE_ENT_VID_MEMBER_LIST); 756 members &= ~port_mask; 757 758 if (!port_mask || !members) { 759 /* last port or force remove - remove VLAN */ 760 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0); 761 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 762 } else { 763 port_mask &= ~ALE_PORT_HOST; 764 cpsw_ale_vlan_del_modify_int(ale, ale_entry, vid, port_mask); 765 } 766 767 cpsw_ale_write(ale, idx, ale_entry); 768 769 return 0; 770 } 771 772 int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, 773 int untag_mask, int reg_mask, int unreg_mask) 774 { 775 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 776 int reg_mcast_members, unreg_mcast_members; 777 int vlan_members, untag_members; 778 int idx, ret = 0; 779 780 idx = cpsw_ale_match_vlan(ale, vid); 781 if (idx >= 0) 782 cpsw_ale_read(ale, idx, ale_entry); 783 784 vlan_members = cpsw_ale_vlan_get_fld(ale, ale_entry, 785 ALE_ENT_VID_MEMBER_LIST); 786 reg_mcast_members = cpsw_ale_vlan_get_fld(ale, ale_entry, 787 ALE_ENT_VID_REG_MCAST_MSK); 788 unreg_mcast_members = 789 cpsw_ale_vlan_get_fld(ale, ale_entry, 790 ALE_ENT_VID_UNREG_MCAST_MSK); 791 untag_members = cpsw_ale_vlan_get_fld(ale, ale_entry, 792 ALE_ENT_VID_FORCE_UNTAGGED_MSK); 793 794 vlan_members |= port_mask; 795 untag_members = (untag_members & ~port_mask) | untag_mask; 796 reg_mcast_members = (reg_mcast_members & ~port_mask) | reg_mask; 797 unreg_mcast_members = (unreg_mcast_members & ~port_mask) | unreg_mask; 798 799 ret = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members, 800 reg_mcast_members, unreg_mcast_members); 801 if (ret) { 802 dev_err(ale->params.dev, "Unable to add vlan\n"); 803 return ret; 804 } 805 dev_dbg(ale->params.dev, "port mask 0x%x untag 0x%x\n", vlan_members, 806 untag_mask); 807 808 return ret; 809 } 810 811 void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, 812 bool add) 813 { 814 u32 ale_entry[ALE_ENTRY_WORDS]; 815 int unreg_members = 0; 816 int type, idx; 817 818 for (idx = 0; idx < ale->params.ale_entries; idx++) { 819 cpsw_ale_read(ale, idx, ale_entry); 820 type = cpsw_ale_get_entry_type(ale_entry); 821 if (type != ALE_TYPE_VLAN) 822 continue; 823 824 unreg_members = 825 cpsw_ale_vlan_get_fld(ale, ale_entry, 826 ALE_ENT_VID_UNREG_MCAST_MSK); 827 if (add) 828 unreg_members |= unreg_mcast_mask; 829 else 830 unreg_members &= ~unreg_mcast_mask; 831 cpsw_ale_vlan_set_fld(ale, ale_entry, 832 ALE_ENT_VID_UNREG_MCAST_MSK, 833 unreg_members); 834 cpsw_ale_write(ale, idx, ale_entry); 835 } 836 } 837 838 static void cpsw_ale_vlan_set_unreg_mcast(struct cpsw_ale *ale, u32 *ale_entry, 839 int allmulti) 840 { 841 int unreg_mcast; 842 843 unreg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry, 844 ALE_ENT_VID_UNREG_MCAST_MSK); 845 if (allmulti) 846 unreg_mcast |= ALE_PORT_HOST; 847 else 848 unreg_mcast &= ~ALE_PORT_HOST; 849 850 cpsw_ale_vlan_set_fld(ale, ale_entry, 851 ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast); 852 } 853 854 static void 855 cpsw_ale_vlan_set_unreg_mcast_idx(struct cpsw_ale *ale, u32 *ale_entry, 856 int allmulti) 857 { 858 int unreg_mcast; 859 int idx; 860 861 idx = cpsw_ale_vlan_get_fld(ale, ale_entry, 862 ALE_ENT_VID_UNREG_MCAST_IDX); 863 864 unreg_mcast = readl(ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 865 866 if (allmulti) 867 unreg_mcast |= ALE_PORT_HOST; 868 else 869 unreg_mcast &= ~ALE_PORT_HOST; 870 871 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 872 } 873 874 void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port) 875 { 876 u32 ale_entry[ALE_ENTRY_WORDS]; 877 int type, idx; 878 879 for (idx = 0; idx < ale->params.ale_entries; idx++) { 880 int vlan_members; 881 882 cpsw_ale_read(ale, idx, ale_entry); 883 type = cpsw_ale_get_entry_type(ale_entry); 884 if (type != ALE_TYPE_VLAN) 885 continue; 886 887 vlan_members = cpsw_ale_vlan_get_fld(ale, ale_entry, 888 ALE_ENT_VID_MEMBER_LIST); 889 890 if (port != -1 && !(vlan_members & BIT(port))) 891 continue; 892 893 if (!ale->params.nu_switch_ale) 894 cpsw_ale_vlan_set_unreg_mcast(ale, ale_entry, allmulti); 895 else 896 cpsw_ale_vlan_set_unreg_mcast_idx(ale, ale_entry, 897 allmulti); 898 899 cpsw_ale_write(ale, idx, ale_entry); 900 } 901 } 902 903 struct ale_control_info { 904 const char *name; 905 int offset, port_offset; 906 int shift, port_shift; 907 int bits; 908 }; 909 910 static struct ale_control_info ale_controls[ALE_NUM_CONTROLS] = { 911 [ALE_ENABLE] = { 912 .name = "enable", 913 .offset = ALE_CONTROL, 914 .port_offset = 0, 915 .shift = 31, 916 .port_shift = 0, 917 .bits = 1, 918 }, 919 [ALE_CLEAR] = { 920 .name = "clear", 921 .offset = ALE_CONTROL, 922 .port_offset = 0, 923 .shift = 30, 924 .port_shift = 0, 925 .bits = 1, 926 }, 927 [ALE_AGEOUT] = { 928 .name = "ageout", 929 .offset = ALE_CONTROL, 930 .port_offset = 0, 931 .shift = 29, 932 .port_shift = 0, 933 .bits = 1, 934 }, 935 [ALE_P0_UNI_FLOOD] = { 936 .name = "port0_unicast_flood", 937 .offset = ALE_CONTROL, 938 .port_offset = 0, 939 .shift = 8, 940 .port_shift = 0, 941 .bits = 1, 942 }, 943 [ALE_VLAN_NOLEARN] = { 944 .name = "vlan_nolearn", 945 .offset = ALE_CONTROL, 946 .port_offset = 0, 947 .shift = 7, 948 .port_shift = 0, 949 .bits = 1, 950 }, 951 [ALE_NO_PORT_VLAN] = { 952 .name = "no_port_vlan", 953 .offset = ALE_CONTROL, 954 .port_offset = 0, 955 .shift = 6, 956 .port_shift = 0, 957 .bits = 1, 958 }, 959 [ALE_OUI_DENY] = { 960 .name = "oui_deny", 961 .offset = ALE_CONTROL, 962 .port_offset = 0, 963 .shift = 5, 964 .port_shift = 0, 965 .bits = 1, 966 }, 967 [ALE_BYPASS] = { 968 .name = "bypass", 969 .offset = ALE_CONTROL, 970 .port_offset = 0, 971 .shift = 4, 972 .port_shift = 0, 973 .bits = 1, 974 }, 975 [ALE_RATE_LIMIT_TX] = { 976 .name = "rate_limit_tx", 977 .offset = ALE_CONTROL, 978 .port_offset = 0, 979 .shift = 3, 980 .port_shift = 0, 981 .bits = 1, 982 }, 983 [ALE_VLAN_AWARE] = { 984 .name = "vlan_aware", 985 .offset = ALE_CONTROL, 986 .port_offset = 0, 987 .shift = 2, 988 .port_shift = 0, 989 .bits = 1, 990 }, 991 [ALE_AUTH_ENABLE] = { 992 .name = "auth_enable", 993 .offset = ALE_CONTROL, 994 .port_offset = 0, 995 .shift = 1, 996 .port_shift = 0, 997 .bits = 1, 998 }, 999 [ALE_RATE_LIMIT] = { 1000 .name = "rate_limit", 1001 .offset = ALE_CONTROL, 1002 .port_offset = 0, 1003 .shift = 0, 1004 .port_shift = 0, 1005 .bits = 1, 1006 }, 1007 [ALE_PORT_STATE] = { 1008 .name = "port_state", 1009 .offset = ALE_PORTCTL, 1010 .port_offset = 4, 1011 .shift = 0, 1012 .port_shift = 0, 1013 .bits = 2, 1014 }, 1015 [ALE_PORT_DROP_UNTAGGED] = { 1016 .name = "drop_untagged", 1017 .offset = ALE_PORTCTL, 1018 .port_offset = 4, 1019 .shift = 2, 1020 .port_shift = 0, 1021 .bits = 1, 1022 }, 1023 [ALE_PORT_DROP_UNKNOWN_VLAN] = { 1024 .name = "drop_unknown", 1025 .offset = ALE_PORTCTL, 1026 .port_offset = 4, 1027 .shift = 3, 1028 .port_shift = 0, 1029 .bits = 1, 1030 }, 1031 [ALE_PORT_NOLEARN] = { 1032 .name = "nolearn", 1033 .offset = ALE_PORTCTL, 1034 .port_offset = 4, 1035 .shift = 4, 1036 .port_shift = 0, 1037 .bits = 1, 1038 }, 1039 [ALE_PORT_NO_SA_UPDATE] = { 1040 .name = "no_source_update", 1041 .offset = ALE_PORTCTL, 1042 .port_offset = 4, 1043 .shift = 5, 1044 .port_shift = 0, 1045 .bits = 1, 1046 }, 1047 [ALE_PORT_MACONLY] = { 1048 .name = "mac_only_port_mode", 1049 .offset = ALE_PORTCTL, 1050 .port_offset = 4, 1051 .shift = 11, 1052 .port_shift = 0, 1053 .bits = 1, 1054 }, 1055 [ALE_PORT_MACONLY_CAF] = { 1056 .name = "mac_only_port_caf", 1057 .offset = ALE_PORTCTL, 1058 .port_offset = 4, 1059 .shift = 13, 1060 .port_shift = 0, 1061 .bits = 1, 1062 }, 1063 [ALE_PORT_MCAST_LIMIT] = { 1064 .name = "mcast_limit", 1065 .offset = ALE_PORTCTL, 1066 .port_offset = 4, 1067 .shift = 16, 1068 .port_shift = 0, 1069 .bits = 8, 1070 }, 1071 [ALE_PORT_BCAST_LIMIT] = { 1072 .name = "bcast_limit", 1073 .offset = ALE_PORTCTL, 1074 .port_offset = 4, 1075 .shift = 24, 1076 .port_shift = 0, 1077 .bits = 8, 1078 }, 1079 [ALE_PORT_UNKNOWN_VLAN_MEMBER] = { 1080 .name = "unknown_vlan_member", 1081 .offset = ALE_UNKNOWNVLAN, 1082 .port_offset = 0, 1083 .shift = 0, 1084 .port_shift = 0, 1085 .bits = 6, 1086 }, 1087 [ALE_PORT_UNKNOWN_MCAST_FLOOD] = { 1088 .name = "unknown_mcast_flood", 1089 .offset = ALE_UNKNOWNVLAN, 1090 .port_offset = 0, 1091 .shift = 8, 1092 .port_shift = 0, 1093 .bits = 6, 1094 }, 1095 [ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = { 1096 .name = "unknown_reg_flood", 1097 .offset = ALE_UNKNOWNVLAN, 1098 .port_offset = 0, 1099 .shift = 16, 1100 .port_shift = 0, 1101 .bits = 6, 1102 }, 1103 [ALE_PORT_UNTAGGED_EGRESS] = { 1104 .name = "untagged_egress", 1105 .offset = ALE_UNKNOWNVLAN, 1106 .port_offset = 0, 1107 .shift = 24, 1108 .port_shift = 0, 1109 .bits = 6, 1110 }, 1111 [ALE_DEFAULT_THREAD_ID] = { 1112 .name = "default_thread_id", 1113 .offset = AM65_CPSW_ALE_THREAD_DEF_REG, 1114 .port_offset = 0, 1115 .shift = 0, 1116 .port_shift = 0, 1117 .bits = 6, 1118 }, 1119 [ALE_DEFAULT_THREAD_ENABLE] = { 1120 .name = "default_thread_id_enable", 1121 .offset = AM65_CPSW_ALE_THREAD_DEF_REG, 1122 .port_offset = 0, 1123 .shift = 15, 1124 .port_shift = 0, 1125 .bits = 1, 1126 }, 1127 }; 1128 1129 int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control, 1130 int value) 1131 { 1132 const struct ale_control_info *info; 1133 int offset, shift; 1134 u32 tmp, mask; 1135 1136 if (control < 0 || control >= ARRAY_SIZE(ale_controls)) 1137 return -EINVAL; 1138 1139 info = &ale_controls[control]; 1140 if (info->port_offset == 0 && info->port_shift == 0) 1141 port = 0; /* global, port is a dont care */ 1142 1143 if (port < 0 || port >= ale->params.ale_ports) 1144 return -EINVAL; 1145 1146 mask = BITMASK(info->bits); 1147 if (value & ~mask) 1148 return -EINVAL; 1149 1150 offset = info->offset + (port * info->port_offset); 1151 shift = info->shift + (port * info->port_shift); 1152 1153 tmp = readl_relaxed(ale->params.ale_regs + offset); 1154 tmp = (tmp & ~(mask << shift)) | (value << shift); 1155 writel_relaxed(tmp, ale->params.ale_regs + offset); 1156 1157 return 0; 1158 } 1159 1160 int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control) 1161 { 1162 const struct ale_control_info *info; 1163 int offset, shift; 1164 u32 tmp; 1165 1166 if (control < 0 || control >= ARRAY_SIZE(ale_controls)) 1167 return -EINVAL; 1168 1169 info = &ale_controls[control]; 1170 if (info->port_offset == 0 && info->port_shift == 0) 1171 port = 0; /* global, port is a dont care */ 1172 1173 if (port < 0 || port >= ale->params.ale_ports) 1174 return -EINVAL; 1175 1176 offset = info->offset + (port * info->port_offset); 1177 shift = info->shift + (port * info->port_shift); 1178 1179 tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift; 1180 return tmp & BITMASK(info->bits); 1181 } 1182 1183 int cpsw_ale_rx_ratelimit_mc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps) 1184 1185 { 1186 int val = ratelimit_pps / ALE_RATE_LIMIT_MIN_PPS; 1187 u32 remainder = ratelimit_pps % ALE_RATE_LIMIT_MIN_PPS; 1188 1189 if (ratelimit_pps && !val) { 1190 dev_err(ale->params.dev, "ALE MC port:%d ratelimit min value 1000pps\n", port); 1191 return -EINVAL; 1192 } 1193 1194 if (remainder) 1195 dev_info(ale->params.dev, "ALE port:%d MC ratelimit set to %dpps (requested %d)\n", 1196 port, ratelimit_pps - remainder, ratelimit_pps); 1197 1198 cpsw_ale_control_set(ale, port, ALE_PORT_MCAST_LIMIT, val); 1199 1200 dev_dbg(ale->params.dev, "ALE port:%d MC ratelimit set %d\n", 1201 port, val * ALE_RATE_LIMIT_MIN_PPS); 1202 return 0; 1203 } 1204 1205 int cpsw_ale_rx_ratelimit_bc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps) 1206 1207 { 1208 int val = ratelimit_pps / ALE_RATE_LIMIT_MIN_PPS; 1209 u32 remainder = ratelimit_pps % ALE_RATE_LIMIT_MIN_PPS; 1210 1211 if (ratelimit_pps && !val) { 1212 dev_err(ale->params.dev, "ALE port:%d BC ratelimit min value 1000pps\n", port); 1213 return -EINVAL; 1214 } 1215 1216 if (remainder) 1217 dev_info(ale->params.dev, "ALE port:%d BC ratelimit set to %dpps (requested %d)\n", 1218 port, ratelimit_pps - remainder, ratelimit_pps); 1219 1220 cpsw_ale_control_set(ale, port, ALE_PORT_BCAST_LIMIT, val); 1221 1222 dev_dbg(ale->params.dev, "ALE port:%d BC ratelimit set %d\n", 1223 port, val * ALE_RATE_LIMIT_MIN_PPS); 1224 return 0; 1225 } 1226 1227 static void cpsw_ale_timer(struct timer_list *t) 1228 { 1229 struct cpsw_ale *ale = timer_container_of(ale, t, timer); 1230 1231 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 1232 1233 if (ale->ageout) { 1234 ale->timer.expires = jiffies + ale->ageout; 1235 add_timer(&ale->timer); 1236 } 1237 } 1238 1239 static void cpsw_ale_hw_aging_timer_start(struct cpsw_ale *ale) 1240 { 1241 u32 aging_timer; 1242 1243 aging_timer = ale->params.bus_freq / 1000000; 1244 aging_timer *= ale->params.ale_ageout; 1245 1246 if (aging_timer & ~ALE_AGING_TIMER_MASK) { 1247 aging_timer = ALE_AGING_TIMER_MASK; 1248 dev_warn(ale->params.dev, 1249 "ALE aging timer overflow, set to max\n"); 1250 } 1251 1252 writel(aging_timer, ale->params.ale_regs + ALE_AGING_TIMER); 1253 } 1254 1255 static void cpsw_ale_hw_aging_timer_stop(struct cpsw_ale *ale) 1256 { 1257 writel(0, ale->params.ale_regs + ALE_AGING_TIMER); 1258 } 1259 1260 static void cpsw_ale_aging_start(struct cpsw_ale *ale) 1261 { 1262 if (!ale->params.ale_ageout) 1263 return; 1264 1265 if (ale->features & CPSW_ALE_F_HW_AUTOAGING) { 1266 cpsw_ale_hw_aging_timer_start(ale); 1267 return; 1268 } 1269 1270 timer_setup(&ale->timer, cpsw_ale_timer, 0); 1271 ale->timer.expires = jiffies + ale->ageout; 1272 add_timer(&ale->timer); 1273 } 1274 1275 static void cpsw_ale_aging_stop(struct cpsw_ale *ale) 1276 { 1277 if (!ale->params.ale_ageout) 1278 return; 1279 1280 if (ale->features & CPSW_ALE_F_HW_AUTOAGING) { 1281 cpsw_ale_hw_aging_timer_stop(ale); 1282 return; 1283 } 1284 1285 timer_delete_sync(&ale->timer); 1286 } 1287 1288 void cpsw_ale_start(struct cpsw_ale *ale) 1289 { 1290 unsigned long ale_prescale; 1291 1292 /* configure Broadcast and Multicast Rate Limit 1293 * number_of_packets = (Fclk / ALE_PRESCALE) * port.BCAST/MCAST_LIMIT 1294 * ALE_PRESCALE width is 19bit and min value 0x10 1295 * port.BCAST/MCAST_LIMIT is 8bit 1296 * 1297 * For multi port configuration support the ALE_PRESCALE is configured to 1ms interval, 1298 * which allows to configure port.BCAST/MCAST_LIMIT per port and achieve: 1299 * min number_of_packets = 1000 when port.BCAST/MCAST_LIMIT = 1 1300 * max number_of_packets = 1000 * 255 = 255000 when port.BCAST/MCAST_LIMIT = 0xFF 1301 */ 1302 ale_prescale = ale->params.bus_freq / ALE_RATE_LIMIT_MIN_PPS; 1303 writel((u32)ale_prescale, ale->params.ale_regs + ALE_PRESCALE); 1304 1305 /* Allow MC/BC rate limiting globally. 1306 * The actual Rate Limit cfg enabled per-port by port.BCAST/MCAST_LIMIT 1307 */ 1308 cpsw_ale_control_set(ale, 0, ALE_RATE_LIMIT, 1); 1309 1310 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1); 1311 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); 1312 1313 cpsw_ale_aging_start(ale); 1314 } 1315 1316 void cpsw_ale_stop(struct cpsw_ale *ale) 1317 { 1318 cpsw_ale_aging_stop(ale); 1319 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); 1320 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0); 1321 } 1322 1323 static const struct reg_field ale_fields_cpsw[] = { 1324 /* CPSW_ALE_IDVER_REG */ 1325 [MINOR_VER] = REG_FIELD(ALE_IDVER, 0, 7), 1326 [MAJOR_VER] = REG_FIELD(ALE_IDVER, 8, 15), 1327 }; 1328 1329 static const struct reg_field ale_fields_cpsw_nu[] = { 1330 /* CPSW_ALE_IDVER_REG */ 1331 [MINOR_VER] = REG_FIELD(ALE_IDVER, 0, 7), 1332 [MAJOR_VER] = REG_FIELD(ALE_IDVER, 8, 10), 1333 /* CPSW_ALE_STATUS_REG */ 1334 [ALE_ENTRIES] = REG_FIELD(ALE_STATUS, 0, 7), 1335 [ALE_POLICERS] = REG_FIELD(ALE_STATUS, 8, 15), 1336 /* CPSW_ALE_POLICER_PORT_OUI_REG */ 1337 [POL_PORT_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 31, 31), 1338 [POL_TRUNK_ID] = REG_FIELD(ALE_POLICER_PORT_OUI, 30, 30), 1339 [POL_PORT_NUM] = REG_FIELD(ALE_POLICER_PORT_OUI, 25, 25), 1340 [POL_PRI_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 19, 19), 1341 [POL_PRI_VAL] = REG_FIELD(ALE_POLICER_PORT_OUI, 16, 18), 1342 [POL_OUI_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 15, 15), 1343 [POL_OUI_INDEX] = REG_FIELD(ALE_POLICER_PORT_OUI, 0, 5), 1344 1345 /* CPSW_ALE_POLICER_DA_SA_REG */ 1346 [POL_DST_MEN] = REG_FIELD(ALE_POLICER_DA_SA, 31, 31), 1347 [POL_DST_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 16, 21), 1348 [POL_SRC_MEN] = REG_FIELD(ALE_POLICER_DA_SA, 15, 15), 1349 [POL_SRC_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 0, 5), 1350 1351 /* CPSW_ALE_POLICER_VLAN_REG */ 1352 [POL_OVLAN_MEN] = REG_FIELD(ALE_POLICER_VLAN, 31, 31), 1353 [POL_OVLAN_INDEX] = REG_FIELD(ALE_POLICER_VLAN, 16, 21), 1354 [POL_IVLAN_MEN] = REG_FIELD(ALE_POLICER_VLAN, 15, 15), 1355 [POL_IVLAN_INDEX] = REG_FIELD(ALE_POLICER_VLAN, 0, 5), 1356 1357 /* CPSW_ALE_POLICER_ETHERTYPE_IPSA_REG */ 1358 [POL_ETHERTYPE_MEN] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 31, 31), 1359 [POL_ETHERTYPE_INDEX] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 16, 21), 1360 [POL_IPSRC_MEN] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 15, 15), 1361 [POL_IPSRC_INDEX] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 0, 5), 1362 1363 /* CPSW_ALE_POLICER_IPDA_REG */ 1364 [POL_IPDST_MEN] = REG_FIELD(ALE_POLICER_IPDA, 31, 31), 1365 [POL_IPDST_INDEX] = REG_FIELD(ALE_POLICER_IPDA, 16, 21), 1366 1367 /* CPSW_ALE_POLICER_TBL_CTL_REG */ 1368 /** 1369 * REG_FIELDS not defined for this as fields cannot be correctly 1370 * used independently 1371 */ 1372 1373 /* CPSW_ALE_POLICER_CTL_REG */ 1374 [POL_EN] = REG_FIELD(ALE_POLICER_CTL, 31, 31), 1375 [POL_RED_DROP_EN] = REG_FIELD(ALE_POLICER_CTL, 29, 29), 1376 [POL_YELLOW_DROP_EN] = REG_FIELD(ALE_POLICER_CTL, 28, 28), 1377 [POL_YELLOW_THRESH] = REG_FIELD(ALE_POLICER_CTL, 24, 26), 1378 [POL_POL_MATCH_MODE] = REG_FIELD(ALE_POLICER_CTL, 22, 23), 1379 [POL_PRIORITY_THREAD_EN] = REG_FIELD(ALE_POLICER_CTL, 21, 21), 1380 [POL_MAC_ONLY_DEF_DIS] = REG_FIELD(ALE_POLICER_CTL, 20, 20), 1381 1382 /* CPSW_ALE_POLICER_TEST_CTL_REG */ 1383 [POL_TEST_CLR] = REG_FIELD(ALE_POLICER_TEST_CTL, 31, 31), 1384 [POL_TEST_CLR_RED] = REG_FIELD(ALE_POLICER_TEST_CTL, 30, 30), 1385 [POL_TEST_CLR_YELLOW] = REG_FIELD(ALE_POLICER_TEST_CTL, 29, 29), 1386 [POL_TEST_CLR_SELECTED] = REG_FIELD(ALE_POLICER_TEST_CTL, 28, 28), 1387 [POL_TEST_ENTRY] = REG_FIELD(ALE_POLICER_TEST_CTL, 0, 4), 1388 1389 /* CPSW_ALE_POLICER_HIT_STATUS_REG */ 1390 [POL_STATUS_HIT] = REG_FIELD(ALE_POLICER_HIT_STATUS, 31, 31), 1391 [POL_STATUS_HIT_RED] = REG_FIELD(ALE_POLICER_HIT_STATUS, 30, 30), 1392 [POL_STATUS_HIT_YELLOW] = REG_FIELD(ALE_POLICER_HIT_STATUS, 29, 29), 1393 1394 /* CPSW_ALE_THREAD_DEF_REG */ 1395 [ALE_DEFAULT_THREAD_EN] = REG_FIELD(ALE_THREAD_DEF, 15, 15), 1396 [ALE_DEFAULT_THREAD_VAL] = REG_FIELD(ALE_THREAD_DEF, 0, 5), 1397 1398 /* CPSW_ALE_THREAD_CTL_REG */ 1399 [ALE_THREAD_CLASS_INDEX] = REG_FIELD(ALE_THREAD_CTL, 0, 4), 1400 1401 /* CPSW_ALE_THREAD_VAL_REG */ 1402 [ALE_THREAD_ENABLE] = REG_FIELD(ALE_THREAD_VAL, 15, 15), 1403 [ALE_THREAD_VALUE] = REG_FIELD(ALE_THREAD_VAL, 0, 5), 1404 }; 1405 1406 static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { 1407 { 1408 /* am3/4/5, dra7. dm814x, 66ak2hk-gbe */ 1409 .dev_id = "cpsw", 1410 .tbl_entries = 1024, 1411 .reg_fields = ale_fields_cpsw, 1412 .num_fields = ARRAY_SIZE(ale_fields_cpsw), 1413 .vlan_entry_tbl = vlan_entry_cpsw, 1414 }, 1415 { 1416 /* 66ak2h_xgbe */ 1417 .dev_id = "66ak2h-xgbe", 1418 .tbl_entries = 2048, 1419 .reg_fields = ale_fields_cpsw, 1420 .num_fields = ARRAY_SIZE(ale_fields_cpsw), 1421 .vlan_entry_tbl = vlan_entry_cpsw, 1422 }, 1423 { 1424 .dev_id = "66ak2el", 1425 .features = CPSW_ALE_F_STATUS_REG, 1426 .reg_fields = ale_fields_cpsw_nu, 1427 .num_fields = ARRAY_SIZE(ale_fields_cpsw_nu), 1428 .nu_switch_ale = true, 1429 .vlan_entry_tbl = vlan_entry_nu, 1430 }, 1431 { 1432 .dev_id = "66ak2g", 1433 .features = CPSW_ALE_F_STATUS_REG, 1434 .tbl_entries = 64, 1435 .reg_fields = ale_fields_cpsw_nu, 1436 .num_fields = ARRAY_SIZE(ale_fields_cpsw_nu), 1437 .nu_switch_ale = true, 1438 .vlan_entry_tbl = vlan_entry_nu, 1439 }, 1440 { 1441 .dev_id = "am65x-cpsw2g", 1442 .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, 1443 .tbl_entries = 64, 1444 .reg_fields = ale_fields_cpsw_nu, 1445 .num_fields = ARRAY_SIZE(ale_fields_cpsw_nu), 1446 .nu_switch_ale = true, 1447 .vlan_entry_tbl = vlan_entry_nu, 1448 }, 1449 { 1450 .dev_id = "j721e-cpswxg", 1451 .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, 1452 .reg_fields = ale_fields_cpsw_nu, 1453 .num_fields = ARRAY_SIZE(ale_fields_cpsw_nu), 1454 .vlan_entry_tbl = vlan_entry_k3_cpswxg, 1455 }, 1456 { 1457 .dev_id = "am64-cpswxg", 1458 .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, 1459 .reg_fields = ale_fields_cpsw_nu, 1460 .num_fields = ARRAY_SIZE(ale_fields_cpsw_nu), 1461 .vlan_entry_tbl = vlan_entry_k3_cpswxg, 1462 .tbl_entries = 512, 1463 }, 1464 { }, 1465 }; 1466 1467 static const struct 1468 cpsw_ale_dev_id *cpsw_ale_match_id(const struct cpsw_ale_dev_id *id, 1469 const char *dev_id) 1470 { 1471 if (!dev_id) 1472 return NULL; 1473 1474 while (id->dev_id) { 1475 if (strcmp(dev_id, id->dev_id) == 0) 1476 return id; 1477 id++; 1478 } 1479 return NULL; 1480 } 1481 1482 static const struct regmap_config ale_regmap_cfg = { 1483 .reg_bits = 32, 1484 .val_bits = 32, 1485 .reg_stride = 4, 1486 .name = "cpsw-ale", 1487 }; 1488 1489 static int cpsw_ale_regfield_init(struct cpsw_ale *ale) 1490 { 1491 const struct reg_field *reg_fields = ale->params.reg_fields; 1492 struct device *dev = ale->params.dev; 1493 struct regmap *regmap = ale->regmap; 1494 int i; 1495 1496 for (i = 0; i < ale->params.num_fields; i++) { 1497 ale->fields[i] = devm_regmap_field_alloc(dev, regmap, 1498 reg_fields[i]); 1499 if (IS_ERR(ale->fields[i])) { 1500 dev_err(dev, "Unable to allocate regmap field %d\n", i); 1501 return PTR_ERR(ale->fields[i]); 1502 } 1503 } 1504 1505 return 0; 1506 } 1507 1508 struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) 1509 { 1510 u32 ale_entries, rev_major, rev_minor, policers; 1511 const struct cpsw_ale_dev_id *ale_dev_id; 1512 struct cpsw_ale *ale; 1513 int ret; 1514 1515 ale_dev_id = cpsw_ale_match_id(cpsw_ale_id_match, params->dev_id); 1516 if (!ale_dev_id) 1517 return ERR_PTR(-EINVAL); 1518 1519 params->ale_entries = ale_dev_id->tbl_entries; 1520 params->nu_switch_ale = ale_dev_id->nu_switch_ale; 1521 params->reg_fields = ale_dev_id->reg_fields; 1522 params->num_fields = ale_dev_id->num_fields; 1523 1524 ale = devm_kzalloc(params->dev, sizeof(*ale), GFP_KERNEL); 1525 if (!ale) 1526 return ERR_PTR(-ENOMEM); 1527 ale->regmap = devm_regmap_init_mmio(params->dev, params->ale_regs, 1528 &ale_regmap_cfg); 1529 if (IS_ERR(ale->regmap)) { 1530 dev_err(params->dev, "Couldn't create CPSW ALE regmap\n"); 1531 return ERR_PTR(-ENOMEM); 1532 } 1533 1534 ale->params = *params; 1535 ret = cpsw_ale_regfield_init(ale); 1536 if (ret) 1537 return ERR_PTR(ret); 1538 1539 ale->p0_untag_vid_mask = devm_bitmap_zalloc(params->dev, VLAN_N_VID, 1540 GFP_KERNEL); 1541 if (!ale->p0_untag_vid_mask) 1542 return ERR_PTR(-ENOMEM); 1543 1544 ale->ageout = ale->params.ale_ageout * HZ; 1545 ale->features = ale_dev_id->features; 1546 ale->vlan_entry_tbl = ale_dev_id->vlan_entry_tbl; 1547 1548 regmap_field_read(ale->fields[MINOR_VER], &rev_minor); 1549 regmap_field_read(ale->fields[MAJOR_VER], &rev_major); 1550 ale->version = rev_major << 8 | rev_minor; 1551 dev_info(ale->params.dev, "initialized cpsw ale version %d.%d\n", 1552 rev_major, rev_minor); 1553 1554 if (ale->features & CPSW_ALE_F_STATUS_REG && 1555 !ale->params.ale_entries) { 1556 regmap_field_read(ale->fields[ALE_ENTRIES], &ale_entries); 1557 /* ALE available on newer NetCP switches has introduced 1558 * a register, ALE_STATUS, to indicate the size of ALE 1559 * table which shows the size as a multiple of 1024 entries. 1560 * For these, params.ale_entries will be set to zero. So 1561 * read the register and update the value of ale_entries. 1562 * return error if ale_entries is zero in ALE_STATUS. 1563 */ 1564 if (!ale_entries) 1565 return ERR_PTR(-EINVAL); 1566 1567 ale_entries *= ALE_TABLE_SIZE_MULTIPLIER; 1568 ale->params.ale_entries = ale_entries; 1569 } 1570 1571 if (ale->features & CPSW_ALE_F_STATUS_REG && 1572 !ale->params.num_policers) { 1573 regmap_field_read(ale->fields[ALE_POLICERS], &policers); 1574 if (!policers) 1575 return ERR_PTR(-EINVAL); 1576 1577 policers *= ALE_POLICER_SIZE_MULTIPLIER; 1578 ale->params.num_policers = policers; 1579 } 1580 1581 dev_info(ale->params.dev, 1582 "ALE Table size %ld, Policers %ld\n", ale->params.ale_entries, 1583 ale->params.num_policers); 1584 1585 /* set default bits for existing h/w */ 1586 ale->port_mask_bits = ale->params.ale_ports; 1587 ale->port_num_bits = order_base_2(ale->params.ale_ports); 1588 ale->vlan_field_bits = ale->params.ale_ports; 1589 1590 /* Set defaults override for ALE on NetCP NU switch and for version 1591 * 1R3 1592 */ 1593 if (ale->params.nu_switch_ale) { 1594 /* Separate registers for unknown vlan configuration. 1595 * Also there are N bits, where N is number of ale 1596 * ports and shift value should be 0 1597 */ 1598 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].bits = 1599 ale->params.ale_ports; 1600 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].offset = 1601 ALE_UNKNOWNVLAN_MEMBER; 1602 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].bits = 1603 ale->params.ale_ports; 1604 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].shift = 0; 1605 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].offset = 1606 ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD; 1607 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].bits = 1608 ale->params.ale_ports; 1609 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].shift = 0; 1610 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].offset = 1611 ALE_UNKNOWNVLAN_REG_MCAST_FLOOD; 1612 ale_controls[ALE_PORT_UNTAGGED_EGRESS].bits = 1613 ale->params.ale_ports; 1614 ale_controls[ALE_PORT_UNTAGGED_EGRESS].shift = 0; 1615 ale_controls[ALE_PORT_UNTAGGED_EGRESS].offset = 1616 ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS; 1617 } 1618 1619 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); 1620 return ale; 1621 } 1622 1623 void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data) 1624 { 1625 int i; 1626 1627 for (i = 0; i < ale->params.ale_entries; i++) { 1628 cpsw_ale_read(ale, i, data); 1629 data += ALE_ENTRY_WORDS; 1630 } 1631 } 1632 1633 void cpsw_ale_restore(struct cpsw_ale *ale, u32 *data) 1634 { 1635 int i; 1636 1637 for (i = 0; i < ale->params.ale_entries; i++) { 1638 cpsw_ale_write(ale, i, data); 1639 data += ALE_ENTRY_WORDS; 1640 } 1641 } 1642 1643 u32 cpsw_ale_get_num_entries(struct cpsw_ale *ale) 1644 { 1645 return ale ? ale->params.ale_entries : 0; 1646 } 1647 1648 /* Reads the specified policer index into ALE POLICER registers */ 1649 static void cpsw_ale_policer_read_idx(struct cpsw_ale *ale, u32 idx) 1650 { 1651 idx &= ALE_POLICER_TBL_INDEX_MASK; 1652 writel_relaxed(idx, ale->params.ale_regs + ALE_POLICER_TBL_CTL); 1653 } 1654 1655 /* Writes the ALE POLICER registers into the specified policer index */ 1656 static void cpsw_ale_policer_write_idx(struct cpsw_ale *ale, u32 idx) 1657 { 1658 idx &= ALE_POLICER_TBL_INDEX_MASK; 1659 idx |= ALE_POLICER_TBL_WRITE_ENABLE; 1660 writel_relaxed(idx, ale->params.ale_regs + ALE_POLICER_TBL_CTL); 1661 } 1662 1663 /* enables/disables the custom thread value for the specified policer index */ 1664 static void cpsw_ale_policer_thread_idx_enable(struct cpsw_ale *ale, u32 idx, 1665 u32 thread_id, bool enable) 1666 { 1667 regmap_field_write(ale->fields[ALE_THREAD_CLASS_INDEX], idx); 1668 regmap_field_write(ale->fields[ALE_THREAD_VALUE], thread_id); 1669 regmap_field_write(ale->fields[ALE_THREAD_ENABLE], enable ? 1 : 0); 1670 } 1671 1672 /* Disable all policer entries and thread mappings */ 1673 static void cpsw_ale_policer_reset(struct cpsw_ale *ale) 1674 { 1675 int i; 1676 1677 for (i = 0; i < ale->params.num_policers ; i++) { 1678 cpsw_ale_policer_read_idx(ale, i); 1679 regmap_field_write(ale->fields[POL_PORT_MEN], 0); 1680 regmap_field_write(ale->fields[POL_PRI_MEN], 0); 1681 regmap_field_write(ale->fields[POL_OUI_MEN], 0); 1682 regmap_field_write(ale->fields[POL_DST_MEN], 0); 1683 regmap_field_write(ale->fields[POL_SRC_MEN], 0); 1684 regmap_field_write(ale->fields[POL_OVLAN_MEN], 0); 1685 regmap_field_write(ale->fields[POL_IVLAN_MEN], 0); 1686 regmap_field_write(ale->fields[POL_ETHERTYPE_MEN], 0); 1687 regmap_field_write(ale->fields[POL_IPSRC_MEN], 0); 1688 regmap_field_write(ale->fields[POL_IPDST_MEN], 0); 1689 regmap_field_write(ale->fields[POL_EN], 0); 1690 regmap_field_write(ale->fields[POL_RED_DROP_EN], 0); 1691 regmap_field_write(ale->fields[POL_YELLOW_DROP_EN], 0); 1692 regmap_field_write(ale->fields[POL_PRIORITY_THREAD_EN], 0); 1693 1694 cpsw_ale_policer_thread_idx_enable(ale, i, 0, 0); 1695 } 1696 } 1697 1698 /* Default classifier is to map 8 user priorities to N receive channels */ 1699 void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch) 1700 { 1701 int pri, idx; 1702 1703 /* Reference: 1704 * IEEE802.1Q-2014, Standard for Local and metropolitan area networks 1705 * Table I-2 - Traffic type acronyms 1706 * Table I-3 - Defining traffic types 1707 * Section I.4 Traffic types and priority values, states: 1708 * "0 is thus used both for default priority and for Best Effort, and 1709 * Background is associated with a priority value of 1. This means 1710 * that the value 1 effectively communicates a lower priority than 0." 1711 * 1712 * In the table below, Priority Code Point (PCP) 0 is assigned 1713 * to a higher priority thread than PCP 1 wherever possible. 1714 * The table maps which thread the PCP traffic needs to be 1715 * sent to for a given number of threads (RX channels). Upper threads 1716 * have higher priority. 1717 * e.g. if number of threads is 8 then user priority 0 will map to 1718 * pri_thread_map[8-1][0] i.e. thread 1 1719 */ 1720 1721 int pri_thread_map[8][8] = { /* BK,BE,EE,CA,VI,VO,IC,NC */ 1722 { 0, 0, 0, 0, 0, 0, 0, 0, }, 1723 { 0, 0, 0, 0, 1, 1, 1, 1, }, 1724 { 0, 0, 0, 0, 1, 1, 2, 2, }, 1725 { 0, 0, 1, 1, 2, 2, 3, 3, }, 1726 { 0, 0, 1, 1, 2, 2, 3, 4, }, 1727 { 1, 0, 2, 2, 3, 3, 4, 5, }, 1728 { 1, 0, 2, 3, 4, 4, 5, 6, }, 1729 { 1, 0, 2, 3, 4, 5, 6, 7 } }; 1730 1731 cpsw_ale_policer_reset(ale); 1732 1733 /* use first 8 classifiers to map 8 (DSCP/PCP) priorities to channels */ 1734 for (pri = 0; pri < 8; pri++) { 1735 idx = pri; 1736 1737 /* Classifier 'idx' match on priority 'pri' */ 1738 cpsw_ale_policer_read_idx(ale, idx); 1739 regmap_field_write(ale->fields[POL_PRI_VAL], pri); 1740 regmap_field_write(ale->fields[POL_PRI_MEN], 1); 1741 cpsw_ale_policer_write_idx(ale, idx); 1742 1743 /* Map Classifier 'idx' to thread provided by the map */ 1744 cpsw_ale_policer_thread_idx_enable(ale, idx, 1745 pri_thread_map[num_rx_ch - 1][pri], 1746 1); 1747 } 1748 } 1749