1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * AMD SoC Power Management Controller Driver
4 *
5 * Copyright (c) 2020, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13 #include <linux/acpi.h>
14 #include <linux/array_size.h>
15 #include <linux/bitfield.h>
16 #include <linux/bits.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/io.h>
20 #include <linux/iopoll.h>
21 #include <linux/limits.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/platform_device.h>
25 #include <linux/rtc.h>
26 #include <linux/serio.h>
27 #include <linux/suspend.h>
28 #include <linux/seq_file.h>
29 #include <linux/uaccess.h>
30
31 #include <asm/amd_node.h>
32
33 #include "pmc.h"
34
35 /* SMU communication registers */
36 #define AMD_PMC_REGISTER_RESPONSE 0x980
37 #define AMD_PMC_REGISTER_ARGUMENT 0x9BC
38
39 /* PMC Scratch Registers */
40 #define AMD_PMC_SCRATCH_REG_CZN 0x94
41 #define AMD_PMC_SCRATCH_REG_YC 0xD14
42 #define AMD_PMC_SCRATCH_REG_1AH 0xF14
43
44 /* STB Registers */
45 #define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001
46 #define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002
47 #define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003
48
49 /* Base address of SMU for mapping physical address to virtual address */
50 #define AMD_PMC_MAPPING_SIZE 0x01000
51 #define AMD_PMC_BASE_ADDR_OFFSET 0x10000
52 #define AMD_PMC_BASE_ADDR_LO 0x13B102E8
53 #define AMD_PMC_BASE_ADDR_HI 0x13B102EC
54 #define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)
55 #define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)
56
57 /* SMU Response Codes */
58 #define AMD_PMC_RESULT_OK 0x01
59 #define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC
60 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD
61 #define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
62 #define AMD_PMC_RESULT_FAILED 0xFF
63
64 /* FCH SSC Registers */
65 #define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
66 #define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
67 #define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
68 #define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
69 #define FCH_SSC_MAPPING_SIZE 0x800
70 #define FCH_BASE_PHY_ADDR_LOW 0xFED81100
71 #define FCH_BASE_PHY_ADDR_HIGH 0x00000000
72
73 /* SMU Message Definations */
74 #define SMU_MSG_GETSMUVERSION 0x02
75 #define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
76 #define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
77 #define SMU_MSG_LOG_START 0x06
78 #define SMU_MSG_LOG_RESET 0x07
79 #define SMU_MSG_LOG_DUMP_DATA 0x08
80 #define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
81
82 #define PMC_MSG_DELAY_MIN_US 50
83 #define RESPONSE_REGISTER_LOOP_MAX 20000
84
85 #define DELAY_MIN_US 2000
86 #define DELAY_MAX_US 3000
87
88 enum amd_pmc_def {
89 MSG_TEST = 0x01,
90 MSG_OS_HINT_PCO,
91 MSG_OS_HINT_RN,
92 };
93
94 struct amd_pmc_bit_map {
95 const char *name;
96 u32 bit_mask;
97 };
98
99 static const struct amd_pmc_bit_map soc15_ip_blk_v2[] = {
100 {"DISPLAY", BIT(0)},
101 {"CPU", BIT(1)},
102 {"GFX", BIT(2)},
103 {"VDD", BIT(3)},
104 {"VDD_CCX", BIT(4)},
105 {"ACP", BIT(5)},
106 {"VCN_0", BIT(6)},
107 {"VCN_1", BIT(7)},
108 {"ISP", BIT(8)},
109 {"NBIO", BIT(9)},
110 {"DF", BIT(10)},
111 {"USB3_0", BIT(11)},
112 {"USB3_1", BIT(12)},
113 {"LAPIC", BIT(13)},
114 {"USB3_2", BIT(14)},
115 {"USB4_RT0", BIT(15)},
116 {"USB4_RT1", BIT(16)},
117 {"USB4_0", BIT(17)},
118 {"USB4_1", BIT(18)},
119 {"MPM", BIT(19)},
120 {"JPEG_0", BIT(20)},
121 {"JPEG_1", BIT(21)},
122 {"IPU", BIT(22)},
123 {"UMSCH", BIT(23)},
124 {"VPE", BIT(24)},
125 };
126
127 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
128 {"DISPLAY", BIT(0)},
129 {"CPU", BIT(1)},
130 {"GFX", BIT(2)},
131 {"VDD", BIT(3)},
132 {"ACP", BIT(4)},
133 {"VCN", BIT(5)},
134 {"ISP", BIT(6)},
135 {"NBIO", BIT(7)},
136 {"DF", BIT(8)},
137 {"USB3_0", BIT(9)},
138 {"USB3_1", BIT(10)},
139 {"LAPIC", BIT(11)},
140 {"USB3_2", BIT(12)},
141 {"USB3_3", BIT(13)},
142 {"USB3_4", BIT(14)},
143 {"USB4_0", BIT(15)},
144 {"USB4_1", BIT(16)},
145 {"MPM", BIT(17)},
146 {"JPEG", BIT(18)},
147 {"IPU", BIT(19)},
148 {"UMSCH", BIT(20)},
149 {"VPE", BIT(21)},
150 };
151
152 static bool disable_workarounds;
153 module_param(disable_workarounds, bool, 0644);
154 MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs");
155
156 static struct amd_pmc_dev pmc;
157
amd_pmc_reg_read(struct amd_pmc_dev * dev,int reg_offset)158 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
159 {
160 return ioread32(dev->regbase + reg_offset);
161 }
162
amd_pmc_reg_write(struct amd_pmc_dev * dev,int reg_offset,u32 val)163 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
164 {
165 iowrite32(val, dev->regbase + reg_offset);
166 }
167
168 struct smu_metrics {
169 u32 table_version;
170 u32 hint_count;
171 u32 s0i3_last_entry_status;
172 u32 timein_s0i2;
173 u64 timeentering_s0i3_lastcapture;
174 u64 timeentering_s0i3_totaltime;
175 u64 timeto_resume_to_os_lastcapture;
176 u64 timeto_resume_to_os_totaltime;
177 u64 timein_s0i3_lastcapture;
178 u64 timein_s0i3_totaltime;
179 u64 timein_swdrips_lastcapture;
180 u64 timein_swdrips_totaltime;
181 u64 timecondition_notmet_lastcapture[32];
182 u64 timecondition_notmet_totaltime[32];
183 } __packed;
184
amd_pmc_get_ip_info(struct amd_pmc_dev * dev)185 static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
186 {
187 switch (dev->cpu_id) {
188 case AMD_CPU_ID_PCO:
189 case AMD_CPU_ID_RN:
190 case AMD_CPU_ID_YC:
191 case AMD_CPU_ID_CB:
192 dev->num_ips = 12;
193 dev->ips_ptr = soc15_ip_blk;
194 dev->smu_msg = 0x538;
195 break;
196 case AMD_CPU_ID_PS:
197 dev->num_ips = 21;
198 dev->ips_ptr = soc15_ip_blk;
199 dev->smu_msg = 0x538;
200 break;
201 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
202 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
203 if (boot_cpu_data.x86_model == 0x70) {
204 dev->num_ips = ARRAY_SIZE(soc15_ip_blk_v2);
205 dev->ips_ptr = soc15_ip_blk_v2;
206 } else {
207 dev->num_ips = ARRAY_SIZE(soc15_ip_blk);
208 dev->ips_ptr = soc15_ip_blk;
209 }
210 dev->smu_msg = 0x938;
211 break;
212 }
213 }
214
amd_pmc_setup_smu_logging(struct amd_pmc_dev * dev)215 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
216 {
217 if (dev->cpu_id == AMD_CPU_ID_PCO) {
218 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
219 return -EINVAL;
220 }
221
222 /* Get Active devices list from SMU */
223 if (!dev->active_ips)
224 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, true);
225
226 /* Get dram address */
227 if (!dev->smu_virt_addr) {
228 u32 phys_addr_low, phys_addr_hi;
229 u64 smu_phys_addr;
230
231 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, true);
232 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, true);
233 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
234
235 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
236 sizeof(struct smu_metrics));
237 if (!dev->smu_virt_addr)
238 return -ENOMEM;
239 }
240
241 /* Start the logging */
242 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, false);
243 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, false);
244
245 return 0;
246 }
247
get_metrics_table(struct amd_pmc_dev * pdev,struct smu_metrics * table)248 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
249 {
250 if (!pdev->smu_virt_addr) {
251 int ret = amd_pmc_setup_smu_logging(pdev);
252
253 if (ret)
254 return ret;
255 }
256
257 if (pdev->cpu_id == AMD_CPU_ID_PCO)
258 return -ENODEV;
259 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
260 return 0;
261 }
262
amd_pmc_validate_deepest(struct amd_pmc_dev * pdev)263 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
264 {
265 struct smu_metrics table;
266
267 if (get_metrics_table(pdev, &table))
268 return;
269
270 if (!table.s0i3_last_entry_status)
271 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
272 pm_report_hw_sleep_time(table.s0i3_last_entry_status ?
273 table.timein_s0i3_lastcapture : 0);
274 }
275
amd_pmc_get_smu_version(struct amd_pmc_dev * dev)276 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
277 {
278 int rc;
279 u32 val;
280
281 if (dev->cpu_id == AMD_CPU_ID_PCO)
282 return -ENODEV;
283
284 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, true);
285 if (rc)
286 return rc;
287
288 dev->smu_program = (val >> 24) & GENMASK(7, 0);
289 dev->major = (val >> 16) & GENMASK(7, 0);
290 dev->minor = (val >> 8) & GENMASK(7, 0);
291 dev->rev = (val >> 0) & GENMASK(7, 0);
292
293 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
294 dev->smu_program, dev->major, dev->minor, dev->rev);
295
296 return 0;
297 }
298
smu_fw_version_show(struct device * d,struct device_attribute * attr,char * buf)299 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr,
300 char *buf)
301 {
302 struct amd_pmc_dev *dev = dev_get_drvdata(d);
303
304 if (!dev->major) {
305 int rc = amd_pmc_get_smu_version(dev);
306
307 if (rc)
308 return rc;
309 }
310 return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev);
311 }
312
smu_program_show(struct device * d,struct device_attribute * attr,char * buf)313 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr,
314 char *buf)
315 {
316 struct amd_pmc_dev *dev = dev_get_drvdata(d);
317
318 if (!dev->major) {
319 int rc = amd_pmc_get_smu_version(dev);
320
321 if (rc)
322 return rc;
323 }
324 return sysfs_emit(buf, "%u\n", dev->smu_program);
325 }
326
327 static DEVICE_ATTR_RO(smu_fw_version);
328 static DEVICE_ATTR_RO(smu_program);
329
pmc_attr_is_visible(struct kobject * kobj,struct attribute * attr,int idx)330 static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
331 {
332 struct device *dev = kobj_to_dev(kobj);
333 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
334
335 if (pdev->cpu_id == AMD_CPU_ID_PCO)
336 return 0;
337 return 0444;
338 }
339
340 static struct attribute *pmc_attrs[] = {
341 &dev_attr_smu_fw_version.attr,
342 &dev_attr_smu_program.attr,
343 NULL,
344 };
345
346 static struct attribute_group pmc_attr_group = {
347 .attrs = pmc_attrs,
348 .is_visible = pmc_attr_is_visible,
349 };
350
351 static const struct attribute_group *pmc_groups[] = {
352 &pmc_attr_group,
353 NULL,
354 };
355
smu_fw_info_show(struct seq_file * s,void * unused)356 static int smu_fw_info_show(struct seq_file *s, void *unused)
357 {
358 struct amd_pmc_dev *dev = s->private;
359 struct smu_metrics table;
360 int idx;
361
362 if (get_metrics_table(dev, &table))
363 return -EINVAL;
364
365 seq_puts(s, "\n=== SMU Statistics ===\n");
366 seq_printf(s, "Table Version: %d\n", table.table_version);
367 seq_printf(s, "Hint Count: %d\n", table.hint_count);
368 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
369 "Unknown/Fail");
370 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
371 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
372 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
373 table.timeto_resume_to_os_lastcapture);
374
375 seq_puts(s, "\n=== Active time (in us) ===\n");
376 for (idx = 0 ; idx < dev->num_ips ; idx++) {
377 if (dev->ips_ptr[idx].bit_mask & dev->active_ips)
378 seq_printf(s, "%-8s : %lld\n", dev->ips_ptr[idx].name,
379 table.timecondition_notmet_lastcapture[idx]);
380 }
381
382 return 0;
383 }
384 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
385
s0ix_stats_show(struct seq_file * s,void * unused)386 static int s0ix_stats_show(struct seq_file *s, void *unused)
387 {
388 struct amd_pmc_dev *dev = s->private;
389 u64 entry_time, exit_time, residency;
390
391 /* Use FCH registers to get the S0ix stats */
392 if (!dev->fch_virt_addr) {
393 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
394 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
395 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
396
397 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
398 if (!dev->fch_virt_addr)
399 return -ENOMEM;
400 }
401
402 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
403 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
404
405 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
406 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
407
408 /* It's in 48MHz. We need to convert it */
409 residency = exit_time - entry_time;
410 do_div(residency, 48);
411
412 seq_puts(s, "=== S0ix statistics ===\n");
413 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
414 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
415 seq_printf(s, "Residency Time: %lld\n", residency);
416
417 return 0;
418 }
419 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
420
amd_pmc_idlemask_read(struct amd_pmc_dev * pdev,struct device * dev,struct seq_file * s)421 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
422 struct seq_file *s)
423 {
424 u32 val;
425 int rc;
426
427 switch (pdev->cpu_id) {
428 case AMD_CPU_ID_CZN:
429 /* we haven't yet read SMU version */
430 if (!pdev->major) {
431 rc = amd_pmc_get_smu_version(pdev);
432 if (rc)
433 return rc;
434 }
435 if (pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37))
436 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
437 else
438 return -EINVAL;
439 break;
440 case AMD_CPU_ID_YC:
441 case AMD_CPU_ID_CB:
442 case AMD_CPU_ID_PS:
443 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
444 break;
445 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
446 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
447 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_1AH);
448 break;
449 default:
450 return -EINVAL;
451 }
452
453 if (dev)
454 pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val);
455
456 if (s)
457 seq_printf(s, "SMU idlemask : 0x%x\n", val);
458
459 return 0;
460 }
461
amd_pmc_idlemask_show(struct seq_file * s,void * unused)462 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
463 {
464 return amd_pmc_idlemask_read(s->private, NULL, s);
465 }
466 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
467
amd_pmc_dbgfs_unregister(struct amd_pmc_dev * dev)468 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
469 {
470 debugfs_remove_recursive(dev->dbgfs_dir);
471 }
472
amd_pmc_dbgfs_register(struct amd_pmc_dev * dev)473 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
474 {
475 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
476 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
477 &smu_fw_info_fops);
478 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
479 &s0ix_stats_fops);
480 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
481 &amd_pmc_idlemask_fops);
482 }
483
amd_pmc_get_msg_port(struct amd_pmc_dev * dev)484 static char *amd_pmc_get_msg_port(struct amd_pmc_dev *dev)
485 {
486 switch (dev->msg_port) {
487 case MSG_PORT_PMC:
488 return "PMC";
489 case MSG_PORT_S2D:
490 return "S2D";
491 default:
492 return "Invalid message port";
493 }
494 }
495
amd_pmc_dump_registers(struct amd_pmc_dev * dev)496 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
497 {
498 u32 value, message, argument, response;
499
500 if (dev->msg_port == MSG_PORT_S2D) {
501 message = dev->stb_arg.msg;
502 argument = dev->stb_arg.arg;
503 response = dev->stb_arg.resp;
504 } else {
505 message = dev->smu_msg;
506 argument = AMD_PMC_REGISTER_ARGUMENT;
507 response = AMD_PMC_REGISTER_RESPONSE;
508 }
509
510 value = amd_pmc_reg_read(dev, response);
511 dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", amd_pmc_get_msg_port(dev), value);
512
513 value = amd_pmc_reg_read(dev, argument);
514 dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", amd_pmc_get_msg_port(dev), value);
515
516 value = amd_pmc_reg_read(dev, message);
517 dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", amd_pmc_get_msg_port(dev), value);
518 }
519
amd_pmc_send_cmd(struct amd_pmc_dev * dev,u32 arg,u32 * data,u8 msg,bool ret)520 int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
521 {
522 int rc;
523 u32 val, message, argument, response;
524
525 guard(mutex)(&dev->lock);
526
527 if (dev->msg_port == MSG_PORT_S2D) {
528 message = dev->stb_arg.msg;
529 argument = dev->stb_arg.arg;
530 response = dev->stb_arg.resp;
531 } else {
532 message = dev->smu_msg;
533 argument = AMD_PMC_REGISTER_ARGUMENT;
534 response = AMD_PMC_REGISTER_RESPONSE;
535 }
536
537 /* Wait until we get a valid response */
538 rc = readx_poll_timeout(ioread32, dev->regbase + response,
539 val, val != 0, PMC_MSG_DELAY_MIN_US,
540 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
541 if (rc) {
542 dev_err(dev->dev, "failed to talk to SMU\n");
543 return rc;
544 }
545
546 /* Write zero to response register */
547 amd_pmc_reg_write(dev, response, 0);
548
549 /* Write argument into response register */
550 amd_pmc_reg_write(dev, argument, arg);
551
552 /* Write message ID to message ID register */
553 amd_pmc_reg_write(dev, message, msg);
554
555 /* Wait until we get a valid response */
556 rc = readx_poll_timeout(ioread32, dev->regbase + response,
557 val, val != 0, PMC_MSG_DELAY_MIN_US,
558 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
559 if (rc) {
560 dev_err(dev->dev, "SMU response timed out\n");
561 return rc;
562 }
563
564 switch (val) {
565 case AMD_PMC_RESULT_OK:
566 if (ret) {
567 /* PMFW may take longer time to return back the data */
568 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
569 *data = amd_pmc_reg_read(dev, argument);
570 }
571 break;
572 case AMD_PMC_RESULT_CMD_REJECT_BUSY:
573 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
574 rc = -EBUSY;
575 break;
576 case AMD_PMC_RESULT_CMD_UNKNOWN:
577 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
578 rc = -EINVAL;
579 break;
580 case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
581 case AMD_PMC_RESULT_FAILED:
582 default:
583 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
584 rc = -EIO;
585 break;
586 }
587
588 amd_pmc_dump_registers(dev);
589 return rc;
590 }
591
amd_pmc_get_os_hint(struct amd_pmc_dev * dev)592 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
593 {
594 switch (dev->cpu_id) {
595 case AMD_CPU_ID_PCO:
596 return MSG_OS_HINT_PCO;
597 case AMD_CPU_ID_RN:
598 case AMD_CPU_ID_YC:
599 case AMD_CPU_ID_CB:
600 case AMD_CPU_ID_PS:
601 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
602 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
603 return MSG_OS_HINT_RN;
604 }
605 return -EINVAL;
606 }
607
amd_pmc_wa_irq1(struct amd_pmc_dev * pdev)608 static int amd_pmc_wa_irq1(struct amd_pmc_dev *pdev)
609 {
610 struct device *d;
611 int rc;
612
613 /* cezanne platform firmware has a fix in 64.66.0 */
614 if (pdev->cpu_id == AMD_CPU_ID_CZN) {
615 if (!pdev->major) {
616 rc = amd_pmc_get_smu_version(pdev);
617 if (rc)
618 return rc;
619 }
620
621 if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65))
622 return 0;
623 }
624
625 d = bus_find_device_by_name(&serio_bus, NULL, "serio0");
626 if (!d)
627 return 0;
628 if (device_may_wakeup(d)) {
629 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n");
630 disable_irq_wake(1);
631 device_set_wakeup_enable(d, false);
632 }
633 put_device(d);
634
635 return 0;
636 }
637
amd_pmc_verify_czn_rtc(struct amd_pmc_dev * pdev,u32 * arg)638 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
639 {
640 struct rtc_device *rtc_device;
641 time64_t then, now, duration;
642 struct rtc_wkalrm alarm;
643 struct rtc_time tm;
644 int rc;
645
646 /* we haven't yet read SMU version */
647 if (!pdev->major) {
648 rc = amd_pmc_get_smu_version(pdev);
649 if (rc)
650 return rc;
651 }
652
653 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
654 return 0;
655
656 rtc_device = rtc_class_open("rtc0");
657 if (!rtc_device)
658 return 0;
659 rc = rtc_read_alarm(rtc_device, &alarm);
660 if (rc)
661 return rc;
662 if (!alarm.enabled) {
663 dev_dbg(pdev->dev, "alarm not enabled\n");
664 return 0;
665 }
666 rc = rtc_read_time(rtc_device, &tm);
667 if (rc)
668 return rc;
669 then = rtc_tm_to_time64(&alarm.time);
670 now = rtc_tm_to_time64(&tm);
671 duration = then-now;
672
673 /* in the past */
674 if (then < now)
675 return 0;
676
677 /* will be stored in upper 16 bits of s0i3 hint argument,
678 * so timer wakeup from s0i3 is limited to ~18 hours or less
679 */
680 if (duration <= 4 || duration > U16_MAX)
681 return -EINVAL;
682
683 *arg |= (duration << 16);
684 rc = rtc_alarm_irq_enable(rtc_device, 0);
685 pm_pr_dbg("wakeup timer programmed for %lld seconds\n", duration);
686
687 return rc;
688 }
689
amd_pmc_s2idle_prepare(void)690 static void amd_pmc_s2idle_prepare(void)
691 {
692 struct amd_pmc_dev *pdev = &pmc;
693 int rc;
694 u8 msg;
695 u32 arg = 1;
696
697 /* Reset and Start SMU logging - to monitor the s0i3 stats */
698 amd_pmc_setup_smu_logging(pdev);
699
700 /* Activate CZN specific platform bug workarounds */
701 if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
702 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
703 if (rc) {
704 dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
705 return;
706 }
707 }
708
709 msg = amd_pmc_get_os_hint(pdev);
710 rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, false);
711 if (rc) {
712 dev_err(pdev->dev, "suspend failed: %d\n", rc);
713 return;
714 }
715
716 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_PREPARE);
717 if (rc)
718 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
719 }
720
amd_pmc_s2idle_check(void)721 static void amd_pmc_s2idle_check(void)
722 {
723 struct amd_pmc_dev *pdev = &pmc;
724 struct smu_metrics table;
725 int rc;
726
727 /* CZN: Ensure that future s0i3 entry attempts at least 10ms passed */
728 if (pdev->cpu_id == AMD_CPU_ID_CZN && !get_metrics_table(pdev, &table) &&
729 table.s0i3_last_entry_status)
730 usleep_range(10000, 20000);
731
732 /* Dump the IdleMask before we add to the STB */
733 amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
734
735 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_CHECK);
736 if (rc)
737 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
738 }
739
amd_pmc_dump_data(struct amd_pmc_dev * pdev)740 static int amd_pmc_dump_data(struct amd_pmc_dev *pdev)
741 {
742 if (pdev->cpu_id == AMD_CPU_ID_PCO)
743 return -ENODEV;
744
745 return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, false);
746 }
747
amd_pmc_s2idle_restore(void)748 static void amd_pmc_s2idle_restore(void)
749 {
750 struct amd_pmc_dev *pdev = &pmc;
751 int rc;
752 u8 msg;
753
754 msg = amd_pmc_get_os_hint(pdev);
755 rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, false);
756 if (rc)
757 dev_err(pdev->dev, "resume failed: %d\n", rc);
758
759 /* Let SMU know that we are looking for stats */
760 amd_pmc_dump_data(pdev);
761
762 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_RESTORE);
763 if (rc)
764 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
765
766 /* Notify on failed entry */
767 amd_pmc_validate_deepest(pdev);
768
769 amd_pmc_process_restore_quirks(pdev);
770 }
771
772 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
773 .prepare = amd_pmc_s2idle_prepare,
774 .check = amd_pmc_s2idle_check,
775 .restore = amd_pmc_s2idle_restore,
776 };
777
amd_pmc_suspend_handler(struct device * dev)778 static int amd_pmc_suspend_handler(struct device *dev)
779 {
780 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
781
782 /*
783 * Must be called only from the same set of dev_pm_ops handlers
784 * as i8042_pm_suspend() is called: currently just from .suspend.
785 */
786 if (pdev->disable_8042_wakeup && !disable_workarounds) {
787 int rc = amd_pmc_wa_irq1(pdev);
788
789 if (rc) {
790 dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc);
791 return rc;
792 }
793 }
794
795 return 0;
796 }
797
798 static const struct dev_pm_ops amd_pmc_pm = {
799 .suspend = amd_pmc_suspend_handler,
800 };
801
802 static const struct pci_device_id pmc_pci_ids[] = {
803 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
804 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
805 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
806 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
807 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
808 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
809 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
810 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
811 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
812 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
813 { }
814 };
815
amd_pmc_probe(struct platform_device * pdev)816 static int amd_pmc_probe(struct platform_device *pdev)
817 {
818 struct amd_pmc_dev *dev = &pmc;
819 struct pci_dev *rdev;
820 u32 base_addr_lo, base_addr_hi;
821 u64 base_addr;
822 int err;
823 u32 val;
824
825 dev->dev = &pdev->dev;
826
827 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
828 if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
829 err = -ENODEV;
830 goto err_pci_dev_put;
831 }
832
833 dev->cpu_id = rdev->device;
834
835 if (dev->cpu_id == AMD_CPU_ID_SP) {
836 dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n");
837 err = -ENODEV;
838 goto err_pci_dev_put;
839 }
840
841 dev->rdev = rdev;
842 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val);
843 if (err) {
844 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO);
845 err = pcibios_err_to_errno(err);
846 goto err_pci_dev_put;
847 }
848
849 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
850
851 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val);
852 if (err) {
853 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI);
854 err = pcibios_err_to_errno(err);
855 goto err_pci_dev_put;
856 }
857
858 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
859 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
860
861 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
862 AMD_PMC_MAPPING_SIZE);
863 if (!dev->regbase) {
864 err = -ENOMEM;
865 goto err_pci_dev_put;
866 }
867
868 mutex_init(&dev->lock);
869
870 /* Get num of IP blocks within the SoC */
871 amd_pmc_get_ip_info(dev);
872
873 platform_set_drvdata(pdev, dev);
874 if (IS_ENABLED(CONFIG_SUSPEND)) {
875 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
876 if (err)
877 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
878 if (!disable_workarounds)
879 amd_pmc_quirks_init(dev);
880 }
881
882 amd_pmc_dbgfs_register(dev);
883 err = amd_stb_s2d_init(dev);
884 if (err)
885 goto err_pci_dev_put;
886
887 if (IS_ENABLED(CONFIG_AMD_MP2_STB))
888 amd_mp2_stb_init(dev);
889 pm_report_max_hw_sleep(U64_MAX);
890 return 0;
891
892 err_pci_dev_put:
893 pci_dev_put(rdev);
894 return err;
895 }
896
amd_pmc_remove(struct platform_device * pdev)897 static void amd_pmc_remove(struct platform_device *pdev)
898 {
899 struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
900
901 if (IS_ENABLED(CONFIG_SUSPEND))
902 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
903 amd_pmc_dbgfs_unregister(dev);
904 pci_dev_put(dev->rdev);
905 if (IS_ENABLED(CONFIG_AMD_MP2_STB))
906 amd_mp2_stb_deinit(dev);
907 mutex_destroy(&dev->lock);
908 }
909
910 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
911 {"AMDI0005", 0},
912 {"AMDI0006", 0},
913 {"AMDI0007", 0},
914 {"AMDI0008", 0},
915 {"AMDI0009", 0},
916 {"AMDI000A", 0},
917 {"AMDI000B", 0},
918 {"AMD0004", 0},
919 {"AMD0005", 0},
920 { }
921 };
922 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
923
924 static struct platform_driver amd_pmc_driver = {
925 .driver = {
926 .name = "amd_pmc",
927 .acpi_match_table = amd_pmc_acpi_ids,
928 .dev_groups = pmc_groups,
929 .pm = pm_sleep_ptr(&amd_pmc_pm),
930 },
931 .probe = amd_pmc_probe,
932 .remove = amd_pmc_remove,
933 };
934 module_platform_driver(amd_pmc_driver);
935
936 MODULE_LICENSE("GPL v2");
937 MODULE_DESCRIPTION("AMD PMC Driver");
938