1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. 4 * 5 * @File cthw20k2.c 6 * 7 * @Brief 8 * This file contains the implementation of hardware access method for 20k2. 9 * 10 * @Author Liu Chun 11 * @Date May 14 2008 12 */ 13 14 #include <linux/types.h> 15 #include <linux/slab.h> 16 #include <linux/pci.h> 17 #include <linux/io.h> 18 #include <linux/string.h> 19 #include <linux/kernel.h> 20 #include <linux/interrupt.h> 21 #include <linux/delay.h> 22 #include "cthw20k2.h" 23 #include "ct20k2reg.h" 24 25 struct hw20k2 { 26 struct hw hw; 27 /* for i2c */ 28 unsigned char dev_id; 29 unsigned char addr_size; 30 unsigned char data_size; 31 32 int mic_source; 33 }; 34 35 static u32 hw_read_20kx(struct hw *hw, u32 reg); 36 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data); 37 38 /* 39 * Type definition block. 40 * The layout of control structures can be directly applied on 20k2 chip. 41 */ 42 43 /* 44 * SRC control block definitions. 45 */ 46 47 /* SRC resource control block */ 48 #define SRCCTL_STATE 0x00000007 49 #define SRCCTL_BM 0x00000008 50 #define SRCCTL_RSR 0x00000030 51 #define SRCCTL_SF 0x000001C0 52 #define SRCCTL_WR 0x00000200 53 #define SRCCTL_PM 0x00000400 54 #define SRCCTL_ROM 0x00001800 55 #define SRCCTL_VO 0x00002000 56 #define SRCCTL_ST 0x00004000 57 #define SRCCTL_IE 0x00008000 58 #define SRCCTL_ILSZ 0x000F0000 59 #define SRCCTL_BP 0x00100000 60 61 #define SRCCCR_CISZ 0x000007FF 62 #define SRCCCR_CWA 0x001FF800 63 #define SRCCCR_D 0x00200000 64 #define SRCCCR_RS 0x01C00000 65 #define SRCCCR_NAL 0x3E000000 66 #define SRCCCR_RA 0xC0000000 67 68 #define SRCCA_CA 0x0FFFFFFF 69 #define SRCCA_RS 0xE0000000 70 71 #define SRCSA_SA 0x0FFFFFFF 72 73 #define SRCLA_LA 0x0FFFFFFF 74 75 /* Mixer Parameter Ring ram Low and Hight register. 76 * Fixed-point value in 8.24 format for parameter channel */ 77 #define MPRLH_PITCH 0xFFFFFFFF 78 79 /* SRC resource register dirty flags */ 80 union src_dirty { 81 struct { 82 u16 ctl:1; 83 u16 ccr:1; 84 u16 sa:1; 85 u16 la:1; 86 u16 ca:1; 87 u16 mpr:1; 88 u16 czbfs:1; /* Clear Z-Buffers */ 89 u16 rsv:9; 90 } bf; 91 u16 data; 92 }; 93 94 struct src_rsc_ctrl_blk { 95 unsigned int ctl; 96 unsigned int ccr; 97 unsigned int ca; 98 unsigned int sa; 99 unsigned int la; 100 unsigned int mpr; 101 union src_dirty dirty; 102 }; 103 104 /* SRC manager control block */ 105 union src_mgr_dirty { 106 struct { 107 u16 enb0:1; 108 u16 enb1:1; 109 u16 enb2:1; 110 u16 enb3:1; 111 u16 enb4:1; 112 u16 enb5:1; 113 u16 enb6:1; 114 u16 enb7:1; 115 u16 enbsa:1; 116 u16 rsv:7; 117 } bf; 118 u16 data; 119 }; 120 121 struct src_mgr_ctrl_blk { 122 unsigned int enbsa; 123 unsigned int enb[8]; 124 union src_mgr_dirty dirty; 125 }; 126 127 /* SRCIMP manager control block */ 128 #define SRCAIM_ARC 0x00000FFF 129 #define SRCAIM_NXT 0x00FF0000 130 #define SRCAIM_SRC 0xFF000000 131 132 struct srcimap { 133 unsigned int srcaim; 134 unsigned int idx; 135 }; 136 137 /* SRCIMP manager register dirty flags */ 138 union srcimp_mgr_dirty { 139 struct { 140 u16 srcimap:1; 141 u16 rsv:15; 142 } bf; 143 u16 data; 144 }; 145 146 struct srcimp_mgr_ctrl_blk { 147 struct srcimap srcimap; 148 union srcimp_mgr_dirty dirty; 149 }; 150 151 /* 152 * Function implementation block. 153 */ 154 155 static int src_get_rsc_ctrl_blk(void **rblk) 156 { 157 struct src_rsc_ctrl_blk *blk; 158 159 *rblk = NULL; 160 blk = kzalloc_obj(*blk); 161 if (!blk) 162 return -ENOMEM; 163 164 *rblk = blk; 165 166 return 0; 167 } 168 169 static int src_put_rsc_ctrl_blk(void *blk) 170 { 171 kfree(blk); 172 173 return 0; 174 } 175 176 static int src_set_state(void *blk, unsigned int state) 177 { 178 struct src_rsc_ctrl_blk *ctl = blk; 179 180 set_field(&ctl->ctl, SRCCTL_STATE, state); 181 ctl->dirty.bf.ctl = 1; 182 return 0; 183 } 184 185 static int src_set_bm(void *blk, unsigned int bm) 186 { 187 struct src_rsc_ctrl_blk *ctl = blk; 188 189 set_field(&ctl->ctl, SRCCTL_BM, bm); 190 ctl->dirty.bf.ctl = 1; 191 return 0; 192 } 193 194 static int src_set_rsr(void *blk, unsigned int rsr) 195 { 196 struct src_rsc_ctrl_blk *ctl = blk; 197 198 set_field(&ctl->ctl, SRCCTL_RSR, rsr); 199 ctl->dirty.bf.ctl = 1; 200 return 0; 201 } 202 203 static int src_set_sf(void *blk, unsigned int sf) 204 { 205 struct src_rsc_ctrl_blk *ctl = blk; 206 207 set_field(&ctl->ctl, SRCCTL_SF, sf); 208 ctl->dirty.bf.ctl = 1; 209 return 0; 210 } 211 212 static int src_set_wr(void *blk, unsigned int wr) 213 { 214 struct src_rsc_ctrl_blk *ctl = blk; 215 216 set_field(&ctl->ctl, SRCCTL_WR, wr); 217 ctl->dirty.bf.ctl = 1; 218 return 0; 219 } 220 221 static int src_set_pm(void *blk, unsigned int pm) 222 { 223 struct src_rsc_ctrl_blk *ctl = blk; 224 225 set_field(&ctl->ctl, SRCCTL_PM, pm); 226 ctl->dirty.bf.ctl = 1; 227 return 0; 228 } 229 230 static int src_set_rom(void *blk, unsigned int rom) 231 { 232 struct src_rsc_ctrl_blk *ctl = blk; 233 234 set_field(&ctl->ctl, SRCCTL_ROM, rom); 235 ctl->dirty.bf.ctl = 1; 236 return 0; 237 } 238 239 static int src_set_vo(void *blk, unsigned int vo) 240 { 241 struct src_rsc_ctrl_blk *ctl = blk; 242 243 set_field(&ctl->ctl, SRCCTL_VO, vo); 244 ctl->dirty.bf.ctl = 1; 245 return 0; 246 } 247 248 static int src_set_st(void *blk, unsigned int st) 249 { 250 struct src_rsc_ctrl_blk *ctl = blk; 251 252 set_field(&ctl->ctl, SRCCTL_ST, st); 253 ctl->dirty.bf.ctl = 1; 254 return 0; 255 } 256 257 static int src_set_ie(void *blk, unsigned int ie) 258 { 259 struct src_rsc_ctrl_blk *ctl = blk; 260 261 set_field(&ctl->ctl, SRCCTL_IE, ie); 262 ctl->dirty.bf.ctl = 1; 263 return 0; 264 } 265 266 static int src_set_ilsz(void *blk, unsigned int ilsz) 267 { 268 struct src_rsc_ctrl_blk *ctl = blk; 269 270 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz); 271 ctl->dirty.bf.ctl = 1; 272 return 0; 273 } 274 275 static int src_set_bp(void *blk, unsigned int bp) 276 { 277 struct src_rsc_ctrl_blk *ctl = blk; 278 279 set_field(&ctl->ctl, SRCCTL_BP, bp); 280 ctl->dirty.bf.ctl = 1; 281 return 0; 282 } 283 284 static int src_set_cisz(void *blk, unsigned int cisz) 285 { 286 struct src_rsc_ctrl_blk *ctl = blk; 287 288 set_field(&ctl->ccr, SRCCCR_CISZ, cisz); 289 ctl->dirty.bf.ccr = 1; 290 return 0; 291 } 292 293 static int src_set_ca(void *blk, unsigned int ca) 294 { 295 struct src_rsc_ctrl_blk *ctl = blk; 296 297 set_field(&ctl->ca, SRCCA_CA, ca); 298 ctl->dirty.bf.ca = 1; 299 return 0; 300 } 301 302 static int src_set_sa(void *blk, unsigned int sa) 303 { 304 struct src_rsc_ctrl_blk *ctl = blk; 305 306 set_field(&ctl->sa, SRCSA_SA, sa); 307 ctl->dirty.bf.sa = 1; 308 return 0; 309 } 310 311 static int src_set_la(void *blk, unsigned int la) 312 { 313 struct src_rsc_ctrl_blk *ctl = blk; 314 315 set_field(&ctl->la, SRCLA_LA, la); 316 ctl->dirty.bf.la = 1; 317 return 0; 318 } 319 320 static int src_set_pitch(void *blk, unsigned int pitch) 321 { 322 struct src_rsc_ctrl_blk *ctl = blk; 323 324 set_field(&ctl->mpr, MPRLH_PITCH, pitch); 325 ctl->dirty.bf.mpr = 1; 326 return 0; 327 } 328 329 static int src_set_clear_zbufs(void *blk, unsigned int clear) 330 { 331 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0); 332 return 0; 333 } 334 335 static int src_set_dirty(void *blk, unsigned int flags) 336 { 337 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff); 338 return 0; 339 } 340 341 static int src_set_dirty_all(void *blk) 342 { 343 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0); 344 return 0; 345 } 346 347 #define AR_SLOT_SIZE 4096 348 #define AR_SLOT_BLOCK_SIZE 16 349 #define AR_PTS_PITCH 6 350 #define AR_PARAM_SRC_OFFSET 0x60 351 352 static unsigned int src_param_pitch_mixer(unsigned int src_idx) 353 { 354 return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE 355 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE; 356 357 } 358 359 static int src_commit_write(struct hw *hw, unsigned int idx, void *blk) 360 { 361 struct src_rsc_ctrl_blk *ctl = blk; 362 int i; 363 364 if (ctl->dirty.bf.czbfs) { 365 /* Clear Z-Buffer registers */ 366 for (i = 0; i < 8; i++) 367 hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0); 368 369 for (i = 0; i < 4; i++) 370 hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0); 371 372 for (i = 0; i < 8; i++) 373 hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0); 374 375 ctl->dirty.bf.czbfs = 0; 376 } 377 if (ctl->dirty.bf.mpr) { 378 /* Take the parameter mixer resource in the same group as that 379 * the idx src is in for simplicity. Unlike src, all conjugate 380 * parameter mixer resources must be programmed for 381 * corresponding conjugate src resources. */ 382 unsigned int pm_idx = src_param_pitch_mixer(idx); 383 hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr); 384 hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3); 385 hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0); 386 ctl->dirty.bf.mpr = 0; 387 } 388 if (ctl->dirty.bf.sa) { 389 hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa); 390 ctl->dirty.bf.sa = 0; 391 } 392 if (ctl->dirty.bf.la) { 393 hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la); 394 ctl->dirty.bf.la = 0; 395 } 396 if (ctl->dirty.bf.ca) { 397 hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca); 398 ctl->dirty.bf.ca = 0; 399 } 400 401 /* Write srccf register */ 402 hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0); 403 404 if (ctl->dirty.bf.ccr) { 405 hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr); 406 ctl->dirty.bf.ccr = 0; 407 } 408 if (ctl->dirty.bf.ctl) { 409 hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl); 410 ctl->dirty.bf.ctl = 0; 411 } 412 413 return 0; 414 } 415 416 static int src_get_ca(struct hw *hw, unsigned int idx, void *blk) 417 { 418 struct src_rsc_ctrl_blk *ctl = blk; 419 420 ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100); 421 ctl->dirty.bf.ca = 0; 422 423 return get_field(ctl->ca, SRCCA_CA); 424 } 425 426 static unsigned int src_get_dirty(void *blk) 427 { 428 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data; 429 } 430 431 static unsigned int src_dirty_conj_mask(void) 432 { 433 return 0x20; 434 } 435 436 static int src_mgr_enbs_src(void *blk, unsigned int idx) 437 { 438 ((struct src_mgr_ctrl_blk *)blk)->enbsa |= (0x1 << ((idx%128)/4)); 439 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1; 440 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32)); 441 return 0; 442 } 443 444 static int src_mgr_enb_src(void *blk, unsigned int idx) 445 { 446 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32)); 447 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32)); 448 return 0; 449 } 450 451 static int src_mgr_dsb_src(void *blk, unsigned int idx) 452 { 453 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32)); 454 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32)); 455 return 0; 456 } 457 458 static int src_mgr_commit_write(struct hw *hw, void *blk) 459 { 460 struct src_mgr_ctrl_blk *ctl = blk; 461 int i; 462 unsigned int ret; 463 464 if (ctl->dirty.bf.enbsa) { 465 do { 466 ret = hw_read_20kx(hw, SRC_ENBSTAT); 467 } while (ret & 0x1); 468 hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa); 469 ctl->dirty.bf.enbsa = 0; 470 } 471 for (i = 0; i < 8; i++) { 472 if ((ctl->dirty.data & (0x1 << i))) { 473 hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]); 474 ctl->dirty.data &= ~(0x1 << i); 475 } 476 } 477 478 return 0; 479 } 480 481 static int src_mgr_get_ctrl_blk(void **rblk) 482 { 483 struct src_mgr_ctrl_blk *blk; 484 485 *rblk = NULL; 486 blk = kzalloc_obj(*blk); 487 if (!blk) 488 return -ENOMEM; 489 490 *rblk = blk; 491 492 return 0; 493 } 494 495 static int src_mgr_put_ctrl_blk(void *blk) 496 { 497 kfree(blk); 498 499 return 0; 500 } 501 502 static int srcimp_mgr_get_ctrl_blk(void **rblk) 503 { 504 struct srcimp_mgr_ctrl_blk *blk; 505 506 *rblk = NULL; 507 blk = kzalloc_obj(*blk); 508 if (!blk) 509 return -ENOMEM; 510 511 *rblk = blk; 512 513 return 0; 514 } 515 516 static int srcimp_mgr_put_ctrl_blk(void *blk) 517 { 518 kfree(blk); 519 520 return 0; 521 } 522 523 static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot) 524 { 525 struct srcimp_mgr_ctrl_blk *ctl = blk; 526 527 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot); 528 ctl->dirty.bf.srcimap = 1; 529 return 0; 530 } 531 532 static int srcimp_mgr_set_imapuser(void *blk, unsigned int user) 533 { 534 struct srcimp_mgr_ctrl_blk *ctl = blk; 535 536 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user); 537 ctl->dirty.bf.srcimap = 1; 538 return 0; 539 } 540 541 static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next) 542 { 543 struct srcimp_mgr_ctrl_blk *ctl = blk; 544 545 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next); 546 ctl->dirty.bf.srcimap = 1; 547 return 0; 548 } 549 550 static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr) 551 { 552 ((struct srcimp_mgr_ctrl_blk *)blk)->srcimap.idx = addr; 553 ((struct srcimp_mgr_ctrl_blk *)blk)->dirty.bf.srcimap = 1; 554 return 0; 555 } 556 557 static int srcimp_mgr_commit_write(struct hw *hw, void *blk) 558 { 559 struct srcimp_mgr_ctrl_blk *ctl = blk; 560 561 if (ctl->dirty.bf.srcimap) { 562 hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100, 563 ctl->srcimap.srcaim); 564 ctl->dirty.bf.srcimap = 0; 565 } 566 567 return 0; 568 } 569 570 /* 571 * AMIXER control block definitions. 572 */ 573 574 #define AMOPLO_M 0x00000003 575 #define AMOPLO_IV 0x00000004 576 #define AMOPLO_X 0x0003FFF0 577 #define AMOPLO_Y 0xFFFC0000 578 579 #define AMOPHI_SADR 0x000000FF 580 #define AMOPHI_SE 0x80000000 581 582 /* AMIXER resource register dirty flags */ 583 union amixer_dirty { 584 struct { 585 u16 amoplo:1; 586 u16 amophi:1; 587 u16 rsv:14; 588 } bf; 589 u16 data; 590 }; 591 592 /* AMIXER resource control block */ 593 struct amixer_rsc_ctrl_blk { 594 unsigned int amoplo; 595 unsigned int amophi; 596 union amixer_dirty dirty; 597 }; 598 599 static int amixer_set_mode(void *blk, unsigned int mode) 600 { 601 struct amixer_rsc_ctrl_blk *ctl = blk; 602 603 set_field(&ctl->amoplo, AMOPLO_M, mode); 604 ctl->dirty.bf.amoplo = 1; 605 return 0; 606 } 607 608 static int amixer_set_iv(void *blk, unsigned int iv) 609 { 610 struct amixer_rsc_ctrl_blk *ctl = blk; 611 612 set_field(&ctl->amoplo, AMOPLO_IV, iv); 613 ctl->dirty.bf.amoplo = 1; 614 return 0; 615 } 616 617 static int amixer_set_x(void *blk, unsigned int x) 618 { 619 struct amixer_rsc_ctrl_blk *ctl = blk; 620 621 set_field(&ctl->amoplo, AMOPLO_X, x); 622 ctl->dirty.bf.amoplo = 1; 623 return 0; 624 } 625 626 static int amixer_set_y(void *blk, unsigned int y) 627 { 628 struct amixer_rsc_ctrl_blk *ctl = blk; 629 630 set_field(&ctl->amoplo, AMOPLO_Y, y); 631 ctl->dirty.bf.amoplo = 1; 632 return 0; 633 } 634 635 static int amixer_set_sadr(void *blk, unsigned int sadr) 636 { 637 struct amixer_rsc_ctrl_blk *ctl = blk; 638 639 set_field(&ctl->amophi, AMOPHI_SADR, sadr); 640 ctl->dirty.bf.amophi = 1; 641 return 0; 642 } 643 644 static int amixer_set_se(void *blk, unsigned int se) 645 { 646 struct amixer_rsc_ctrl_blk *ctl = blk; 647 648 set_field(&ctl->amophi, AMOPHI_SE, se); 649 ctl->dirty.bf.amophi = 1; 650 return 0; 651 } 652 653 static int amixer_set_dirty(void *blk, unsigned int flags) 654 { 655 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff); 656 return 0; 657 } 658 659 static int amixer_set_dirty_all(void *blk) 660 { 661 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0); 662 return 0; 663 } 664 665 static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk) 666 { 667 struct amixer_rsc_ctrl_blk *ctl = blk; 668 669 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) { 670 hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo); 671 ctl->dirty.bf.amoplo = 0; 672 hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi); 673 ctl->dirty.bf.amophi = 0; 674 } 675 676 return 0; 677 } 678 679 static int amixer_get_y(void *blk) 680 { 681 struct amixer_rsc_ctrl_blk *ctl = blk; 682 683 return get_field(ctl->amoplo, AMOPLO_Y); 684 } 685 686 static unsigned int amixer_get_dirty(void *blk) 687 { 688 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data; 689 } 690 691 static int amixer_rsc_get_ctrl_blk(void **rblk) 692 { 693 struct amixer_rsc_ctrl_blk *blk; 694 695 *rblk = NULL; 696 blk = kzalloc_obj(*blk); 697 if (!blk) 698 return -ENOMEM; 699 700 *rblk = blk; 701 702 return 0; 703 } 704 705 static int amixer_rsc_put_ctrl_blk(void *blk) 706 { 707 kfree(blk); 708 709 return 0; 710 } 711 712 static int amixer_mgr_get_ctrl_blk(void **rblk) 713 { 714 *rblk = NULL; 715 716 return 0; 717 } 718 719 static int amixer_mgr_put_ctrl_blk(void *blk) 720 { 721 return 0; 722 } 723 724 /* 725 * DAIO control block definitions. 726 */ 727 728 /* Receiver Sample Rate Tracker Control register */ 729 #define SRTCTL_SRCO 0x000000FF 730 #define SRTCTL_SRCM 0x0000FF00 731 #define SRTCTL_RSR 0x00030000 732 #define SRTCTL_DRAT 0x00300000 733 #define SRTCTL_EC 0x01000000 734 #define SRTCTL_ET 0x10000000 735 736 /* DAIO Receiver register dirty flags */ 737 union dai_dirty { 738 struct { 739 u16 srt:1; 740 u16 rsv:15; 741 } bf; 742 u16 data; 743 }; 744 745 /* DAIO Receiver control block */ 746 struct dai_ctrl_blk { 747 unsigned int srt; 748 union dai_dirty dirty; 749 }; 750 751 /* Audio Input Mapper RAM */ 752 #define AIM_ARC 0x00000FFF 753 #define AIM_NXT 0x007F0000 754 755 struct daoimap { 756 unsigned int aim; 757 unsigned int idx; 758 }; 759 760 /* Audio Transmitter Control and Status register */ 761 #define ATXCTL_EN 0x00000001 762 #define ATXCTL_MODE 0x00000010 763 #define ATXCTL_CD 0x00000020 764 #define ATXCTL_RAW 0x00000100 765 #define ATXCTL_MT 0x00000200 766 #define ATXCTL_NUC 0x00003000 767 #define ATXCTL_BEN 0x00010000 768 #define ATXCTL_BMUX 0x00700000 769 #define ATXCTL_B24 0x01000000 770 #define ATXCTL_CPF 0x02000000 771 #define ATXCTL_RIV 0x10000000 772 #define ATXCTL_LIV 0x20000000 773 #define ATXCTL_RSAT 0x40000000 774 #define ATXCTL_LSAT 0x80000000 775 776 /* XDIF Transmitter register dirty flags */ 777 union dao_dirty { 778 struct { 779 u16 atxcsl:1; 780 u16 rsv:15; 781 } bf; 782 u16 data; 783 }; 784 785 /* XDIF Transmitter control block */ 786 struct dao_ctrl_blk { 787 /* XDIF Transmitter Channel Status Low Register */ 788 unsigned int atxcsl; 789 union dao_dirty dirty; 790 }; 791 792 /* Audio Receiver Control register */ 793 #define ARXCTL_EN 0x00000001 794 795 /* DAIO manager register dirty flags */ 796 union daio_mgr_dirty { 797 struct { 798 u32 atxctl:8; 799 u32 arxctl:8; 800 u32 daoimap:1; 801 u32 rsv:15; 802 } bf; 803 u32 data; 804 }; 805 806 /* DAIO manager control block */ 807 struct daio_mgr_ctrl_blk { 808 struct daoimap daoimap; 809 unsigned int txctl[8]; 810 unsigned int rxctl[8]; 811 union daio_mgr_dirty dirty; 812 }; 813 814 static int dai_srt_set_srco(void *blk, unsigned int src) 815 { 816 struct dai_ctrl_blk *ctl = blk; 817 818 set_field(&ctl->srt, SRTCTL_SRCO, src); 819 ctl->dirty.bf.srt = 1; 820 return 0; 821 } 822 823 static int dai_srt_set_srcm(void *blk, unsigned int src) 824 { 825 struct dai_ctrl_blk *ctl = blk; 826 827 set_field(&ctl->srt, SRTCTL_SRCM, src); 828 ctl->dirty.bf.srt = 1; 829 return 0; 830 } 831 832 static int dai_srt_set_rsr(void *blk, unsigned int rsr) 833 { 834 struct dai_ctrl_blk *ctl = blk; 835 836 set_field(&ctl->srt, SRTCTL_RSR, rsr); 837 ctl->dirty.bf.srt = 1; 838 return 0; 839 } 840 841 static int dai_srt_set_drat(void *blk, unsigned int drat) 842 { 843 struct dai_ctrl_blk *ctl = blk; 844 845 set_field(&ctl->srt, SRTCTL_DRAT, drat); 846 ctl->dirty.bf.srt = 1; 847 return 0; 848 } 849 850 static int dai_srt_set_ec(void *blk, unsigned int ec) 851 { 852 struct dai_ctrl_blk *ctl = blk; 853 854 set_field(&ctl->srt, SRTCTL_EC, ec ? 1 : 0); 855 ctl->dirty.bf.srt = 1; 856 return 0; 857 } 858 859 static int dai_srt_set_et(void *blk, unsigned int et) 860 { 861 struct dai_ctrl_blk *ctl = blk; 862 863 set_field(&ctl->srt, SRTCTL_ET, et ? 1 : 0); 864 ctl->dirty.bf.srt = 1; 865 return 0; 866 } 867 868 static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk) 869 { 870 struct dai_ctrl_blk *ctl = blk; 871 872 if (ctl->dirty.bf.srt) { 873 hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt); 874 ctl->dirty.bf.srt = 0; 875 } 876 877 return 0; 878 } 879 880 static int dai_get_ctrl_blk(void **rblk) 881 { 882 struct dai_ctrl_blk *blk; 883 884 *rblk = NULL; 885 blk = kzalloc_obj(*blk); 886 if (!blk) 887 return -ENOMEM; 888 889 *rblk = blk; 890 891 return 0; 892 } 893 894 static int dai_put_ctrl_blk(void *blk) 895 { 896 kfree(blk); 897 898 return 0; 899 } 900 901 static int dao_set_spos(void *blk, unsigned int spos) 902 { 903 ((struct dao_ctrl_blk *)blk)->atxcsl = spos; 904 ((struct dao_ctrl_blk *)blk)->dirty.bf.atxcsl = 1; 905 return 0; 906 } 907 908 static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk) 909 { 910 struct dao_ctrl_blk *ctl = blk; 911 912 if (ctl->dirty.bf.atxcsl) { 913 if ((idx < 4) && ((hw->model != CTOK0010) || (idx < 3))) { 914 /* S/PDIF SPOSx */ 915 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx, 916 ctl->atxcsl); 917 } 918 ctl->dirty.bf.atxcsl = 0; 919 } 920 921 return 0; 922 } 923 924 static int dao_get_spos(void *blk, unsigned int *spos) 925 { 926 *spos = ((struct dao_ctrl_blk *)blk)->atxcsl; 927 return 0; 928 } 929 930 static int dao_get_ctrl_blk(void **rblk) 931 { 932 struct dao_ctrl_blk *blk; 933 934 *rblk = NULL; 935 blk = kzalloc_obj(*blk); 936 if (!blk) 937 return -ENOMEM; 938 939 *rblk = blk; 940 941 return 0; 942 } 943 944 static int dao_put_ctrl_blk(void *blk) 945 { 946 kfree(blk); 947 948 return 0; 949 } 950 951 static int daio_mgr_enb_dai(void *blk, unsigned int idx) 952 { 953 struct daio_mgr_ctrl_blk *ctl = blk; 954 955 set_field(&ctl->rxctl[idx], ARXCTL_EN, 1); 956 ctl->dirty.bf.arxctl |= (0x1 << idx); 957 return 0; 958 } 959 960 static int daio_mgr_dsb_dai(void *blk, unsigned int idx) 961 { 962 struct daio_mgr_ctrl_blk *ctl = blk; 963 964 set_field(&ctl->rxctl[idx], ARXCTL_EN, 0); 965 966 ctl->dirty.bf.arxctl |= (0x1 << idx); 967 return 0; 968 } 969 970 static int daio_mgr_enb_dao(void *blk, unsigned int idx) 971 { 972 struct daio_mgr_ctrl_blk *ctl = blk; 973 974 set_field(&ctl->txctl[idx], ATXCTL_EN, 1); 975 ctl->dirty.bf.atxctl |= (0x1 << idx); 976 return 0; 977 } 978 979 static int daio_mgr_dsb_dao(void *blk, unsigned int idx) 980 { 981 struct daio_mgr_ctrl_blk *ctl = blk; 982 983 set_field(&ctl->txctl[idx], ATXCTL_EN, 0); 984 ctl->dirty.bf.atxctl |= (0x1 << idx); 985 return 0; 986 } 987 988 static int daio_mgr_dao_init(struct hw *hw, void *blk, unsigned int idx, unsigned int conf) 989 { 990 struct daio_mgr_ctrl_blk *ctl = blk; 991 992 /* Port 3 is dedicated to RCA on SE-300PCIE */ 993 if ((idx < 4) && ((hw->model != CTOK0010) || (idx < 3))) { 994 /* S/PDIF output */ 995 switch ((conf & 0xf)) { 996 case 1: 997 case 9: 998 set_field(&ctl->txctl[idx], ATXCTL_NUC, 0); 999 break; 1000 case 2: 1001 set_field(&ctl->txctl[idx], ATXCTL_NUC, 1); 1002 break; 1003 case 4: 1004 set_field(&ctl->txctl[idx], ATXCTL_NUC, 2); 1005 break; 1006 case 8: 1007 set_field(&ctl->txctl[idx], ATXCTL_NUC, 3); 1008 break; 1009 default: 1010 break; 1011 } 1012 /* CDIF */ 1013 set_field(&ctl->txctl[idx], ATXCTL_CD, (!(conf & 0x7))); 1014 /* Non-audio */ 1015 set_field(&ctl->txctl[idx], ATXCTL_LIV, (conf >> 4) & 0x1); 1016 /* Non-audio */ 1017 set_field(&ctl->txctl[idx], ATXCTL_RIV, (conf >> 4) & 0x1); 1018 set_field(&ctl->txctl[idx], ATXCTL_RAW, 1019 ((conf >> 3) & 0x1) ? 0 : 0); 1020 ctl->dirty.bf.atxctl |= (0x1 << idx); 1021 } else { 1022 /* I2S output */ 1023 /*idx %= 4; */ 1024 } 1025 return 0; 1026 } 1027 1028 static int daio_mgr_set_imaparc(void *blk, unsigned int slot) 1029 { 1030 struct daio_mgr_ctrl_blk *ctl = blk; 1031 1032 set_field(&ctl->daoimap.aim, AIM_ARC, slot); 1033 ctl->dirty.bf.daoimap = 1; 1034 return 0; 1035 } 1036 1037 static int daio_mgr_set_imapnxt(void *blk, unsigned int next) 1038 { 1039 struct daio_mgr_ctrl_blk *ctl = blk; 1040 1041 set_field(&ctl->daoimap.aim, AIM_NXT, next); 1042 ctl->dirty.bf.daoimap = 1; 1043 return 0; 1044 } 1045 1046 static int daio_mgr_set_imapaddr(void *blk, unsigned int addr) 1047 { 1048 ((struct daio_mgr_ctrl_blk *)blk)->daoimap.idx = addr; 1049 ((struct daio_mgr_ctrl_blk *)blk)->dirty.bf.daoimap = 1; 1050 return 0; 1051 } 1052 1053 static int daio_mgr_commit_write(struct hw *hw, void *blk) 1054 { 1055 struct daio_mgr_ctrl_blk *ctl = blk; 1056 unsigned int data; 1057 int i; 1058 1059 for (i = 0; i < 8; i++) { 1060 if ((ctl->dirty.bf.atxctl & (0x1 << i))) { 1061 data = ctl->txctl[i]; 1062 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data); 1063 ctl->dirty.bf.atxctl &= ~(0x1 << i); 1064 mdelay(1); 1065 } 1066 if ((ctl->dirty.bf.arxctl & (0x1 << i))) { 1067 data = ctl->rxctl[i]; 1068 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data); 1069 ctl->dirty.bf.arxctl &= ~(0x1 << i); 1070 mdelay(1); 1071 } 1072 } 1073 if (ctl->dirty.bf.daoimap) { 1074 hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4, 1075 ctl->daoimap.aim); 1076 ctl->dirty.bf.daoimap = 0; 1077 } 1078 1079 return 0; 1080 } 1081 1082 static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk) 1083 { 1084 struct daio_mgr_ctrl_blk *blk; 1085 int i; 1086 1087 *rblk = NULL; 1088 blk = kzalloc_obj(*blk); 1089 if (!blk) 1090 return -ENOMEM; 1091 1092 for (i = 0; i < 8; i++) { 1093 blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i)); 1094 blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i)); 1095 } 1096 1097 *rblk = blk; 1098 1099 return 0; 1100 } 1101 1102 static int daio_mgr_put_ctrl_blk(void *blk) 1103 { 1104 kfree(blk); 1105 1106 return 0; 1107 } 1108 1109 /* Timer interrupt */ 1110 static int set_timer_irq(struct hw *hw, int enable) 1111 { 1112 hw_write_20kx(hw, GIE, enable ? IT_INT : 0); 1113 return 0; 1114 } 1115 1116 static int set_timer_tick(struct hw *hw, unsigned int ticks) 1117 { 1118 if (ticks) 1119 ticks |= TIMR_IE | TIMR_IP; 1120 hw_write_20kx(hw, TIMR, ticks); 1121 return 0; 1122 } 1123 1124 static unsigned int get_wc(struct hw *hw) 1125 { 1126 return hw_read_20kx(hw, WC); 1127 } 1128 1129 /* Card hardware initialization block */ 1130 struct dac_conf { 1131 unsigned int msr; /* master sample rate in rsrs */ 1132 }; 1133 1134 struct adc_conf { 1135 unsigned int msr; /* master sample rate in rsrs */ 1136 unsigned char input; /* the input source of ADC */ 1137 unsigned char mic20db; /* boost mic by 20db if input is microphone */ 1138 }; 1139 1140 struct daio_conf { 1141 unsigned int msr; /* master sample rate in rsrs */ 1142 }; 1143 1144 struct trn_conf { 1145 unsigned long vm_pgt_phys; 1146 }; 1147 1148 static int hw_daio_init(struct hw *hw, const struct daio_conf *info) 1149 { 1150 u32 data; 1151 int i; 1152 1153 /* Program I2S with proper sample rate and enable the correct I2S 1154 * channel. ED(0/8/16/24): Enable all I2S/I2X master clock output */ 1155 if (1 == info->msr) { 1156 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101); 1157 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101); 1158 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0); 1159 } else if (2 == info->msr) { 1160 if (hw->model != CTSB1270) { 1161 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111); 1162 } else { 1163 /* PCM4220 on Titanium HD is different. */ 1164 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11011111); 1165 } 1166 /* Specify all playing 96khz 1167 * EA [0] - Enabled 1168 * RTA [4:5] - 96kHz 1169 * EB [8] - Enabled 1170 * RTB [12:13] - 96kHz 1171 * EC [16] - Enabled 1172 * RTC [20:21] - 96kHz 1173 * ED [24] - Enabled 1174 * RTD [28:29] - 96kHz */ 1175 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111); 1176 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0); 1177 } else if ((4 == info->msr) && (hw->model == CTSB1270)) { 1178 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x21011111); 1179 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x21212121); 1180 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0); 1181 } else if ((4 == info->msr) && (hw->model == CTOK0010)) { 1182 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x21212121); 1183 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x21212121); 1184 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0); 1185 } else { 1186 dev_alert(hw->card->dev, 1187 "ERROR!!! Invalid sampling rate!!!\n"); 1188 return -EINVAL; 1189 } 1190 1191 for (i = 0; i < 8; i++) { 1192 /* Port 3 is configured as I2S on SE-300PCIE */ 1193 if ((i < 4) && ((hw->model != CTOK0010) || (i < 3))) { 1194 /* This comment looks wrong since loop is over 4 */ 1195 /* channels and emu20k2 supports 4 spdif IOs. */ 1196 /* 1st 3 channels are SPDIFs (SB0960) */ 1197 if (i == 3) 1198 data = 0x1001001; 1199 else 1200 data = 0x1000001; 1201 1202 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data); 1203 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data); 1204 1205 /* Initialize the SPDIF Out Channel status registers. 1206 * The value specified here is based on the typical 1207 * values provided in the specification, namely: Clock 1208 * Accuracy of 1000ppm, Sample Rate of 48KHz, 1209 * unspecified source number, Generation status = 1, 1210 * Category code = 0x12 (Digital Signal Mixer), 1211 * Mode = 0, Emph = 0, Copy Permitted, AN = 0 1212 * (indicating that we're transmitting digital audio, 1213 * and the Professional Use bit is 0. */ 1214 1215 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i), 1216 0x02109204); /* Default to 48kHz */ 1217 1218 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B); 1219 } else { 1220 /* Again, loop is over 4 channels not 5. */ 1221 /* Next 5 channels are I2S (SB0960) */ 1222 data = 0x11; 1223 hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), data); 1224 if (2 == info->msr) { 1225 /* Four channels per sample period */ 1226 data |= 0x1000; 1227 } else if (4 == info->msr) { 1228 /* FIXME: check this against the chip spec */ 1229 data |= 0x2000; 1230 } 1231 hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), data); 1232 } 1233 } 1234 1235 return 0; 1236 } 1237 1238 /* TRANSPORT operations */ 1239 static int hw_trn_init(struct hw *hw, const struct trn_conf *info) 1240 { 1241 u32 vmctl, data; 1242 u32 ptp_phys_low, ptp_phys_high; 1243 int i; 1244 1245 /* Set up device page table */ 1246 if ((~0UL) == info->vm_pgt_phys) { 1247 dev_alert(hw->card->dev, 1248 "Wrong device page table page address!!!\n"); 1249 return -1; 1250 } 1251 1252 vmctl = 0x80000C0F; /* 32-bit, 4k-size page */ 1253 ptp_phys_low = (u32)info->vm_pgt_phys; 1254 ptp_phys_high = upper_32_bits(info->vm_pgt_phys); 1255 if (sizeof(void *) == 8) /* 64bit address */ 1256 vmctl |= (3 << 8); 1257 /* Write page table physical address to all PTPAL registers */ 1258 for (i = 0; i < 64; i++) { 1259 hw_write_20kx(hw, VMEM_PTPAL+(16*i), ptp_phys_low); 1260 hw_write_20kx(hw, VMEM_PTPAH+(16*i), ptp_phys_high); 1261 } 1262 /* Enable virtual memory transfer */ 1263 hw_write_20kx(hw, VMEM_CTL, vmctl); 1264 /* Enable transport bus master and queueing of request */ 1265 hw_write_20kx(hw, TRANSPORT_CTL, 0x03); 1266 hw_write_20kx(hw, TRANSPORT_INT, 0x200c01); 1267 /* Enable transport ring */ 1268 data = hw_read_20kx(hw, TRANSPORT_ENB); 1269 hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03)); 1270 1271 return 0; 1272 } 1273 1274 /* Card initialization */ 1275 #define GCTL_AIE 0x00000001 1276 #define GCTL_UAA 0x00000002 1277 #define GCTL_DPC 0x00000004 1278 #define GCTL_DBP 0x00000008 1279 #define GCTL_ABP 0x00000010 1280 #define GCTL_TBP 0x00000020 1281 #define GCTL_SBP 0x00000040 1282 #define GCTL_FBP 0x00000080 1283 #define GCTL_ME 0x00000100 1284 #define GCTL_AID 0x00001000 1285 1286 #define PLLCTL_SRC 0x00000007 1287 #define PLLCTL_SPE 0x00000008 1288 #define PLLCTL_RD 0x000000F0 1289 #define PLLCTL_FD 0x0001FF00 1290 #define PLLCTL_OD 0x00060000 1291 #define PLLCTL_B 0x00080000 1292 #define PLLCTL_AS 0x00100000 1293 #define PLLCTL_LF 0x03E00000 1294 #define PLLCTL_SPS 0x1C000000 1295 #define PLLCTL_AD 0x60000000 1296 1297 #define PLLSTAT_CCS 0x00000007 1298 #define PLLSTAT_SPL 0x00000008 1299 #define PLLSTAT_CRD 0x000000F0 1300 #define PLLSTAT_CFD 0x0001FF00 1301 #define PLLSTAT_SL 0x00020000 1302 #define PLLSTAT_FAS 0x00040000 1303 #define PLLSTAT_B 0x00080000 1304 #define PLLSTAT_PD 0x00100000 1305 #define PLLSTAT_OCA 0x00200000 1306 #define PLLSTAT_NCA 0x00400000 1307 1308 static int hw_pll_init(struct hw *hw, unsigned int rsr) 1309 { 1310 unsigned int pllenb; 1311 unsigned int pllctl; 1312 unsigned int pllstat; 1313 int i; 1314 1315 pllenb = 0xB; 1316 hw_write_20kx(hw, PLL_ENB, pllenb); 1317 pllctl = 0x20C00000; 1318 set_field(&pllctl, PLLCTL_B, 0); 1319 set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 4 : 147 - 4); 1320 set_field(&pllctl, PLLCTL_RD, 48000 == rsr ? 1 - 1 : 10 - 1); 1321 hw_write_20kx(hw, PLL_CTL, pllctl); 1322 msleep(40); 1323 1324 pllctl = hw_read_20kx(hw, PLL_CTL); 1325 set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 2 : 147 - 2); 1326 hw_write_20kx(hw, PLL_CTL, pllctl); 1327 msleep(40); 1328 1329 for (i = 0; i < 1000; i++) { 1330 pllstat = hw_read_20kx(hw, PLL_STAT); 1331 if (get_field(pllstat, PLLSTAT_PD)) 1332 continue; 1333 1334 if (get_field(pllstat, PLLSTAT_B) != 1335 get_field(pllctl, PLLCTL_B)) 1336 continue; 1337 1338 if (get_field(pllstat, PLLSTAT_CCS) != 1339 get_field(pllctl, PLLCTL_SRC)) 1340 continue; 1341 1342 if (get_field(pllstat, PLLSTAT_CRD) != 1343 get_field(pllctl, PLLCTL_RD)) 1344 continue; 1345 1346 if (get_field(pllstat, PLLSTAT_CFD) != 1347 get_field(pllctl, PLLCTL_FD)) 1348 continue; 1349 1350 break; 1351 } 1352 if (i >= 1000) { 1353 dev_alert(hw->card->dev, 1354 "PLL initialization failed!!!\n"); 1355 return -EBUSY; 1356 } 1357 1358 return 0; 1359 } 1360 1361 static int hw_auto_init(struct hw *hw) 1362 { 1363 unsigned int gctl; 1364 int i; 1365 1366 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL); 1367 set_field(&gctl, GCTL_AIE, 0); 1368 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl); 1369 set_field(&gctl, GCTL_AIE, 1); 1370 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl); 1371 mdelay(10); 1372 for (i = 0; i < 400000; i++) { 1373 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL); 1374 if (get_field(gctl, GCTL_AID)) 1375 break; 1376 } 1377 if (!get_field(gctl, GCTL_AID)) { 1378 dev_alert(hw->card->dev, "Card Auto-init failed!!!\n"); 1379 return -EBUSY; 1380 } 1381 1382 return 0; 1383 } 1384 1385 /* DAC operations */ 1386 1387 #define CS4382_MC1 0x1 1388 #define CS4382_MC2 0x2 1389 #define CS4382_MC3 0x3 1390 #define CS4382_FC 0x4 1391 #define CS4382_IC 0x5 1392 #define CS4382_XC1 0x6 1393 #define CS4382_VCA1 0x7 1394 #define CS4382_VCB1 0x8 1395 #define CS4382_XC2 0x9 1396 #define CS4382_VCA2 0xA 1397 #define CS4382_VCB2 0xB 1398 #define CS4382_XC3 0xC 1399 #define CS4382_VCA3 0xD 1400 #define CS4382_VCB3 0xE 1401 #define CS4382_XC4 0xF 1402 #define CS4382_VCA4 0x10 1403 #define CS4382_VCB4 0x11 1404 #define CS4382_CREV 0x12 1405 1406 /* I2C status */ 1407 #define STATE_LOCKED 0x00 1408 #define STATE_UNLOCKED 0xAA 1409 #define DATA_READY 0x800000 /* Used with I2C_IF_STATUS */ 1410 #define DATA_ABORT 0x10000 /* Used with I2C_IF_STATUS */ 1411 1412 #define I2C_STATUS_DCM 0x00000001 1413 #define I2C_STATUS_BC 0x00000006 1414 #define I2C_STATUS_APD 0x00000008 1415 #define I2C_STATUS_AB 0x00010000 1416 #define I2C_STATUS_DR 0x00800000 1417 1418 #define I2C_ADDRESS_PTAD 0x0000FFFF 1419 #define I2C_ADDRESS_SLAD 0x007F0000 1420 1421 struct regs_cs4382 { 1422 u32 mode_control_1; 1423 u32 mode_control_2; 1424 u32 mode_control_3; 1425 1426 u32 filter_control; 1427 u32 invert_control; 1428 1429 u32 mix_control_P1; 1430 u32 vol_control_A1; 1431 u32 vol_control_B1; 1432 1433 u32 mix_control_P2; 1434 u32 vol_control_A2; 1435 u32 vol_control_B2; 1436 1437 u32 mix_control_P3; 1438 u32 vol_control_A3; 1439 u32 vol_control_B3; 1440 1441 u32 mix_control_P4; 1442 u32 vol_control_A4; 1443 u32 vol_control_B4; 1444 }; 1445 1446 static int hw20k2_i2c_unlock_full_access(struct hw *hw) 1447 { 1448 u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] = {0xB3, 0xD4}; 1449 1450 /* Send keys for forced BIOS mode */ 1451 hw_write_20kx(hw, I2C_IF_WLOCK, 1452 UnlockKeySequence_FLASH_FULLACCESS_MODE[0]); 1453 hw_write_20kx(hw, I2C_IF_WLOCK, 1454 UnlockKeySequence_FLASH_FULLACCESS_MODE[1]); 1455 /* Check whether the chip is unlocked */ 1456 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_UNLOCKED) 1457 return 0; 1458 1459 return -1; 1460 } 1461 1462 static int hw20k2_i2c_lock_chip(struct hw *hw) 1463 { 1464 /* Write twice */ 1465 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED); 1466 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED); 1467 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_LOCKED) 1468 return 0; 1469 1470 return -1; 1471 } 1472 1473 static int hw20k2_i2c_init(struct hw *hw, u8 dev_id, u8 addr_size, u8 data_size) 1474 { 1475 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw; 1476 int err; 1477 unsigned int i2c_status; 1478 unsigned int i2c_addr; 1479 1480 err = hw20k2_i2c_unlock_full_access(hw); 1481 if (err < 0) 1482 return err; 1483 1484 hw20k2->addr_size = addr_size; 1485 hw20k2->data_size = data_size; 1486 hw20k2->dev_id = dev_id; 1487 1488 i2c_addr = 0; 1489 set_field(&i2c_addr, I2C_ADDRESS_SLAD, dev_id); 1490 1491 hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr); 1492 1493 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS); 1494 1495 set_field(&i2c_status, I2C_STATUS_DCM, 1); /* Direct control mode */ 1496 1497 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status); 1498 1499 return 0; 1500 } 1501 1502 static int hw20k2_i2c_uninit(struct hw *hw) 1503 { 1504 unsigned int i2c_status; 1505 unsigned int i2c_addr; 1506 1507 i2c_addr = 0; 1508 set_field(&i2c_addr, I2C_ADDRESS_SLAD, 0x57); /* I2C id */ 1509 1510 hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr); 1511 1512 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS); 1513 1514 set_field(&i2c_status, I2C_STATUS_DCM, 0); /* I2C mode */ 1515 1516 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status); 1517 1518 return hw20k2_i2c_lock_chip(hw); 1519 } 1520 1521 static int hw20k2_i2c_wait_data_ready(struct hw *hw) 1522 { 1523 int i = 0x400000; 1524 unsigned int ret; 1525 1526 do { 1527 ret = hw_read_20kx(hw, I2C_IF_STATUS); 1528 } while ((!(ret & DATA_READY)) && --i); 1529 1530 return i; 1531 } 1532 1533 static int hw20k2_i2c_read(struct hw *hw, u16 addr, u32 *datap) 1534 { 1535 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw; 1536 unsigned int i2c_status; 1537 1538 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS); 1539 set_field(&i2c_status, I2C_STATUS_BC, 1540 (4 == hw20k2->addr_size) ? 0 : hw20k2->addr_size); 1541 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status); 1542 if (!hw20k2_i2c_wait_data_ready(hw)) 1543 return -1; 1544 1545 hw_write_20kx(hw, I2C_IF_WDATA, addr); 1546 if (!hw20k2_i2c_wait_data_ready(hw)) 1547 return -1; 1548 1549 /* Force a read operation */ 1550 hw_write_20kx(hw, I2C_IF_RDATA, 0); 1551 if (!hw20k2_i2c_wait_data_ready(hw)) 1552 return -1; 1553 1554 *datap = hw_read_20kx(hw, I2C_IF_RDATA); 1555 1556 return 0; 1557 } 1558 1559 static int hw20k2_i2c_write(struct hw *hw, u16 addr, u32 data) 1560 { 1561 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw; 1562 unsigned int i2c_data = (data << (hw20k2->addr_size * 8)) | addr; 1563 unsigned int i2c_status; 1564 1565 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS); 1566 1567 set_field(&i2c_status, I2C_STATUS_BC, 1568 (4 == (hw20k2->addr_size + hw20k2->data_size)) ? 1569 0 : (hw20k2->addr_size + hw20k2->data_size)); 1570 1571 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status); 1572 hw20k2_i2c_wait_data_ready(hw); 1573 /* Dummy write to trigger the write operation */ 1574 hw_write_20kx(hw, I2C_IF_WDATA, 0); 1575 hw20k2_i2c_wait_data_ready(hw); 1576 1577 /* This is the real data */ 1578 hw_write_20kx(hw, I2C_IF_WDATA, i2c_data); 1579 hw20k2_i2c_wait_data_ready(hw); 1580 1581 return 0; 1582 } 1583 1584 static void hw_dac_stop(struct hw *hw) 1585 { 1586 u32 data; 1587 data = hw_read_20kx(hw, GPIO_DATA); 1588 data &= 0xFFFFFFFD; 1589 hw_write_20kx(hw, GPIO_DATA, data); 1590 usleep_range(10000, 11000); 1591 } 1592 1593 static void hw_dac_start(struct hw *hw) 1594 { 1595 u32 data; 1596 data = hw_read_20kx(hw, GPIO_DATA); 1597 data |= 0x2; 1598 hw_write_20kx(hw, GPIO_DATA, data); 1599 msleep(50); 1600 } 1601 1602 static void hw_dac_reset(struct hw *hw) 1603 { 1604 hw_dac_stop(hw); 1605 hw_dac_start(hw); 1606 } 1607 1608 static int hw_dac_init(struct hw *hw, const struct dac_conf *info) 1609 { 1610 int err; 1611 u32 data; 1612 int i; 1613 struct regs_cs4382 cs_read = {0}; 1614 struct regs_cs4382 cs_def = { 1615 .mode_control_1 = 0x00000001, /* Mode Control 1 */ 1616 .mode_control_2 = 0x00000000, /* Mode Control 2 */ 1617 .mode_control_3 = 0x00000084, /* Mode Control 3 */ 1618 .filter_control = 0x00000000, /* Filter Control */ 1619 .invert_control = 0x00000000, /* Invert Control */ 1620 .mix_control_P1 = 0x00000024, /* Mixing Control Pair 1 */ 1621 .vol_control_A1 = 0x00000000, /* Vol Control A1 */ 1622 .vol_control_B1 = 0x00000000, /* Vol Control B1 */ 1623 .mix_control_P2 = 0x00000024, /* Mixing Control Pair 2 */ 1624 .vol_control_A2 = 0x00000000, /* Vol Control A2 */ 1625 .vol_control_B2 = 0x00000000, /* Vol Control B2 */ 1626 .mix_control_P3 = 0x00000024, /* Mixing Control Pair 3 */ 1627 .vol_control_A3 = 0x00000000, /* Vol Control A3 */ 1628 .vol_control_B3 = 0x00000000, /* Vol Control B3 */ 1629 .mix_control_P4 = 0x00000024, /* Mixing Control Pair 4 */ 1630 .vol_control_A4 = 0x00000000, /* Vol Control A4 */ 1631 .vol_control_B4 = 0x00000000 /* Vol Control B4 */ 1632 }; 1633 1634 if (hw->model == CTSB1270) { 1635 hw_dac_stop(hw); 1636 data = hw_read_20kx(hw, GPIO_DATA); 1637 data &= ~0x0600; 1638 if (1 == info->msr) 1639 data |= 0x0000; /* Single Speed Mode 0-50kHz */ 1640 else if (2 == info->msr) 1641 data |= 0x0200; /* Double Speed Mode 50-100kHz */ 1642 else 1643 data |= 0x0600; /* Quad Speed Mode 100-200kHz */ 1644 hw_write_20kx(hw, GPIO_DATA, data); 1645 hw_dac_start(hw); 1646 return 0; 1647 } else if (hw->model == CTOK0010) { 1648 hw_dac_stop(hw); 1649 data = hw_read_20kx(hw, GPIO_DATA); 1650 data |= 0x1000; 1651 hw_write_20kx(hw, GPIO_DATA, data); 1652 hw_dac_start(hw); 1653 return 0; 1654 } 1655 1656 /* Set DAC reset bit as output */ 1657 data = hw_read_20kx(hw, GPIO_CTRL); 1658 data |= 0x02; 1659 hw_write_20kx(hw, GPIO_CTRL, data); 1660 1661 err = hw20k2_i2c_init(hw, 0x18, 1, 1); 1662 if (err < 0) 1663 goto End; 1664 1665 for (i = 0; i < 2; i++) { 1666 /* Reset DAC twice just in-case the chip 1667 * didn't initialized properly */ 1668 hw_dac_reset(hw); 1669 hw_dac_reset(hw); 1670 1671 if (hw20k2_i2c_read(hw, CS4382_MC1, &cs_read.mode_control_1)) 1672 continue; 1673 1674 if (hw20k2_i2c_read(hw, CS4382_MC2, &cs_read.mode_control_2)) 1675 continue; 1676 1677 if (hw20k2_i2c_read(hw, CS4382_MC3, &cs_read.mode_control_3)) 1678 continue; 1679 1680 if (hw20k2_i2c_read(hw, CS4382_FC, &cs_read.filter_control)) 1681 continue; 1682 1683 if (hw20k2_i2c_read(hw, CS4382_IC, &cs_read.invert_control)) 1684 continue; 1685 1686 if (hw20k2_i2c_read(hw, CS4382_XC1, &cs_read.mix_control_P1)) 1687 continue; 1688 1689 if (hw20k2_i2c_read(hw, CS4382_VCA1, &cs_read.vol_control_A1)) 1690 continue; 1691 1692 if (hw20k2_i2c_read(hw, CS4382_VCB1, &cs_read.vol_control_B1)) 1693 continue; 1694 1695 if (hw20k2_i2c_read(hw, CS4382_XC2, &cs_read.mix_control_P2)) 1696 continue; 1697 1698 if (hw20k2_i2c_read(hw, CS4382_VCA2, &cs_read.vol_control_A2)) 1699 continue; 1700 1701 if (hw20k2_i2c_read(hw, CS4382_VCB2, &cs_read.vol_control_B2)) 1702 continue; 1703 1704 if (hw20k2_i2c_read(hw, CS4382_XC3, &cs_read.mix_control_P3)) 1705 continue; 1706 1707 if (hw20k2_i2c_read(hw, CS4382_VCA3, &cs_read.vol_control_A3)) 1708 continue; 1709 1710 if (hw20k2_i2c_read(hw, CS4382_VCB3, &cs_read.vol_control_B3)) 1711 continue; 1712 1713 if (hw20k2_i2c_read(hw, CS4382_XC4, &cs_read.mix_control_P4)) 1714 continue; 1715 1716 if (hw20k2_i2c_read(hw, CS4382_VCA4, &cs_read.vol_control_A4)) 1717 continue; 1718 1719 if (hw20k2_i2c_read(hw, CS4382_VCB4, &cs_read.vol_control_B4)) 1720 continue; 1721 1722 if (memcmp(&cs_read, &cs_def, sizeof(cs_read))) 1723 continue; 1724 else 1725 break; 1726 } 1727 1728 if (i >= 2) 1729 goto End; 1730 1731 /* Note: Every I2C write must have some delay. 1732 * This is not a requirement but the delay works here... */ 1733 hw20k2_i2c_write(hw, CS4382_MC1, 0x80); 1734 hw20k2_i2c_write(hw, CS4382_MC2, 0x10); 1735 if (1 == info->msr) { 1736 hw20k2_i2c_write(hw, CS4382_XC1, 0x24); 1737 hw20k2_i2c_write(hw, CS4382_XC2, 0x24); 1738 hw20k2_i2c_write(hw, CS4382_XC3, 0x24); 1739 hw20k2_i2c_write(hw, CS4382_XC4, 0x24); 1740 } else if (2 == info->msr) { 1741 hw20k2_i2c_write(hw, CS4382_XC1, 0x25); 1742 hw20k2_i2c_write(hw, CS4382_XC2, 0x25); 1743 hw20k2_i2c_write(hw, CS4382_XC3, 0x25); 1744 hw20k2_i2c_write(hw, CS4382_XC4, 0x25); 1745 } else { 1746 hw20k2_i2c_write(hw, CS4382_XC1, 0x26); 1747 hw20k2_i2c_write(hw, CS4382_XC2, 0x26); 1748 hw20k2_i2c_write(hw, CS4382_XC3, 0x26); 1749 hw20k2_i2c_write(hw, CS4382_XC4, 0x26); 1750 } 1751 1752 return 0; 1753 End: 1754 1755 hw20k2_i2c_uninit(hw); 1756 return -1; 1757 } 1758 1759 /* ADC operations */ 1760 #define MAKE_WM8775_ADDR(addr, data) (u32)(((addr<<1)&0xFE)|((data>>8)&0x1)) 1761 #define MAKE_WM8775_DATA(data) (u32)(data&0xFF) 1762 1763 #define WM8775_IC 0x0B 1764 #define WM8775_MMC 0x0C 1765 #define WM8775_AADCL 0x0E 1766 #define WM8775_AADCR 0x0F 1767 #define WM8775_ADCMC 0x15 1768 #define WM8775_RESET 0x17 1769 1770 static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type) 1771 { 1772 u32 data; 1773 if ((hw->model == CTSB1270) || (hw->model == CTOK0010)) { 1774 /* Titanium HD has two ADC chips, one for line in and one */ 1775 /* for MIC. Also, SE-300PCIE has a single ADC chip that */ 1776 /* simultaneously supports 4-channel input. We don't need */ 1777 /* to switch the ADC input. */ 1778 return 1; 1779 } 1780 data = hw_read_20kx(hw, GPIO_DATA); 1781 switch (type) { 1782 case ADC_MICIN: 1783 data = (data & (0x1 << 14)) ? 1 : 0; 1784 break; 1785 case ADC_LINEIN: 1786 data = (data & (0x1 << 14)) ? 0 : 1; 1787 break; 1788 default: 1789 data = 0; 1790 } 1791 return data; 1792 } 1793 1794 #define MIC_BOOST_0DB 0xCF 1795 #define MIC_BOOST_STEPS_PER_DB 2 1796 1797 static void hw_wm8775_input_select(struct hw *hw, u8 input, s8 gain_in_db) 1798 { 1799 u32 adcmc, gain; 1800 1801 if (input > 3) 1802 input = 3; 1803 1804 adcmc = ((u32)1 << input) | 0x100; /* Link L+R gain... */ 1805 1806 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, adcmc), 1807 MAKE_WM8775_DATA(adcmc)); 1808 1809 if (gain_in_db < -103) 1810 gain_in_db = -103; 1811 if (gain_in_db > 24) 1812 gain_in_db = 24; 1813 1814 gain = gain_in_db * MIC_BOOST_STEPS_PER_DB + MIC_BOOST_0DB; 1815 1816 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, gain), 1817 MAKE_WM8775_DATA(gain)); 1818 /* ...so there should be no need for the following. */ 1819 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, gain), 1820 MAKE_WM8775_DATA(gain)); 1821 } 1822 1823 static int hw_adc_input_select(struct hw *hw, enum ADCSRC type) 1824 { 1825 u32 data; 1826 data = hw_read_20kx(hw, GPIO_DATA); 1827 switch (type) { 1828 case ADC_MICIN: 1829 data |= (0x1 << 14); 1830 hw_write_20kx(hw, GPIO_DATA, data); 1831 hw_wm8775_input_select(hw, 0, 20); /* Mic, 20dB */ 1832 break; 1833 case ADC_LINEIN: 1834 data &= ~(0x1 << 14); 1835 hw_write_20kx(hw, GPIO_DATA, data); 1836 hw_wm8775_input_select(hw, 1, 0); /* Line-in, 0dB */ 1837 break; 1838 default: 1839 break; 1840 } 1841 1842 return 0; 1843 } 1844 1845 static void hw_adc_stop(struct hw *hw) 1846 { 1847 u32 data; 1848 /* Reset the ADC (reset is active low). */ 1849 data = hw_read_20kx(hw, GPIO_DATA); 1850 data &= ~(0x1 << 15); 1851 hw_write_20kx(hw, GPIO_DATA, data); 1852 usleep_range(10000, 11000); 1853 } 1854 1855 static void hw_adc_start(struct hw *hw) 1856 { 1857 u32 data; 1858 /* Return the ADC to normal operation. */ 1859 data = hw_read_20kx(hw, GPIO_DATA); 1860 data |= (0x1 << 15); 1861 hw_write_20kx(hw, GPIO_DATA, data); 1862 msleep(50); 1863 } 1864 1865 static void hw_adc_reset(struct hw *hw) 1866 { 1867 hw_adc_stop(hw); 1868 hw_adc_start(hw); 1869 } 1870 1871 static int hw_adc_init(struct hw *hw, const struct adc_conf *info) 1872 { 1873 int err; 1874 u32 data, ctl; 1875 1876 /* Set ADC reset bit as output */ 1877 data = hw_read_20kx(hw, GPIO_CTRL); 1878 data |= (0x1 << 15); 1879 hw_write_20kx(hw, GPIO_CTRL, data); 1880 1881 if (hw->model == CTOK0010) { 1882 /* Manual ADC setup for SE-300PCIE is not needed. */ 1883 hw_adc_reset(hw); 1884 return 0; 1885 } 1886 1887 /* Initialize I2C */ 1888 err = hw20k2_i2c_init(hw, 0x1A, 1, 1); 1889 if (err < 0) { 1890 dev_alert(hw->card->dev, "Failure to acquire I2C!!!\n"); 1891 goto error; 1892 } 1893 1894 hw_adc_stop(hw); 1895 1896 if (hw->model == CTSB1270) { 1897 /* Set up the PCM4220 ADC on Titanium HD */ 1898 data &= ~0x0C; 1899 if (1 == info->msr) 1900 data |= 0x00; /* Single Speed Mode 32-50kHz */ 1901 else if (2 == info->msr) 1902 data |= 0x08; /* Double Speed Mode 50-108kHz */ 1903 else 1904 data |= 0x04; /* Quad Speed Mode 108kHz-216kHz */ 1905 hw_write_20kx(hw, GPIO_DATA, data); 1906 } 1907 1908 hw_adc_start(hw); 1909 1910 /* I2C write to register offset 0x0B to set ADC LRCLK polarity */ 1911 /* invert bit, interface format to I2S, word length to 24-bit, */ 1912 /* enable ADC high pass filter. Fixes bug 5323? */ 1913 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_IC, 0x26), 1914 MAKE_WM8775_DATA(0x26)); 1915 1916 /* Set the master mode (256fs) */ 1917 if (1 == info->msr) { 1918 /* slave mode, 128x oversampling 256fs */ 1919 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02), 1920 MAKE_WM8775_DATA(0x02)); 1921 } else if ((2 == info->msr) || (4 == info->msr)) { 1922 /* slave mode, 64x oversampling, 256fs */ 1923 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A), 1924 MAKE_WM8775_DATA(0x0A)); 1925 } else { 1926 dev_alert(hw->card->dev, 1927 "Invalid master sampling rate (msr %d)!!!\n", 1928 info->msr); 1929 err = -EINVAL; 1930 goto error; 1931 } 1932 1933 if (hw->model != CTSB1270) { 1934 /* Configure GPIO bit 14 change to line-in/mic-in */ 1935 ctl = hw_read_20kx(hw, GPIO_CTRL); 1936 ctl |= 0x1 << 14; 1937 hw_write_20kx(hw, GPIO_CTRL, ctl); 1938 hw_adc_input_select(hw, ADC_LINEIN); 1939 } else { 1940 hw_wm8775_input_select(hw, 0, 0); 1941 } 1942 1943 return 0; 1944 error: 1945 hw20k2_i2c_uninit(hw); 1946 return err; 1947 } 1948 1949 static struct capabilities hw_capabilities(struct hw *hw) 1950 { 1951 struct capabilities cap; 1952 1953 cap.digit_io_switch = 0; 1954 cap.dedicated_mic = (hw->model == CTSB1270) || (hw->model == CTOK0010); 1955 cap.dedicated_rca = hw->model == CTOK0010; 1956 cap.output_switch = hw->model == CTSB1270; 1957 cap.mic_source_switch = hw->model == CTSB1270; 1958 1959 return cap; 1960 } 1961 1962 static int hw_output_switch_get(struct hw *hw) 1963 { 1964 u32 data = hw_read_20kx(hw, GPIO_EXT_DATA); 1965 1966 switch (data & 0x30) { 1967 case 0x00: 1968 return 0; 1969 case 0x10: 1970 return 1; 1971 case 0x20: 1972 return 2; 1973 default: 1974 return 3; 1975 } 1976 } 1977 1978 static int hw_output_switch_put(struct hw *hw, int position) 1979 { 1980 u32 data; 1981 1982 if (position == hw_output_switch_get(hw)) 1983 return 0; 1984 1985 /* Mute line and headphones (intended for anti-pop). */ 1986 data = hw_read_20kx(hw, GPIO_DATA); 1987 data |= (0x03 << 11); 1988 hw_write_20kx(hw, GPIO_DATA, data); 1989 1990 data = hw_read_20kx(hw, GPIO_EXT_DATA) & ~0x30; 1991 switch (position) { 1992 case 0: 1993 break; 1994 case 1: 1995 data |= 0x10; 1996 break; 1997 default: 1998 data |= 0x20; 1999 } 2000 hw_write_20kx(hw, GPIO_EXT_DATA, data); 2001 2002 /* Unmute line and headphones. */ 2003 data = hw_read_20kx(hw, GPIO_DATA); 2004 data &= ~(0x03 << 11); 2005 hw_write_20kx(hw, GPIO_DATA, data); 2006 2007 return 1; 2008 } 2009 2010 static int hw_mic_source_switch_get(struct hw *hw) 2011 { 2012 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw; 2013 2014 return hw20k2->mic_source; 2015 } 2016 2017 static int hw_mic_source_switch_put(struct hw *hw, int position) 2018 { 2019 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw; 2020 2021 if (position == hw20k2->mic_source) 2022 return 0; 2023 2024 switch (position) { 2025 case 0: 2026 hw_wm8775_input_select(hw, 0, 0); /* Mic, 0dB */ 2027 break; 2028 case 1: 2029 hw_wm8775_input_select(hw, 1, 0); /* FP Mic, 0dB */ 2030 break; 2031 case 2: 2032 hw_wm8775_input_select(hw, 3, 0); /* Aux Ext, 0dB */ 2033 break; 2034 default: 2035 return 0; 2036 } 2037 2038 hw20k2->mic_source = position; 2039 2040 return 1; 2041 } 2042 2043 static irqreturn_t ct_20k2_interrupt(int irq, void *dev_id) 2044 { 2045 struct hw *hw = dev_id; 2046 unsigned int status; 2047 2048 status = hw_read_20kx(hw, GIP); 2049 if (!status) 2050 return IRQ_NONE; 2051 2052 if (hw->irq_callback) 2053 hw->irq_callback(hw->irq_callback_data, status); 2054 2055 hw_write_20kx(hw, GIP, status); 2056 return IRQ_HANDLED; 2057 } 2058 2059 static int hw_card_start(struct hw *hw) 2060 { 2061 int err = 0; 2062 struct pci_dev *pci = hw->pci; 2063 unsigned int gctl; 2064 const unsigned int dma_bits = BITS_PER_LONG; 2065 2066 err = pci_enable_device(pci); 2067 if (err < 0) 2068 return err; 2069 2070 /* Set DMA transfer mask */ 2071 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) 2072 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 2073 2074 if (!hw->io_base) { 2075 err = pci_request_regions(pci, "XFi"); 2076 if (err < 0) 2077 goto error1; 2078 2079 hw->io_base = pci_resource_start(hw->pci, 2); 2080 hw->mem_base = ioremap(hw->io_base, 2081 pci_resource_len(hw->pci, 2)); 2082 if (!hw->mem_base) { 2083 err = -ENOENT; 2084 goto error2; 2085 } 2086 } 2087 2088 /* Switch to 20k2 mode from UAA mode. */ 2089 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL); 2090 set_field(&gctl, GCTL_UAA, 0); 2091 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl); 2092 2093 if (hw->irq < 0) { 2094 err = request_irq(pci->irq, ct_20k2_interrupt, IRQF_SHARED, 2095 KBUILD_MODNAME, hw); 2096 if (err < 0) { 2097 dev_err(hw->card->dev, 2098 "XFi: Cannot get irq %d\n", pci->irq); 2099 goto error2; 2100 } 2101 hw->irq = pci->irq; 2102 hw->card->sync_irq = hw->irq; 2103 } 2104 2105 pci_set_master(pci); 2106 2107 return 0; 2108 2109 /*error3: 2110 iounmap((void *)hw->mem_base); 2111 hw->mem_base = (unsigned long)NULL;*/ 2112 error2: 2113 pci_release_regions(pci); 2114 hw->io_base = 0; 2115 error1: 2116 pci_disable_device(pci); 2117 return err; 2118 } 2119 2120 static int hw_card_stop(struct hw *hw) 2121 { 2122 unsigned int data; 2123 2124 /* disable transport bus master and queueing of request */ 2125 hw_write_20kx(hw, TRANSPORT_CTL, 0x00); 2126 2127 /* disable pll */ 2128 data = hw_read_20kx(hw, PLL_ENB); 2129 hw_write_20kx(hw, PLL_ENB, (data & (~0x07))); 2130 2131 /* TODO: Disable interrupt and so on... */ 2132 return 0; 2133 } 2134 2135 static int hw_card_shutdown(struct hw *hw) 2136 { 2137 if (hw->irq >= 0) 2138 free_irq(hw->irq, hw); 2139 2140 hw->irq = -1; 2141 iounmap(hw->mem_base); 2142 hw->mem_base = NULL; 2143 2144 if (hw->io_base) 2145 pci_release_regions(hw->pci); 2146 2147 hw->io_base = 0; 2148 2149 pci_disable_device(hw->pci); 2150 2151 return 0; 2152 } 2153 2154 static int hw_card_init(struct hw *hw, struct card_conf *info) 2155 { 2156 int err; 2157 unsigned int gctl; 2158 u32 data = 0; 2159 struct dac_conf dac_info = {0}; 2160 struct adc_conf adc_info = {0}; 2161 struct daio_conf daio_info = {0}; 2162 struct trn_conf trn_info = {0}; 2163 2164 /* Get PCI io port/memory base address and 2165 * do 20kx core switch if needed. */ 2166 err = hw_card_start(hw); 2167 if (err) 2168 return err; 2169 2170 /* PLL init */ 2171 err = hw_pll_init(hw, info->rsr); 2172 if (err < 0) 2173 return err; 2174 2175 /* kick off auto-init */ 2176 err = hw_auto_init(hw); 2177 if (err < 0) 2178 return err; 2179 2180 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL); 2181 set_field(&gctl, GCTL_DBP, 1); 2182 set_field(&gctl, GCTL_TBP, 1); 2183 set_field(&gctl, GCTL_FBP, 1); 2184 set_field(&gctl, GCTL_DPC, 0); 2185 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl); 2186 2187 /* Reset all global pending interrupts */ 2188 hw_write_20kx(hw, GIE, 0); 2189 /* Reset all SRC pending interrupts */ 2190 hw_write_20kx(hw, SRC_IP, 0); 2191 2192 if (hw->model == CTSB1270) { 2193 hw_write_20kx(hw, GPIO_CTRL, 0x9E5F); 2194 } else if (hw->model == CTOK0010) { 2195 hw_write_20kx(hw, GPIO_CTRL, 0x9902); 2196 } else { 2197 /* TODO: detect the card ID and configure GPIO accordingly. */ 2198 /* Configures GPIO (0xD802 0x98028) */ 2199 /*hw_write_20kx(hw, GPIO_CTRL, 0x7F07);*/ 2200 /* Configures GPIO (SB0880) */ 2201 /*hw_write_20kx(hw, GPIO_CTRL, 0xFF07);*/ 2202 hw_write_20kx(hw, GPIO_CTRL, 0xD802); 2203 } 2204 /* Enable audio ring */ 2205 hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01); 2206 2207 trn_info.vm_pgt_phys = info->vm_pgt_phys; 2208 err = hw_trn_init(hw, &trn_info); 2209 if (err < 0) 2210 return err; 2211 2212 daio_info.msr = info->msr; 2213 err = hw_daio_init(hw, &daio_info); 2214 if (err < 0) 2215 return err; 2216 2217 dac_info.msr = info->msr; 2218 err = hw_dac_init(hw, &dac_info); 2219 if (err < 0) 2220 return err; 2221 2222 adc_info.msr = info->msr; 2223 adc_info.input = ADC_LINEIN; 2224 adc_info.mic20db = 0; 2225 err = hw_adc_init(hw, &adc_info); 2226 if (err < 0) 2227 return err; 2228 2229 data = hw_read_20kx(hw, SRC_MCTL); 2230 data |= 0x1; /* Enables input from the audio ring */ 2231 hw_write_20kx(hw, SRC_MCTL, data); 2232 2233 return 0; 2234 } 2235 2236 #ifdef CONFIG_PM_SLEEP 2237 static int hw_suspend(struct hw *hw) 2238 { 2239 hw_card_stop(hw); 2240 return 0; 2241 } 2242 2243 static int hw_resume(struct hw *hw, struct card_conf *info) 2244 { 2245 /* Re-initialize card hardware. */ 2246 return hw_card_init(hw, info); 2247 } 2248 #endif 2249 2250 static u32 hw_read_20kx(struct hw *hw, u32 reg) 2251 { 2252 return readl(hw->mem_base + reg); 2253 } 2254 2255 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data) 2256 { 2257 writel(data, hw->mem_base + reg); 2258 } 2259 2260 static const struct hw ct20k2_preset = { 2261 .irq = -1, 2262 2263 .card_init = hw_card_init, 2264 .card_stop = hw_card_stop, 2265 .pll_init = hw_pll_init, 2266 .is_adc_source_selected = hw_is_adc_input_selected, 2267 .select_adc_source = hw_adc_input_select, 2268 .capabilities = hw_capabilities, 2269 .output_switch_get = hw_output_switch_get, 2270 .output_switch_put = hw_output_switch_put, 2271 .mic_source_switch_get = hw_mic_source_switch_get, 2272 .mic_source_switch_put = hw_mic_source_switch_put, 2273 #ifdef CONFIG_PM_SLEEP 2274 .suspend = hw_suspend, 2275 .resume = hw_resume, 2276 #endif 2277 2278 .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk, 2279 .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk, 2280 .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk, 2281 .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk, 2282 .src_set_state = src_set_state, 2283 .src_set_bm = src_set_bm, 2284 .src_set_rsr = src_set_rsr, 2285 .src_set_sf = src_set_sf, 2286 .src_set_wr = src_set_wr, 2287 .src_set_pm = src_set_pm, 2288 .src_set_rom = src_set_rom, 2289 .src_set_vo = src_set_vo, 2290 .src_set_st = src_set_st, 2291 .src_set_ie = src_set_ie, 2292 .src_set_ilsz = src_set_ilsz, 2293 .src_set_bp = src_set_bp, 2294 .src_set_cisz = src_set_cisz, 2295 .src_set_ca = src_set_ca, 2296 .src_set_sa = src_set_sa, 2297 .src_set_la = src_set_la, 2298 .src_set_pitch = src_set_pitch, 2299 .src_set_dirty = src_set_dirty, 2300 .src_set_clear_zbufs = src_set_clear_zbufs, 2301 .src_set_dirty_all = src_set_dirty_all, 2302 .src_commit_write = src_commit_write, 2303 .src_get_ca = src_get_ca, 2304 .src_get_dirty = src_get_dirty, 2305 .src_dirty_conj_mask = src_dirty_conj_mask, 2306 .src_mgr_enbs_src = src_mgr_enbs_src, 2307 .src_mgr_enb_src = src_mgr_enb_src, 2308 .src_mgr_dsb_src = src_mgr_dsb_src, 2309 .src_mgr_commit_write = src_mgr_commit_write, 2310 2311 .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk, 2312 .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk, 2313 .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc, 2314 .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser, 2315 .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt, 2316 .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr, 2317 .srcimp_mgr_commit_write = srcimp_mgr_commit_write, 2318 2319 .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk, 2320 .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk, 2321 .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk, 2322 .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk, 2323 .amixer_set_mode = amixer_set_mode, 2324 .amixer_set_iv = amixer_set_iv, 2325 .amixer_set_x = amixer_set_x, 2326 .amixer_set_y = amixer_set_y, 2327 .amixer_set_sadr = amixer_set_sadr, 2328 .amixer_set_se = amixer_set_se, 2329 .amixer_set_dirty = amixer_set_dirty, 2330 .amixer_set_dirty_all = amixer_set_dirty_all, 2331 .amixer_commit_write = amixer_commit_write, 2332 .amixer_get_y = amixer_get_y, 2333 .amixer_get_dirty = amixer_get_dirty, 2334 2335 .dai_get_ctrl_blk = dai_get_ctrl_blk, 2336 .dai_put_ctrl_blk = dai_put_ctrl_blk, 2337 .dai_srt_set_srco = dai_srt_set_srco, 2338 .dai_srt_set_srcm = dai_srt_set_srcm, 2339 .dai_srt_set_rsr = dai_srt_set_rsr, 2340 .dai_srt_set_drat = dai_srt_set_drat, 2341 .dai_srt_set_ec = dai_srt_set_ec, 2342 .dai_srt_set_et = dai_srt_set_et, 2343 .dai_commit_write = dai_commit_write, 2344 2345 .dao_get_ctrl_blk = dao_get_ctrl_blk, 2346 .dao_put_ctrl_blk = dao_put_ctrl_blk, 2347 .dao_set_spos = dao_set_spos, 2348 .dao_commit_write = dao_commit_write, 2349 .dao_get_spos = dao_get_spos, 2350 2351 .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk, 2352 .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk, 2353 .daio_mgr_enb_dai = daio_mgr_enb_dai, 2354 .daio_mgr_dsb_dai = daio_mgr_dsb_dai, 2355 .daio_mgr_enb_dao = daio_mgr_enb_dao, 2356 .daio_mgr_dsb_dao = daio_mgr_dsb_dao, 2357 .daio_mgr_dao_init = daio_mgr_dao_init, 2358 .daio_mgr_set_imaparc = daio_mgr_set_imaparc, 2359 .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt, 2360 .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr, 2361 .daio_mgr_commit_write = daio_mgr_commit_write, 2362 2363 .set_timer_irq = set_timer_irq, 2364 .set_timer_tick = set_timer_tick, 2365 .get_wc = get_wc, 2366 }; 2367 2368 int create_20k2_hw_obj(struct hw **rhw) 2369 { 2370 struct hw20k2 *hw20k2; 2371 2372 *rhw = NULL; 2373 hw20k2 = kzalloc_obj(*hw20k2); 2374 if (!hw20k2) 2375 return -ENOMEM; 2376 2377 hw20k2->hw = ct20k2_preset; 2378 *rhw = &hw20k2->hw; 2379 2380 return 0; 2381 } 2382 2383 int destroy_20k2_hw_obj(struct hw *hw) 2384 { 2385 if (hw->io_base) 2386 hw_card_shutdown(hw); 2387 2388 kfree(hw); 2389 return 0; 2390 } 2391