1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2023, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/kobject.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/nvmem-consumer.h> 13 #include <linux/nvmem-provider.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/reset.h> 19 #include <linux/slab.h> 20 #include <linux/sys_soc.h> 21 22 #include <soc/tegra/common.h> 23 #include <soc/tegra/fuse.h> 24 25 #include "fuse.h" 26 27 struct tegra_sku_info tegra_sku_info; 28 EXPORT_SYMBOL(tegra_sku_info); 29 30 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { 31 [TEGRA_REVISION_UNKNOWN] = "unknown", 32 [TEGRA_REVISION_A01] = "A01", 33 [TEGRA_REVISION_A02] = "A02", 34 [TEGRA_REVISION_A03] = "A03", 35 [TEGRA_REVISION_A03p] = "A03 prime", 36 [TEGRA_REVISION_A04] = "A04", 37 [TEGRA_REVISION_B01] = "B01", 38 }; 39 40 static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = { 41 [TEGRA_PLATFORM_SILICON] = "Silicon", 42 [TEGRA_PLATFORM_QT] = "QT", 43 [TEGRA_PLATFORM_SYSTEM_FPGA] = "System FPGA", 44 [TEGRA_PLATFORM_UNIT_FPGA] = "Unit FPGA", 45 [TEGRA_PLATFORM_ASIM_QT] = "Asim QT", 46 [TEGRA_PLATFORM_ASIM_LINSIM] = "Asim Linsim", 47 [TEGRA_PLATFORM_DSIM_ASIM_LINSIM] = "Dsim Asim Linsim", 48 [TEGRA_PLATFORM_VERIFICATION_SIMULATION] = "Verification Simulation", 49 [TEGRA_PLATFORM_VDK] = "VDK", 50 [TEGRA_PLATFORM_VSP] = "VSP", 51 }; 52 53 static const struct of_device_id car_match[] __initconst = { 54 { .compatible = "nvidia,tegra20-car", }, 55 { .compatible = "nvidia,tegra30-car", }, 56 { .compatible = "nvidia,tegra114-car", }, 57 { .compatible = "nvidia,tegra124-car", }, 58 { .compatible = "nvidia,tegra132-car", }, 59 { .compatible = "nvidia,tegra210-car", }, 60 {}, 61 }; 62 63 static struct tegra_fuse *fuse = &(struct tegra_fuse) { 64 .base = NULL, 65 .soc = NULL, 66 }; 67 68 static const struct of_device_id tegra_fuse_match[] = { 69 #ifdef CONFIG_ARCH_TEGRA_264_SOC 70 { .compatible = "nvidia,tegra264-efuse", .data = &tegra264_fuse_soc }, 71 #endif 72 #ifdef CONFIG_ARCH_TEGRA_234_SOC 73 { .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc }, 74 #endif 75 #ifdef CONFIG_ARCH_TEGRA_194_SOC 76 { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc }, 77 #endif 78 #ifdef CONFIG_ARCH_TEGRA_186_SOC 79 { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc }, 80 #endif 81 #ifdef CONFIG_ARCH_TEGRA_210_SOC 82 { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc }, 83 #endif 84 #ifdef CONFIG_ARCH_TEGRA_132_SOC 85 { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc }, 86 #endif 87 #ifdef CONFIG_ARCH_TEGRA_124_SOC 88 { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc }, 89 #endif 90 #ifdef CONFIG_ARCH_TEGRA_114_SOC 91 { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc }, 92 #endif 93 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 94 { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc }, 95 #endif 96 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 97 { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc }, 98 #endif 99 { /* sentinel */ } 100 }; 101 102 static int tegra_fuse_read(void *priv, unsigned int offset, void *value, 103 size_t bytes) 104 { 105 unsigned int count = bytes / 4, i; 106 struct tegra_fuse *fuse = priv; 107 u32 *buffer = value; 108 109 for (i = 0; i < count; i++) 110 buffer[i] = fuse->read(fuse, offset + i * 4); 111 112 return 0; 113 } 114 115 static void tegra_fuse_restore(void *base) 116 { 117 fuse->base = (void __iomem *)base; 118 fuse->clk = NULL; 119 } 120 121 static void tegra_fuse_print_sku_info(struct tegra_sku_info *tegra_sku_info) 122 { 123 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n", 124 tegra_revision_name[tegra_sku_info->revision], 125 tegra_sku_info->sku_id, tegra_sku_info->cpu_process_id, 126 tegra_sku_info->soc_process_id); 127 pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n", 128 tegra_sku_info->cpu_speedo_id, tegra_sku_info->soc_speedo_id); 129 } 130 131 static int tegra_fuse_add_lookups(struct tegra_fuse *fuse) 132 { 133 fuse->lookups = kmemdup_array(fuse->soc->lookups, fuse->soc->num_lookups, 134 sizeof(*fuse->lookups), GFP_KERNEL); 135 if (!fuse->lookups) 136 return -ENOMEM; 137 138 nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups); 139 140 return 0; 141 } 142 143 static int tegra_fuse_probe(struct platform_device *pdev) 144 { 145 void __iomem *base = fuse->base; 146 struct nvmem_config nvmem; 147 struct resource *res; 148 int err; 149 150 err = devm_add_action(&pdev->dev, tegra_fuse_restore, (void __force *)base); 151 if (err) 152 return err; 153 154 /* take over the memory region from the early initialization */ 155 fuse->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 156 if (IS_ERR(fuse->base)) 157 return PTR_ERR(fuse->base); 158 fuse->phys = res->start; 159 160 /* Initialize the soc data and lookups if using ACPI boot. */ 161 if (is_acpi_node(dev_fwnode(&pdev->dev)) && !fuse->soc) { 162 u8 chip; 163 164 tegra_acpi_init_apbmisc(); 165 166 chip = tegra_get_chip_id(); 167 switch (chip) { 168 #if defined(CONFIG_ARCH_TEGRA_194_SOC) 169 case TEGRA194: 170 fuse->soc = &tegra194_fuse_soc; 171 break; 172 #endif 173 #if defined(CONFIG_ARCH_TEGRA_234_SOC) 174 case TEGRA234: 175 fuse->soc = &tegra234_fuse_soc; 176 break; 177 #endif 178 #if defined(CONFIG_ARCH_TEGRA_241_SOC) 179 case TEGRA241: 180 fuse->soc = &tegra241_fuse_soc; 181 break; 182 #endif 183 #if defined(CONFIG_ARCH_TEGRA_264_SOC) 184 case TEGRA264: 185 fuse->soc = &tegra264_fuse_soc; 186 break; 187 #endif 188 default: 189 return dev_err_probe(&pdev->dev, -EINVAL, "Unsupported SoC: %02x\n", chip); 190 } 191 192 fuse->soc->init(fuse); 193 } 194 195 fuse->clk = devm_clk_get_optional(&pdev->dev, "fuse"); 196 if (IS_ERR(fuse->clk)) 197 return dev_err_probe(&pdev->dev, PTR_ERR(fuse->clk), "failed to get FUSE clock\n"); 198 199 platform_set_drvdata(pdev, fuse); 200 fuse->dev = &pdev->dev; 201 202 err = devm_pm_runtime_enable(&pdev->dev); 203 if (err) 204 return err; 205 206 if (fuse->soc->probe) { 207 err = fuse->soc->probe(fuse); 208 if (err < 0) 209 return err; 210 } 211 212 memset(&nvmem, 0, sizeof(nvmem)); 213 nvmem.dev = &pdev->dev; 214 nvmem.name = "fuse"; 215 nvmem.id = -1; 216 nvmem.owner = THIS_MODULE; 217 nvmem.cells = fuse->soc->cells; 218 nvmem.ncells = fuse->soc->num_cells; 219 nvmem.keepout = fuse->soc->keepouts; 220 nvmem.nkeepout = fuse->soc->num_keepouts; 221 nvmem.type = NVMEM_TYPE_OTP; 222 nvmem.read_only = true; 223 nvmem.root_only = false; 224 nvmem.reg_read = tegra_fuse_read; 225 nvmem.size = fuse->soc->info->size; 226 nvmem.word_size = 4; 227 nvmem.stride = 4; 228 nvmem.priv = fuse; 229 230 fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem); 231 if (IS_ERR(fuse->nvmem)) { 232 err = PTR_ERR(fuse->nvmem); 233 dev_err(&pdev->dev, "failed to register NVMEM device: %d\n", 234 err); 235 return err; 236 } 237 238 err = tegra_fuse_add_lookups(fuse); 239 if (err) 240 return dev_err_probe(&pdev->dev, err, "failed to add FUSE lookups\n"); 241 242 fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse"); 243 if (IS_ERR(fuse->rst)) 244 return dev_err_probe(&pdev->dev, PTR_ERR(fuse->rst), "failed to get FUSE reset\n"); 245 246 /* 247 * FUSE clock is enabled at a boot time, hence this resume/suspend 248 * disables the clock besides the h/w resetting. 249 */ 250 err = pm_runtime_resume_and_get(&pdev->dev); 251 if (err) 252 return err; 253 254 err = reset_control_reset(fuse->rst); 255 pm_runtime_put(&pdev->dev); 256 257 if (err < 0) { 258 dev_err(&pdev->dev, "failed to reset FUSE: %d\n", err); 259 return err; 260 } 261 262 /* release the early I/O memory mapping */ 263 iounmap(base); 264 265 return 0; 266 } 267 268 static int __maybe_unused tegra_fuse_runtime_resume(struct device *dev) 269 { 270 struct tegra_fuse *fuse = dev_get_drvdata(dev); 271 int err; 272 273 err = clk_prepare_enable(fuse->clk); 274 if (err < 0) { 275 dev_err(dev, "failed to enable FUSE clock: %d\n", err); 276 return err; 277 } 278 279 return 0; 280 } 281 282 static int __maybe_unused tegra_fuse_runtime_suspend(struct device *dev) 283 { 284 struct tegra_fuse *fuse = dev_get_drvdata(dev); 285 286 clk_disable_unprepare(fuse->clk); 287 288 return 0; 289 } 290 291 static int __maybe_unused tegra_fuse_suspend(struct device *dev) 292 { 293 struct tegra_fuse *fuse = dev_get_drvdata(dev); 294 int ret; 295 296 /* 297 * Critical for RAM re-repair operation, which must occur on resume 298 * from LP1 system suspend and as part of CCPLEX cluster switching. 299 */ 300 if (fuse->soc->clk_suspend_on) 301 ret = pm_runtime_resume_and_get(dev); 302 else 303 ret = pm_runtime_force_suspend(dev); 304 305 return ret; 306 } 307 308 static int __maybe_unused tegra_fuse_resume(struct device *dev) 309 { 310 struct tegra_fuse *fuse = dev_get_drvdata(dev); 311 int ret = 0; 312 313 if (fuse->soc->clk_suspend_on) 314 pm_runtime_put(dev); 315 else 316 ret = pm_runtime_force_resume(dev); 317 318 return ret; 319 } 320 321 static const struct dev_pm_ops tegra_fuse_pm = { 322 SET_RUNTIME_PM_OPS(tegra_fuse_runtime_suspend, tegra_fuse_runtime_resume, 323 NULL) 324 SET_SYSTEM_SLEEP_PM_OPS(tegra_fuse_suspend, tegra_fuse_resume) 325 }; 326 327 static const struct acpi_device_id tegra_fuse_acpi_match[] = { 328 { "NVDA200F" }, 329 { /* sentinel */ } 330 }; 331 MODULE_DEVICE_TABLE(acpi, tegra_fuse_acpi_match); 332 333 static struct platform_driver tegra_fuse_driver = { 334 .driver = { 335 .name = "tegra-fuse", 336 .of_match_table = tegra_fuse_match, 337 .acpi_match_table = tegra_fuse_acpi_match, 338 .pm = &tegra_fuse_pm, 339 .suppress_bind_attrs = true, 340 }, 341 .probe = tegra_fuse_probe, 342 }; 343 builtin_platform_driver(tegra_fuse_driver); 344 345 u32 __init tegra_fuse_read_spare(unsigned int spare) 346 { 347 unsigned int offset = fuse->soc->info->spare + spare * 4; 348 349 return fuse->read_early(fuse, offset) & 1; 350 } 351 352 u32 __init tegra_fuse_read_early(unsigned int offset) 353 { 354 return fuse->read_early(fuse, offset); 355 } 356 357 int tegra_fuse_readl(unsigned long offset, u32 *value) 358 { 359 if (!fuse->dev) 360 return -EPROBE_DEFER; 361 362 /* 363 * Wait for fuse->clk to be initialized if device-tree boot is used. 364 */ 365 if (is_of_node(dev_fwnode(fuse->dev)) && !fuse->clk) 366 return -EPROBE_DEFER; 367 368 if (!fuse->read) 369 return -EPROBE_DEFER; 370 371 if (IS_ERR(fuse->clk)) 372 return PTR_ERR(fuse->clk); 373 374 *value = fuse->read(fuse, offset); 375 376 return 0; 377 } 378 EXPORT_SYMBOL(tegra_fuse_readl); 379 380 static void tegra_enable_fuse_clk(void __iomem *base) 381 { 382 u32 reg; 383 384 reg = readl_relaxed(base + 0x48); 385 reg |= 1 << 28; 386 writel(reg, base + 0x48); 387 388 /* 389 * Enable FUSE clock. This needs to be hardcoded because the clock 390 * subsystem is not active during early boot. 391 */ 392 reg = readl(base + 0x14); 393 reg |= 1 << 7; 394 writel(reg, base + 0x14); 395 } 396 397 static ssize_t major_show(struct device *dev, struct device_attribute *attr, 398 char *buf) 399 { 400 return sprintf(buf, "%d\n", tegra_get_major_rev()); 401 } 402 403 static DEVICE_ATTR_RO(major); 404 405 static ssize_t minor_show(struct device *dev, struct device_attribute *attr, 406 char *buf) 407 { 408 return sprintf(buf, "%d\n", tegra_get_minor_rev()); 409 } 410 411 static DEVICE_ATTR_RO(minor); 412 413 static struct attribute *tegra_soc_attr[] = { 414 &dev_attr_major.attr, 415 &dev_attr_minor.attr, 416 NULL, 417 }; 418 419 const struct attribute_group tegra_soc_attr_group = { 420 .attrs = tegra_soc_attr, 421 }; 422 423 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ 424 IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \ 425 IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC) || \ 426 IS_ENABLED(CONFIG_ARCH_TEGRA_264_SOC) 427 static ssize_t platform_show(struct device *dev, struct device_attribute *attr, 428 char *buf) 429 { 430 /* 431 * Displays the value in the 'pre_si_platform' field of the HIDREV 432 * register for Tegra194 devices. A value of 0 indicates that the 433 * platform type is silicon and all other non-zero values indicate 434 * the type of simulation platform is being used. 435 */ 436 return sprintf(buf, "%d\n", tegra_get_platform()); 437 } 438 439 static DEVICE_ATTR_RO(platform); 440 441 static struct attribute *tegra194_soc_attr[] = { 442 &dev_attr_major.attr, 443 &dev_attr_minor.attr, 444 &dev_attr_platform.attr, 445 NULL, 446 }; 447 448 const struct attribute_group tegra194_soc_attr_group = { 449 .attrs = tegra194_soc_attr, 450 }; 451 #endif 452 453 struct device *tegra_soc_device_register(void) 454 { 455 struct soc_device_attribute *attr; 456 struct soc_device *dev; 457 458 attr = kzalloc_obj(*attr); 459 if (!attr) 460 return NULL; 461 462 attr->family = kasprintf(GFP_KERNEL, "Tegra"); 463 if (tegra_is_silicon()) 464 attr->revision = kasprintf(GFP_KERNEL, "%s %s", 465 tegra_platform_name[tegra_sku_info.platform], 466 tegra_revision_name[tegra_sku_info.revision]); 467 else 468 attr->revision = kasprintf(GFP_KERNEL, "%s", 469 tegra_platform_name[tegra_sku_info.platform]); 470 attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); 471 attr->custom_attr_group = fuse->soc->soc_attr_group; 472 473 dev = soc_device_register(attr); 474 if (IS_ERR(dev)) { 475 kfree(attr->soc_id); 476 kfree(attr->revision); 477 kfree(attr->family); 478 kfree(attr); 479 return ERR_CAST(dev); 480 } 481 482 return soc_device_to_device(dev); 483 } 484 485 static int __init tegra_init_fuse(void) 486 { 487 const struct of_device_id *match; 488 struct device_node *np; 489 struct resource regs; 490 int err = 0; 491 492 tegra_init_apbmisc(); 493 494 np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match); 495 if (!np) { 496 /* 497 * Fall back to legacy initialization for 32-bit ARM only. All 498 * 64-bit ARM device tree files for Tegra are required to have 499 * a FUSE node. 500 * 501 * This is for backwards-compatibility with old device trees 502 * that didn't contain a FUSE node. 503 */ 504 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 505 u8 chip = tegra_get_chip_id(); 506 507 regs.start = 0x7000f800; 508 regs.end = 0x7000fbff; 509 regs.flags = IORESOURCE_MEM; 510 511 switch (chip) { 512 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 513 case TEGRA20: 514 fuse->soc = &tegra20_fuse_soc; 515 break; 516 #endif 517 518 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 519 case TEGRA30: 520 fuse->soc = &tegra30_fuse_soc; 521 break; 522 #endif 523 524 #ifdef CONFIG_ARCH_TEGRA_114_SOC 525 case TEGRA114: 526 fuse->soc = &tegra114_fuse_soc; 527 break; 528 #endif 529 530 #ifdef CONFIG_ARCH_TEGRA_124_SOC 531 case TEGRA124: 532 fuse->soc = &tegra124_fuse_soc; 533 break; 534 #endif 535 536 default: 537 pr_warn("Unsupported SoC: %02x\n", chip); 538 break; 539 } 540 } else { 541 /* 542 * At this point we're not running on Tegra, so play 543 * nice with multi-platform kernels. 544 */ 545 return 0; 546 } 547 } else { 548 /* 549 * Extract information from the device tree if we've found a 550 * matching node. 551 */ 552 if (of_address_to_resource(np, 0, ®s) < 0) { 553 pr_err("failed to get FUSE register\n"); 554 return -ENXIO; 555 } 556 557 fuse->soc = match->data; 558 } 559 560 np = of_find_matching_node(NULL, car_match); 561 if (np) { 562 void __iomem *base = of_iomap(np, 0); 563 of_node_put(np); 564 if (base) { 565 tegra_enable_fuse_clk(base); 566 iounmap(base); 567 } else { 568 pr_err("failed to map clock registers\n"); 569 return -ENXIO; 570 } 571 } 572 573 fuse->base = ioremap(regs.start, resource_size(®s)); 574 if (!fuse->base) { 575 pr_err("failed to map FUSE registers\n"); 576 return -ENXIO; 577 } 578 579 fuse->soc->init(fuse); 580 581 tegra_fuse_print_sku_info(&tegra_sku_info); 582 583 return err; 584 } 585 early_initcall(tegra_init_fuse); 586 587 #ifdef CONFIG_ARM64 588 static int __init tegra_init_soc(void) 589 { 590 struct device_node *np; 591 struct device *soc; 592 593 /* make sure we're running on Tegra */ 594 np = of_find_matching_node(NULL, tegra_fuse_match); 595 if (!np) 596 return 0; 597 598 of_node_put(np); 599 600 soc = tegra_soc_device_register(); 601 if (IS_ERR(soc)) { 602 pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc)); 603 return PTR_ERR(soc); 604 } 605 606 return 0; 607 } 608 device_initcall(tegra_init_soc); 609 #endif 610