1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/log2.h> 17 #include <linux/sched.h> 18 #include <linux/sched/mm.h> 19 #include <linux/sched/task.h> 20 #include <linux/delay.h> 21 #include <rdma/ib_user_verbs.h> 22 #include <rdma/ib_addr.h> 23 #include <rdma/ib_cache.h> 24 #include <linux/mlx5/port.h> 25 #include <linux/mlx5/vport.h> 26 #include <linux/mlx5/fs.h> 27 #include <linux/mlx5/eswitch.h> 28 #include <linux/mlx5/data_direct.h> 29 #include <linux/mlx5/driver.h> 30 #include <linux/mlx5/lag.h> 31 #include <linux/list.h> 32 #include <rdma/ib_smi.h> 33 #include <rdma/ib_umem_odp.h> 34 #include <rdma/lag.h> 35 #include <linux/in.h> 36 #include <linux/etherdevice.h> 37 #include "mlx5_ib.h" 38 #include "ib_rep.h" 39 #include "cmd.h" 40 #include "devx.h" 41 #include "dm.h" 42 #include "fs.h" 43 #include "srq.h" 44 #include "qp.h" 45 #include "wr.h" 46 #include "restrack.h" 47 #include "counters.h" 48 #include "umr.h" 49 #include <rdma/uverbs_std_types.h> 50 #include <rdma/uverbs_ioctl.h> 51 #include <rdma/mlx5_user_ioctl_verbs.h> 52 #include <rdma/mlx5_user_ioctl_cmds.h> 53 #include <rdma/ib_ucaps.h> 54 #include "macsec.h" 55 #include "dmah.h" 56 57 #define UVERBS_MODULE_NAME mlx5_ib 58 #include <rdma/uverbs_named_ioctl.h> 59 60 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 61 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 62 MODULE_LICENSE("Dual BSD/GPL"); 63 64 struct mlx5_ib_event_work { 65 struct work_struct work; 66 union { 67 struct mlx5_ib_dev *dev; 68 struct mlx5_ib_multiport_info *mpi; 69 }; 70 bool is_slave; 71 unsigned int event; 72 void *param; 73 }; 74 75 enum { 76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 77 }; 78 79 static struct workqueue_struct *mlx5_ib_event_wq; 80 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 81 static LIST_HEAD(mlx5_ib_dev_list); 82 /* 83 * This mutex should be held when accessing either of the above lists 84 */ 85 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 86 87 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 88 { 89 struct mlx5_ib_dev *dev; 90 91 mutex_lock(&mlx5_ib_multiport_mutex); 92 dev = mpi->ibdev; 93 mutex_unlock(&mlx5_ib_multiport_mutex); 94 return dev; 95 } 96 97 static enum rdma_link_layer 98 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 99 { 100 switch (port_type_cap) { 101 case MLX5_CAP_PORT_TYPE_IB: 102 return IB_LINK_LAYER_INFINIBAND; 103 case MLX5_CAP_PORT_TYPE_ETH: 104 return IB_LINK_LAYER_ETHERNET; 105 default: 106 return IB_LINK_LAYER_UNSPECIFIED; 107 } 108 } 109 110 static enum rdma_link_layer 111 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 112 { 113 struct mlx5_ib_dev *dev = to_mdev(device); 114 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 115 116 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 117 } 118 119 static int get_port_state(struct ib_device *ibdev, 120 u32 port_num, 121 enum ib_port_state *state) 122 { 123 struct ib_port_attr attr; 124 int ret; 125 126 memset(&attr, 0, sizeof(attr)); 127 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 128 if (!ret) 129 *state = attr.state; 130 return ret; 131 } 132 133 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 134 struct net_device *ndev, 135 struct net_device *upper, 136 u32 *port_num) 137 { 138 struct net_device *rep_ndev; 139 struct mlx5_ib_port *port; 140 int i; 141 142 for (i = 0; i < dev->num_ports; i++) { 143 port = &dev->port[i]; 144 if (!port->rep) 145 continue; 146 147 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 148 *port_num = i + 1; 149 return &port->roce; 150 } 151 152 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 153 continue; 154 rep_ndev = ib_device_get_netdev(&dev->ib_dev, i + 1); 155 if (rep_ndev && rep_ndev == ndev) { 156 dev_put(rep_ndev); 157 *port_num = i + 1; 158 return &port->roce; 159 } 160 161 dev_put(rep_ndev); 162 } 163 164 return NULL; 165 } 166 167 static bool mlx5_netdev_send_event(struct mlx5_ib_dev *dev, 168 struct net_device *ndev, 169 struct net_device *upper, 170 struct net_device *ib_ndev) 171 { 172 if (!dev->ib_active) 173 return false; 174 175 /* Event is about our upper device */ 176 if (upper == ndev) 177 return true; 178 179 /* RDMA device is not in lag and not in switchdev */ 180 if (!dev->is_rep && !upper && ndev == ib_ndev) 181 return true; 182 183 /* RDMA devie is in switchdev */ 184 if (dev->is_rep && ndev == ib_ndev) 185 return true; 186 187 return false; 188 } 189 190 static struct net_device *mlx5_ib_get_rep_uplink_netdev(struct mlx5_ib_dev *ibdev) 191 { 192 struct mlx5_ib_port *port; 193 int i; 194 195 for (i = 0; i < ibdev->num_ports; i++) { 196 port = &ibdev->port[i]; 197 if (port->rep && port->rep->vport == MLX5_VPORT_UPLINK) { 198 return ib_device_get_netdev(&ibdev->ib_dev, i + 1); 199 } 200 } 201 202 return NULL; 203 } 204 205 static int mlx5_netdev_event(struct notifier_block *this, 206 unsigned long event, void *ptr) 207 { 208 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 209 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 210 u32 port_num = roce->native_port_num; 211 struct net_device *ib_ndev = NULL; 212 struct mlx5_core_dev *mdev; 213 struct mlx5_ib_dev *ibdev; 214 215 ibdev = roce->dev; 216 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 217 if (!mdev) 218 return NOTIFY_DONE; 219 220 switch (event) { 221 case NETDEV_REGISTER: 222 /* Should already be registered during the load */ 223 if (ibdev->is_rep) 224 break; 225 226 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 227 /* Exit if already registered */ 228 if (ib_ndev) 229 goto put_ndev; 230 231 if (ndev->dev.parent == mdev->device) 232 ib_device_set_netdev(&ibdev->ib_dev, ndev, port_num); 233 break; 234 235 case NETDEV_UNREGISTER: 236 /* In case of reps, ib device goes away before the netdevs */ 237 if (ibdev->is_rep) 238 break; 239 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 240 if (ib_ndev == ndev) 241 ib_device_set_netdev(&ibdev->ib_dev, NULL, port_num); 242 goto put_ndev; 243 244 case NETDEV_CHANGE: 245 case NETDEV_UP: 246 case NETDEV_DOWN: { 247 struct net_device *upper = NULL; 248 249 if (!netif_is_lag_master(ndev) && !netif_is_lag_port(ndev) && 250 !mlx5_core_mp_enabled(mdev)) 251 return NOTIFY_DONE; 252 253 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 254 struct net_device *lag_ndev; 255 256 if(mlx5_lag_is_roce(mdev)) 257 lag_ndev = ib_device_get_netdev(&ibdev->ib_dev, 1); 258 else /* sriov lag */ 259 lag_ndev = mlx5_ib_get_rep_uplink_netdev(ibdev); 260 261 if (lag_ndev) { 262 upper = netdev_master_upper_dev_get(lag_ndev); 263 dev_put(lag_ndev); 264 } else { 265 goto done; 266 } 267 } 268 269 if (ibdev->is_rep) 270 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 271 if (!roce) 272 return NOTIFY_DONE; 273 274 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 275 276 if (mlx5_netdev_send_event(ibdev, ndev, upper, ib_ndev)) { 277 struct ib_event ibev = { }; 278 enum ib_port_state port_state; 279 280 if (get_port_state(&ibdev->ib_dev, port_num, 281 &port_state)) 282 goto put_ndev; 283 284 if (roce->last_port_state == port_state) 285 goto put_ndev; 286 287 roce->last_port_state = port_state; 288 ibev.device = &ibdev->ib_dev; 289 if (port_state == IB_PORT_DOWN) 290 ibev.event = IB_EVENT_PORT_ERR; 291 else if (port_state == IB_PORT_ACTIVE) 292 ibev.event = IB_EVENT_PORT_ACTIVE; 293 else 294 goto put_ndev; 295 296 ibev.element.port_num = port_num; 297 ib_dispatch_event(&ibev); 298 } 299 break; 300 } 301 302 default: 303 break; 304 } 305 put_ndev: 306 dev_put(ib_ndev); 307 done: 308 mlx5_ib_put_native_port_mdev(ibdev, port_num); 309 return NOTIFY_DONE; 310 } 311 312 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 313 u32 ib_port_num, 314 u32 *native_port_num) 315 { 316 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 317 ib_port_num); 318 struct mlx5_core_dev *mdev = NULL; 319 struct mlx5_ib_multiport_info *mpi; 320 struct mlx5_ib_port *port; 321 322 if (ibdev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 323 if (native_port_num) 324 *native_port_num = smi_to_native_portnum(ibdev, 325 ib_port_num); 326 return ibdev->mdev; 327 328 } 329 330 if (!mlx5_core_mp_enabled(ibdev->mdev) || 331 ll != IB_LINK_LAYER_ETHERNET) { 332 if (native_port_num) 333 *native_port_num = ib_port_num; 334 return ibdev->mdev; 335 } 336 337 if (native_port_num) 338 *native_port_num = 1; 339 340 port = &ibdev->port[ib_port_num - 1]; 341 spin_lock(&port->mp.mpi_lock); 342 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 343 if (mpi && !mpi->unaffiliate) { 344 mdev = mpi->mdev; 345 /* If it's the master no need to refcount, it'll exist 346 * as long as the ib_dev exists. 347 */ 348 if (!mpi->is_master) 349 mpi->mdev_refcnt++; 350 } 351 spin_unlock(&port->mp.mpi_lock); 352 353 return mdev; 354 } 355 356 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 357 { 358 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 359 port_num); 360 struct mlx5_ib_multiport_info *mpi; 361 struct mlx5_ib_port *port; 362 363 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 364 return; 365 366 port = &ibdev->port[port_num - 1]; 367 368 spin_lock(&port->mp.mpi_lock); 369 mpi = ibdev->port[port_num - 1].mp.mpi; 370 if (mpi->is_master) 371 goto out; 372 373 mpi->mdev_refcnt--; 374 if (mpi->unaffiliate) 375 complete(&mpi->unref_comp); 376 out: 377 spin_unlock(&port->mp.mpi_lock); 378 } 379 380 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 381 u16 *active_speed, u8 *active_width) 382 { 383 switch (eth_proto_oper) { 384 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 385 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 386 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 387 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 388 *active_width = IB_WIDTH_1X; 389 *active_speed = IB_SPEED_SDR; 390 break; 391 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 392 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 393 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 394 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 395 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 396 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 397 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 398 *active_width = IB_WIDTH_1X; 399 *active_speed = IB_SPEED_QDR; 400 break; 401 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 402 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 403 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 404 *active_width = IB_WIDTH_1X; 405 *active_speed = IB_SPEED_EDR; 406 break; 407 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 408 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 409 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 410 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 411 *active_width = IB_WIDTH_4X; 412 *active_speed = IB_SPEED_QDR; 413 break; 414 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 415 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 416 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 417 *active_width = IB_WIDTH_1X; 418 *active_speed = IB_SPEED_HDR; 419 break; 420 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 421 *active_width = IB_WIDTH_4X; 422 *active_speed = IB_SPEED_FDR; 423 break; 424 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 425 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 426 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 427 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 428 *active_width = IB_WIDTH_4X; 429 *active_speed = IB_SPEED_EDR; 430 break; 431 default: 432 return -EINVAL; 433 } 434 435 return 0; 436 } 437 438 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 439 u8 *active_width) 440 { 441 switch (eth_proto_oper) { 442 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 443 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 444 *active_width = IB_WIDTH_1X; 445 *active_speed = IB_SPEED_SDR; 446 break; 447 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 448 *active_width = IB_WIDTH_1X; 449 *active_speed = IB_SPEED_DDR; 450 break; 451 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 452 *active_width = IB_WIDTH_1X; 453 *active_speed = IB_SPEED_QDR; 454 break; 455 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 456 *active_width = IB_WIDTH_4X; 457 *active_speed = IB_SPEED_QDR; 458 break; 459 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 460 *active_width = IB_WIDTH_1X; 461 *active_speed = IB_SPEED_EDR; 462 break; 463 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 464 *active_width = IB_WIDTH_2X; 465 *active_speed = IB_SPEED_EDR; 466 break; 467 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 468 *active_width = IB_WIDTH_1X; 469 *active_speed = IB_SPEED_HDR; 470 break; 471 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 472 *active_width = IB_WIDTH_4X; 473 *active_speed = IB_SPEED_EDR; 474 break; 475 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 476 *active_width = IB_WIDTH_2X; 477 *active_speed = IB_SPEED_HDR; 478 break; 479 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 480 *active_width = IB_WIDTH_1X; 481 *active_speed = IB_SPEED_NDR; 482 break; 483 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 484 *active_width = IB_WIDTH_4X; 485 *active_speed = IB_SPEED_HDR; 486 break; 487 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 488 *active_width = IB_WIDTH_2X; 489 *active_speed = IB_SPEED_NDR; 490 break; 491 case MLX5E_PROT_MASK(MLX5E_200GAUI_1_200GBASE_CR1_KR1): 492 *active_width = IB_WIDTH_1X; 493 *active_speed = IB_SPEED_XDR; 494 break; 495 case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8): 496 *active_width = IB_WIDTH_8X; 497 *active_speed = IB_SPEED_HDR; 498 break; 499 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 500 *active_width = IB_WIDTH_4X; 501 *active_speed = IB_SPEED_NDR; 502 break; 503 case MLX5E_PROT_MASK(MLX5E_400GAUI_2_400GBASE_CR2_KR2): 504 *active_width = IB_WIDTH_2X; 505 *active_speed = IB_SPEED_XDR; 506 break; 507 case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8): 508 *active_width = IB_WIDTH_8X; 509 *active_speed = IB_SPEED_NDR; 510 break; 511 case MLX5E_PROT_MASK(MLX5E_800GAUI_4_800GBASE_CR4_KR4): 512 *active_width = IB_WIDTH_4X; 513 *active_speed = IB_SPEED_XDR; 514 break; 515 case MLX5E_PROT_MASK(MLX5E_1600GAUI_8_1600GBASE_CR8_KR8): 516 *active_width = IB_WIDTH_8X; 517 *active_speed = IB_SPEED_XDR; 518 break; 519 default: 520 return -EINVAL; 521 } 522 523 return 0; 524 } 525 526 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 527 u8 *active_width, bool ext) 528 { 529 return ext ? 530 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 531 active_width) : 532 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 533 active_width); 534 } 535 536 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 537 struct ib_port_attr *props) 538 { 539 struct mlx5_ib_dev *dev = to_mdev(device); 540 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 541 struct mlx5_core_dev *mdev; 542 struct net_device *ndev, *upper; 543 enum ib_mtu ndev_ib_mtu; 544 bool put_mdev = true; 545 u32 eth_prot_oper; 546 u32 mdev_port_num; 547 bool ext; 548 int err; 549 550 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 551 if (!mdev) { 552 /* This means the port isn't affiliated yet. Get the 553 * info for the master port instead. 554 */ 555 put_mdev = false; 556 mdev = dev->mdev; 557 mdev_port_num = 1; 558 port_num = 1; 559 } 560 561 /* Possible bad flows are checked before filling out props so in case 562 * of an error it will still be zeroed out. 563 * Use native port in case of reps 564 */ 565 if (dev->is_rep) { 566 struct mlx5_eswitch_rep *rep; 567 568 rep = dev->port[port_num - 1].rep; 569 if (rep) { 570 mdev = mlx5_eswitch_get_core_dev(rep->esw); 571 WARN_ON(!mdev); 572 } 573 mdev_port_num = 1; 574 } 575 576 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 577 mdev_port_num, 0); 578 579 if (err) 580 goto out; 581 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 582 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 583 584 props->active_width = IB_WIDTH_4X; 585 props->active_speed = IB_SPEED_QDR; 586 587 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 588 &props->active_width, ext); 589 590 if (!dev->is_rep && dev->mdev->roce.roce_en) { 591 u16 qkey_viol_cntr; 592 593 props->port_cap_flags |= IB_PORT_CM_SUP; 594 props->ip_gids = true; 595 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 596 roce_address_table_size); 597 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 598 props->qkey_viol_cntr = qkey_viol_cntr; 599 } 600 props->max_mtu = IB_MTU_4096; 601 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 602 props->pkey_tbl_len = 1; 603 props->state = IB_PORT_DOWN; 604 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 605 606 /* If this is a stub query for an unaffiliated port stop here */ 607 if (!put_mdev) 608 goto out; 609 610 ndev = ib_device_get_netdev(device, port_num); 611 if (!ndev) 612 goto out; 613 614 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 615 rcu_read_lock(); 616 upper = netdev_master_upper_dev_get_rcu(ndev); 617 if (upper) { 618 dev_put(ndev); 619 ndev = upper; 620 dev_hold(ndev); 621 } 622 rcu_read_unlock(); 623 } 624 625 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 626 props->state = IB_PORT_ACTIVE; 627 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 628 } 629 630 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 631 632 dev_put(ndev); 633 634 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 635 out: 636 if (put_mdev) 637 mlx5_ib_put_native_port_mdev(dev, port_num); 638 return err; 639 } 640 641 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 642 unsigned int index, const union ib_gid *gid, 643 const struct ib_gid_attr *attr) 644 { 645 enum ib_gid_type gid_type; 646 u16 vlan_id = 0xffff; 647 u8 roce_version = 0; 648 u8 roce_l3_type = 0; 649 u8 mac[ETH_ALEN]; 650 int ret; 651 652 gid_type = attr->gid_type; 653 if (gid) { 654 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 655 if (ret) 656 return ret; 657 } 658 659 switch (gid_type) { 660 case IB_GID_TYPE_ROCE: 661 roce_version = MLX5_ROCE_VERSION_1; 662 break; 663 case IB_GID_TYPE_ROCE_UDP_ENCAP: 664 roce_version = MLX5_ROCE_VERSION_2; 665 if (gid && ipv6_addr_v4mapped((void *)gid)) 666 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 667 else 668 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 669 break; 670 671 default: 672 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 673 } 674 675 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 676 roce_l3_type, gid->raw, mac, 677 vlan_id < VLAN_CFI_MASK, vlan_id, 678 port_num); 679 } 680 681 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 682 __always_unused void **context) 683 { 684 int ret; 685 686 ret = mlx5r_add_gid_macsec_operations(attr); 687 if (ret) 688 return ret; 689 690 return set_roce_addr(to_mdev(attr->device), attr->port_num, 691 attr->index, &attr->gid, attr); 692 } 693 694 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 695 __always_unused void **context) 696 { 697 int ret; 698 699 ret = set_roce_addr(to_mdev(attr->device), attr->port_num, 700 attr->index, NULL, attr); 701 if (ret) 702 return ret; 703 704 mlx5r_del_gid_macsec_operations(attr); 705 return 0; 706 } 707 708 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 709 const struct ib_gid_attr *attr) 710 { 711 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 712 return 0; 713 714 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 715 } 716 717 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 718 { 719 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 720 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 721 return 0; 722 } 723 724 enum { 725 MLX5_VPORT_ACCESS_METHOD_MAD, 726 MLX5_VPORT_ACCESS_METHOD_HCA, 727 MLX5_VPORT_ACCESS_METHOD_NIC, 728 }; 729 730 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 731 { 732 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 733 return MLX5_VPORT_ACCESS_METHOD_MAD; 734 735 if (mlx5_ib_port_link_layer(ibdev, 1) == 736 IB_LINK_LAYER_ETHERNET) 737 return MLX5_VPORT_ACCESS_METHOD_NIC; 738 739 return MLX5_VPORT_ACCESS_METHOD_HCA; 740 } 741 742 static void get_atomic_caps(struct mlx5_ib_dev *dev, 743 u8 atomic_size_qp, 744 struct ib_device_attr *props) 745 { 746 u8 tmp; 747 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 748 u8 atomic_req_8B_endianness_mode = 749 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 750 751 /* Check if HW supports 8 bytes standard atomic operations and capable 752 * of host endianness respond 753 */ 754 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 755 if (((atomic_operations & tmp) == tmp) && 756 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 757 (atomic_req_8B_endianness_mode)) { 758 props->atomic_cap = IB_ATOMIC_HCA; 759 } else { 760 props->atomic_cap = IB_ATOMIC_NONE; 761 } 762 } 763 764 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 765 struct ib_device_attr *props) 766 { 767 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 768 769 get_atomic_caps(dev, atomic_size_qp, props); 770 } 771 772 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 773 __be64 *sys_image_guid) 774 { 775 struct mlx5_ib_dev *dev = to_mdev(ibdev); 776 struct mlx5_core_dev *mdev = dev->mdev; 777 u64 tmp; 778 int err; 779 780 switch (mlx5_get_vport_access_method(ibdev)) { 781 case MLX5_VPORT_ACCESS_METHOD_MAD: 782 return mlx5_query_mad_ifc_system_image_guid(ibdev, 783 sys_image_guid); 784 785 case MLX5_VPORT_ACCESS_METHOD_HCA: 786 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 787 break; 788 789 case MLX5_VPORT_ACCESS_METHOD_NIC: 790 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 791 break; 792 793 default: 794 return -EINVAL; 795 } 796 797 if (!err) 798 *sys_image_guid = cpu_to_be64(tmp); 799 800 return err; 801 802 } 803 804 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 805 u16 *max_pkeys) 806 { 807 struct mlx5_ib_dev *dev = to_mdev(ibdev); 808 struct mlx5_core_dev *mdev = dev->mdev; 809 810 switch (mlx5_get_vport_access_method(ibdev)) { 811 case MLX5_VPORT_ACCESS_METHOD_MAD: 812 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 813 814 case MLX5_VPORT_ACCESS_METHOD_HCA: 815 case MLX5_VPORT_ACCESS_METHOD_NIC: 816 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 817 pkey_table_size)); 818 return 0; 819 820 default: 821 return -EINVAL; 822 } 823 } 824 825 static int mlx5_query_vendor_id(struct ib_device *ibdev, 826 u32 *vendor_id) 827 { 828 struct mlx5_ib_dev *dev = to_mdev(ibdev); 829 830 switch (mlx5_get_vport_access_method(ibdev)) { 831 case MLX5_VPORT_ACCESS_METHOD_MAD: 832 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 833 834 case MLX5_VPORT_ACCESS_METHOD_HCA: 835 case MLX5_VPORT_ACCESS_METHOD_NIC: 836 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 837 838 default: 839 return -EINVAL; 840 } 841 } 842 843 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 844 __be64 *node_guid) 845 { 846 u64 tmp; 847 int err; 848 849 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 850 case MLX5_VPORT_ACCESS_METHOD_MAD: 851 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 852 853 case MLX5_VPORT_ACCESS_METHOD_HCA: 854 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 855 break; 856 857 case MLX5_VPORT_ACCESS_METHOD_NIC: 858 err = mlx5_query_nic_vport_node_guid(dev->mdev, 0, false, &tmp); 859 break; 860 861 default: 862 return -EINVAL; 863 } 864 865 if (!err) 866 *node_guid = cpu_to_be64(tmp); 867 868 return err; 869 } 870 871 struct mlx5_reg_node_desc { 872 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 873 }; 874 875 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 876 { 877 struct mlx5_reg_node_desc in; 878 879 if (mlx5_use_mad_ifc(dev)) 880 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 881 882 memset(&in, 0, sizeof(in)); 883 884 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 885 sizeof(struct mlx5_reg_node_desc), 886 MLX5_REG_NODE_DESC, 0, 0); 887 } 888 889 static void fill_esw_mgr_reg_c0(struct mlx5_core_dev *mdev, 890 struct mlx5_ib_query_device_resp *resp) 891 { 892 struct mlx5_eswitch *esw = mdev->priv.eswitch; 893 u16 vport = mlx5_eswitch_manager_vport(mdev); 894 895 resp->reg_c0.value = mlx5_eswitch_get_vport_metadata_for_match(esw, 896 vport); 897 resp->reg_c0.mask = mlx5_eswitch_get_vport_metadata_mask(); 898 } 899 900 /* 901 * Calculate maximum SQ overhead across all QP types. 902 * Other QP types (REG_UMR, UC, RC, UD/SMI/GSI, XRC_TGT) 903 * have smaller overhead than the types calculated below, 904 * so they are implicitly included. 905 */ 906 static u32 mlx5_ib_calc_max_sq_overhead(void) 907 { 908 u32 max_overhead_xrc, overhead_ud_lso, a, b; 909 910 /* XRC_INI */ 911 max_overhead_xrc = sizeof(struct mlx5_wqe_xrc_seg); 912 max_overhead_xrc += sizeof(struct mlx5_wqe_ctrl_seg); 913 a = sizeof(struct mlx5_wqe_atomic_seg) + 914 sizeof(struct mlx5_wqe_raddr_seg); 915 b = sizeof(struct mlx5_wqe_umr_ctrl_seg) + 916 sizeof(struct mlx5_mkey_seg) + 917 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / MLX5_IB_UMR_OCTOWORD; 918 max_overhead_xrc += max(a, b); 919 920 /* UD with LSO */ 921 overhead_ud_lso = sizeof(struct mlx5_wqe_ctrl_seg); 922 overhead_ud_lso += sizeof(struct mlx5_wqe_eth_pad); 923 overhead_ud_lso += sizeof(struct mlx5_wqe_eth_seg); 924 overhead_ud_lso += sizeof(struct mlx5_wqe_datagram_seg); 925 926 return max(max_overhead_xrc, overhead_ud_lso); 927 } 928 929 static u32 mlx5_ib_calc_max_qp_wr(struct mlx5_ib_dev *dev) 930 { 931 struct mlx5_core_dev *mdev = dev->mdev; 932 u32 max_wqe_bb_units = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 933 u32 max_wqe_size; 934 /* max QP overhead + 1 SGE, no inline, no special features */ 935 max_wqe_size = mlx5_ib_calc_max_sq_overhead() + 936 sizeof(struct mlx5_wqe_data_seg); 937 938 max_wqe_size = roundup_pow_of_two(max_wqe_size); 939 940 max_wqe_size = ALIGN(max_wqe_size, MLX5_SEND_WQE_BB); 941 942 return (max_wqe_bb_units * MLX5_SEND_WQE_BB) / max_wqe_size; 943 } 944 945 static int mlx5_ib_query_device(struct ib_device *ibdev, 946 struct ib_device_attr *props, 947 struct ib_udata *uhw) 948 { 949 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 950 struct mlx5_ib_dev *dev = to_mdev(ibdev); 951 struct mlx5_core_dev *mdev = dev->mdev; 952 int err = -ENOMEM; 953 int max_sq_desc; 954 int max_rq_sg; 955 int max_sq_sg; 956 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 957 bool raw_support = !mlx5_core_mp_enabled(mdev); 958 struct mlx5_ib_query_device_resp resp = {}; 959 size_t resp_len; 960 u64 max_tso; 961 962 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 963 if (uhw_outlen && uhw_outlen < resp_len) 964 return -EINVAL; 965 966 resp.response_length = resp_len; 967 968 err = ib_is_udata_in_empty(uhw); 969 if (err) 970 return err; 971 972 err = mlx5_query_system_image_guid(ibdev, 973 &props->sys_image_guid); 974 if (err) 975 return err; 976 977 props->max_pkeys = dev->pkey_table_len; 978 979 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 980 if (err) 981 return err; 982 983 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 984 (fw_rev_min(dev->mdev) << 16) | 985 fw_rev_sub(dev->mdev); 986 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 987 IB_DEVICE_PORT_ACTIVE_EVENT | 988 IB_DEVICE_SYS_IMAGE_GUID | 989 IB_DEVICE_RC_RNR_NAK_GEN; 990 991 if (MLX5_CAP_GEN(mdev, pkv)) 992 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 993 if (MLX5_CAP_GEN(mdev, qkv)) 994 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 995 if (MLX5_CAP_GEN(mdev, apm)) 996 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 997 if (MLX5_CAP_GEN(mdev, xrc)) 998 props->device_cap_flags |= IB_DEVICE_XRC; 999 if (MLX5_CAP_GEN(mdev, imaicl)) { 1000 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 1001 IB_DEVICE_MEM_WINDOW_TYPE_2B; 1002 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 1003 /* We support 'Gappy' memory registration too */ 1004 props->kernel_cap_flags |= IBK_SG_GAPS_REG; 1005 } 1006 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 1007 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 1008 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 1009 if (MLX5_CAP_GEN(mdev, sho)) { 1010 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER; 1011 /* At this stage no support for signature handover */ 1012 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 1013 IB_PROT_T10DIF_TYPE_2 | 1014 IB_PROT_T10DIF_TYPE_3; 1015 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 1016 IB_GUARD_T10DIF_CSUM; 1017 } 1018 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 1019 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK; 1020 1021 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 1022 if (MLX5_CAP_ETH(mdev, csum_cap)) { 1023 /* Legacy bit to support old userspace libraries */ 1024 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 1025 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 1026 } 1027 1028 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 1029 props->raw_packet_caps |= 1030 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 1031 1032 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 1033 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 1034 if (max_tso) { 1035 resp.tso_caps.max_tso = 1 << max_tso; 1036 resp.tso_caps.supported_qpts |= 1037 1 << IB_QPT_RAW_PACKET; 1038 resp.response_length += sizeof(resp.tso_caps); 1039 } 1040 } 1041 1042 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 1043 resp.rss_caps.rx_hash_function = 1044 MLX5_RX_HASH_FUNC_TOEPLITZ; 1045 resp.rss_caps.rx_hash_fields_mask = 1046 MLX5_RX_HASH_SRC_IPV4 | 1047 MLX5_RX_HASH_DST_IPV4 | 1048 MLX5_RX_HASH_SRC_IPV6 | 1049 MLX5_RX_HASH_DST_IPV6 | 1050 MLX5_RX_HASH_SRC_PORT_TCP | 1051 MLX5_RX_HASH_DST_PORT_TCP | 1052 MLX5_RX_HASH_SRC_PORT_UDP | 1053 MLX5_RX_HASH_DST_PORT_UDP | 1054 MLX5_RX_HASH_INNER; 1055 resp.response_length += sizeof(resp.rss_caps); 1056 } 1057 } else { 1058 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 1059 resp.response_length += sizeof(resp.tso_caps); 1060 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 1061 resp.response_length += sizeof(resp.rss_caps); 1062 } 1063 1064 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1065 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1066 props->kernel_cap_flags |= IBK_UD_TSO; 1067 } 1068 1069 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 1070 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 1071 raw_support) 1072 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 1073 1074 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 1075 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 1076 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1077 1078 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1079 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 1080 raw_support) { 1081 /* Legacy bit to support old userspace libraries */ 1082 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 1083 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 1084 } 1085 1086 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 1087 props->max_dm_size = 1088 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 1089 } 1090 1091 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 1092 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 1093 1094 if (MLX5_CAP_GEN(mdev, end_pad)) 1095 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 1096 1097 props->vendor_part_id = mdev->pdev->device; 1098 props->hw_ver = mdev->pdev->revision; 1099 1100 props->max_mr_size = ~0ull; 1101 props->page_size_cap = ~(min_page_size - 1); 1102 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 1103 props->max_qp_wr = mlx5_ib_calc_max_qp_wr(dev); 1104 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 1105 sizeof(struct mlx5_wqe_data_seg); 1106 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 1107 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 1108 sizeof(struct mlx5_wqe_raddr_seg)) / 1109 sizeof(struct mlx5_wqe_data_seg); 1110 props->max_send_sge = max_sq_sg; 1111 props->max_recv_sge = max_rq_sg; 1112 props->max_sge_rd = MLX5_MAX_SGE_RD; 1113 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 1114 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 1115 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 1116 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 1117 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 1118 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 1119 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 1120 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 1121 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 1122 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 1123 props->max_srq_sge = max_rq_sg - 1; 1124 props->max_fast_reg_page_list_len = 1125 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 1126 props->max_pi_fast_reg_page_list_len = 1127 props->max_fast_reg_page_list_len / 2; 1128 props->max_sgl_rd = 1129 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 1130 get_atomic_caps_qp(dev, props); 1131 props->masked_atomic_cap = IB_ATOMIC_NONE; 1132 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1133 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1134 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1135 props->max_mcast_grp; 1136 props->max_ah = INT_MAX; 1137 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1138 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1139 1140 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1141 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 1142 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING; 1143 props->odp_caps = dev->odp_caps; 1144 if (!uhw) { 1145 /* ODP for kernel QPs is not implemented for receive 1146 * WQEs and SRQ WQEs 1147 */ 1148 props->odp_caps.per_transport_caps.rc_odp_caps &= 1149 ~(IB_ODP_SUPPORT_READ | 1150 IB_ODP_SUPPORT_SRQ_RECV); 1151 props->odp_caps.per_transport_caps.uc_odp_caps &= 1152 ~(IB_ODP_SUPPORT_READ | 1153 IB_ODP_SUPPORT_SRQ_RECV); 1154 props->odp_caps.per_transport_caps.ud_odp_caps &= 1155 ~(IB_ODP_SUPPORT_READ | 1156 IB_ODP_SUPPORT_SRQ_RECV); 1157 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1158 ~(IB_ODP_SUPPORT_READ | 1159 IB_ODP_SUPPORT_SRQ_RECV); 1160 } 1161 } 1162 1163 if (mlx5_core_is_vf(mdev)) 1164 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION; 1165 1166 if (mlx5_ib_port_link_layer(ibdev, 1) == 1167 IB_LINK_LAYER_ETHERNET && raw_support) { 1168 props->rss_caps.max_rwq_indirection_tables = 1169 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1170 props->rss_caps.max_rwq_indirection_table_size = 1171 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1172 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1173 props->max_wq_type_rq = 1174 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1175 } 1176 1177 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1178 props->tm_caps.max_num_tags = 1179 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1180 props->tm_caps.max_ops = 1181 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1182 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1183 } 1184 1185 if (MLX5_CAP_GEN(mdev, tag_matching) && 1186 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1187 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1188 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1189 } 1190 1191 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1192 props->cq_caps.max_cq_moderation_count = 1193 MLX5_MAX_CQ_COUNT; 1194 props->cq_caps.max_cq_moderation_period = 1195 MLX5_MAX_CQ_PERIOD; 1196 } 1197 1198 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1199 resp.response_length += sizeof(resp.cqe_comp_caps); 1200 1201 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1202 resp.cqe_comp_caps.max_num = 1203 MLX5_CAP_GEN(dev->mdev, 1204 cqe_compression_max_num); 1205 1206 resp.cqe_comp_caps.supported_format = 1207 MLX5_IB_CQE_RES_FORMAT_HASH | 1208 MLX5_IB_CQE_RES_FORMAT_CSUM; 1209 1210 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1211 resp.cqe_comp_caps.supported_format |= 1212 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1213 } 1214 } 1215 1216 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen) { 1217 if (MLX5_CAP_GEN(mdev, qos)) { 1218 if (MLX5_CAP_QOS(mdev, packet_pacing) && raw_support) 1219 resp.packet_pacing_caps.supported_qpts |= 1220 BIT(IB_QPT_RAW_PACKET); 1221 if (MLX5_CAP_QOS(mdev, packet_pacing_req_ud)) 1222 resp.packet_pacing_caps.supported_qpts |= 1223 BIT(IB_QPT_UD); 1224 if (MLX5_CAP_QOS(mdev, packet_pacing_req_uc)) 1225 resp.packet_pacing_caps.supported_qpts |= 1226 BIT(IB_QPT_UC); 1227 1228 if (resp.packet_pacing_caps.supported_qpts) { 1229 resp.packet_pacing_caps.qp_rate_limit_max = 1230 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1231 resp.packet_pacing_caps.qp_rate_limit_min = 1232 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1233 1234 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1235 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1236 resp.packet_pacing_caps.cap_flags |= 1237 MLX5_IB_PP_SUPPORT_BURST; 1238 } 1239 } 1240 resp.response_length += sizeof(resp.packet_pacing_caps); 1241 } 1242 1243 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1244 uhw_outlen) { 1245 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1246 resp.mlx5_ib_support_multi_pkt_send_wqes = 1247 MLX5_IB_ALLOW_MPW; 1248 1249 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1250 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1251 MLX5_IB_SUPPORT_EMPW; 1252 1253 resp.response_length += 1254 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1255 } 1256 1257 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1258 resp.response_length += sizeof(resp.flags); 1259 1260 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1261 resp.flags |= 1262 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1263 1264 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1265 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1266 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1267 resp.flags |= 1268 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1269 1270 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1271 1272 if (MLX5_CAP_GEN_2(mdev, dp_ordering_force) && 1273 (MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_xrc) || 1274 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_dc) || 1275 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_rc) || 1276 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_ud) || 1277 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_uc))) 1278 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_OOO_DP; 1279 } 1280 1281 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1282 resp.response_length += sizeof(resp.sw_parsing_caps); 1283 if (MLX5_CAP_ETH(mdev, swp)) { 1284 resp.sw_parsing_caps.sw_parsing_offloads |= 1285 MLX5_IB_SW_PARSING; 1286 1287 if (MLX5_CAP_ETH(mdev, swp_csum)) 1288 resp.sw_parsing_caps.sw_parsing_offloads |= 1289 MLX5_IB_SW_PARSING_CSUM; 1290 1291 if (MLX5_CAP_ETH(mdev, swp_lso)) 1292 resp.sw_parsing_caps.sw_parsing_offloads |= 1293 MLX5_IB_SW_PARSING_LSO; 1294 1295 if (resp.sw_parsing_caps.sw_parsing_offloads) 1296 resp.sw_parsing_caps.supported_qpts = 1297 BIT(IB_QPT_RAW_PACKET); 1298 } 1299 } 1300 1301 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1302 raw_support) { 1303 resp.response_length += sizeof(resp.striding_rq_caps); 1304 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1305 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1306 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1307 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1308 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1309 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1310 resp.striding_rq_caps 1311 .min_single_wqe_log_num_of_strides = 1312 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1313 else 1314 resp.striding_rq_caps 1315 .min_single_wqe_log_num_of_strides = 1316 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1317 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1318 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1319 resp.striding_rq_caps.supported_qpts = 1320 BIT(IB_QPT_RAW_PACKET); 1321 } 1322 } 1323 1324 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1325 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1326 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1327 resp.tunnel_offloads_caps |= 1328 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1329 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1330 resp.tunnel_offloads_caps |= 1331 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1332 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1333 resp.tunnel_offloads_caps |= 1334 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1335 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1336 resp.tunnel_offloads_caps |= 1337 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1338 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1339 resp.tunnel_offloads_caps |= 1340 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1341 } 1342 1343 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1344 resp.response_length += sizeof(resp.dci_streams_caps); 1345 1346 resp.dci_streams_caps.max_log_num_concurent = 1347 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1348 1349 resp.dci_streams_caps.max_log_num_errored = 1350 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1351 } 1352 1353 if (offsetofend(typeof(resp), reserved) <= uhw_outlen) 1354 resp.response_length += sizeof(resp.reserved); 1355 1356 if (offsetofend(typeof(resp), reg_c0) <= uhw_outlen) { 1357 struct mlx5_eswitch *esw = mdev->priv.eswitch; 1358 1359 resp.response_length += sizeof(resp.reg_c0); 1360 1361 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS && 1362 mlx5_eswitch_vport_match_metadata_enabled(esw)) 1363 fill_esw_mgr_reg_c0(mdev, &resp); 1364 } 1365 1366 if (uhw_outlen) { 1367 err = ib_respond_udata(uhw, resp); 1368 1369 if (err) 1370 return err; 1371 } 1372 1373 return 0; 1374 } 1375 1376 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1377 u8 *ib_width) 1378 { 1379 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1380 1381 if (active_width & MLX5_PTYS_WIDTH_1X) 1382 *ib_width = IB_WIDTH_1X; 1383 else if (active_width & MLX5_PTYS_WIDTH_2X) 1384 *ib_width = IB_WIDTH_2X; 1385 else if (active_width & MLX5_PTYS_WIDTH_4X) 1386 *ib_width = IB_WIDTH_4X; 1387 else if (active_width & MLX5_PTYS_WIDTH_8X) 1388 *ib_width = IB_WIDTH_8X; 1389 else if (active_width & MLX5_PTYS_WIDTH_12X) 1390 *ib_width = IB_WIDTH_12X; 1391 else { 1392 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1393 active_width); 1394 *ib_width = IB_WIDTH_4X; 1395 } 1396 1397 return; 1398 } 1399 1400 static int mlx5_mtu_to_ib_mtu(int mtu) 1401 { 1402 switch (mtu) { 1403 case 256: return 1; 1404 case 512: return 2; 1405 case 1024: return 3; 1406 case 2048: return 4; 1407 case 4096: return 5; 1408 default: 1409 pr_warn("invalid mtu\n"); 1410 return -1; 1411 } 1412 } 1413 1414 enum ib_max_vl_num { 1415 __IB_MAX_VL_0 = 1, 1416 __IB_MAX_VL_0_1 = 2, 1417 __IB_MAX_VL_0_3 = 3, 1418 __IB_MAX_VL_0_7 = 4, 1419 __IB_MAX_VL_0_14 = 5, 1420 }; 1421 1422 enum mlx5_vl_hw_cap { 1423 MLX5_VL_HW_0 = 1, 1424 MLX5_VL_HW_0_1 = 2, 1425 MLX5_VL_HW_0_2 = 3, 1426 MLX5_VL_HW_0_3 = 4, 1427 MLX5_VL_HW_0_4 = 5, 1428 MLX5_VL_HW_0_5 = 6, 1429 MLX5_VL_HW_0_6 = 7, 1430 MLX5_VL_HW_0_7 = 8, 1431 MLX5_VL_HW_0_14 = 15 1432 }; 1433 1434 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1435 u8 *max_vl_num) 1436 { 1437 switch (vl_hw_cap) { 1438 case MLX5_VL_HW_0: 1439 *max_vl_num = __IB_MAX_VL_0; 1440 break; 1441 case MLX5_VL_HW_0_1: 1442 *max_vl_num = __IB_MAX_VL_0_1; 1443 break; 1444 case MLX5_VL_HW_0_3: 1445 *max_vl_num = __IB_MAX_VL_0_3; 1446 break; 1447 case MLX5_VL_HW_0_7: 1448 *max_vl_num = __IB_MAX_VL_0_7; 1449 break; 1450 case MLX5_VL_HW_0_14: 1451 *max_vl_num = __IB_MAX_VL_0_14; 1452 break; 1453 1454 default: 1455 return -EINVAL; 1456 } 1457 1458 return 0; 1459 } 1460 1461 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1462 struct ib_port_attr *props) 1463 { 1464 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1465 struct mlx5_core_dev *mdev = dev->mdev; 1466 struct mlx5_hca_vport_context *rep; 1467 u8 vl_hw_cap, plane_index = 0; 1468 u16 max_mtu; 1469 u16 oper_mtu; 1470 int err; 1471 u16 ib_link_width_oper; 1472 1473 rep = kzalloc_obj(*rep); 1474 if (!rep) { 1475 err = -ENOMEM; 1476 goto out; 1477 } 1478 1479 /* props being zeroed by the caller, avoid zeroing it here */ 1480 1481 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) { 1482 plane_index = port; 1483 port = smi_to_native_portnum(dev, port); 1484 } 1485 1486 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1487 if (err) 1488 goto out; 1489 1490 props->lid = rep->lid; 1491 props->lmc = rep->lmc; 1492 props->sm_lid = rep->sm_lid; 1493 props->sm_sl = rep->sm_sl; 1494 props->state = rep->vport_state; 1495 props->phys_state = rep->port_physical_state; 1496 1497 props->port_cap_flags = rep->cap_mask1; 1498 if (dev->num_plane) { 1499 props->port_cap_flags |= IB_PORT_SM_DISABLED; 1500 props->port_cap_flags &= ~IB_PORT_SM; 1501 } else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 1502 props->port_cap_flags &= ~IB_PORT_CM_SUP; 1503 1504 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1505 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1506 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1507 props->bad_pkey_cntr = rep->pkey_violation_counter; 1508 props->qkey_viol_cntr = rep->qkey_violation_counter; 1509 props->subnet_timeout = rep->subnet_timeout; 1510 props->init_type_reply = rep->init_type_reply; 1511 1512 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1513 props->port_cap_flags2 = rep->cap_mask2; 1514 1515 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1516 &props->active_speed, port, plane_index); 1517 if (err) 1518 goto out; 1519 1520 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1521 1522 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1523 1524 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1525 1526 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1527 1528 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1529 1530 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1531 if (err) 1532 goto out; 1533 1534 err = translate_max_vl_num(ibdev, vl_hw_cap, 1535 &props->max_vl_num); 1536 out: 1537 kfree(rep); 1538 return err; 1539 } 1540 1541 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1542 struct ib_port_attr *props) 1543 { 1544 unsigned int count; 1545 int ret; 1546 1547 switch (mlx5_get_vport_access_method(ibdev)) { 1548 case MLX5_VPORT_ACCESS_METHOD_MAD: 1549 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1550 break; 1551 1552 case MLX5_VPORT_ACCESS_METHOD_HCA: 1553 ret = mlx5_query_hca_port(ibdev, port, props); 1554 break; 1555 1556 case MLX5_VPORT_ACCESS_METHOD_NIC: 1557 ret = mlx5_query_port_roce(ibdev, port, props); 1558 break; 1559 1560 default: 1561 ret = -EINVAL; 1562 } 1563 1564 if (!ret && props) { 1565 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1566 struct mlx5_core_dev *mdev; 1567 bool put_mdev = true; 1568 1569 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1570 if (!mdev) { 1571 /* If the port isn't affiliated yet query the master. 1572 * The master and slave will have the same values. 1573 */ 1574 mdev = dev->mdev; 1575 port = 1; 1576 put_mdev = false; 1577 } 1578 count = mlx5_core_reserved_gids_count(mdev); 1579 if (put_mdev) 1580 mlx5_ib_put_native_port_mdev(dev, port); 1581 props->gid_tbl_len -= count; 1582 } 1583 return ret; 1584 } 1585 1586 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1587 struct ib_port_attr *props) 1588 { 1589 return mlx5_query_port_roce(ibdev, port, props); 1590 } 1591 1592 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1593 u16 *pkey) 1594 { 1595 /* Default special Pkey for representor device port as per the 1596 * IB specification 1.3 section 10.9.1.2. 1597 */ 1598 *pkey = 0xffff; 1599 return 0; 1600 } 1601 1602 static int mlx5_ib_query_port_speed_from_port(struct mlx5_ib_dev *dev, 1603 u32 port_num, u64 *speed) 1604 { 1605 struct ib_port_speed_info speed_info; 1606 struct ib_port_attr attr = {}; 1607 int err; 1608 1609 err = mlx5_ib_query_port(&dev->ib_dev, port_num, &attr); 1610 if (err) 1611 return err; 1612 1613 if (attr.state == IB_PORT_DOWN) { 1614 *speed = 0; 1615 return 0; 1616 } 1617 1618 err = ib_port_attr_to_speed_info(&attr, &speed_info); 1619 if (err) 1620 return err; 1621 1622 *speed = speed_info.rate; 1623 return 0; 1624 } 1625 1626 static int mlx5_ib_query_port_speed_from_vport(struct mlx5_core_dev *mdev, 1627 u8 op_mod, u16 vport, 1628 u8 other_vport, u64 *speed, 1629 struct mlx5_ib_dev *dev, 1630 u32 port_num) 1631 { 1632 u32 max_tx_speed; 1633 u8 vport_state; 1634 int err; 1635 1636 err = mlx5_query_vport_max_tx_speed(mdev, op_mod, vport, other_vport, 1637 &max_tx_speed, &vport_state); 1638 if (err) 1639 return err; 1640 1641 if (vport_state == VPORT_STATE_DOWN || max_tx_speed == 0) 1642 /* Value 0 indicates field not supported, fallback */ 1643 return mlx5_ib_query_port_speed_from_port(dev, port_num, 1644 speed); 1645 1646 *speed = max_tx_speed; 1647 return 0; 1648 } 1649 1650 static int mlx5_ib_query_port_speed_from_bond(struct mlx5_ib_dev *dev, 1651 u32 port_num, u64 *speed) 1652 { 1653 struct mlx5_core_dev *mdev = dev->mdev; 1654 u32 bond_speed; 1655 int err; 1656 1657 err = mlx5_lag_query_bond_speed(mdev, &bond_speed); 1658 if (err) 1659 return err; 1660 1661 *speed = bond_speed / MLX5_MAX_TX_SPEED_UNIT; 1662 1663 return 0; 1664 } 1665 1666 static int mlx5_ib_query_port_speed_non_rep(struct mlx5_ib_dev *dev, 1667 u32 port_num, u64 *speed) 1668 { 1669 u16 op_mod = MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT; 1670 1671 if (mlx5_lag_is_roce(dev->mdev)) 1672 return mlx5_ib_query_port_speed_from_bond(dev, port_num, 1673 speed); 1674 1675 return mlx5_ib_query_port_speed_from_vport(dev->mdev, op_mod, 0, false, 1676 speed, dev, port_num); 1677 } 1678 1679 static int mlx5_ib_query_port_speed_rep(struct mlx5_ib_dev *dev, u32 port_num, 1680 u64 *speed) 1681 { 1682 struct mlx5_eswitch_rep *rep; 1683 struct mlx5_core_dev *mdev; 1684 u16 op_mod; 1685 1686 if (!dev->port[port_num - 1].rep) 1687 return -ENODEV; 1688 1689 rep = dev->port[port_num - 1].rep; 1690 mdev = mlx5_eswitch_get_core_dev(rep->esw); 1691 if (!mdev) 1692 return -ENODEV; 1693 1694 if (rep->vport == MLX5_VPORT_UPLINK) { 1695 if (mlx5_lag_is_sriov(mdev)) 1696 return mlx5_ib_query_port_speed_from_bond(dev, 1697 port_num, 1698 speed); 1699 1700 return mlx5_ib_query_port_speed_from_port(dev, port_num, 1701 speed); 1702 } 1703 1704 op_mod = MLX5_VPORT_STATE_OP_MOD_ESW_VPORT; 1705 return mlx5_ib_query_port_speed_from_vport(dev->mdev, op_mod, 1706 rep->vport, true, speed, dev, 1707 port_num); 1708 } 1709 1710 int mlx5_ib_query_port_speed(struct ib_device *ibdev, u32 port_num, u64 *speed) 1711 { 1712 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1713 1714 if (mlx5_ib_port_link_layer(ibdev, port_num) == 1715 IB_LINK_LAYER_INFINIBAND || mlx5_core_mp_enabled(dev->mdev)) 1716 return mlx5_ib_query_port_speed_from_port(dev, port_num, speed); 1717 else if (!dev->is_rep) 1718 return mlx5_ib_query_port_speed_non_rep(dev, port_num, speed); 1719 else 1720 return mlx5_ib_query_port_speed_rep(dev, port_num, speed); 1721 } 1722 1723 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1724 union ib_gid *gid) 1725 { 1726 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1727 struct mlx5_core_dev *mdev = dev->mdev; 1728 1729 switch (mlx5_get_vport_access_method(ibdev)) { 1730 case MLX5_VPORT_ACCESS_METHOD_MAD: 1731 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1732 1733 case MLX5_VPORT_ACCESS_METHOD_HCA: 1734 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1735 1736 default: 1737 return -EINVAL; 1738 } 1739 1740 } 1741 1742 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1743 u16 index, u16 *pkey) 1744 { 1745 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1746 struct mlx5_core_dev *mdev; 1747 bool put_mdev = true; 1748 u32 mdev_port_num; 1749 int err; 1750 1751 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1752 if (!mdev) { 1753 /* The port isn't affiliated yet, get the PKey from the master 1754 * port. For RoCE the PKey tables will be the same. 1755 */ 1756 put_mdev = false; 1757 mdev = dev->mdev; 1758 mdev_port_num = 1; 1759 } 1760 1761 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1762 index, pkey); 1763 if (put_mdev) 1764 mlx5_ib_put_native_port_mdev(dev, port); 1765 1766 return err; 1767 } 1768 1769 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1770 u16 *pkey) 1771 { 1772 switch (mlx5_get_vport_access_method(ibdev)) { 1773 case MLX5_VPORT_ACCESS_METHOD_MAD: 1774 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1775 1776 case MLX5_VPORT_ACCESS_METHOD_HCA: 1777 case MLX5_VPORT_ACCESS_METHOD_NIC: 1778 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1779 default: 1780 return -EINVAL; 1781 } 1782 } 1783 1784 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1785 struct ib_device_modify *props) 1786 { 1787 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1788 struct mlx5_reg_node_desc in; 1789 struct mlx5_reg_node_desc out; 1790 int err; 1791 1792 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1793 return -EOPNOTSUPP; 1794 1795 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1796 return 0; 1797 1798 /* 1799 * If possible, pass node desc to FW, so it can generate 1800 * a 144 trap. If cmd fails, just ignore. 1801 */ 1802 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1803 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1804 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1805 if (err) 1806 return err; 1807 1808 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1809 1810 return err; 1811 } 1812 1813 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1814 u32 value) 1815 { 1816 struct mlx5_hca_vport_context ctx = {}; 1817 struct mlx5_core_dev *mdev; 1818 u32 mdev_port_num; 1819 int err; 1820 1821 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1822 if (!mdev) 1823 return -ENODEV; 1824 1825 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1826 if (err) 1827 goto out; 1828 1829 if (~ctx.cap_mask1_perm & mask) { 1830 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1831 mask, ctx.cap_mask1_perm); 1832 err = -EINVAL; 1833 goto out; 1834 } 1835 1836 ctx.cap_mask1 = value; 1837 ctx.cap_mask1_perm = mask; 1838 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1839 0, &ctx); 1840 1841 out: 1842 mlx5_ib_put_native_port_mdev(dev, port_num); 1843 1844 return err; 1845 } 1846 1847 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1848 struct ib_port_modify *props) 1849 { 1850 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1851 struct ib_port_attr attr; 1852 u32 tmp; 1853 int err; 1854 u32 change_mask; 1855 u32 value; 1856 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1857 IB_LINK_LAYER_INFINIBAND); 1858 1859 /* CM layer calls ib_modify_port() regardless of the link layer. For 1860 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1861 */ 1862 if (!is_ib) 1863 return 0; 1864 1865 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1866 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1867 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1868 return set_port_caps_atomic(dev, port, change_mask, value); 1869 } 1870 1871 mutex_lock(&dev->cap_mask_mutex); 1872 1873 err = ib_query_port(ibdev, port, &attr); 1874 if (err) 1875 goto out; 1876 1877 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1878 ~props->clr_port_cap_mask; 1879 1880 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1881 1882 out: 1883 mutex_unlock(&dev->cap_mask_mutex); 1884 return err; 1885 } 1886 1887 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1888 { 1889 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1890 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1891 } 1892 1893 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1894 { 1895 /* Large page with non 4k uar support might limit the dynamic size */ 1896 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1897 return MLX5_MIN_DYN_BFREGS; 1898 1899 return MLX5_MAX_DYN_BFREGS; 1900 } 1901 1902 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1903 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1904 struct mlx5_bfreg_info *bfregi) 1905 { 1906 int uars_per_sys_page; 1907 int bfregs_per_sys_page; 1908 int ref_bfregs = req->total_num_bfregs; 1909 1910 if (req->total_num_bfregs == 0) 1911 return -EINVAL; 1912 1913 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1914 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1915 1916 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1917 return -ENOMEM; 1918 1919 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1920 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1921 /* This holds the required static allocation asked by the user */ 1922 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1923 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1924 return -EINVAL; 1925 1926 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1927 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1928 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1929 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1930 1931 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1932 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1933 lib_uar_4k ? "yes" : "no", ref_bfregs, 1934 req->total_num_bfregs, bfregi->total_num_bfregs, 1935 bfregi->num_sys_pages); 1936 1937 return 0; 1938 } 1939 1940 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1941 { 1942 struct mlx5_bfreg_info *bfregi; 1943 int err; 1944 int i; 1945 1946 bfregi = &context->bfregi; 1947 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1948 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1949 context->devx_uid); 1950 if (err) 1951 goto error; 1952 1953 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1954 } 1955 1956 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1957 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1958 1959 return 0; 1960 1961 error: 1962 for (--i; i >= 0; i--) 1963 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1964 context->devx_uid)) 1965 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1966 1967 return err; 1968 } 1969 1970 static void deallocate_uars(struct mlx5_ib_dev *dev, 1971 struct mlx5_ib_ucontext *context) 1972 { 1973 struct mlx5_bfreg_info *bfregi; 1974 int i; 1975 1976 bfregi = &context->bfregi; 1977 for (i = 0; i < bfregi->num_sys_pages; i++) 1978 if (i < bfregi->num_static_sys_pages || 1979 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1980 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1981 context->devx_uid); 1982 } 1983 1984 static int mlx5_ib_enable_lb_mp(struct mlx5_core_dev *master, 1985 struct mlx5_core_dev *slave, 1986 struct mlx5_ib_lb_state *lb_state) 1987 { 1988 int err; 1989 1990 err = mlx5_nic_vport_update_local_lb(master, true); 1991 if (err) 1992 return err; 1993 1994 err = mlx5_nic_vport_update_local_lb(slave, true); 1995 if (err) 1996 goto out; 1997 1998 lb_state->force_enable = true; 1999 return 0; 2000 2001 out: 2002 mlx5_nic_vport_update_local_lb(master, false); 2003 return err; 2004 } 2005 2006 static void mlx5_ib_disable_lb_mp(struct mlx5_core_dev *master, 2007 struct mlx5_core_dev *slave, 2008 struct mlx5_ib_lb_state *lb_state) 2009 { 2010 mlx5_nic_vport_update_local_lb(slave, false); 2011 mlx5_nic_vport_update_local_lb(master, false); 2012 2013 lb_state->force_enable = false; 2014 } 2015 2016 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 2017 { 2018 int err = 0; 2019 2020 if (dev->lb.force_enable) 2021 return 0; 2022 2023 mutex_lock(&dev->lb.mutex); 2024 if (td) 2025 dev->lb.user_td++; 2026 if (qp) 2027 dev->lb.qps++; 2028 2029 if (dev->lb.user_td == 2 || 2030 dev->lb.qps == 1) { 2031 if (!dev->lb.enabled) { 2032 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 2033 if (err) 2034 goto err_rollback; 2035 2036 dev->lb.enabled = true; 2037 } 2038 } 2039 2040 mutex_unlock(&dev->lb.mutex); 2041 2042 return err; 2043 2044 err_rollback: 2045 if (td) 2046 dev->lb.user_td--; 2047 if (qp) 2048 dev->lb.qps--; 2049 mutex_unlock(&dev->lb.mutex); 2050 return err; 2051 } 2052 2053 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 2054 { 2055 if (dev->lb.force_enable) 2056 return; 2057 2058 mutex_lock(&dev->lb.mutex); 2059 if (td) 2060 dev->lb.user_td--; 2061 if (qp) 2062 dev->lb.qps--; 2063 2064 if (dev->lb.user_td == 1 && 2065 dev->lb.qps == 0) { 2066 if (dev->lb.enabled) { 2067 mlx5_nic_vport_update_local_lb(dev->mdev, false); 2068 dev->lb.enabled = false; 2069 } 2070 } 2071 2072 mutex_unlock(&dev->lb.mutex); 2073 } 2074 2075 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 2076 u16 uid) 2077 { 2078 int err; 2079 2080 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 2081 return 0; 2082 2083 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 2084 if (err) 2085 return err; 2086 2087 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 2088 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 2089 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 2090 return 0; 2091 2092 err = mlx5_ib_enable_lb(dev, true, false); 2093 if (err) 2094 mlx5_cmd_dealloc_transport_domain(dev->mdev, *tdn, uid); 2095 2096 return err; 2097 } 2098 2099 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 2100 u16 uid) 2101 { 2102 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 2103 return; 2104 2105 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 2106 2107 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 2108 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 2109 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 2110 return; 2111 2112 mlx5_ib_disable_lb(dev, true, false); 2113 } 2114 2115 static int set_ucontext_resp(struct ib_ucontext *uctx, 2116 struct mlx5_ib_alloc_ucontext_resp *resp) 2117 { 2118 struct ib_device *ibdev = uctx->device; 2119 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2120 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 2121 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2122 2123 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 2124 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey; 2125 resp->comp_mask |= 2126 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 2127 } 2128 2129 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 2130 if (mlx5_wc_support_get(dev->mdev)) 2131 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 2132 log_bf_reg_size); 2133 resp->cache_line_size = cache_line_size(); 2134 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 2135 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 2136 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 2137 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 2138 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 2139 resp->cqe_version = context->cqe_version; 2140 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2141 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 2142 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2143 MLX5_CAP_GEN(dev->mdev, 2144 num_of_uars_per_page) : 1; 2145 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 2146 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 2147 resp->num_ports = dev->num_ports; 2148 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 2149 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 2150 2151 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 2152 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 2153 resp->eth_min_inline++; 2154 } 2155 2156 if (dev->mdev->clock_info) 2157 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 2158 2159 /* 2160 * We don't want to expose information from the PCI bar that is located 2161 * after 4096 bytes, so if the arch only supports larger pages, let's 2162 * pretend we don't support reading the HCA's core clock. This is also 2163 * forced by mmap function. 2164 */ 2165 if (PAGE_SIZE <= 4096) { 2166 resp->comp_mask |= 2167 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 2168 resp->hca_core_clock_offset = 2169 offsetof(struct mlx5_init_seg, 2170 internal_timer_h) % PAGE_SIZE; 2171 } 2172 2173 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2174 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 2175 2176 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 2177 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 2178 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 2179 resp->comp_mask |= 2180 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 2181 2182 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 2183 2184 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 2185 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 2186 2187 resp->comp_mask |= 2188 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG; 2189 2190 return 0; 2191 } 2192 2193 static bool uctx_rdma_ctrl_is_enabled(u64 enabled_caps) 2194 { 2195 return UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_LOCAL) || 2196 UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 2197 } 2198 2199 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 2200 struct ib_udata *udata) 2201 { 2202 struct ib_device *ibdev = uctx->device; 2203 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2204 struct mlx5_ib_alloc_ucontext_req_v2 req; 2205 struct mlx5_ib_alloc_ucontext_resp resp = {}; 2206 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 2207 struct mlx5_bfreg_info *bfregi; 2208 int ver; 2209 int err; 2210 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 2211 max_cqe_version); 2212 bool lib_uar_4k; 2213 bool lib_uar_dyn; 2214 2215 if (!dev->ib_active) 2216 return -EAGAIN; 2217 2218 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 2219 ver = 0; 2220 else if (udata->inlen >= min_req_v2) 2221 ver = 2; 2222 else 2223 return -EINVAL; 2224 2225 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 2226 if (err) 2227 return err; 2228 2229 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 2230 return -EOPNOTSUPP; 2231 2232 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 2233 return -EOPNOTSUPP; 2234 2235 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 2236 MLX5_NON_FP_BFREGS_PER_UAR); 2237 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 2238 return -EINVAL; 2239 2240 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 2241 err = mlx5_ib_devx_create(dev, true, uctx->enabled_caps); 2242 if (err < 0) 2243 goto out_ctx; 2244 context->devx_uid = err; 2245 2246 if (uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) { 2247 err = mlx5_cmd_add_privileged_uid(dev->mdev, 2248 context->devx_uid); 2249 if (err) 2250 goto out_devx; 2251 } 2252 } 2253 2254 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 2255 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 2256 bfregi = &context->bfregi; 2257 2258 if (lib_uar_dyn) { 2259 bfregi->lib_uar_dyn = lib_uar_dyn; 2260 goto uar_done; 2261 } 2262 2263 /* updates req->total_num_bfregs */ 2264 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 2265 if (err) 2266 goto out_ucap; 2267 2268 mutex_init(&bfregi->lock); 2269 bfregi->lib_uar_4k = lib_uar_4k; 2270 bfregi->count = kzalloc_objs(*bfregi->count, bfregi->total_num_bfregs); 2271 if (!bfregi->count) { 2272 err = -ENOMEM; 2273 goto out_ucap; 2274 } 2275 2276 bfregi->sys_pages = 2277 kzalloc_objs(*bfregi->sys_pages, bfregi->num_sys_pages); 2278 if (!bfregi->sys_pages) { 2279 err = -ENOMEM; 2280 goto out_count; 2281 } 2282 2283 err = allocate_uars(dev, context); 2284 if (err) 2285 goto out_sys_pages; 2286 2287 uar_done: 2288 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 2289 context->devx_uid); 2290 if (err) 2291 goto out_uars; 2292 2293 INIT_LIST_HEAD(&context->db_page_list); 2294 mutex_init(&context->db_page_mutex); 2295 2296 context->cqe_version = min_t(__u8, 2297 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 2298 req.max_cqe_version); 2299 2300 err = set_ucontext_resp(uctx, &resp); 2301 if (err) 2302 goto out_mdev; 2303 2304 resp.response_length = min(udata->outlen, sizeof(resp)); 2305 err = ib_respond_udata(udata, resp); 2306 if (err) 2307 goto out_mdev; 2308 2309 bfregi->ver = ver; 2310 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 2311 context->lib_caps = req.lib_caps; 2312 print_lib_caps(dev, context->lib_caps); 2313 2314 if (mlx5_ib_lag_should_assign_affinity(dev)) { 2315 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 2316 2317 atomic_set(&context->tx_port_affinity, 2318 atomic_add_return( 2319 1, &dev->port[port].roce.tx_port_affinity)); 2320 } 2321 2322 return 0; 2323 2324 out_mdev: 2325 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2326 2327 out_uars: 2328 deallocate_uars(dev, context); 2329 2330 out_sys_pages: 2331 kfree(bfregi->sys_pages); 2332 2333 out_count: 2334 kfree(bfregi->count); 2335 2336 out_ucap: 2337 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX && 2338 uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) 2339 mlx5_cmd_remove_privileged_uid(dev->mdev, context->devx_uid); 2340 2341 out_devx: 2342 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 2343 mlx5_ib_devx_destroy(dev, context->devx_uid); 2344 2345 out_ctx: 2346 return err; 2347 } 2348 2349 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 2350 struct uverbs_attr_bundle *attrs) 2351 { 2352 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 2353 int ret; 2354 2355 ret = set_ucontext_resp(ibcontext, &uctx_resp); 2356 if (ret) 2357 return ret; 2358 2359 uctx_resp.response_length = 2360 min_t(size_t, 2361 uverbs_attr_get_len(attrs, 2362 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 2363 sizeof(uctx_resp)); 2364 2365 ret = uverbs_copy_to_struct_or_zero(attrs, 2366 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 2367 &uctx_resp, 2368 sizeof(uctx_resp)); 2369 return ret; 2370 } 2371 2372 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 2373 { 2374 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2375 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2376 struct mlx5_bfreg_info *bfregi; 2377 2378 bfregi = &context->bfregi; 2379 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2380 2381 deallocate_uars(dev, context); 2382 kfree(bfregi->sys_pages); 2383 kfree(bfregi->count); 2384 2385 if (context->devx_uid) { 2386 if (uctx_rdma_ctrl_is_enabled(ibcontext->enabled_caps)) 2387 mlx5_cmd_remove_privileged_uid(dev->mdev, 2388 context->devx_uid); 2389 mlx5_ib_devx_destroy(dev, context->devx_uid); 2390 } 2391 } 2392 2393 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2394 int uar_idx) 2395 { 2396 int fw_uars_per_page; 2397 2398 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2399 2400 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2401 } 2402 2403 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2404 int uar_idx) 2405 { 2406 unsigned int fw_uars_per_page; 2407 2408 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2409 MLX5_UARS_IN_PAGE : 1; 2410 2411 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2412 } 2413 2414 static int get_command(unsigned long offset) 2415 { 2416 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2417 } 2418 2419 static int get_arg(unsigned long offset) 2420 { 2421 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2422 } 2423 2424 static int get_index(unsigned long offset) 2425 { 2426 return get_arg(offset); 2427 } 2428 2429 /* Index resides in an extra byte to enable larger values than 255 */ 2430 static int get_extended_index(unsigned long offset) 2431 { 2432 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2433 } 2434 2435 2436 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2437 { 2438 } 2439 2440 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2441 { 2442 switch (cmd) { 2443 case MLX5_IB_MMAP_WC_PAGE: 2444 return "WC"; 2445 case MLX5_IB_MMAP_REGULAR_PAGE: 2446 return "best effort WC"; 2447 case MLX5_IB_MMAP_NC_PAGE: 2448 return "NC"; 2449 case MLX5_IB_MMAP_DEVICE_MEM: 2450 return "Device Memory"; 2451 default: 2452 return "Unknown"; 2453 } 2454 } 2455 2456 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2457 struct vm_area_struct *vma, 2458 struct mlx5_ib_ucontext *context) 2459 { 2460 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2461 !(vma->vm_flags & VM_SHARED)) 2462 return -EINVAL; 2463 2464 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2465 return -EOPNOTSUPP; 2466 2467 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2468 return -EPERM; 2469 vm_flags_clear(vma, VM_MAYWRITE); 2470 2471 if (!dev->mdev->clock_info) 2472 return -EOPNOTSUPP; 2473 2474 return vm_insert_page(vma, vma->vm_start, 2475 virt_to_page(dev->mdev->clock_info)); 2476 } 2477 2478 static int phys_addr_to_bar(struct pci_dev *pdev, phys_addr_t pa) 2479 { 2480 resource_size_t start, end; 2481 int bar; 2482 2483 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 2484 /* Skip BARs not present or not memory-mapped */ 2485 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) 2486 continue; 2487 2488 start = pci_resource_start(pdev, bar); 2489 end = pci_resource_end(pdev, bar); 2490 2491 if (!start || !end) 2492 continue; 2493 2494 if (pa >= start && pa <= end) 2495 return bar; 2496 } 2497 2498 return -1; 2499 } 2500 2501 static int mlx5_ib_mmap_get_pfns(struct rdma_user_mmap_entry *entry, 2502 struct phys_vec *phys_vec, 2503 struct p2pdma_provider **provider) 2504 { 2505 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2506 struct pci_dev *pdev = to_mdev(entry->ucontext->device)->mdev->pdev; 2507 int bar; 2508 2509 phys_vec->paddr = mentry->address; 2510 phys_vec->len = entry->npages * PAGE_SIZE; 2511 2512 bar = phys_addr_to_bar(pdev, phys_vec->paddr); 2513 if (bar < 0) 2514 return -EINVAL; 2515 2516 *provider = pcim_p2pdma_provider(pdev, bar); 2517 /* If the kernel was not compiled with CONFIG_PCI_P2PDMA the 2518 * functionality is not supported. 2519 */ 2520 if (!*provider) 2521 return -EOPNOTSUPP; 2522 2523 return 0; 2524 } 2525 2526 static struct rdma_user_mmap_entry * 2527 mlx5_ib_pgoff_to_mmap_entry(struct ib_ucontext *ucontext, off_t pg_off) 2528 { 2529 unsigned long entry_pgoff; 2530 unsigned long idx; 2531 u8 command; 2532 2533 pg_off = pg_off >> PAGE_SHIFT; 2534 command = get_command(pg_off); 2535 idx = get_extended_index(pg_off); 2536 2537 entry_pgoff = command << 16 | idx; 2538 2539 return rdma_user_mmap_entry_get_pgoff(ucontext, entry_pgoff); 2540 } 2541 2542 static void mlx5_ib_free_var_mmap_entry(struct mlx5_user_mmap_entry *mentry, 2543 struct mlx5_var_region *var_region) 2544 { 2545 mutex_lock(&var_region->bitmap_lock); 2546 clear_bit(mentry->page_idx, var_region->bitmap); 2547 mutex_unlock(&var_region->bitmap_lock); 2548 kfree(mentry); 2549 } 2550 2551 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2552 { 2553 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2554 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2555 struct mlx5_var_table *var_table = &dev->var_table; 2556 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2557 struct mlx5_var_region *var_region; 2558 2559 switch (mentry->mmap_flag) { 2560 case MLX5_IB_MMAP_TYPE_MEMIC: 2561 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2562 mlx5_ib_dm_mmap_free(dev, mentry); 2563 break; 2564 case MLX5_IB_MMAP_TYPE_VAR: 2565 var_region = &var_table->var_region; 2566 mlx5_ib_free_var_mmap_entry(mentry, var_region); 2567 break; 2568 case MLX5_IB_MMAP_TYPE_TLP_VAR: 2569 var_region = &var_table->tlp_var_region; 2570 mlx5_ib_free_var_mmap_entry(mentry, var_region); 2571 break; 2572 case MLX5_IB_MMAP_TYPE_UAR_WC: 2573 case MLX5_IB_MMAP_TYPE_UAR_NC: 2574 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2575 context->devx_uid); 2576 kfree(mentry); 2577 break; 2578 default: 2579 WARN_ON(true); 2580 } 2581 } 2582 2583 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2584 struct vm_area_struct *vma, 2585 struct mlx5_ib_ucontext *context) 2586 { 2587 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2588 int err; 2589 unsigned long idx; 2590 phys_addr_t pfn; 2591 pgprot_t prot; 2592 u32 bfreg_dyn_idx = 0; 2593 u32 uar_index; 2594 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2595 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2596 bfregi->num_static_sys_pages; 2597 2598 if (bfregi->lib_uar_dyn) 2599 return -EINVAL; 2600 2601 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2602 return -EINVAL; 2603 2604 if (dyn_uar) 2605 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2606 else 2607 idx = get_index(vma->vm_pgoff); 2608 2609 if (idx >= max_valid_idx) { 2610 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2611 idx, max_valid_idx); 2612 return -EINVAL; 2613 } 2614 2615 switch (cmd) { 2616 case MLX5_IB_MMAP_WC_PAGE: 2617 case MLX5_IB_MMAP_ALLOC_WC: 2618 case MLX5_IB_MMAP_REGULAR_PAGE: 2619 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2620 prot = pgprot_writecombine(vma->vm_page_prot); 2621 break; 2622 case MLX5_IB_MMAP_NC_PAGE: 2623 prot = pgprot_noncached(vma->vm_page_prot); 2624 break; 2625 default: 2626 return -EINVAL; 2627 } 2628 2629 if (dyn_uar) { 2630 int uars_per_page; 2631 2632 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2633 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2634 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2635 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2636 bfreg_dyn_idx, bfregi->total_num_bfregs); 2637 return -EINVAL; 2638 } 2639 2640 mutex_lock(&bfregi->lock); 2641 /* Fail if uar already allocated, first bfreg index of each 2642 * page holds its count. 2643 */ 2644 if (bfregi->count[bfreg_dyn_idx]) { 2645 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2646 mutex_unlock(&bfregi->lock); 2647 return -EINVAL; 2648 } 2649 2650 bfregi->count[bfreg_dyn_idx]++; 2651 mutex_unlock(&bfregi->lock); 2652 2653 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2654 context->devx_uid); 2655 if (err) { 2656 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2657 goto free_bfreg; 2658 } 2659 } else { 2660 uar_index = bfregi->sys_pages[idx]; 2661 } 2662 2663 pfn = uar_index2pfn(dev, uar_index); 2664 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2665 2666 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2667 prot, NULL); 2668 if (err) { 2669 mlx5_ib_err(dev, 2670 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2671 err, mmap_cmd2str(cmd)); 2672 goto err; 2673 } 2674 2675 if (dyn_uar) 2676 bfregi->sys_pages[idx] = uar_index; 2677 return 0; 2678 2679 err: 2680 if (!dyn_uar) 2681 return err; 2682 2683 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, context->devx_uid); 2684 2685 free_bfreg: 2686 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2687 2688 return err; 2689 } 2690 2691 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2692 { 2693 unsigned long idx; 2694 u8 command; 2695 2696 command = get_command(vma->vm_pgoff); 2697 idx = get_extended_index(vma->vm_pgoff); 2698 2699 return (command << 16 | idx); 2700 } 2701 2702 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2703 struct vm_area_struct *vma, 2704 struct ib_ucontext *ucontext) 2705 { 2706 struct mlx5_user_mmap_entry *mentry; 2707 struct rdma_user_mmap_entry *entry; 2708 unsigned long pgoff; 2709 pgprot_t prot; 2710 phys_addr_t pfn; 2711 int ret; 2712 2713 pgoff = mlx5_vma_to_pgoff(vma); 2714 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2715 if (!entry) 2716 return -EINVAL; 2717 2718 mentry = to_mmmap(entry); 2719 pfn = (mentry->address >> PAGE_SHIFT); 2720 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2721 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_TLP_VAR || 2722 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2723 prot = pgprot_noncached(vma->vm_page_prot); 2724 else 2725 prot = pgprot_writecombine(vma->vm_page_prot); 2726 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2727 entry->npages * PAGE_SIZE, 2728 prot, 2729 entry); 2730 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2731 return ret; 2732 } 2733 2734 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2735 { 2736 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2737 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2738 2739 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2740 (index & 0xFF)) << PAGE_SHIFT; 2741 } 2742 2743 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2744 { 2745 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2746 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2747 unsigned long command; 2748 phys_addr_t pfn; 2749 2750 command = get_command(vma->vm_pgoff); 2751 switch (command) { 2752 case MLX5_IB_MMAP_WC_PAGE: 2753 case MLX5_IB_MMAP_ALLOC_WC: 2754 if (!mlx5_wc_support_get(dev->mdev)) 2755 return -EPERM; 2756 fallthrough; 2757 case MLX5_IB_MMAP_NC_PAGE: 2758 case MLX5_IB_MMAP_REGULAR_PAGE: 2759 return uar_mmap(dev, command, vma, context); 2760 2761 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2762 return -ENOSYS; 2763 2764 case MLX5_IB_MMAP_CORE_CLOCK: 2765 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2766 return -EINVAL; 2767 2768 if (vma->vm_flags & VM_WRITE) 2769 return -EPERM; 2770 vm_flags_clear(vma, VM_MAYWRITE); 2771 2772 /* Don't expose to user-space information it shouldn't have */ 2773 if (PAGE_SIZE > 4096) 2774 return -EOPNOTSUPP; 2775 2776 pfn = (dev->mdev->bar_addr + 2777 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2778 PAGE_SHIFT; 2779 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2780 PAGE_SIZE, 2781 pgprot_noncached(vma->vm_page_prot), 2782 NULL); 2783 case MLX5_IB_MMAP_CLOCK_INFO: 2784 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2785 2786 default: 2787 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2788 } 2789 2790 return 0; 2791 } 2792 2793 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2794 { 2795 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2796 struct ib_device *ibdev = ibpd->device; 2797 struct mlx5_ib_alloc_pd_resp resp = {}; 2798 int err; 2799 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2800 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2801 u16 uid = 0; 2802 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2803 udata, struct mlx5_ib_ucontext, ibucontext); 2804 2805 uid = context ? context->devx_uid : 0; 2806 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2807 MLX5_SET(alloc_pd_in, in, uid, uid); 2808 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2809 if (err) 2810 return err; 2811 2812 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2813 pd->uid = uid; 2814 if (udata) { 2815 resp.pdn = pd->pdn; 2816 err = ib_respond_udata(udata, resp); 2817 if (err) { 2818 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2819 return err; 2820 } 2821 } 2822 2823 return 0; 2824 } 2825 2826 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2827 { 2828 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2829 struct mlx5_ib_pd *mpd = to_mpd(pd); 2830 2831 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2832 } 2833 2834 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2835 { 2836 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2837 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2838 int err; 2839 u16 uid; 2840 2841 uid = ibqp->pd ? 2842 to_mpd(ibqp->pd)->uid : 0; 2843 2844 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2845 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2846 return -EOPNOTSUPP; 2847 } 2848 2849 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2850 if (err) 2851 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2852 ibqp->qp_num, gid->raw); 2853 2854 return err; 2855 } 2856 2857 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2858 { 2859 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2860 int err; 2861 u16 uid; 2862 2863 uid = ibqp->pd ? 2864 to_mpd(ibqp->pd)->uid : 0; 2865 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2866 if (err) 2867 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2868 ibqp->qp_num, gid->raw); 2869 2870 return err; 2871 } 2872 2873 static int init_node_data(struct mlx5_ib_dev *dev) 2874 { 2875 int err; 2876 2877 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2878 if (err) 2879 return err; 2880 2881 dev->mdev->rev_id = dev->mdev->pdev->revision; 2882 2883 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2884 } 2885 2886 static ssize_t fw_pages_show(struct device *device, 2887 struct device_attribute *attr, char *buf) 2888 { 2889 struct mlx5_ib_dev *dev = 2890 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2891 2892 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2893 } 2894 static DEVICE_ATTR_RO(fw_pages); 2895 2896 static ssize_t reg_pages_show(struct device *device, 2897 struct device_attribute *attr, char *buf) 2898 { 2899 struct mlx5_ib_dev *dev = 2900 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2901 2902 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2903 } 2904 static DEVICE_ATTR_RO(reg_pages); 2905 2906 static ssize_t hca_type_show(struct device *device, 2907 struct device_attribute *attr, char *buf) 2908 { 2909 struct mlx5_ib_dev *dev = 2910 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2911 2912 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2913 } 2914 static DEVICE_ATTR_RO(hca_type); 2915 2916 static ssize_t hw_rev_show(struct device *device, 2917 struct device_attribute *attr, char *buf) 2918 { 2919 struct mlx5_ib_dev *dev = 2920 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2921 2922 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2923 } 2924 static DEVICE_ATTR_RO(hw_rev); 2925 2926 static ssize_t board_id_show(struct device *device, 2927 struct device_attribute *attr, char *buf) 2928 { 2929 struct mlx5_ib_dev *dev = 2930 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2931 2932 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2933 dev->mdev->board_id); 2934 } 2935 static DEVICE_ATTR_RO(board_id); 2936 2937 static struct attribute *mlx5_class_attributes[] = { 2938 &dev_attr_hw_rev.attr, 2939 &dev_attr_hca_type.attr, 2940 &dev_attr_board_id.attr, 2941 &dev_attr_fw_pages.attr, 2942 &dev_attr_reg_pages.attr, 2943 NULL, 2944 }; 2945 2946 static const struct attribute_group mlx5_attr_group = { 2947 .attrs = mlx5_class_attributes, 2948 }; 2949 2950 static void pkey_change_handler(struct work_struct *work) 2951 { 2952 struct mlx5_ib_port_resources *ports = 2953 container_of(work, struct mlx5_ib_port_resources, 2954 pkey_change_work); 2955 2956 if (!ports->gsi) 2957 /* 2958 * We got this event before device was fully configured 2959 * and MAD registration code wasn't called/finished yet. 2960 */ 2961 return; 2962 2963 mlx5_ib_gsi_pkey_change(ports->gsi); 2964 } 2965 2966 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2967 { 2968 struct mlx5_ib_qp *mqp; 2969 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2970 struct mlx5_core_cq *mcq; 2971 struct list_head cq_armed_list; 2972 unsigned long flags_qp; 2973 unsigned long flags_cq; 2974 unsigned long flags; 2975 2976 INIT_LIST_HEAD(&cq_armed_list); 2977 2978 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2979 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2980 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2981 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2982 if (mqp->sq.tail != mqp->sq.head) { 2983 send_mcq = to_mcq(mqp->ibqp.send_cq); 2984 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2985 if (send_mcq->mcq.comp && 2986 mqp->ibqp.send_cq->comp_handler) { 2987 if (!send_mcq->mcq.reset_notify_added) { 2988 send_mcq->mcq.reset_notify_added = 1; 2989 list_add_tail(&send_mcq->mcq.reset_notify, 2990 &cq_armed_list); 2991 } 2992 } 2993 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2994 } 2995 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2996 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2997 /* no handling is needed for SRQ */ 2998 if (!mqp->ibqp.srq) { 2999 if (mqp->rq.tail != mqp->rq.head) { 3000 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3001 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3002 if (recv_mcq->mcq.comp && 3003 mqp->ibqp.recv_cq->comp_handler) { 3004 if (!recv_mcq->mcq.reset_notify_added) { 3005 recv_mcq->mcq.reset_notify_added = 1; 3006 list_add_tail(&recv_mcq->mcq.reset_notify, 3007 &cq_armed_list); 3008 } 3009 } 3010 spin_unlock_irqrestore(&recv_mcq->lock, 3011 flags_cq); 3012 } 3013 } 3014 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3015 } 3016 /*At that point all inflight post send were put to be executed as of we 3017 * lock/unlock above locks Now need to arm all involved CQs. 3018 */ 3019 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 3020 mcq->comp(mcq, NULL); 3021 } 3022 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3023 } 3024 3025 static void delay_drop_handler(struct work_struct *work) 3026 { 3027 int err; 3028 struct mlx5_ib_delay_drop *delay_drop = 3029 container_of(work, struct mlx5_ib_delay_drop, 3030 delay_drop_work); 3031 3032 atomic_inc(&delay_drop->events_cnt); 3033 3034 mutex_lock(&delay_drop->lock); 3035 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 3036 if (err) { 3037 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 3038 delay_drop->timeout); 3039 delay_drop->activate = false; 3040 } 3041 mutex_unlock(&delay_drop->lock); 3042 } 3043 3044 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 3045 struct ib_event *ibev) 3046 { 3047 u32 port = (eqe->data.port.port >> 4) & 0xf; 3048 3049 switch (eqe->sub_type) { 3050 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 3051 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 3052 IB_LINK_LAYER_ETHERNET) 3053 schedule_work(&ibdev->delay_drop.delay_drop_work); 3054 break; 3055 default: /* do nothing */ 3056 return; 3057 } 3058 } 3059 3060 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 3061 struct ib_event *ibev) 3062 { 3063 u32 port = (eqe->data.port.port >> 4) & 0xf; 3064 3065 ibev->element.port_num = port; 3066 3067 switch (eqe->sub_type) { 3068 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 3069 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 3070 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 3071 if (ibdev->ib_active) { 3072 struct ib_event speed_event = {}; 3073 3074 speed_event.device = &ibdev->ib_dev; 3075 speed_event.event = IB_EVENT_DEVICE_SPEED_CHANGE; 3076 ib_dispatch_event(&speed_event); 3077 } 3078 3079 /* In RoCE, port up/down events are handled in 3080 * mlx5_netdev_event(). 3081 */ 3082 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 3083 IB_LINK_LAYER_ETHERNET) 3084 return -EINVAL; 3085 3086 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 3087 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3088 break; 3089 3090 case MLX5_PORT_CHANGE_SUBTYPE_LID: 3091 ibev->event = IB_EVENT_LID_CHANGE; 3092 break; 3093 3094 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 3095 ibev->event = IB_EVENT_PKEY_CHANGE; 3096 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 3097 break; 3098 3099 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 3100 ibev->event = IB_EVENT_GID_CHANGE; 3101 break; 3102 3103 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 3104 ibev->event = IB_EVENT_CLIENT_REREGISTER; 3105 break; 3106 default: 3107 return -EINVAL; 3108 } 3109 3110 return 0; 3111 } 3112 3113 static void mlx5_ib_handle_event(struct work_struct *_work) 3114 { 3115 struct mlx5_ib_event_work *work = 3116 container_of(_work, struct mlx5_ib_event_work, work); 3117 struct mlx5_ib_dev *ibdev; 3118 struct ib_event ibev; 3119 3120 if (work->is_slave) { 3121 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 3122 if (!ibdev) 3123 goto out; 3124 } else { 3125 ibdev = work->dev; 3126 } 3127 3128 switch (work->event) { 3129 case MLX5_EVENT_TYPE_PORT_CHANGE: 3130 if (handle_port_change(ibdev, work->param, &ibev)) 3131 goto out; 3132 break; 3133 case MLX5_EVENT_TYPE_GENERAL_EVENT: 3134 handle_general_event(ibdev, work->param, &ibev); 3135 fallthrough; 3136 default: 3137 goto out; 3138 } 3139 3140 ibev.device = &ibdev->ib_dev; 3141 3142 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 3143 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 3144 goto out; 3145 } 3146 3147 if (ibdev->ib_active) 3148 ib_dispatch_event(&ibev); 3149 3150 out: 3151 kfree(work); 3152 } 3153 3154 static int mlx5_ib_event(struct notifier_block *nb, 3155 unsigned long event, void *param) 3156 { 3157 struct mlx5_ib_event_work *work; 3158 3159 work = kmalloc_obj(*work, GFP_ATOMIC); 3160 if (!work) 3161 return NOTIFY_DONE; 3162 3163 INIT_WORK(&work->work, mlx5_ib_handle_event); 3164 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 3165 work->is_slave = false; 3166 work->param = param; 3167 work->event = event; 3168 3169 queue_work(mlx5_ib_event_wq, &work->work); 3170 3171 return NOTIFY_OK; 3172 } 3173 3174 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 3175 unsigned long event, void *param) 3176 { 3177 struct mlx5_ib_event_work *work; 3178 3179 work = kmalloc_obj(*work, GFP_ATOMIC); 3180 if (!work) 3181 return NOTIFY_DONE; 3182 3183 INIT_WORK(&work->work, mlx5_ib_handle_event); 3184 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 3185 work->is_slave = true; 3186 work->param = param; 3187 work->event = event; 3188 queue_work(mlx5_ib_event_wq, &work->work); 3189 3190 return NOTIFY_OK; 3191 } 3192 3193 static void mlx5_ib_handle_sys_error_event(struct work_struct *_work) 3194 { 3195 struct mlx5_ib_event_work *work = 3196 container_of(_work, struct mlx5_ib_event_work, work); 3197 struct mlx5_ib_dev *ibdev = work->dev; 3198 struct ib_event ibev; 3199 3200 ibev.event = IB_EVENT_DEVICE_FATAL; 3201 mlx5_ib_handle_internal_error(ibdev); 3202 ibev.element.port_num = (u8)(unsigned long)work->param; 3203 ibev.device = &ibdev->ib_dev; 3204 3205 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 3206 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 3207 goto out; 3208 } 3209 3210 if (ibdev->ib_active) 3211 ib_dispatch_event(&ibev); 3212 3213 ibdev->ib_active = false; 3214 out: 3215 kfree(work); 3216 } 3217 3218 static int mlx5_ib_sys_error_event(struct notifier_block *nb, 3219 unsigned long event, void *param) 3220 { 3221 struct mlx5_ib_event_work *work; 3222 3223 if (event != MLX5_DEV_EVENT_SYS_ERROR) 3224 return NOTIFY_DONE; 3225 3226 work = kmalloc_obj(*work, GFP_ATOMIC); 3227 if (!work) 3228 return NOTIFY_DONE; 3229 3230 INIT_WORK(&work->work, mlx5_ib_handle_sys_error_event); 3231 work->dev = container_of(nb, struct mlx5_ib_dev, sys_error_events); 3232 work->is_slave = false; 3233 work->param = param; 3234 work->event = event; 3235 3236 queue_work(mlx5_ib_event_wq, &work->work); 3237 3238 return NOTIFY_OK; 3239 } 3240 3241 static int mlx5_ib_stage_sys_error_notifier_init(struct mlx5_ib_dev *dev) 3242 { 3243 dev->sys_error_events.notifier_call = mlx5_ib_sys_error_event; 3244 mlx5_notifier_register(dev->mdev, &dev->sys_error_events); 3245 return 0; 3246 } 3247 3248 static void mlx5_ib_stage_sys_error_notifier_cleanup(struct mlx5_ib_dev *dev) 3249 { 3250 mlx5_notifier_unregister(dev->mdev, &dev->sys_error_events); 3251 } 3252 3253 static int mlx5_ib_get_plane_num(struct mlx5_core_dev *mdev, u8 *num_plane) 3254 { 3255 struct mlx5_hca_vport_context vport_ctx; 3256 int err; 3257 3258 *num_plane = 0; 3259 if (!MLX5_CAP_GEN(mdev, ib_virt) || !MLX5_CAP_GEN_2(mdev, multiplane)) 3260 return 0; 3261 3262 err = mlx5_query_hca_vport_context(mdev, 0, 1, 0, &vport_ctx); 3263 if (err) 3264 return err; 3265 3266 *num_plane = vport_ctx.num_plane; 3267 return 0; 3268 } 3269 3270 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 3271 { 3272 struct mlx5_hca_vport_context vport_ctx; 3273 int err; 3274 int port; 3275 3276 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 3277 return 0; 3278 3279 for (port = 1; port <= dev->num_ports; port++) { 3280 if (dev->num_plane) { 3281 dev->port_caps[port - 1].has_smi = false; 3282 continue; 3283 } else if (!MLX5_CAP_GEN(dev->mdev, ib_virt) || 3284 dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 3285 dev->port_caps[port - 1].has_smi = true; 3286 continue; 3287 } 3288 3289 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0, 3290 &vport_ctx); 3291 if (err) { 3292 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 3293 port, err); 3294 return err; 3295 } 3296 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi; 3297 } 3298 3299 return 0; 3300 } 3301 3302 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 3303 { 3304 unsigned int port; 3305 3306 rdma_for_each_port (&dev->ib_dev, port) 3307 mlx5_query_ext_port_caps(dev, port); 3308 } 3309 3310 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3311 { 3312 switch (umr_fence_cap) { 3313 case MLX5_CAP_UMR_FENCE_NONE: 3314 return MLX5_FENCE_MODE_NONE; 3315 case MLX5_CAP_UMR_FENCE_SMALL: 3316 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3317 default: 3318 return MLX5_FENCE_MODE_STRONG_ORDERING; 3319 } 3320 } 3321 3322 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev) 3323 { 3324 struct mlx5_ib_resources *devr = &dev->devr; 3325 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3326 struct ib_device *ibdev; 3327 struct ib_pd *pd; 3328 struct ib_cq *cq; 3329 int ret = 0; 3330 3331 3332 /* 3333 * devr->c0 is set once, never changed until device unload. 3334 * Avoid taking the mutex if initialization is already done. 3335 */ 3336 if (smp_load_acquire(&devr->c0)) 3337 return 0; 3338 3339 mutex_lock(&devr->cq_lock); 3340 if (devr->c0) 3341 goto unlock; 3342 3343 ibdev = &dev->ib_dev; 3344 pd = ib_alloc_pd(ibdev, 0); 3345 if (IS_ERR(pd)) { 3346 ret = PTR_ERR(pd); 3347 mlx5_ib_err(dev, "Couldn't allocate PD for res init, err=%pe\n", 3348 pd); 3349 goto unlock; 3350 } 3351 3352 cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 3353 if (IS_ERR(cq)) { 3354 ret = PTR_ERR(cq); 3355 mlx5_ib_err(dev, "Couldn't create CQ for res init, err=%pe\n", 3356 cq); 3357 ib_dealloc_pd(pd); 3358 goto unlock; 3359 } 3360 3361 devr->p0 = pd; 3362 smp_store_release(&devr->c0, cq); 3363 3364 unlock: 3365 mutex_unlock(&devr->cq_lock); 3366 return ret; 3367 } 3368 3369 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev) 3370 { 3371 struct mlx5_ib_resources *devr = &dev->devr; 3372 struct ib_srq_init_attr attr; 3373 struct ib_srq *s0 = NULL, *s1; 3374 int ret = 0; 3375 3376 /* 3377 * devr->s1 is set once, never changed until device unload. 3378 * Avoid taking the mutex if initialization is already done. 3379 */ 3380 if (smp_load_acquire(&devr->s1)) 3381 return 0; 3382 3383 mutex_lock(&devr->srq_lock); 3384 if (devr->s1) 3385 goto unlock; 3386 3387 ret = mlx5_ib_dev_res_cq_init(dev); 3388 if (ret) 3389 goto unlock; 3390 3391 /* 3392 * s0 is an XRC-type placeholder SRQ used as the default XRQN for 3393 * XRC QPs. Skip it when XRC is absent; all devr->s0 accesses in 3394 * qp.c are inside XRC QP paths that the verbs layer blocks before 3395 * reaching this driver when xrc=0, so NULL is safe. 3396 */ 3397 if (MLX5_CAP_GEN(dev->mdev, xrc)) { 3398 memset(&attr, 0, sizeof(attr)); 3399 attr.attr.max_sge = 1; 3400 attr.attr.max_wr = 1; 3401 attr.srq_type = IB_SRQT_XRC; 3402 attr.ext.cq = devr->c0; 3403 3404 s0 = ib_create_srq(devr->p0, &attr); 3405 if (IS_ERR(s0)) { 3406 ret = PTR_ERR(s0); 3407 mlx5_ib_err(dev, 3408 "Couldn't create SRQ 0 for res init, err=%pe\n", 3409 s0); 3410 goto unlock; 3411 } 3412 } 3413 3414 memset(&attr, 0, sizeof(attr)); 3415 attr.attr.max_sge = 1; 3416 attr.attr.max_wr = 1; 3417 attr.srq_type = IB_SRQT_BASIC; 3418 3419 s1 = ib_create_srq(devr->p0, &attr); 3420 if (IS_ERR(s1)) { 3421 ret = PTR_ERR(s1); 3422 mlx5_ib_err(dev, 3423 "Couldn't create SRQ 1 for res init, err=%pe\n", 3424 s1); 3425 if (s0) 3426 ib_destroy_srq(s0); 3427 goto unlock; 3428 } 3429 3430 devr->s0 = s0; 3431 smp_store_release(&devr->s1, s1); 3432 3433 unlock: 3434 mutex_unlock(&devr->srq_lock); 3435 return ret; 3436 } 3437 3438 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 3439 { 3440 struct mlx5_ib_resources *devr = &dev->devr; 3441 int ret; 3442 3443 mutex_init(&devr->cq_lock); 3444 mutex_init(&devr->srq_lock); 3445 3446 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 3447 return 0; 3448 3449 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 3450 if (ret) 3451 return ret; 3452 3453 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 3454 if (ret) { 3455 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3456 return ret; 3457 } 3458 3459 return 0; 3460 } 3461 3462 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 3463 { 3464 struct mlx5_ib_resources *devr = &dev->devr; 3465 3466 /* After s0/s1 init, they are not unset during the device lifetime. */ 3467 if (devr->s1) { 3468 ib_destroy_srq(devr->s1); 3469 if (devr->s0) 3470 ib_destroy_srq(devr->s0); 3471 } 3472 if (MLX5_CAP_GEN(dev->mdev, xrc)) { 3473 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3474 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3475 } 3476 /* After p0/c0 init, they are not unset during the device lifetime. */ 3477 if (devr->c0) { 3478 ib_destroy_cq(devr->c0); 3479 ib_dealloc_pd(devr->p0); 3480 } 3481 mutex_destroy(&devr->cq_lock); 3482 mutex_destroy(&devr->srq_lock); 3483 } 3484 3485 static u32 get_core_cap_flags(struct ib_device *ibdev, 3486 struct mlx5_hca_vport_context *rep) 3487 { 3488 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3489 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3490 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3491 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3492 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3493 u32 ret = 0; 3494 3495 if (rep->grh_required) 3496 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 3497 3498 if (dev->num_plane) 3499 return ret | RDMA_CORE_CAP_PROT_IB | RDMA_CORE_CAP_IB_MAD | 3500 RDMA_CORE_CAP_IB_CM | RDMA_CORE_CAP_IB_SA | 3501 RDMA_CORE_CAP_AF_IB; 3502 else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3503 return ret | RDMA_CORE_CAP_IB_MAD | RDMA_CORE_CAP_IB_SMI; 3504 3505 if (ll == IB_LINK_LAYER_INFINIBAND) 3506 return ret | RDMA_CORE_PORT_IBA_IB; 3507 3508 if (raw_support) 3509 ret |= RDMA_CORE_PORT_RAW_PACKET; 3510 3511 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3512 return ret; 3513 3514 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3515 return ret; 3516 3517 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3518 ret |= RDMA_CORE_PORT_IBA_ROCE; 3519 3520 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3521 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3522 3523 return ret; 3524 } 3525 3526 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 3527 struct ib_port_immutable *immutable) 3528 { 3529 struct ib_port_attr attr; 3530 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3531 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3532 struct mlx5_hca_vport_context rep = {0}; 3533 int err; 3534 3535 err = ib_query_port(ibdev, port_num, &attr); 3536 if (err) 3537 return err; 3538 3539 if (ll == IB_LINK_LAYER_INFINIBAND) { 3540 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3541 port_num = smi_to_native_portnum(dev, port_num); 3542 3543 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 3544 &rep); 3545 if (err) 3546 return err; 3547 } 3548 3549 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3550 immutable->gid_tbl_len = attr.gid_tbl_len; 3551 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 3552 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3553 3554 return 0; 3555 } 3556 3557 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 3558 struct ib_port_immutable *immutable) 3559 { 3560 struct ib_port_attr attr; 3561 int err; 3562 3563 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3564 3565 err = ib_query_port(ibdev, port_num, &attr); 3566 if (err) 3567 return err; 3568 3569 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3570 immutable->gid_tbl_len = attr.gid_tbl_len; 3571 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3572 3573 return 0; 3574 } 3575 3576 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3577 { 3578 struct mlx5_ib_dev *dev = 3579 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3580 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3581 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3582 fw_rev_sub(dev->mdev)); 3583 } 3584 3585 static int lag_event(struct notifier_block *nb, unsigned long event, void *data) 3586 { 3587 struct mlx5_ib_dev *dev = container_of(nb, struct mlx5_ib_dev, 3588 lag_events); 3589 struct mlx5_core_dev *mdev = dev->mdev; 3590 struct ib_device *ibdev = &dev->ib_dev; 3591 struct net_device *old_ndev = NULL; 3592 struct mlx5_ib_port *port; 3593 struct net_device *ndev; 3594 u32 portnum = 0; 3595 int ret = 0; 3596 int i; 3597 3598 switch (event) { 3599 case MLX5_DRIVER_EVENT_ACTIVE_BACKUP_LAG_CHANGE_LOWERSTATE: 3600 ndev = data; 3601 if (ndev) { 3602 if (!mlx5_lag_is_roce(mdev)) { 3603 // sriov lag 3604 for (i = 0; i < dev->num_ports; i++) { 3605 port = &dev->port[i]; 3606 if (port->rep && port->rep->vport == 3607 MLX5_VPORT_UPLINK) { 3608 portnum = i; 3609 break; 3610 } 3611 } 3612 } 3613 old_ndev = ib_device_get_netdev(ibdev, portnum + 1); 3614 ret = ib_device_set_netdev(ibdev, ndev, portnum + 1); 3615 if (ret) 3616 goto out; 3617 3618 if (old_ndev) 3619 roce_del_all_netdev_gids(ibdev, portnum + 1, 3620 old_ndev); 3621 rdma_roce_rescan_port(ibdev, portnum + 1); 3622 } 3623 break; 3624 default: 3625 return NOTIFY_DONE; 3626 } 3627 3628 out: 3629 dev_put(old_ndev); 3630 return notifier_from_errno(ret); 3631 } 3632 3633 static void mlx5e_lag_event_register(struct mlx5_ib_dev *dev) 3634 { 3635 dev->lag_events.notifier_call = lag_event; 3636 blocking_notifier_chain_register(&dev->mdev->priv.lag_nh, 3637 &dev->lag_events); 3638 } 3639 3640 static void mlx5e_lag_event_unregister(struct mlx5_ib_dev *dev) 3641 { 3642 blocking_notifier_chain_unregister(&dev->mdev->priv.lag_nh, 3643 &dev->lag_events); 3644 } 3645 3646 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3647 { 3648 struct mlx5_flow_table_attr ft_attr = {}; 3649 struct mlx5_core_dev *mdev = dev->mdev; 3650 struct mlx5_flow_namespace *ns; 3651 int err; 3652 3653 ns = mlx5_get_flow_namespace(mdev, MLX5_FLOW_NAMESPACE_LAG); 3654 if (!ns || !mlx5_lag_is_active(mdev)) 3655 return 0; 3656 3657 err = mlx5_cmd_create_vport_lag(mdev); 3658 if (err) 3659 return err; 3660 3661 ft_attr.level = 0; 3662 ft_attr.prio = 0; 3663 ft_attr.max_fte = dev->num_ports; 3664 3665 err = mlx5_lag_demux_init(mdev, &ft_attr); 3666 if (err) 3667 goto err_destroy_vport_lag; 3668 3669 mlx5e_lag_event_register(dev); 3670 dev->lag_ports = mlx5_lag_get_num_ports(mdev); 3671 dev->lag_active = true; 3672 return 0; 3673 3674 err_destroy_vport_lag: 3675 mlx5_cmd_destroy_vport_lag(mdev); 3676 return err; 3677 } 3678 3679 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3680 { 3681 struct mlx5_core_dev *mdev = dev->mdev; 3682 3683 if (dev->lag_active) { 3684 dev->lag_active = false; 3685 3686 mlx5e_lag_event_unregister(dev); 3687 mlx5_lag_demux_cleanup(mdev); 3688 3689 mlx5_cmd_destroy_vport_lag(mdev); 3690 } 3691 } 3692 3693 static void mlx5_netdev_notifier_register(struct mlx5_roce *roce, 3694 struct net_device *netdev) 3695 { 3696 int err; 3697 3698 if (roce->tracking_netdev) 3699 return; 3700 roce->tracking_netdev = netdev; 3701 roce->nb.notifier_call = mlx5_netdev_event; 3702 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn); 3703 WARN_ON(err); 3704 } 3705 3706 static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce) 3707 { 3708 if (!roce->tracking_netdev) 3709 return; 3710 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb, 3711 &roce->nn); 3712 roce->tracking_netdev = NULL; 3713 } 3714 3715 static int mlx5e_mdev_notifier_event(struct notifier_block *nb, 3716 unsigned long event, void *data) 3717 { 3718 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb); 3719 struct net_device *netdev = data; 3720 3721 switch (event) { 3722 case MLX5_DRIVER_EVENT_UPLINK_NETDEV: 3723 if (netdev) 3724 mlx5_netdev_notifier_register(roce, netdev); 3725 else 3726 mlx5_netdev_notifier_unregister(roce); 3727 break; 3728 default: 3729 return NOTIFY_DONE; 3730 } 3731 3732 return NOTIFY_OK; 3733 } 3734 3735 static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num) 3736 { 3737 struct mlx5_roce *roce = &dev->port[port_num].roce; 3738 3739 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event; 3740 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb); 3741 mlx5_core_uplink_netdev_event_replay(dev->mdev); 3742 } 3743 3744 static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num) 3745 { 3746 struct mlx5_roce *roce = &dev->port[port_num].roce; 3747 3748 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb); 3749 mlx5_netdev_notifier_unregister(roce); 3750 } 3751 3752 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3753 { 3754 int err; 3755 3756 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3757 err = mlx5_nic_vport_enable_roce(dev->mdev); 3758 if (err) 3759 return err; 3760 } 3761 3762 err = mlx5_eth_lag_init(dev); 3763 if (err) 3764 goto err_disable_roce; 3765 3766 return 0; 3767 3768 err_disable_roce: 3769 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3770 mlx5_nic_vport_disable_roce(dev->mdev); 3771 3772 return err; 3773 } 3774 3775 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3776 { 3777 mlx5_eth_lag_cleanup(dev); 3778 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3779 mlx5_nic_vport_disable_roce(dev->mdev); 3780 } 3781 3782 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3783 enum rdma_netdev_t type, 3784 struct rdma_netdev_alloc_params *params) 3785 { 3786 if (type != RDMA_NETDEV_IPOIB) 3787 return -EOPNOTSUPP; 3788 3789 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3790 } 3791 3792 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3793 size_t count, loff_t *pos) 3794 { 3795 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3796 char lbuf[20]; 3797 int len; 3798 3799 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3800 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3801 } 3802 3803 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3804 size_t count, loff_t *pos) 3805 { 3806 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3807 u32 timeout; 3808 u32 var; 3809 3810 if (kstrtouint_from_user(buf, count, 0, &var)) 3811 return -EFAULT; 3812 3813 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3814 1000); 3815 if (timeout != var) 3816 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3817 timeout); 3818 3819 delay_drop->timeout = timeout; 3820 3821 return count; 3822 } 3823 3824 static const struct file_operations fops_delay_drop_timeout = { 3825 .owner = THIS_MODULE, 3826 .open = simple_open, 3827 .write = delay_drop_timeout_write, 3828 .read = delay_drop_timeout_read, 3829 }; 3830 3831 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3832 struct mlx5_ib_multiport_info *mpi) 3833 { 3834 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3835 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3836 int comps; 3837 int err; 3838 int i; 3839 3840 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3841 3842 mlx5_ib_disable_lb_mp(ibdev->mdev, mpi->mdev, &ibdev->lb); 3843 3844 mlx5_core_mp_event_replay(ibdev->mdev, 3845 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3846 NULL); 3847 mlx5_core_mp_event_replay(mpi->mdev, 3848 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3849 NULL); 3850 3851 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3852 3853 spin_lock(&port->mp.mpi_lock); 3854 if (!mpi->ibdev) { 3855 spin_unlock(&port->mp.mpi_lock); 3856 return; 3857 } 3858 3859 mpi->ibdev = NULL; 3860 3861 spin_unlock(&port->mp.mpi_lock); 3862 if (mpi->mdev_events.notifier_call) 3863 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3864 mpi->mdev_events.notifier_call = NULL; 3865 mlx5_mdev_netdev_untrack(ibdev, port_num); 3866 spin_lock(&port->mp.mpi_lock); 3867 3868 comps = mpi->mdev_refcnt; 3869 if (comps) { 3870 mpi->unaffiliate = true; 3871 init_completion(&mpi->unref_comp); 3872 spin_unlock(&port->mp.mpi_lock); 3873 3874 for (i = 0; i < comps; i++) 3875 wait_for_completion(&mpi->unref_comp); 3876 3877 spin_lock(&port->mp.mpi_lock); 3878 mpi->unaffiliate = false; 3879 } 3880 3881 port->mp.mpi = NULL; 3882 3883 spin_unlock(&port->mp.mpi_lock); 3884 3885 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3886 3887 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3888 /* Log an error, still needed to cleanup the pointers and add 3889 * it back to the list. 3890 */ 3891 if (err) 3892 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3893 port_num + 1); 3894 3895 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3896 } 3897 3898 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3899 struct mlx5_ib_multiport_info *mpi) 3900 { 3901 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3902 u64 key; 3903 int err; 3904 3905 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3906 3907 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3908 if (ibdev->port[port_num].mp.mpi) { 3909 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3910 port_num + 1); 3911 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3912 return false; 3913 } 3914 3915 ibdev->port[port_num].mp.mpi = mpi; 3916 mpi->ibdev = ibdev; 3917 mpi->mdev_events.notifier_call = NULL; 3918 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3919 3920 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3921 if (err) 3922 goto unbind; 3923 3924 mlx5_mdev_netdev_track(ibdev, port_num); 3925 3926 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3927 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3928 3929 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3930 3931 key = mpi->mdev->priv.adev_idx; 3932 mlx5_core_mp_event_replay(mpi->mdev, 3933 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3934 &key); 3935 mlx5_core_mp_event_replay(ibdev->mdev, 3936 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3937 &key); 3938 3939 err = mlx5_ib_enable_lb_mp(ibdev->mdev, mpi->mdev, &ibdev->lb); 3940 if (err) 3941 goto unbind; 3942 3943 return true; 3944 3945 unbind: 3946 mlx5_ib_unbind_slave_port(ibdev, mpi); 3947 return false; 3948 } 3949 3950 static int mlx5_ib_data_direct_event(struct notifier_block *nb, 3951 unsigned long action, void *data) 3952 { 3953 struct mlx5_ib_dev *dev = 3954 container_of(nb, struct mlx5_ib_dev, data_direct_nb); 3955 3956 if (action != MLX5_DATA_DIRECT_UNBIND) 3957 return NOTIFY_DONE; 3958 3959 mutex_lock(&dev->data_direct_lock); 3960 mlx5_ib_revoke_data_direct_mrs(dev); 3961 mutex_unlock(&dev->data_direct_lock); 3962 3963 return NOTIFY_OK; 3964 } 3965 3966 static int mlx5_ib_data_direct_init(struct mlx5_ib_dev *dev) 3967 { 3968 int ret; 3969 3970 if (!mlx5_data_direct_supported(dev->mdev)) 3971 return 0; 3972 3973 INIT_LIST_HEAD(&dev->data_direct_mr_list); 3974 dev->data_direct_nb.notifier_call = mlx5_ib_data_direct_event; 3975 ret = mlx5_data_direct_register(dev->mdev, &dev->data_direct_nb); 3976 3977 return ret; 3978 } 3979 3980 static void mlx5_ib_data_direct_cleanup(struct mlx5_ib_dev *dev) 3981 { 3982 if (!mlx5_data_direct_supported(dev->mdev)) 3983 return; 3984 3985 mlx5_data_direct_unregister(dev->mdev, &dev->data_direct_nb); 3986 } 3987 3988 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3989 { 3990 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3991 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3992 port_num + 1); 3993 struct mlx5_ib_multiport_info *mpi; 3994 int err; 3995 u32 i; 3996 3997 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3998 return 0; 3999 4000 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 4001 &dev->sys_image_guid); 4002 if (err) 4003 return err; 4004 4005 err = mlx5_nic_vport_enable_roce(dev->mdev); 4006 if (err) 4007 return err; 4008 4009 mutex_lock(&mlx5_ib_multiport_mutex); 4010 for (i = 0; i < dev->num_ports; i++) { 4011 bool bound = false; 4012 4013 /* build a stub multiport info struct for the native port. */ 4014 if (i == port_num) { 4015 mpi = kzalloc_obj(*mpi); 4016 if (!mpi) { 4017 mutex_unlock(&mlx5_ib_multiport_mutex); 4018 mlx5_nic_vport_disable_roce(dev->mdev); 4019 return -ENOMEM; 4020 } 4021 4022 mpi->is_master = true; 4023 mpi->mdev = dev->mdev; 4024 mpi->sys_image_guid = dev->sys_image_guid; 4025 dev->port[i].mp.mpi = mpi; 4026 mpi->ibdev = dev; 4027 mpi = NULL; 4028 continue; 4029 } 4030 4031 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 4032 list) { 4033 if (dev->sys_image_guid == mpi->sys_image_guid && 4034 (mlx5_core_native_port_num(mpi->mdev) - 1) == i && 4035 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) { 4036 bound = mlx5_ib_bind_slave_port(dev, mpi); 4037 } 4038 4039 if (bound) { 4040 dev_dbg(mpi->mdev->device, 4041 "removing port from unaffiliated list.\n"); 4042 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 4043 list_del(&mpi->list); 4044 break; 4045 } 4046 } 4047 if (!bound) 4048 mlx5_ib_dbg(dev, "no free port found for port %d\n", 4049 i + 1); 4050 } 4051 4052 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 4053 mutex_unlock(&mlx5_ib_multiport_mutex); 4054 return err; 4055 } 4056 4057 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 4058 { 4059 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4060 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 4061 port_num + 1); 4062 u32 i; 4063 4064 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 4065 return; 4066 4067 mutex_lock(&mlx5_ib_multiport_mutex); 4068 for (i = 0; i < dev->num_ports; i++) { 4069 if (dev->port[i].mp.mpi) { 4070 /* Destroy the native port stub */ 4071 if (i == port_num) { 4072 kfree(dev->port[i].mp.mpi); 4073 dev->port[i].mp.mpi = NULL; 4074 } else { 4075 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 4076 i + 1); 4077 list_add_tail(&dev->port[i].mp.mpi->list, 4078 &mlx5_ib_unaffiliated_port_list); 4079 mlx5_ib_unbind_slave_port(dev, 4080 dev->port[i].mp.mpi); 4081 } 4082 } 4083 } 4084 4085 mlx5_ib_dbg(dev, "removing from devlist\n"); 4086 list_del(&dev->ib_dev_list); 4087 mutex_unlock(&mlx5_ib_multiport_mutex); 4088 4089 mlx5_nic_vport_disable_roce(dev->mdev); 4090 } 4091 4092 static int mmap_obj_cleanup(struct ib_uobject *uobject, 4093 enum rdma_remove_reason why, 4094 struct uverbs_attr_bundle *attrs) 4095 { 4096 struct mlx5_user_mmap_entry *obj = uobject->object; 4097 4098 rdma_user_mmap_entry_remove(&obj->rdma_entry); 4099 return 0; 4100 } 4101 4102 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 4103 struct mlx5_user_mmap_entry *entry, 4104 size_t length) 4105 { 4106 return rdma_user_mmap_entry_insert_range( 4107 &c->ibucontext, &entry->rdma_entry, length, 4108 (MLX5_IB_MMAP_OFFSET_START << 16), 4109 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 4110 } 4111 4112 static struct mlx5_user_mmap_entry * 4113 alloc_var_entry(struct mlx5_ib_ucontext *c, u32 flags) 4114 { 4115 struct mlx5_user_mmap_entry *entry; 4116 struct mlx5_var_region *var_region; 4117 struct mlx5_var_table *var_table; 4118 u32 page_idx; 4119 int err; 4120 4121 var_table = &to_mdev(c->ibucontext.device)->var_table; 4122 if (flags & MLX5_IB_UAPI_VAR_ALLOC_FLAG_TLP) 4123 var_region = &var_table->tlp_var_region; 4124 else 4125 var_region = &var_table->var_region; 4126 4127 entry = kzalloc_obj(*entry); 4128 if (!entry) 4129 return ERR_PTR(-ENOMEM); 4130 4131 mutex_lock(&var_region->bitmap_lock); 4132 page_idx = find_first_zero_bit(var_region->bitmap, 4133 var_region->num_var_hw_entries); 4134 if (page_idx >= var_region->num_var_hw_entries) { 4135 err = -ENOSPC; 4136 mutex_unlock(&var_region->bitmap_lock); 4137 goto end; 4138 } 4139 4140 set_bit(page_idx, var_region->bitmap); 4141 mutex_unlock(&var_region->bitmap_lock); 4142 4143 entry->address = var_region->hw_start_addr + 4144 (page_idx * var_region->stride_size); 4145 entry->page_idx = page_idx; 4146 entry->mmap_flag = flags & MLX5_IB_UAPI_VAR_ALLOC_FLAG_TLP ? 4147 MLX5_IB_MMAP_TYPE_TLP_VAR : 4148 MLX5_IB_MMAP_TYPE_VAR; 4149 4150 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 4151 var_region->stride_size); 4152 if (err) 4153 goto err_insert; 4154 4155 return entry; 4156 4157 err_insert: 4158 mutex_lock(&var_region->bitmap_lock); 4159 clear_bit(page_idx, var_region->bitmap); 4160 mutex_unlock(&var_region->bitmap_lock); 4161 end: 4162 kfree(entry); 4163 return ERR_PTR(err); 4164 } 4165 4166 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 4167 struct uverbs_attr_bundle *attrs) 4168 { 4169 struct ib_uobject *uobj = uverbs_attr_get_uobject( 4170 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 4171 struct mlx5_user_mmap_entry *entry; 4172 struct mlx5_ib_ucontext *c; 4173 u64 mmap_offset; 4174 u32 flags = 0; 4175 u32 length; 4176 int err; 4177 4178 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 4179 if (IS_ERR(c)) 4180 return PTR_ERR(c); 4181 4182 err = uverbs_get_flags32(&flags, attrs, 4183 MLX5_IB_ATTR_VAR_OBJ_ALLOC_FLAGS, 4184 MLX5_IB_UAPI_VAR_ALLOC_FLAG_TLP); 4185 if (err) 4186 return err; 4187 4188 if (flags & MLX5_IB_UAPI_VAR_ALLOC_FLAG_TLP) { 4189 if (!MLX5_CAP_GEN(to_mdev(c->ibucontext.device)->mdev, 4190 tlp_device_emulation_manager)) 4191 return -EOPNOTSUPP; 4192 } else { 4193 if (!(MLX5_CAP_GEN_64(to_mdev(c->ibucontext.device)->mdev, 4194 general_obj_types) & 4195 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q)) 4196 return -EOPNOTSUPP; 4197 } 4198 4199 entry = alloc_var_entry(c, flags); 4200 if (IS_ERR(entry)) 4201 return PTR_ERR(entry); 4202 4203 mmap_offset = mlx5_entry_to_mmap_offset(entry); 4204 length = entry->rdma_entry.npages * PAGE_SIZE; 4205 uobj->object = entry; 4206 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 4207 4208 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 4209 &mmap_offset, sizeof(mmap_offset)); 4210 if (err) 4211 return err; 4212 4213 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 4214 &entry->page_idx, sizeof(entry->page_idx)); 4215 if (err) 4216 return err; 4217 4218 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 4219 &length, sizeof(length)); 4220 return err; 4221 } 4222 4223 DECLARE_UVERBS_NAMED_METHOD( 4224 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 4225 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 4226 MLX5_IB_OBJECT_VAR, 4227 UVERBS_ACCESS_NEW, 4228 UA_MANDATORY), 4229 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_VAR_OBJ_ALLOC_FLAGS, 4230 enum mlx5_ib_uapi_var_alloc_flags, 4231 UA_OPTIONAL), 4232 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 4233 UVERBS_ATTR_TYPE(u32), 4234 UA_MANDATORY), 4235 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 4236 UVERBS_ATTR_TYPE(u32), 4237 UA_MANDATORY), 4238 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 4239 UVERBS_ATTR_TYPE(u64), 4240 UA_MANDATORY)); 4241 4242 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 4243 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 4244 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 4245 MLX5_IB_OBJECT_VAR, 4246 UVERBS_ACCESS_DESTROY, 4247 UA_MANDATORY)); 4248 4249 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 4250 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 4251 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 4252 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 4253 4254 static bool var_is_supported(struct ib_device *device) 4255 { 4256 struct mlx5_ib_dev *dev = to_mdev(device); 4257 4258 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4259 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) || 4260 MLX5_CAP_GEN(dev->mdev, tlp_device_emulation_manager); 4261 } 4262 4263 static struct mlx5_user_mmap_entry * 4264 alloc_uar_entry(struct mlx5_ib_ucontext *c, 4265 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 4266 { 4267 struct mlx5_user_mmap_entry *entry; 4268 struct mlx5_ib_dev *dev; 4269 u32 uar_index; 4270 int err; 4271 4272 entry = kzalloc_obj(*entry); 4273 if (!entry) 4274 return ERR_PTR(-ENOMEM); 4275 4276 dev = to_mdev(c->ibucontext.device); 4277 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 4278 if (err) 4279 goto end; 4280 4281 entry->page_idx = uar_index; 4282 entry->address = uar_index2paddress(dev, uar_index); 4283 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 4284 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 4285 else 4286 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 4287 4288 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 4289 if (err) 4290 goto err_insert; 4291 4292 return entry; 4293 4294 err_insert: 4295 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 4296 end: 4297 kfree(entry); 4298 return ERR_PTR(err); 4299 } 4300 4301 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 4302 struct uverbs_attr_bundle *attrs) 4303 { 4304 struct ib_uobject *uobj = uverbs_attr_get_uobject( 4305 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 4306 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 4307 struct mlx5_ib_ucontext *c; 4308 struct mlx5_user_mmap_entry *entry; 4309 u64 mmap_offset; 4310 u32 length; 4311 int err; 4312 4313 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 4314 if (IS_ERR(c)) 4315 return PTR_ERR(c); 4316 4317 err = uverbs_get_const(&alloc_type, attrs, 4318 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 4319 if (err) 4320 return err; 4321 4322 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 4323 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 4324 return -EOPNOTSUPP; 4325 4326 if (!mlx5_wc_support_get(to_mdev(c->ibucontext.device)->mdev) && 4327 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 4328 return -EOPNOTSUPP; 4329 4330 entry = alloc_uar_entry(c, alloc_type); 4331 if (IS_ERR(entry)) 4332 return PTR_ERR(entry); 4333 4334 mmap_offset = mlx5_entry_to_mmap_offset(entry); 4335 length = entry->rdma_entry.npages * PAGE_SIZE; 4336 uobj->object = entry; 4337 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 4338 4339 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 4340 &mmap_offset, sizeof(mmap_offset)); 4341 if (err) 4342 return err; 4343 4344 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 4345 &entry->page_idx, sizeof(entry->page_idx)); 4346 if (err) 4347 return err; 4348 4349 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 4350 &length, sizeof(length)); 4351 return err; 4352 } 4353 4354 DECLARE_UVERBS_NAMED_METHOD( 4355 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 4356 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 4357 MLX5_IB_OBJECT_UAR, 4358 UVERBS_ACCESS_NEW, 4359 UA_MANDATORY), 4360 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 4361 enum mlx5_ib_uapi_uar_alloc_type, 4362 UA_MANDATORY), 4363 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 4364 UVERBS_ATTR_TYPE(u32), 4365 UA_MANDATORY), 4366 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 4367 UVERBS_ATTR_TYPE(u32), 4368 UA_MANDATORY), 4369 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 4370 UVERBS_ATTR_TYPE(u64), 4371 UA_MANDATORY)); 4372 4373 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 4374 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 4375 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 4376 MLX5_IB_OBJECT_UAR, 4377 UVERBS_ACCESS_DESTROY, 4378 UA_MANDATORY)); 4379 4380 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 4381 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 4382 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 4383 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 4384 4385 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4386 mlx5_ib_query_context, 4387 UVERBS_OBJECT_DEVICE, 4388 UVERBS_METHOD_QUERY_CONTEXT, 4389 UVERBS_ATTR_PTR_OUT( 4390 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 4391 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 4392 dump_fill_mkey), 4393 UA_MANDATORY)); 4394 4395 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4396 mlx5_ib_reg_dmabuf_mr, 4397 UVERBS_OBJECT_MR, 4398 UVERBS_METHOD_REG_DMABUF_MR, 4399 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_REG_DMABUF_MR_ACCESS_FLAGS, 4400 enum mlx5_ib_uapi_reg_dmabuf_flags, 4401 UA_OPTIONAL)); 4402 4403 static const struct uapi_definition mlx5_ib_defs[] = { 4404 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 4405 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 4406 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 4407 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 4408 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 4409 UAPI_DEF_CHAIN(mlx5_ib_create_cq_defs), 4410 UAPI_DEF_CHAIN(mlx5_ib_create_qp_defs), 4411 UAPI_DEF_CHAIN(mlx5_ib_create_srq_defs), 4412 4413 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 4414 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_MR, &mlx5_ib_reg_dmabuf_mr), 4415 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 4416 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 4417 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 4418 {} 4419 }; 4420 4421 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 4422 { 4423 mlx5_cmd_cleanup_async_ctx(&dev->async_ctx); 4424 mlx5_ib_data_direct_cleanup(dev); 4425 mlx5_ib_cleanup_multiport_master(dev); 4426 WARN_ON(!xa_empty(&dev->odp_mkeys)); 4427 mutex_destroy(&dev->cap_mask_mutex); 4428 WARN_ON(!xa_empty(&dev->sig_mrs)); 4429 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 4430 mlx5r_macsec_dealloc_gids(dev); 4431 } 4432 4433 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 4434 { 4435 struct mlx5_core_dev *mdev = dev->mdev; 4436 int err, i; 4437 4438 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 4439 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 4440 dev->ib_dev.dev.parent = mdev->device; 4441 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 4442 4443 for (i = 0; i < dev->num_ports; i++) { 4444 spin_lock_init(&dev->port[i].mp.mpi_lock); 4445 dev->port[i].roce.dev = dev; 4446 dev->port[i].roce.native_port_num = i + 1; 4447 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 4448 } 4449 4450 mutex_init(&dev->lb.mutex); 4451 4452 err = mlx5r_cmd_query_special_mkeys(dev); 4453 if (err) 4454 return err; 4455 4456 err = mlx5r_macsec_init_gids_and_devlist(dev); 4457 if (err) 4458 return err; 4459 4460 err = mlx5_ib_init_multiport_master(dev); 4461 if (err) 4462 goto err; 4463 4464 err = set_has_smi_cap(dev); 4465 if (err) 4466 goto err_mp; 4467 4468 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 4469 if (err) 4470 goto err_mp; 4471 4472 if (mlx5_use_mad_ifc(dev)) 4473 get_ext_port_caps(dev); 4474 4475 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_max(mdev); 4476 4477 mutex_init(&dev->cap_mask_mutex); 4478 mutex_init(&dev->data_direct_lock); 4479 INIT_LIST_HEAD(&dev->qp_list); 4480 spin_lock_init(&dev->reset_flow_resource_lock); 4481 xa_init(&dev->odp_mkeys); 4482 xa_init(&dev->sig_mrs); 4483 atomic_set(&dev->mkey_var, 0); 4484 4485 spin_lock_init(&dev->dm.lock); 4486 dev->dm.dev = mdev; 4487 err = mlx5_ib_data_direct_init(dev); 4488 if (err) 4489 goto err_mp; 4490 4491 err = pcim_p2pdma_init(mdev->pdev); 4492 if (err && err != -EOPNOTSUPP) 4493 goto err_dd; 4494 4495 mlx5_cmd_init_async_ctx(mdev, &dev->async_ctx); 4496 4497 return 0; 4498 err_dd: 4499 mlx5_ib_data_direct_cleanup(dev); 4500 err_mp: 4501 mlx5_ib_cleanup_multiport_master(dev); 4502 err: 4503 mlx5r_macsec_dealloc_gids(dev); 4504 return err; 4505 } 4506 4507 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 4508 enum rdma_nl_dev_type type, 4509 const char *name); 4510 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev); 4511 4512 static const struct ib_device_ops mlx5_ib_dev_ops = { 4513 .owner = THIS_MODULE, 4514 .driver_id = RDMA_DRIVER_MLX5, 4515 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 4516 4517 .add_gid = mlx5_ib_add_gid, 4518 .add_sub_dev = mlx5_ib_add_sub_dev, 4519 .alloc_mr = mlx5_ib_alloc_mr, 4520 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 4521 .alloc_pd = mlx5_ib_alloc_pd, 4522 .alloc_ucontext = mlx5_ib_alloc_ucontext, 4523 .attach_mcast = mlx5_ib_mcg_attach, 4524 .check_mr_status = mlx5_ib_check_mr_status, 4525 .create_ah = mlx5_ib_create_ah, 4526 .create_cq = mlx5_ib_create_cq, 4527 .create_user_cq = mlx5_ib_create_user_cq, 4528 .create_qp = mlx5_ib_create_qp, 4529 .create_srq = mlx5_ib_create_srq, 4530 .create_user_ah = mlx5_ib_create_ah, 4531 .dealloc_pd = mlx5_ib_dealloc_pd, 4532 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 4533 .del_gid = mlx5_ib_del_gid, 4534 .del_sub_dev = mlx5_ib_del_sub_dev, 4535 .dereg_mr = mlx5_ib_dereg_mr, 4536 .destroy_ah = mlx5_ib_destroy_ah, 4537 .destroy_cq = mlx5_ib_destroy_cq, 4538 .destroy_qp = mlx5_ib_destroy_qp, 4539 .destroy_srq = mlx5_ib_destroy_srq, 4540 .detach_mcast = mlx5_ib_mcg_detach, 4541 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 4542 .drain_rq = mlx5_ib_drain_rq, 4543 .drain_sq = mlx5_ib_drain_sq, 4544 .device_group = &mlx5_attr_group, 4545 .get_dev_fw_str = get_dev_fw_str, 4546 .get_dma_mr = mlx5_ib_get_dma_mr, 4547 .get_link_layer = mlx5_ib_port_link_layer, 4548 .map_mr_sg = mlx5_ib_map_mr_sg, 4549 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 4550 .mmap = mlx5_ib_mmap, 4551 .mmap_free = mlx5_ib_mmap_free, 4552 .mmap_get_pfns = mlx5_ib_mmap_get_pfns, 4553 .modify_cq = mlx5_ib_modify_cq, 4554 .modify_device = mlx5_ib_modify_device, 4555 .modify_port = mlx5_ib_modify_port, 4556 .modify_qp = mlx5_ib_modify_qp, 4557 .modify_srq = mlx5_ib_modify_srq, 4558 .pgoff_to_mmap_entry = mlx5_ib_pgoff_to_mmap_entry, 4559 .pre_destroy_cq = mlx5_ib_pre_destroy_cq, 4560 .poll_cq = mlx5_ib_poll_cq, 4561 .post_destroy_cq = mlx5_ib_post_destroy_cq, 4562 .post_recv = mlx5_ib_post_recv_nodrain, 4563 .post_send = mlx5_ib_post_send_nodrain, 4564 .post_srq_recv = mlx5_ib_post_srq_recv, 4565 .process_mad = mlx5_ib_process_mad, 4566 .query_ah = mlx5_ib_query_ah, 4567 .query_device = mlx5_ib_query_device, 4568 .query_gid = mlx5_ib_query_gid, 4569 .query_pkey = mlx5_ib_query_pkey, 4570 .query_port_speed = mlx5_ib_query_port_speed, 4571 .query_qp = mlx5_ib_query_qp, 4572 .query_srq = mlx5_ib_query_srq, 4573 .query_ucontext = mlx5_ib_query_ucontext, 4574 .reg_user_mr = mlx5_ib_reg_user_mr, 4575 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 4576 .req_notify_cq = mlx5_ib_arm_cq, 4577 .rereg_user_mr = mlx5_ib_rereg_user_mr, 4578 .resize_user_cq = mlx5_ib_resize_cq, 4579 .ufile_hw_cleanup = mlx5_ib_ufile_hw_cleanup, 4580 4581 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 4582 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 4583 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 4584 INIT_RDMA_OBJ_SIZE(ib_dmah, mlx5_ib_dmah, ibdmah), 4585 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 4586 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 4587 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 4588 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 4589 }; 4590 4591 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 4592 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 4593 }; 4594 4595 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 4596 .get_vf_config = mlx5_ib_get_vf_config, 4597 .get_vf_guid = mlx5_ib_get_vf_guid, 4598 .get_vf_stats = mlx5_ib_get_vf_stats, 4599 .set_vf_guid = mlx5_ib_set_vf_guid, 4600 .set_vf_link_state = mlx5_ib_set_vf_link_state, 4601 }; 4602 4603 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 4604 .alloc_mw = mlx5_ib_alloc_mw, 4605 .dealloc_mw = mlx5_ib_dealloc_mw, 4606 4607 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 4608 }; 4609 4610 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 4611 .alloc_xrcd = mlx5_ib_alloc_xrcd, 4612 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 4613 4614 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 4615 }; 4616 4617 static int mlx5_ib_init_var_region(struct mlx5_ib_dev *dev) 4618 { 4619 struct mlx5_var_region *var_region = &dev->var_table.var_region; 4620 struct mlx5_core_dev *mdev = dev->mdev; 4621 u8 log_doorbell_bar_size; 4622 u8 log_doorbell_stride; 4623 u64 bar_size; 4624 4625 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4626 log_doorbell_bar_size); 4627 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4628 log_doorbell_stride); 4629 var_region->hw_start_addr = dev->mdev->bar_addr + 4630 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 4631 doorbell_bar_offset); 4632 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 4633 var_region->stride_size = 1ULL << log_doorbell_stride; 4634 var_region->num_var_hw_entries = div_u64(bar_size, 4635 var_region->stride_size); 4636 mutex_init(&var_region->bitmap_lock); 4637 var_region->bitmap = bitmap_zalloc(var_region->num_var_hw_entries, 4638 GFP_KERNEL); 4639 return (var_region->bitmap) ? 0 : -ENOMEM; 4640 } 4641 4642 static int mlx5_ib_init_tlp_var_region(struct mlx5_ib_dev *dev) 4643 { 4644 struct mlx5_var_region *var_region = &dev->var_table.tlp_var_region; 4645 struct mlx5_core_dev *mdev = dev->mdev; 4646 u8 log_tlp_var_stride; 4647 4648 log_tlp_var_stride = 4649 MLX5_CAP_DEV_TLP_EMULATION(mdev, log_tlp_rsp_gw_page_stride); 4650 var_region->hw_start_addr = 4651 dev->mdev->bar_addr + 4652 MLX5_CAP64_DEV_TLP_EMULATION(mdev, tlp_rsp_gw_pages_bar_offset); 4653 4654 var_region->stride_size = (1ULL << log_tlp_var_stride) * 4096; 4655 var_region->num_var_hw_entries = 4656 MLX5_CAP_DEV_TLP_EMULATION(mdev, tlp_rsp_gw_num_pages); 4657 4658 mutex_init(&var_region->bitmap_lock); 4659 var_region->bitmap = bitmap_zalloc(var_region->num_var_hw_entries, 4660 GFP_KERNEL); 4661 return (var_region->bitmap) ? 0 : -ENOMEM; 4662 } 4663 4664 static void mlx5_ib_cleanup_ucaps(struct mlx5_ib_dev *dev) 4665 { 4666 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4667 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4668 4669 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4670 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) 4671 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4672 } 4673 4674 static int mlx5_ib_init_ucaps(struct mlx5_ib_dev *dev) 4675 { 4676 int ret; 4677 4678 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) { 4679 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4680 if (ret) 4681 return ret; 4682 } 4683 4684 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4685 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) { 4686 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4687 if (ret) 4688 goto remove_local; 4689 } 4690 4691 return 0; 4692 4693 remove_local: 4694 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4695 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4696 return ret; 4697 } 4698 4699 static void mlx5_ib_cleanup_var_table(struct mlx5_ib_dev *dev) 4700 { 4701 bitmap_free(dev->var_table.var_region.bitmap); 4702 bitmap_free(dev->var_table.tlp_var_region.bitmap); 4703 } 4704 4705 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 4706 { 4707 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4708 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) 4709 mlx5_ib_cleanup_ucaps(dev); 4710 4711 mlx5_ib_cleanup_var_table(dev); 4712 } 4713 4714 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4715 { 4716 struct mlx5_core_dev *mdev = dev->mdev; 4717 int err; 4718 4719 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 4720 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 4721 ib_set_device_ops(&dev->ib_dev, 4722 &mlx5_ib_dev_ipoib_enhanced_ops); 4723 4724 if (mlx5_core_is_pf(mdev)) 4725 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 4726 4727 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4728 4729 if (MLX5_CAP_GEN(mdev, imaicl)) 4730 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 4731 4732 if (MLX5_CAP_GEN(mdev, xrc)) 4733 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 4734 4735 if (MLX5_CAP_DEV_MEM(mdev, memic) || 4736 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4737 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 4738 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 4739 4740 if (mdev->st) 4741 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dmah_ops); 4742 4743 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 4744 4745 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 4746 dev->ib_dev.driver_def = mlx5_ib_defs; 4747 4748 err = init_node_data(dev); 4749 if (err) 4750 return err; 4751 4752 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4753 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 4754 err = mlx5_ib_init_var_region(dev); 4755 if (err) 4756 return err; 4757 } 4758 4759 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4760 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) { 4761 err = mlx5_ib_init_ucaps(dev); 4762 if (err) 4763 goto err_ucaps; 4764 } 4765 4766 if (MLX5_CAP_GEN(dev->mdev, tlp_device_emulation_manager)) { 4767 err = mlx5_ib_init_tlp_var_region(dev); 4768 if (err) 4769 goto err_tlp_var; 4770 } 4771 4772 dev->ib_dev.use_cq_dim = true; 4773 4774 return 0; 4775 4776 err_tlp_var: 4777 mlx5_ib_cleanup_ucaps(dev); 4778 err_ucaps: 4779 bitmap_free(dev->var_table.var_region.bitmap); 4780 return err; 4781 } 4782 4783 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 4784 .get_port_immutable = mlx5_port_immutable, 4785 .query_port = mlx5_ib_query_port, 4786 }; 4787 4788 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4789 { 4790 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 4791 return 0; 4792 } 4793 4794 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 4795 .get_port_immutable = mlx5_port_rep_immutable, 4796 .query_port = mlx5_ib_rep_query_port, 4797 .query_pkey = mlx5_ib_rep_query_pkey, 4798 }; 4799 4800 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 4801 { 4802 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 4803 return 0; 4804 } 4805 4806 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 4807 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 4808 .create_wq = mlx5_ib_create_wq, 4809 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 4810 .destroy_wq = mlx5_ib_destroy_wq, 4811 .modify_wq = mlx5_ib_modify_wq, 4812 4813 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 4814 ib_rwq_ind_tbl), 4815 }; 4816 4817 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4818 { 4819 struct mlx5_core_dev *mdev = dev->mdev; 4820 enum rdma_link_layer ll; 4821 int port_type_cap; 4822 u32 port_num = 0; 4823 int err; 4824 4825 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4826 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4827 4828 if (ll == IB_LINK_LAYER_ETHERNET) { 4829 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4830 4831 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4832 4833 /* Register only for native ports */ 4834 mlx5_mdev_netdev_track(dev, port_num); 4835 4836 err = mlx5_enable_eth(dev); 4837 if (err) 4838 goto cleanup; 4839 } 4840 4841 return 0; 4842 cleanup: 4843 mlx5_mdev_netdev_untrack(dev, port_num); 4844 return err; 4845 } 4846 4847 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4848 { 4849 struct mlx5_core_dev *mdev = dev->mdev; 4850 enum rdma_link_layer ll; 4851 int port_type_cap; 4852 u32 port_num; 4853 4854 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4855 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4856 4857 if (ll == IB_LINK_LAYER_ETHERNET) { 4858 mlx5_disable_eth(dev); 4859 4860 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4861 mlx5_mdev_netdev_untrack(dev, port_num); 4862 } 4863 } 4864 4865 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4866 { 4867 mlx5_ib_init_cong_debugfs(dev, 4868 mlx5_core_native_port_num(dev->mdev) - 1); 4869 return 0; 4870 } 4871 4872 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4873 { 4874 mlx5_ib_cleanup_cong_debugfs(dev, 4875 mlx5_core_native_port_num(dev->mdev) - 1); 4876 } 4877 4878 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4879 { 4880 int err; 4881 4882 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4883 if (err) 4884 return err; 4885 4886 if (MLX5_CAP_GEN(dev->mdev, qp_latency_sensitive_disable)) 4887 return 0; 4888 4889 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4890 if (err) 4891 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4892 4893 return err; 4894 } 4895 4896 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4897 { 4898 if (!MLX5_CAP_GEN(dev->mdev, qp_latency_sensitive_disable)) 4899 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4900 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4901 } 4902 4903 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4904 { 4905 const char *name; 4906 4907 if (dev->sub_dev_name) { 4908 name = dev->sub_dev_name; 4909 ib_mark_name_assigned_by_user(&dev->ib_dev); 4910 } else if (!mlx5_lag_is_active(dev->mdev)) 4911 name = "mlx5_%d"; 4912 else 4913 name = "mlx5_bond_%d"; 4914 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4915 } 4916 4917 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4918 { 4919 mlx5r_frmr_pools_cleanup(&dev->ib_dev); 4920 mlx5r_umr_resource_cleanup(dev); 4921 mlx5r_umr_cleanup(dev); 4922 } 4923 4924 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4925 { 4926 ib_unregister_device(&dev->ib_dev); 4927 } 4928 4929 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4930 { 4931 int ret; 4932 4933 ret = mlx5r_umr_init(dev); 4934 if (ret) 4935 return ret; 4936 4937 ret = mlx5r_frmr_pools_init(&dev->ib_dev); 4938 if (ret) 4939 mlx5_ib_warn(dev, "frmr pools init failed %d\n", ret); 4940 4941 return ret; 4942 } 4943 4944 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4945 { 4946 struct dentry *root; 4947 4948 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4949 return 0; 4950 4951 mutex_init(&dev->delay_drop.lock); 4952 dev->delay_drop.dev = dev; 4953 dev->delay_drop.activate = false; 4954 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4955 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4956 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4957 atomic_set(&dev->delay_drop.events_cnt, 0); 4958 4959 if (!mlx5_debugfs_root) 4960 return 0; 4961 4962 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 4963 dev->delay_drop.dir_debugfs = root; 4964 4965 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4966 &dev->delay_drop.events_cnt); 4967 debugfs_create_atomic_t("num_rqs", 0400, root, 4968 &dev->delay_drop.rqs_cnt); 4969 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4970 &fops_delay_drop_timeout); 4971 return 0; 4972 } 4973 4974 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4975 { 4976 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4977 return; 4978 4979 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4980 if (!dev->delay_drop.dir_debugfs) 4981 return; 4982 4983 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4984 dev->delay_drop.dir_debugfs = NULL; 4985 } 4986 4987 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4988 { 4989 struct mlx5_ib_resources *devr = &dev->devr; 4990 int port; 4991 4992 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 4993 INIT_WORK(&devr->ports[port].pkey_change_work, 4994 pkey_change_handler); 4995 4996 dev->mdev_events.notifier_call = mlx5_ib_event; 4997 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4998 4999 mlx5r_macsec_event_register(dev); 5000 5001 return 0; 5002 } 5003 5004 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 5005 { 5006 struct mlx5_ib_resources *devr = &dev->devr; 5007 int port; 5008 5009 mlx5r_macsec_event_unregister(dev); 5010 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 5011 5012 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 5013 cancel_work_sync(&devr->ports[port].pkey_change_work); 5014 } 5015 5016 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 5017 const struct mlx5_ib_profile *profile, 5018 int stage) 5019 { 5020 dev->ib_active = false; 5021 5022 /* Number of stages to cleanup */ 5023 while (stage) { 5024 stage--; 5025 if (profile->stage[stage].cleanup) 5026 profile->stage[stage].cleanup(dev); 5027 } 5028 5029 kfree(dev->port); 5030 ib_dealloc_device(&dev->ib_dev); 5031 } 5032 5033 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 5034 const struct mlx5_ib_profile *profile) 5035 { 5036 int err; 5037 int i; 5038 5039 dev->profile = profile; 5040 5041 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 5042 if (profile->stage[i].init) { 5043 err = profile->stage[i].init(dev); 5044 if (err) 5045 goto err_out; 5046 } 5047 } 5048 5049 dev->ib_active = true; 5050 return 0; 5051 5052 err_out: 5053 /* Clean up stages which were initialized */ 5054 while (i) { 5055 i--; 5056 if (profile->stage[i].cleanup) 5057 profile->stage[i].cleanup(dev); 5058 } 5059 return err; 5060 } 5061 5062 static const struct mlx5_ib_profile pf_profile = { 5063 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5064 mlx5_ib_stage_init_init, 5065 mlx5_ib_stage_init_cleanup), 5066 STAGE_CREATE(MLX5_IB_STAGE_FS, 5067 mlx5_ib_fs_init, 5068 mlx5_ib_fs_cleanup), 5069 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5070 mlx5_ib_stage_caps_init, 5071 mlx5_ib_stage_caps_cleanup), 5072 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5073 mlx5_ib_stage_non_default_cb, 5074 NULL), 5075 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 5076 mlx5_ib_roce_init, 5077 mlx5_ib_roce_cleanup), 5078 STAGE_CREATE(MLX5_IB_STAGE_QP, 5079 mlx5_init_qp_table, 5080 mlx5_cleanup_qp_table), 5081 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 5082 mlx5_init_srq_table, 5083 mlx5_cleanup_srq_table), 5084 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5085 mlx5_ib_dev_res_init, 5086 mlx5_ib_dev_res_cleanup), 5087 STAGE_CREATE(MLX5_IB_STAGE_ODP, 5088 mlx5_ib_odp_init_one, 5089 mlx5_ib_odp_cleanup_one), 5090 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 5091 mlx5_ib_counters_init, 5092 mlx5_ib_counters_cleanup), 5093 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 5094 mlx5_ib_stage_cong_debugfs_init, 5095 mlx5_ib_stage_cong_debugfs_cleanup), 5096 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5097 mlx5_ib_stage_bfrag_init, 5098 mlx5_ib_stage_bfrag_cleanup), 5099 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 5100 NULL, 5101 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 5102 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 5103 mlx5_ib_devx_init, 5104 mlx5_ib_devx_cleanup), 5105 STAGE_CREATE(MLX5_IB_STAGE_SYS_ERROR_NOTIFIER, 5106 mlx5_ib_stage_sys_error_notifier_init, 5107 mlx5_ib_stage_sys_error_notifier_cleanup), 5108 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5109 mlx5_ib_stage_ib_reg_init, 5110 mlx5_ib_stage_ib_reg_cleanup), 5111 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 5112 mlx5_ib_stage_dev_notifier_init, 5113 mlx5_ib_stage_dev_notifier_cleanup), 5114 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 5115 mlx5_ib_stage_post_ib_reg_umr_init, 5116 NULL), 5117 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 5118 mlx5_ib_stage_delay_drop_init, 5119 mlx5_ib_stage_delay_drop_cleanup), 5120 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 5121 mlx5_ib_restrack_init, 5122 NULL), 5123 }; 5124 5125 const struct mlx5_ib_profile raw_eth_profile = { 5126 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5127 mlx5_ib_stage_init_init, 5128 mlx5_ib_stage_init_cleanup), 5129 STAGE_CREATE(MLX5_IB_STAGE_FS, 5130 mlx5_ib_fs_init, 5131 mlx5_ib_fs_cleanup), 5132 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5133 mlx5_ib_stage_caps_init, 5134 mlx5_ib_stage_caps_cleanup), 5135 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5136 mlx5_ib_stage_raw_eth_non_default_cb, 5137 NULL), 5138 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 5139 mlx5_ib_roce_init, 5140 mlx5_ib_roce_cleanup), 5141 STAGE_CREATE(MLX5_IB_STAGE_QP, 5142 mlx5_init_qp_table, 5143 mlx5_cleanup_qp_table), 5144 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 5145 mlx5_init_srq_table, 5146 mlx5_cleanup_srq_table), 5147 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5148 mlx5_ib_dev_res_init, 5149 mlx5_ib_dev_res_cleanup), 5150 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 5151 mlx5_ib_counters_init, 5152 mlx5_ib_counters_cleanup), 5153 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 5154 mlx5_ib_stage_cong_debugfs_init, 5155 mlx5_ib_stage_cong_debugfs_cleanup), 5156 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5157 mlx5_ib_stage_bfrag_init, 5158 mlx5_ib_stage_bfrag_cleanup), 5159 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 5160 NULL, 5161 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 5162 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 5163 mlx5_ib_devx_init, 5164 mlx5_ib_devx_cleanup), 5165 STAGE_CREATE(MLX5_IB_STAGE_SYS_ERROR_NOTIFIER, 5166 mlx5_ib_stage_sys_error_notifier_init, 5167 mlx5_ib_stage_sys_error_notifier_cleanup), 5168 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5169 mlx5_ib_stage_ib_reg_init, 5170 mlx5_ib_stage_ib_reg_cleanup), 5171 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 5172 mlx5_ib_stage_dev_notifier_init, 5173 mlx5_ib_stage_dev_notifier_cleanup), 5174 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 5175 mlx5_ib_stage_post_ib_reg_umr_init, 5176 NULL), 5177 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 5178 mlx5_ib_stage_delay_drop_init, 5179 mlx5_ib_stage_delay_drop_cleanup), 5180 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 5181 mlx5_ib_restrack_init, 5182 NULL), 5183 }; 5184 5185 static const struct mlx5_ib_profile plane_profile = { 5186 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5187 mlx5_ib_stage_init_init, 5188 mlx5_ib_stage_init_cleanup), 5189 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5190 mlx5_ib_stage_caps_init, 5191 mlx5_ib_stage_caps_cleanup), 5192 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5193 mlx5_ib_stage_non_default_cb, 5194 NULL), 5195 STAGE_CREATE(MLX5_IB_STAGE_QP, 5196 mlx5_init_qp_table, 5197 mlx5_cleanup_qp_table), 5198 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 5199 mlx5_init_srq_table, 5200 mlx5_cleanup_srq_table), 5201 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5202 mlx5_ib_dev_res_init, 5203 mlx5_ib_dev_res_cleanup), 5204 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5205 mlx5_ib_stage_bfrag_init, 5206 mlx5_ib_stage_bfrag_cleanup), 5207 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5208 mlx5_ib_stage_ib_reg_init, 5209 mlx5_ib_stage_ib_reg_cleanup), 5210 }; 5211 5212 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 5213 enum rdma_nl_dev_type type, 5214 const char *name) 5215 { 5216 struct mlx5_ib_dev *mparent = to_mdev(parent), *mplane; 5217 enum rdma_link_layer ll; 5218 int ret; 5219 5220 if (mparent->smi_dev) 5221 return ERR_PTR(-EEXIST); 5222 5223 ll = mlx5_port_type_cap_to_rdma_ll(MLX5_CAP_GEN(mparent->mdev, 5224 port_type)); 5225 if (type != RDMA_DEVICE_TYPE_SMI || !mparent->num_plane || 5226 ll != IB_LINK_LAYER_INFINIBAND || 5227 !MLX5_CAP_GEN_2(mparent->mdev, multiplane_qp_ud)) 5228 return ERR_PTR(-EOPNOTSUPP); 5229 5230 mplane = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, 5231 mlx5_core_net(mparent->mdev)); 5232 if (!mplane) 5233 return ERR_PTR(-ENOMEM); 5234 5235 mplane->port = kzalloc_objs(*mplane->port, 5236 mparent->num_plane * mparent->num_ports); 5237 if (!mplane->port) { 5238 ret = -ENOMEM; 5239 goto fail_kcalloc; 5240 } 5241 5242 mplane->ib_dev.type = type; 5243 mplane->mdev = mparent->mdev; 5244 mplane->num_ports = mparent->num_plane; 5245 mplane->sub_dev_name = name; 5246 mplane->ib_dev.phys_port_cnt = mplane->num_ports; 5247 5248 ret = __mlx5_ib_add(mplane, &plane_profile); 5249 if (ret) 5250 goto fail_ib_add; 5251 5252 mparent->smi_dev = mplane; 5253 return &mplane->ib_dev; 5254 5255 fail_ib_add: 5256 kfree(mplane->port); 5257 fail_kcalloc: 5258 ib_dealloc_device(&mplane->ib_dev); 5259 return ERR_PTR(ret); 5260 } 5261 5262 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev) 5263 { 5264 struct mlx5_ib_dev *mdev = to_mdev(sub_dev); 5265 5266 to_mdev(sub_dev->parent)->smi_dev = NULL; 5267 __mlx5_ib_remove(mdev, mdev->profile, MLX5_IB_STAGE_MAX); 5268 } 5269 5270 static int mlx5r_mp_probe(struct auxiliary_device *adev, 5271 const struct auxiliary_device_id *id) 5272 { 5273 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 5274 struct mlx5_core_dev *mdev = idev->mdev; 5275 struct mlx5_ib_multiport_info *mpi; 5276 struct mlx5_ib_dev *dev; 5277 bool bound = false; 5278 int err; 5279 5280 mpi = kzalloc_obj(*mpi); 5281 if (!mpi) 5282 return -ENOMEM; 5283 5284 mpi->mdev = mdev; 5285 err = mlx5_query_nic_vport_system_image_guid(mdev, 5286 &mpi->sys_image_guid); 5287 if (err) { 5288 kfree(mpi); 5289 return err; 5290 } 5291 5292 mutex_lock(&mlx5_ib_multiport_mutex); 5293 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 5294 if (dev->sys_image_guid == mpi->sys_image_guid && 5295 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) 5296 bound = mlx5_ib_bind_slave_port(dev, mpi); 5297 5298 if (bound) { 5299 rdma_roce_rescan_device(&dev->ib_dev); 5300 mpi->ibdev->ib_active = true; 5301 break; 5302 } 5303 } 5304 5305 if (!bound) { 5306 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5307 dev_dbg(mdev->device, 5308 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 5309 } 5310 mutex_unlock(&mlx5_ib_multiport_mutex); 5311 5312 auxiliary_set_drvdata(adev, mpi); 5313 return 0; 5314 } 5315 5316 static void mlx5r_mp_remove(struct auxiliary_device *adev) 5317 { 5318 struct mlx5_ib_multiport_info *mpi; 5319 5320 mpi = auxiliary_get_drvdata(adev); 5321 mutex_lock(&mlx5_ib_multiport_mutex); 5322 if (mpi->ibdev) 5323 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 5324 else 5325 list_del(&mpi->list); 5326 mutex_unlock(&mlx5_ib_multiport_mutex); 5327 kfree(mpi); 5328 } 5329 5330 static int mlx5r_probe(struct auxiliary_device *adev, 5331 const struct auxiliary_device_id *id) 5332 { 5333 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 5334 struct mlx5_core_dev *mdev = idev->mdev; 5335 const struct mlx5_ib_profile *profile; 5336 int port_type_cap, num_ports, ret; 5337 enum rdma_link_layer ll; 5338 struct mlx5_ib_dev *dev; 5339 5340 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5341 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5342 5343 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 5344 MLX5_CAP_GEN(mdev, num_vhca_ports)); 5345 dev = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, 5346 mlx5_core_net(mdev)); 5347 if (!dev) 5348 return -ENOMEM; 5349 5350 if (ll == IB_LINK_LAYER_INFINIBAND) { 5351 ret = mlx5_ib_get_plane_num(mdev, &dev->num_plane); 5352 if (ret) 5353 goto fail; 5354 } 5355 5356 dev->port = kzalloc_objs(*dev->port, num_ports); 5357 if (!dev->port) { 5358 ret = -ENOMEM; 5359 goto fail; 5360 } 5361 5362 dev->mdev = mdev; 5363 dev->num_ports = num_ports; 5364 dev->ib_dev.phys_port_cnt = num_ports; 5365 5366 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev)) 5367 profile = &raw_eth_profile; 5368 else 5369 profile = &pf_profile; 5370 5371 ret = __mlx5_ib_add(dev, profile); 5372 if (ret) 5373 goto fail_ib_add; 5374 5375 auxiliary_set_drvdata(adev, dev); 5376 return 0; 5377 5378 fail_ib_add: 5379 kfree(dev->port); 5380 fail: 5381 ib_dealloc_device(&dev->ib_dev); 5382 return ret; 5383 } 5384 5385 static void mlx5r_remove(struct auxiliary_device *adev) 5386 { 5387 struct mlx5_ib_dev *dev; 5388 5389 dev = auxiliary_get_drvdata(adev); 5390 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 5391 } 5392 5393 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 5394 { .name = MLX5_ADEV_NAME ".multiport", }, 5395 {}, 5396 }; 5397 5398 static const struct auxiliary_device_id mlx5r_id_table[] = { 5399 { .name = MLX5_ADEV_NAME ".rdma", }, 5400 {}, 5401 }; 5402 5403 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 5404 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 5405 5406 static struct auxiliary_driver mlx5r_mp_driver = { 5407 .name = "multiport", 5408 .probe = mlx5r_mp_probe, 5409 .remove = mlx5r_mp_remove, 5410 .id_table = mlx5r_mp_id_table, 5411 }; 5412 5413 static struct auxiliary_driver mlx5r_driver = { 5414 .name = "rdma", 5415 .probe = mlx5r_probe, 5416 .remove = mlx5r_remove, 5417 .id_table = mlx5r_id_table, 5418 }; 5419 5420 static int __init mlx5_ib_init(void) 5421 { 5422 int ret; 5423 5424 xlt_emergency_page = kmalloc(PAGE_SIZE, GFP_KERNEL); 5425 if (!xlt_emergency_page) 5426 return -ENOMEM; 5427 5428 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 5429 if (!mlx5_ib_event_wq) { 5430 kfree(xlt_emergency_page); 5431 return -ENOMEM; 5432 } 5433 5434 ret = mlx5_ib_qp_event_init(); 5435 if (ret) 5436 goto qp_event_err; 5437 5438 mlx5_ib_odp_init(); 5439 ret = mlx5r_rep_init(); 5440 if (ret) 5441 goto rep_err; 5442 ret = auxiliary_driver_register(&mlx5r_mp_driver); 5443 if (ret) 5444 goto mp_err; 5445 ret = auxiliary_driver_register(&mlx5r_driver); 5446 if (ret) 5447 goto drv_err; 5448 5449 return 0; 5450 5451 drv_err: 5452 auxiliary_driver_unregister(&mlx5r_mp_driver); 5453 mp_err: 5454 mlx5r_rep_cleanup(); 5455 rep_err: 5456 rcu_barrier(); 5457 mlx5_ib_qp_event_cleanup(); 5458 qp_event_err: 5459 destroy_workqueue(mlx5_ib_event_wq); 5460 kfree(xlt_emergency_page); 5461 return ret; 5462 } 5463 5464 static void __exit mlx5_ib_cleanup(void) 5465 { 5466 auxiliary_driver_unregister(&mlx5r_driver); 5467 auxiliary_driver_unregister(&mlx5r_mp_driver); 5468 mlx5r_rep_cleanup(); 5469 rcu_barrier(); 5470 5471 mlx5_ib_qp_event_cleanup(); 5472 destroy_workqueue(mlx5_ib_event_wq); 5473 kfree(xlt_emergency_page); 5474 } 5475 5476 module_init(mlx5_ib_init); 5477 module_exit(mlx5_ib_cleanup); 5478