xref: /linux/drivers/crypto/intel/qat/qat_common/adf_gen4_tl.h (revision 06d07429858317ded2db7986113a9e0129cd599b)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2023 Intel Corporation. */
3 #ifndef ADF_GEN4_TL_H
4 #define ADF_GEN4_TL_H
5 
6 #include <linux/stddef.h>
7 #include <linux/types.h>
8 
9 struct adf_tl_hw_data;
10 
11 /* Computation constants. */
12 #define ADF_GEN4_CPP_NS_PER_CYCLE		2
13 #define ADF_GEN4_TL_BW_HW_UNITS_TO_BYTES	64
14 
15 /* Maximum aggregation time. Value in milliseconds. */
16 #define ADF_GEN4_TL_MAX_AGGR_TIME_MS		4000
17 /* Num of buffers to store historic values. */
18 #define ADF_GEN4_TL_NUM_HIST_BUFFS \
19 	(ADF_GEN4_TL_MAX_AGGR_TIME_MS / ADF_TL_DATA_WR_INTERVAL_MS)
20 
21 /* Max number of HW resources of one type. */
22 #define ADF_GEN4_TL_MAX_SLICES_PER_TYPE		24
23 
24 /* Max number of simultaneously monitored ring pairs. */
25 #define ADF_GEN4_TL_MAX_RP_NUM			4
26 
27 /**
28  * struct adf_gen4_tl_slice_data_regs - HW slice data as populated by FW.
29  * @reg_tm_slice_exec_cnt: Slice execution count.
30  * @reg_tm_slice_util: Slice utilization.
31  */
32 struct adf_gen4_tl_slice_data_regs {
33 	__u32 reg_tm_slice_exec_cnt;
34 	__u32 reg_tm_slice_util;
35 };
36 
37 #define ADF_GEN4_TL_SLICE_REG_SZ sizeof(struct adf_gen4_tl_slice_data_regs)
38 
39 /**
40  * struct adf_gen4_tl_device_data_regs - This structure stores device telemetry
41  * counter values as are being populated periodically by device.
42  * @reg_tl_rd_lat_acc: read latency accumulator
43  * @reg_tl_gp_lat_acc: get-put latency accumulator
44  * @reg_tl_at_page_req_lat_acc: AT/DevTLB page request latency accumulator
45  * @reg_tl_at_trans_lat_acc: DevTLB transaction latency accumulator
46  * @reg_tl_re_acc: accumulated ring empty time
47  * @reg_tl_pci_trans_cnt: PCIe partial transactions
48  * @reg_tl_rd_lat_max: maximum logged read latency
49  * @reg_tl_rd_cmpl_cnt: read requests completed count
50  * @reg_tl_gp_lat_max: maximum logged get to put latency
51  * @reg_tl_ae_put_cnt: Accelerator Engine put counts across all rings
52  * @reg_tl_bw_in: PCIe write bandwidth
53  * @reg_tl_bw_out: PCIe read bandwidth
54  * @reg_tl_at_page_req_cnt: DevTLB page requests count
55  * @reg_tl_at_trans_lat_cnt: DevTLB transaction latency samples count
56  * @reg_tl_at_max_tlb_used: maximum uTLB used
57  * @reg_tl_re_cnt: ring empty time samples count
58  * @reserved: reserved
59  * @ath_slices: array of Authentication slices utilization registers
60  * @cph_slices: array of Cipher slices utilization registers
61  * @cpr_slices: array of Compression slices utilization registers
62  * @xlt_slices: array of Translator slices utilization registers
63  * @dcpr_slices: array of Decompression slices utilization registers
64  * @pke_slices: array of PKE slices utilization registers
65  * @ucs_slices: array of UCS slices utilization registers
66  * @wat_slices: array of Wireless Authentication slices utilization registers
67  * @wcp_slices: array of Wireless Cipher slices utilization registers
68  */
69 struct adf_gen4_tl_device_data_regs {
70 	__u64 reg_tl_rd_lat_acc;
71 	__u64 reg_tl_gp_lat_acc;
72 	__u64 reg_tl_at_page_req_lat_acc;
73 	__u64 reg_tl_at_trans_lat_acc;
74 	__u64 reg_tl_re_acc;
75 	__u32 reg_tl_pci_trans_cnt;
76 	__u32 reg_tl_rd_lat_max;
77 	__u32 reg_tl_rd_cmpl_cnt;
78 	__u32 reg_tl_gp_lat_max;
79 	__u32 reg_tl_ae_put_cnt;
80 	__u32 reg_tl_bw_in;
81 	__u32 reg_tl_bw_out;
82 	__u32 reg_tl_at_page_req_cnt;
83 	__u32 reg_tl_at_trans_lat_cnt;
84 	__u32 reg_tl_at_max_tlb_used;
85 	__u32 reg_tl_re_cnt;
86 	__u32 reserved;
87 	struct adf_gen4_tl_slice_data_regs ath_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
88 	struct adf_gen4_tl_slice_data_regs cph_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
89 	struct adf_gen4_tl_slice_data_regs cpr_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
90 	struct adf_gen4_tl_slice_data_regs xlt_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
91 	struct adf_gen4_tl_slice_data_regs dcpr_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
92 	struct adf_gen4_tl_slice_data_regs pke_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
93 	struct adf_gen4_tl_slice_data_regs ucs_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
94 	struct adf_gen4_tl_slice_data_regs wat_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
95 	struct adf_gen4_tl_slice_data_regs wcp_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];
96 };
97 
98 /**
99  * struct adf_gen4_tl_ring_pair_data_regs - This structure stores Ring Pair
100  * telemetry counter values as are being populated periodically by device.
101  * @reg_tl_gp_lat_acc: get-put latency accumulator
102  * @reserved: reserved
103  * @reg_tl_pci_trans_cnt: PCIe partial transactions
104  * @reg_tl_ae_put_cnt: Accelerator Engine put counts across all rings
105  * @reg_tl_bw_in: PCIe write bandwidth
106  * @reg_tl_bw_out: PCIe read bandwidth
107  * @reg_tl_at_glob_devtlb_hit: Message descriptor DevTLB hit rate
108  * @reg_tl_at_glob_devtlb_miss: Message descriptor DevTLB miss rate
109  * @reg_tl_at_payld_devtlb_hit: Payload DevTLB hit rate
110  * @reg_tl_at_payld_devtlb_miss: Payload DevTLB miss rate
111  * @reg_tl_re_cnt: ring empty time samples count
112  * @reserved1: reserved
113  */
114 struct adf_gen4_tl_ring_pair_data_regs {
115 	__u64 reg_tl_gp_lat_acc;
116 	__u64 reserved;
117 	__u32 reg_tl_pci_trans_cnt;
118 	__u32 reg_tl_ae_put_cnt;
119 	__u32 reg_tl_bw_in;
120 	__u32 reg_tl_bw_out;
121 	__u32 reg_tl_at_glob_devtlb_hit;
122 	__u32 reg_tl_at_glob_devtlb_miss;
123 	__u32 reg_tl_at_payld_devtlb_hit;
124 	__u32 reg_tl_at_payld_devtlb_miss;
125 	__u32 reg_tl_re_cnt;
126 	__u32 reserved1;
127 };
128 
129 #define ADF_GEN4_TL_RP_REG_SZ sizeof(struct adf_gen4_tl_ring_pair_data_regs)
130 
131 /**
132  * struct adf_gen4_tl_layout - This structure represents entire telemetry
133  * counters data: Device + 4 Ring Pairs as are being populated periodically
134  * by device.
135  * @tl_device_data_regs: structure of device telemetry registers
136  * @tl_ring_pairs_data_regs: array of ring pairs telemetry registers
137  * @reg_tl_msg_cnt: telemetry messages counter
138  * @reserved: reserved
139  */
140 struct adf_gen4_tl_layout {
141 	struct adf_gen4_tl_device_data_regs tl_device_data_regs;
142 	struct adf_gen4_tl_ring_pair_data_regs
143 			tl_ring_pairs_data_regs[ADF_GEN4_TL_MAX_RP_NUM];
144 	__u32 reg_tl_msg_cnt;
145 	__u32 reserved;
146 };
147 
148 #define ADF_GEN4_TL_LAYOUT_SZ	sizeof(struct adf_gen4_tl_layout)
149 #define ADF_GEN4_TL_MSG_CNT_OFF	offsetof(struct adf_gen4_tl_layout, reg_tl_msg_cnt)
150 
151 #ifdef CONFIG_DEBUG_FS
152 void adf_gen4_init_tl_data(struct adf_tl_hw_data *tl_data);
153 #else
adf_gen4_init_tl_data(struct adf_tl_hw_data * tl_data)154 static inline void adf_gen4_init_tl_data(struct adf_tl_hw_data *tl_data)
155 {
156 }
157 #endif /* CONFIG_DEBUG_FS */
158 #endif /* ADF_GEN4_TL_H */
159