xref: /linux/drivers/staging/media/atomisp/pci/css_2401_system/host/pixelgen_private.h (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Support for Intel Camera Imaging ISP subsystem.
4  * Copyright (c) 2015, Intel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  */
15 
16 #ifndef __PIXELGEN_PRIVATE_H_INCLUDED__
17 #define __PIXELGEN_PRIVATE_H_INCLUDED__
18 #include "pixelgen_public.h"
19 #include "PixelGen_SysBlock_defs.h"
20 #include "device_access.h"	/* ia_css_device_load_uint32 */
21 #include "assert_support.h" /* assert */
22 
23 /*****************************************************
24  *
25  * Device level interface (DLI).
26  *
27  *****************************************************/
28 /**
29  * @brief Load the register value.
30  * Refer to "pixelgen_public.h" for details.
31  */
pixelgen_ctrl_reg_load(const pixelgen_ID_t ID,const hrt_address reg)32 STORAGE_CLASS_PIXELGEN_C hrt_data pixelgen_ctrl_reg_load(
33     const pixelgen_ID_t ID,
34     const hrt_address reg)
35 {
36 	assert(ID < N_PIXELGEN_ID);
37 	assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address) - 1);
38 	return ia_css_device_load_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof(
39 					     hrt_data));
40 }
41 
42 /**
43  * @brief Store a value to the register.
44  * Refer to "pixelgen_ctrl_public.h" for details.
45  */
pixelgen_ctrl_reg_store(const pixelgen_ID_t ID,const hrt_address reg,const hrt_data value)46 STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_reg_store(
47     const pixelgen_ID_t ID,
48     const hrt_address reg,
49     const hrt_data value)
50 {
51 	assert(ID < N_PIXELGEN_ID);
52 	assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1);
53 
54 	ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof(hrt_data),
55 				   value);
56 }
57 
58 /* end of DLI */
59 
60 /*****************************************************
61  *
62  * Native command interface (NCI).
63  *
64  *****************************************************/
65 /**
66  * @brief Get the pixelgen state.
67  * Refer to "pixelgen_public.h" for details.
68  */
pixelgen_ctrl_get_state(const pixelgen_ID_t ID,pixelgen_ctrl_state_t * state)69 STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_get_state(
70     const pixelgen_ID_t ID,
71     pixelgen_ctrl_state_t *state)
72 {
73 	state->com_enable =
74 	    pixelgen_ctrl_reg_load(ID, _PXG_COM_ENABLE_REG_IDX);
75 	state->prbs_rstval0 =
76 	    pixelgen_ctrl_reg_load(ID, _PXG_PRBS_RSTVAL_REG0_IDX);
77 	state->prbs_rstval1 =
78 	    pixelgen_ctrl_reg_load(ID, _PXG_PRBS_RSTVAL_REG1_IDX);
79 	state->syng_sid =
80 	    pixelgen_ctrl_reg_load(ID, _PXG_SYNG_SID_REG_IDX);
81 	state->syng_free_run =
82 	    pixelgen_ctrl_reg_load(ID, _PXG_SYNG_FREE_RUN_REG_IDX);
83 	state->syng_pause =
84 	    pixelgen_ctrl_reg_load(ID, _PXG_SYNG_PAUSE_REG_IDX);
85 	state->syng_nof_frames =
86 	    pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_FRAME_REG_IDX);
87 	state->syng_nof_pixels =
88 	    pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_PIXEL_REG_IDX);
89 	state->syng_nof_line =
90 	    pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_LINE_REG_IDX);
91 	state->syng_hblank_cyc =
92 	    pixelgen_ctrl_reg_load(ID, _PXG_SYNG_HBLANK_CYC_REG_IDX);
93 	state->syng_vblank_cyc =
94 	    pixelgen_ctrl_reg_load(ID, _PXG_SYNG_VBLANK_CYC_REG_IDX);
95 	state->syng_stat_hcnt =
96 	    pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_HCNT_REG_IDX);
97 	state->syng_stat_vcnt =
98 	    pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_VCNT_REG_IDX);
99 	state->syng_stat_fcnt =
100 	    pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_FCNT_REG_IDX);
101 	state->syng_stat_done =
102 	    pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_DONE_REG_IDX);
103 	state->tpg_mode =
104 	    pixelgen_ctrl_reg_load(ID, _PXG_TPG_MODE_REG_IDX);
105 	state->tpg_hcnt_mask =
106 	    pixelgen_ctrl_reg_load(ID, _PXG_TPG_HCNT_MASK_REG_IDX);
107 	state->tpg_vcnt_mask =
108 	    pixelgen_ctrl_reg_load(ID, _PXG_TPG_VCNT_MASK_REG_IDX);
109 	state->tpg_xycnt_mask =
110 	    pixelgen_ctrl_reg_load(ID, _PXG_TPG_XYCNT_MASK_REG_IDX);
111 	state->tpg_hcnt_delta =
112 	    pixelgen_ctrl_reg_load(ID, _PXG_TPG_HCNT_DELTA_REG_IDX);
113 	state->tpg_vcnt_delta =
114 	    pixelgen_ctrl_reg_load(ID, _PXG_TPG_VCNT_DELTA_REG_IDX);
115 	state->tpg_r1 =
116 	    pixelgen_ctrl_reg_load(ID, _PXG_TPG_R1_REG_IDX);
117 	state->tpg_g1 =
118 	    pixelgen_ctrl_reg_load(ID, _PXG_TPG_G1_REG_IDX);
119 	state->tpg_b1 =
120 	    pixelgen_ctrl_reg_load(ID, _PXG_TPG_B1_REG_IDX);
121 	state->tpg_r2 =
122 	    pixelgen_ctrl_reg_load(ID, _PXG_TPG_R2_REG_IDX);
123 	state->tpg_g2 =
124 	    pixelgen_ctrl_reg_load(ID, _PXG_TPG_G2_REG_IDX);
125 	state->tpg_b2 =
126 	    pixelgen_ctrl_reg_load(ID, _PXG_TPG_B2_REG_IDX);
127 }
128 
129 /**
130  * @brief Dump the pixelgen state.
131  * Refer to "pixelgen_public.h" for details.
132  */
pixelgen_ctrl_dump_state(const pixelgen_ID_t ID,pixelgen_ctrl_state_t * state)133 STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_dump_state(
134     const pixelgen_ID_t ID,
135     pixelgen_ctrl_state_t *state)
136 {
137 	ia_css_print("Pixel Generator ID %d Enable  0x%x\n", ID, state->com_enable);
138 	ia_css_print("Pixel Generator ID %d PRBS reset value 0 0x%x\n", ID,
139 		     state->prbs_rstval0);
140 	ia_css_print("Pixel Generator ID %d PRBS reset value 1 0x%x\n", ID,
141 		     state->prbs_rstval1);
142 	ia_css_print("Pixel Generator ID %d SYNC SID 0x%x\n", ID, state->syng_sid);
143 	ia_css_print("Pixel Generator ID %d syng free run 0x%x\n", ID,
144 		     state->syng_free_run);
145 	ia_css_print("Pixel Generator ID %d syng pause 0x%x\n", ID, state->syng_pause);
146 	ia_css_print("Pixel Generator ID %d syng no of frames 0x%x\n", ID,
147 		     state->syng_nof_frames);
148 	ia_css_print("Pixel Generator ID %d syng no of pixels 0x%x\n", ID,
149 		     state->syng_nof_pixels);
150 	ia_css_print("Pixel Generator ID %d syng no of line 0x%x\n", ID,
151 		     state->syng_nof_line);
152 	ia_css_print("Pixel Generator ID %d syng hblank cyc  0x%x\n", ID,
153 		     state->syng_hblank_cyc);
154 	ia_css_print("Pixel Generator ID %d syng vblank cyc  0x%x\n", ID,
155 		     state->syng_vblank_cyc);
156 	ia_css_print("Pixel Generator ID %d syng stat hcnt  0x%x\n", ID,
157 		     state->syng_stat_hcnt);
158 	ia_css_print("Pixel Generator ID %d syng stat vcnt  0x%x\n", ID,
159 		     state->syng_stat_vcnt);
160 	ia_css_print("Pixel Generator ID %d syng stat fcnt  0x%x\n", ID,
161 		     state->syng_stat_fcnt);
162 	ia_css_print("Pixel Generator ID %d syng stat done  0x%x\n", ID,
163 		     state->syng_stat_done);
164 	ia_css_print("Pixel Generator ID %d tpg mode  0x%x\n", ID, state->tpg_mode);
165 	ia_css_print("Pixel Generator ID %d tpg hcnt mask  0x%x\n", ID,
166 		     state->tpg_hcnt_mask);
167 	ia_css_print("Pixel Generator ID %d tpg hcnt mask  0x%x\n", ID,
168 		     state->tpg_hcnt_mask);
169 	ia_css_print("Pixel Generator ID %d tpg xycnt mask  0x%x\n", ID,
170 		     state->tpg_xycnt_mask);
171 	ia_css_print("Pixel Generator ID %d tpg hcnt delta  0x%x\n", ID,
172 		     state->tpg_hcnt_delta);
173 	ia_css_print("Pixel Generator ID %d tpg vcnt delta  0x%x\n", ID,
174 		     state->tpg_vcnt_delta);
175 	ia_css_print("Pixel Generator ID %d tpg r1 0x%x\n", ID, state->tpg_r1);
176 	ia_css_print("Pixel Generator ID %d tpg g1 0x%x\n", ID, state->tpg_g1);
177 	ia_css_print("Pixel Generator ID %d tpg b1 0x%x\n", ID, state->tpg_b1);
178 	ia_css_print("Pixel Generator ID %d tpg r2 0x%x\n", ID, state->tpg_r2);
179 	ia_css_print("Pixel Generator ID %d tpg g2 0x%x\n", ID, state->tpg_g2);
180 	ia_css_print("Pixel Generator ID %d tpg b2 0x%x\n", ID, state->tpg_b2);
181 }
182 
183 /* end of NCI */
184 #endif /* __PIXELGEN_PRIVATE_H_INCLUDED__ */
185