1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "display_mode_util.h" 28 29 static dml_float_t _log(float in) 30 { 31 int * const exp_ptr = (int *)(&in); 32 int x = *exp_ptr; 33 const int log_2 = ((x >> 23) & 255) - 128; 34 35 x &= ~(255 << 23); 36 x += 127 << 23; 37 *exp_ptr = x; 38 39 in = ((-1.0f / 3) * in + 2) * in - 2.0f / 3; 40 41 return (in + log_2); 42 } 43 44 dml_bool_t dml_util_is_420(enum dml_source_format_class source_format) 45 { 46 dml_bool_t val = false; 47 48 switch (source_format) { 49 case dml_444_16: 50 val = 0; 51 break; 52 case dml_444_32: 53 val = 0; 54 break; 55 case dml_444_64: 56 val = 0; 57 break; 58 case dml_420_8: 59 val = 1; 60 break; 61 case dml_420_10: 62 val = 1; 63 break; 64 case dml_422_8: 65 val = 0; 66 break; 67 case dml_422_10: 68 val = 0; 69 break; 70 default: 71 ASSERT(0); 72 break; 73 } 74 return val; 75 } 76 77 static inline float dcn_bw_pow(float a, float exp) 78 { 79 float temp; 80 /*ASSERT(exp == (int)exp);*/ 81 if ((int)exp == 0) 82 return 1; 83 temp = dcn_bw_pow(a, (float)(exp / 2)); 84 if (((int)exp % 2) == 0) { 85 return temp * temp; 86 } else { 87 if ((int)exp > 0) 88 return a * temp * temp; 89 else 90 return (temp * temp) / a; 91 } 92 } 93 94 static inline float dcn_bw_ceil2(const float arg, const float significance) 95 { 96 ASSERT(significance != 0); 97 98 return ((int)(arg / significance + 0.99999)) * significance; 99 } 100 101 static inline float dcn_bw_floor2(const float arg, const float significance) 102 { 103 ASSERT(significance != 0); 104 105 return ((int)(arg / significance)) * significance; 106 } 107 108 dml_float_t dml_ceil(dml_float_t x, dml_float_t granularity) 109 { 110 if (granularity == 0) 111 return 0; 112 //return (dml_float_t) (ceil(x / granularity) * granularity); 113 return (dml_float_t)dcn_bw_ceil2((float)x, (float)granularity); 114 } 115 116 dml_float_t dml_floor(dml_float_t x, dml_float_t granularity) 117 { 118 if (granularity == 0) 119 return 0; 120 //return (dml_float_t) (floor(x / granularity) * granularity); 121 return (dml_float_t)dcn_bw_floor2((float)x, (float)granularity); 122 } 123 124 dml_float_t dml_min(dml_float_t x, dml_float_t y) 125 { 126 if (x != x) 127 return y; 128 if (y != y) 129 return x; 130 if (x < y) 131 return x; 132 else 133 return y; 134 } 135 136 dml_float_t dml_min3(dml_float_t x, dml_float_t y, dml_float_t z) 137 { 138 return dml_min(dml_min(x, y), z); 139 } 140 141 dml_float_t dml_min4(dml_float_t x, dml_float_t y, dml_float_t z, dml_float_t w) 142 { 143 return dml_min(dml_min(dml_min(x, y), z), w); 144 } 145 146 dml_float_t dml_max(dml_float_t x, dml_float_t y) 147 { 148 if (x != x) 149 return y; 150 if (y != y) 151 return x; 152 if (x > y) 153 return x; 154 else 155 return y; 156 } 157 dml_float_t dml_max3(dml_float_t x, dml_float_t y, dml_float_t z) 158 { 159 return dml_max(dml_max(x, y), z); 160 } 161 dml_float_t dml_max4(dml_float_t a, dml_float_t b, dml_float_t c, dml_float_t d) 162 { 163 return dml_max(dml_max(a, b), dml_max(c, d)); 164 } 165 dml_float_t dml_max5(dml_float_t a, dml_float_t b, dml_float_t c, dml_float_t d, dml_float_t e) 166 { 167 return dml_max(dml_max4(a, b, c, d), e); 168 } 169 dml_float_t dml_log(dml_float_t x, dml_float_t base) 170 { 171 return (dml_float_t) (_log((float)x) / _log((float)base)); 172 } 173 174 dml_float_t dml_log2(dml_float_t x) 175 { 176 return (dml_float_t) (_log((float)x) / _log(2.0f)); 177 } 178 179 dml_float_t dml_round(dml_float_t val, dml_bool_t bankers_rounding) 180 { 181 (void)bankers_rounding; 182 // if (bankers_rounding) 183 // return (dml_float_t) lrint(val); 184 // else { 185 // return round(val); 186 double round_pt = 0.5; 187 double ceil = dml_ceil(val, 1.0); 188 double floor = dml_floor(val, 1.0); 189 190 if (val - floor >= round_pt) 191 return (dml_float_t)ceil; 192 else 193 return (dml_float_t)floor; 194 // } 195 } 196 197 dml_float_t dml_pow(dml_float_t base, int exp) 198 { 199 return (dml_float_t) dcn_bw_pow((float)base, (float)exp); 200 } 201 202 dml_uint_t dml_round_to_multiple(dml_uint_t num, dml_uint_t multiple, dml_bool_t up) 203 { 204 dml_uint_t remainder; 205 206 if (multiple == 0) 207 return num; 208 209 remainder = num % multiple; 210 if (remainder == 0) 211 return num; 212 213 if (up) 214 return (num + multiple - remainder); 215 else 216 return (num - remainder); 217 } 218 219 void dml_print_data_rq_regs_st(const dml_display_plane_rq_regs_st *rq_regs) 220 { 221 (void)rq_regs; 222 dml_print("DML: ===================================== \n"); 223 dml_print("DML: DISPLAY_PLANE_RQ_REGS_ST\n"); 224 dml_print("DML: chunk_size = 0x%x\n", rq_regs->chunk_size); 225 dml_print("DML: min_chunk_size = 0x%x\n", rq_regs->min_chunk_size); 226 dml_print("DML: meta_chunk_size = 0x%x\n", rq_regs->meta_chunk_size); 227 dml_print("DML: min_meta_chunk_size = 0x%x\n", rq_regs->min_meta_chunk_size); 228 dml_print("DML: dpte_group_size = 0x%x\n", rq_regs->dpte_group_size); 229 dml_print("DML: mpte_group_size = 0x%x\n", rq_regs->mpte_group_size); 230 dml_print("DML: swath_height = 0x%x\n", rq_regs->swath_height); 231 dml_print("DML: pte_row_height_linear = 0x%x\n", rq_regs->pte_row_height_linear); 232 dml_print("DML: ===================================== \n"); 233 } 234 235 void dml_print_rq_regs_st(const dml_display_rq_regs_st *rq_regs) 236 { 237 dml_print("DML: ===================================== \n"); 238 dml_print("DML: DISPLAY_RQ_REGS_ST\n"); 239 dml_print("DML: <LUMA> \n"); 240 dml_print_data_rq_regs_st(&rq_regs->rq_regs_l); 241 dml_print("DML: <CHROMA> \n"); 242 dml_print_data_rq_regs_st(&rq_regs->rq_regs_c); 243 dml_print("DML: drq_expansion_mode = 0x%x\n", rq_regs->drq_expansion_mode); 244 dml_print("DML: prq_expansion_mode = 0x%x\n", rq_regs->prq_expansion_mode); 245 dml_print("DML: mrq_expansion_mode = 0x%x\n", rq_regs->mrq_expansion_mode); 246 dml_print("DML: crq_expansion_mode = 0x%x\n", rq_regs->crq_expansion_mode); 247 dml_print("DML: plane1_base_address = 0x%x\n", rq_regs->plane1_base_address); 248 dml_print("DML: ===================================== \n"); 249 } 250 251 void dml_print_dlg_regs_st(const dml_display_dlg_regs_st *dlg_regs) 252 { 253 (void)dlg_regs; 254 dml_print("DML: ===================================== \n"); 255 dml_print("DML: DISPLAY_DLG_REGS_ST \n"); 256 dml_print("DML: refcyc_h_blank_end = 0x%x\n", dlg_regs->refcyc_h_blank_end); 257 dml_print("DML: dlg_vblank_end = 0x%x\n", dlg_regs->dlg_vblank_end); 258 dml_print("DML: min_dst_y_next_start = 0x%x\n", dlg_regs->min_dst_y_next_start); 259 dml_print("DML: refcyc_per_htotal = 0x%x\n", dlg_regs->refcyc_per_htotal); 260 dml_print("DML: refcyc_x_after_scaler = 0x%x\n", dlg_regs->refcyc_x_after_scaler); 261 dml_print("DML: dst_y_after_scaler = 0x%x\n", dlg_regs->dst_y_after_scaler); 262 dml_print("DML: dst_y_prefetch = 0x%x\n", dlg_regs->dst_y_prefetch); 263 dml_print("DML: dst_y_per_vm_vblank = 0x%x\n", dlg_regs->dst_y_per_vm_vblank); 264 dml_print("DML: dst_y_per_row_vblank = 0x%x\n", dlg_regs->dst_y_per_row_vblank); 265 dml_print("DML: dst_y_per_vm_flip = 0x%x\n", dlg_regs->dst_y_per_vm_flip); 266 dml_print("DML: dst_y_per_row_flip = 0x%x\n", dlg_regs->dst_y_per_row_flip); 267 dml_print("DML: ref_freq_to_pix_freq = 0x%x\n", dlg_regs->ref_freq_to_pix_freq); 268 dml_print("DML: vratio_prefetch = 0x%x\n", dlg_regs->vratio_prefetch); 269 dml_print("DML: vratio_prefetch_c = 0x%x\n", dlg_regs->vratio_prefetch_c); 270 dml_print("DML: refcyc_per_pte_group_vblank_l = 0x%x\n", dlg_regs->refcyc_per_pte_group_vblank_l); 271 dml_print("DML: refcyc_per_pte_group_vblank_c = 0x%x\n", dlg_regs->refcyc_per_pte_group_vblank_c); 272 dml_print("DML: refcyc_per_meta_chunk_vblank_l = 0x%x\n", dlg_regs->refcyc_per_meta_chunk_vblank_l); 273 dml_print("DML: refcyc_per_meta_chunk_vblank_c = 0x%x\n", dlg_regs->refcyc_per_meta_chunk_vblank_c); 274 dml_print("DML: refcyc_per_pte_group_flip_l = 0x%x\n", dlg_regs->refcyc_per_pte_group_flip_l); 275 dml_print("DML: refcyc_per_pte_group_flip_c = 0x%x\n", dlg_regs->refcyc_per_pte_group_flip_c); 276 dml_print("DML: refcyc_per_meta_chunk_flip_l = 0x%x\n", dlg_regs->refcyc_per_meta_chunk_flip_l); 277 dml_print("DML: refcyc_per_meta_chunk_flip_c = 0x%x\n", dlg_regs->refcyc_per_meta_chunk_flip_c); 278 dml_print("DML: dst_y_per_pte_row_nom_l = 0x%x\n", dlg_regs->dst_y_per_pte_row_nom_l); 279 dml_print("DML: dst_y_per_pte_row_nom_c = 0x%x\n", dlg_regs->dst_y_per_pte_row_nom_c); 280 dml_print("DML: refcyc_per_pte_group_nom_l = 0x%x\n", dlg_regs->refcyc_per_pte_group_nom_l); 281 dml_print("DML: refcyc_per_pte_group_nom_c = 0x%x\n", dlg_regs->refcyc_per_pte_group_nom_c); 282 dml_print("DML: dst_y_per_meta_row_nom_l = 0x%x\n", dlg_regs->dst_y_per_meta_row_nom_l); 283 dml_print("DML: dst_y_per_meta_row_nom_c = 0x%x\n", dlg_regs->dst_y_per_meta_row_nom_c); 284 dml_print("DML: refcyc_per_meta_chunk_nom_l = 0x%x\n", dlg_regs->refcyc_per_meta_chunk_nom_l); 285 dml_print("DML: refcyc_per_meta_chunk_nom_c = 0x%x\n", dlg_regs->refcyc_per_meta_chunk_nom_c); 286 dml_print("DML: refcyc_per_line_delivery_pre_l = 0x%x\n", dlg_regs->refcyc_per_line_delivery_pre_l); 287 dml_print("DML: refcyc_per_line_delivery_pre_c = 0x%x\n", dlg_regs->refcyc_per_line_delivery_pre_c); 288 dml_print("DML: refcyc_per_line_delivery_l = 0x%x\n", dlg_regs->refcyc_per_line_delivery_l); 289 dml_print("DML: refcyc_per_line_delivery_c = 0x%x\n", dlg_regs->refcyc_per_line_delivery_c); 290 dml_print("DML: refcyc_per_vm_group_vblank = 0x%x\n", dlg_regs->refcyc_per_vm_group_vblank); 291 dml_print("DML: refcyc_per_vm_group_flip = 0x%x\n", dlg_regs->refcyc_per_vm_group_flip); 292 dml_print("DML: refcyc_per_vm_req_vblank = 0x%x\n", dlg_regs->refcyc_per_vm_req_vblank); 293 dml_print("DML: refcyc_per_vm_req_flip = 0x%x\n", dlg_regs->refcyc_per_vm_req_flip); 294 dml_print("DML: chunk_hdl_adjust_cur0 = 0x%x\n", dlg_regs->chunk_hdl_adjust_cur0); 295 dml_print("DML: dst_y_offset_cur1 = 0x%x\n", dlg_regs->dst_y_offset_cur1); 296 dml_print("DML: chunk_hdl_adjust_cur1 = 0x%x\n", dlg_regs->chunk_hdl_adjust_cur1); 297 dml_print("DML: vready_after_vcount0 = 0x%x\n", dlg_regs->vready_after_vcount0); 298 dml_print("DML: dst_y_delta_drq_limit = 0x%x\n", dlg_regs->dst_y_delta_drq_limit); 299 dml_print("DML: refcyc_per_vm_dmdata = 0x%x\n", dlg_regs->refcyc_per_vm_dmdata); 300 dml_print("DML: ===================================== \n"); 301 } 302 303 void dml_print_ttu_regs_st(const dml_display_ttu_regs_st *ttu_regs) 304 { 305 (void)ttu_regs; 306 dml_print("DML: ===================================== \n"); 307 dml_print("DML: DISPLAY_TTU_REGS_ST \n"); 308 dml_print("DML: qos_level_low_wm = 0x%x\n", ttu_regs->qos_level_low_wm); 309 dml_print("DML: qos_level_high_wm = 0x%x\n", ttu_regs->qos_level_high_wm); 310 dml_print("DML: min_ttu_vblank = 0x%x\n", ttu_regs->min_ttu_vblank); 311 dml_print("DML: qos_level_flip = 0x%x\n", ttu_regs->qos_level_flip); 312 dml_print("DML: refcyc_per_req_delivery_pre_l = 0x%x\n", ttu_regs->refcyc_per_req_delivery_pre_l); 313 dml_print("DML: refcyc_per_req_delivery_l = 0x%x\n", ttu_regs->refcyc_per_req_delivery_l); 314 dml_print("DML: refcyc_per_req_delivery_pre_c = 0x%x\n", ttu_regs->refcyc_per_req_delivery_pre_c); 315 dml_print("DML: refcyc_per_req_delivery_c = 0x%x\n", ttu_regs->refcyc_per_req_delivery_c); 316 dml_print("DML: refcyc_per_req_delivery_cur0 = 0x%x\n", ttu_regs->refcyc_per_req_delivery_cur0); 317 dml_print("DML: refcyc_per_req_delivery_pre_cur0 = 0x%x\n", ttu_regs->refcyc_per_req_delivery_pre_cur0); 318 dml_print("DML: refcyc_per_req_delivery_cur1 = 0x%x\n", ttu_regs->refcyc_per_req_delivery_cur1); 319 dml_print("DML: refcyc_per_req_delivery_pre_cur1 = 0x%x\n", ttu_regs->refcyc_per_req_delivery_pre_cur1); 320 dml_print("DML: qos_level_fixed_l = 0x%x\n", ttu_regs->qos_level_fixed_l); 321 dml_print("DML: qos_ramp_disable_l = 0x%x\n", ttu_regs->qos_ramp_disable_l); 322 dml_print("DML: qos_level_fixed_c = 0x%x\n", ttu_regs->qos_level_fixed_c); 323 dml_print("DML: qos_ramp_disable_c = 0x%x\n", ttu_regs->qos_ramp_disable_c); 324 dml_print("DML: qos_level_fixed_cur0 = 0x%x\n", ttu_regs->qos_level_fixed_cur0); 325 dml_print("DML: qos_ramp_disable_cur0 = 0x%x\n", ttu_regs->qos_ramp_disable_cur0); 326 dml_print("DML: qos_level_fixed_cur1 = 0x%x\n", ttu_regs->qos_level_fixed_cur1); 327 dml_print("DML: qos_ramp_disable_cur1 = 0x%x\n", ttu_regs->qos_ramp_disable_cur1); 328 dml_print("DML: ===================================== \n"); 329 } 330 331 void dml_print_dml_policy(const struct dml_mode_eval_policy_st *policy) 332 { 333 (void)policy; 334 dml_print("DML: ===================================== \n"); 335 dml_print("DML: DML_MODE_EVAL_POLICY_ST\n"); 336 dml_print("DML: Policy: UseUnboundedRequesting = 0x%x\n", policy->UseUnboundedRequesting); 337 dml_print("DML: Policy: UseMinimumRequiredDCFCLK = 0x%x\n", policy->UseMinimumRequiredDCFCLK); 338 dml_print("DML: Policy: DRAMClockChangeRequirementFinal = 0x%x\n", policy->DRAMClockChangeRequirementFinal); 339 dml_print("DML: Policy: FCLKChangeRequirementFinal = 0x%x\n", policy->FCLKChangeRequirementFinal); 340 dml_print("DML: Policy: USRRetrainingRequiredFinal = 0x%x\n", policy->USRRetrainingRequiredFinal); 341 dml_print("DML: Policy: EnhancedPrefetchScheduleAccelerationFinal = 0x%x\n", policy->EnhancedPrefetchScheduleAccelerationFinal); 342 dml_print("DML: Policy: NomDETInKByteOverrideEnable = 0x%x\n", policy->NomDETInKByteOverrideEnable); 343 dml_print("DML: Policy: NomDETInKByteOverrideValue = 0x%x\n", policy->NomDETInKByteOverrideValue); 344 dml_print("DML: Policy: DCCProgrammingAssumesScanDirectionUnknownFinal = 0x%x\n", policy->DCCProgrammingAssumesScanDirectionUnknownFinal); 345 dml_print("DML: Policy: SynchronizeTimingsFinal = 0x%x\n", policy->SynchronizeTimingsFinal); 346 dml_print("DML: Policy: SynchronizeDRRDisplaysForUCLKPStateChangeFinal = 0x%x\n", policy->SynchronizeDRRDisplaysForUCLKPStateChangeFinal); 347 dml_print("DML: Policy: AssumeModeSupportAtMaxPwrStateEvenDRAMClockChangeNotSupported = 0x%x\n", policy->AssumeModeSupportAtMaxPwrStateEvenDRAMClockChangeNotSupported); 348 dml_print("DML: Policy: AssumeModeSupportAtMaxPwrStateEvenFClockChangeNotSupported = 0x%x\n", policy->AssumeModeSupportAtMaxPwrStateEvenFClockChangeNotSupported); 349 350 for (dml_uint_t i = 0; i < DCN_DML__NUM_PLANE; i++) { 351 dml_print("DML: i=%0d, Policy: MPCCombineUse = 0x%x\n", i, policy->MPCCombineUse[i]); 352 dml_print("DML: i=%0d, Policy: ODMUse = 0x%x\n", i, policy->ODMUse[i]); 353 dml_print("DML: i=%0d, Policy: ImmediateFlipRequirement = 0x%x\n", i, policy->ImmediateFlipRequirement[i]); 354 dml_print("DML: i=%0d, Policy: AllowForPStateChangeOrStutterInVBlank = 0x%x\n", i, policy->AllowForPStateChangeOrStutterInVBlank[i]); 355 } 356 dml_print("DML: ===================================== \n"); 357 } 358 359 void dml_print_mode_support(struct display_mode_lib_st *mode_lib, dml_uint_t j) 360 { 361 (void)j; 362 (void)mode_lib; 363 dml_print("DML: MODE SUPPORT: ===============================================\n"); 364 dml_print("DML: MODE SUPPORT: Voltage State %d\n", j); 365 dml_print("DML: MODE SUPPORT: Mode Supported : %s\n", mode_lib->ms.support.ModeSupport[j] == true ? "Supported" : "NOT Supported"); 366 dml_print("DML: MODE SUPPORT: Scale Ratio And Taps : %s\n", mode_lib->ms.support.ScaleRatioAndTapsSupport == true ? "Supported" : "NOT Supported"); 367 dml_print("DML: MODE SUPPORT: Source Format Pixel And Scan : %s\n", mode_lib->ms.support.SourceFormatPixelAndScanSupport == true ? "Supported" : "NOT Supported"); 368 dml_print("DML: MODE SUPPORT: Viewport Size : %s\n", mode_lib->ms.support.ViewportSizeSupport[j] == true ? "Supported" : "NOT Supported"); 369 dml_print("DML: MODE SUPPORT: Link Rate Does Not Match DP Version : %s\n", mode_lib->ms.support.LinkRateDoesNotMatchDPVersion == false ? "Supported" : "NOT Supported"); 370 dml_print("DML: MODE SUPPORT: Link Rate For Multistream Not Indicated : %s\n", mode_lib->ms.support.LinkRateForMultistreamNotIndicated == false ? "Supported" : "NOT Supported"); 371 dml_print("DML: MODE SUPPORT: BPP For Multi stream Not Indicated : %s\n", mode_lib->ms.support.BPPForMultistreamNotIndicated == false ? "Supported" : "NOT Supported"); 372 dml_print("DML: MODE SUPPORT: Multistream With HDMI Or eDP : %s\n", mode_lib->ms.support.MultistreamWithHDMIOreDP == false ? "Supported" : "NOT Supported"); 373 dml_print("DML: MODE SUPPORT: Exceeded Multistream Slots : %s\n", mode_lib->ms.support.ExceededMultistreamSlots == false ? "Supported" : "NOT Supported"); 374 dml_print("DML: MODE SUPPORT: MSO Or ODM Split With Non DP Link : %s\n", mode_lib->ms.support.MSOOrODMSplitWithNonDPLink == false ? "Supported" : "NOT Supported"); 375 dml_print("DML: MODE SUPPORT: Not Enough Lanes For MSO : %s\n", mode_lib->ms.support.NotEnoughLanesForMSO == false ? "Supported" : "NOT Supported"); 376 dml_print("DML: MODE SUPPORT: LinkCapacitySupport : %s\n", mode_lib->ms.support.LinkCapacitySupport == true ? "Supported" : "NOT Supported"); 377 dml_print("DML: MODE SUPPORT: P2IWith420 : %s\n", mode_lib->ms.support.P2IWith420 == false ? "Supported" : "NOT Supported"); 378 dml_print("DML: MODE SUPPORT: DSCOnlyIfNecessaryWithBPP : %s\n", mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP == false ? "Supported" : "NOT Supported"); 379 dml_print("DML: MODE SUPPORT: DSC422NativeNotSupported : %s\n", mode_lib->ms.support.DSC422NativeNotSupported == false ? "Supported" : "NOT Supported"); 380 dml_print("DML: MODE SUPPORT: MPCCombineMethodIncompatible : %s\n", mode_lib->ms.support.MPCCombineMethodIncompatible == false ? "Supported" : "NOT Supported"); 381 dml_print("DML: MODE SUPPORT: ODMCombineTwoToOneSupportCheckOK : %s\n", mode_lib->ms.support.ODMCombineTwoToOneSupportCheckOK == true ? "Supported" : "NOT Supported"); 382 dml_print("DML: MODE SUPPORT: ODMCombineFourToOneSupportCheckOK : %s\n", mode_lib->ms.support.ODMCombineFourToOneSupportCheckOK == true ? "Supported" : "NOT Supported"); 383 dml_print("DML: MODE SUPPORT: NotEnoughDSCUnits : %s\n", mode_lib->ms.support.NotEnoughDSCUnits == false ? "Supported" : "NOT Supported"); 384 dml_print("DML: MODE SUPPORT: NotEnoughDSCSlices : %s\n", mode_lib->ms.support.NotEnoughDSCSlices == false ? "Supported" : "NOT Supported"); 385 dml_print("DML: MODE SUPPORT: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe : %s\n", mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == false ? "Supported" : "NOT Supported"); 386 dml_print("DML: MODE SUPPORT: InvalidCombinationOfMALLUseForPStateAndStaticScreen : %s\n", mode_lib->ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen == false ? "Supported" : "NOT Supported"); 387 dml_print("DML: MODE SUPPORT: DSCCLKRequiredMoreThanSupported : %s\n", mode_lib->ms.support.DSCCLKRequiredMoreThanSupported == false ? "Supported" : "NOT Supported"); 388 dml_print("DML: MODE SUPPORT: PixelsPerLinePerDSCUnitSupport : %s\n", mode_lib->ms.support.PixelsPerLinePerDSCUnitSupport == true ? "Supported" : "NOT Supported"); 389 dml_print("DML: MODE SUPPORT: DTBCLKRequiredMoreThanSupported : %s\n", mode_lib->ms.support.DTBCLKRequiredMoreThanSupported == false ? "Supported" : "NOT Supported"); 390 dml_print("DML: MODE SUPPORT: InvalidCombinationOfMALLUseForPState : %s\n", mode_lib->ms.support.InvalidCombinationOfMALLUseForPState == false ? "Supported" : "NOT Supported"); 391 dml_print("DML: MODE SUPPORT: ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified : %s\n", mode_lib->ms.support.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified == false ? "Supported" : "NOT Supported"); 392 dml_print("DML: MODE SUPPORT: ROB Support : %s\n", mode_lib->ms.support.ROBSupport[j] == true ? "Supported" : "NOT Supported"); 393 dml_print("DML: MODE SUPPORT: DISPCLK DPPCLK Support : %s\n", mode_lib->ms.support.DISPCLK_DPPCLK_Support[j] == true ? "Supported" : "NOT Supported"); 394 dml_print("DML: MODE SUPPORT: Total Available Pipes Support : %s\n", mode_lib->ms.support.TotalAvailablePipesSupport[j] == true ? "Supported" : "NOT Supported"); 395 dml_print("DML: MODE SUPPORT: Number Of OTG Support : %s\n", mode_lib->ms.support.NumberOfOTGSupport == true ? "Supported" : "NOT Supported"); 396 dml_print("DML: MODE SUPPORT: Number Of HDMI FRL Support : %s\n", mode_lib->ms.support.NumberOfHDMIFRLSupport == true ? "Supported" : "NOT Supported"); 397 dml_print("DML: MODE SUPPORT: Number Of DP2p0 Support : %s\n", mode_lib->ms.support.NumberOfDP2p0Support == true ? "Supported" : "NOT Supported"); 398 dml_print("DML: MODE SUPPORT: Writeback Latency Support : %s\n", mode_lib->ms.support.WritebackLatencySupport == true ? "Supported" : "NOT Supported"); 399 dml_print("DML: MODE SUPPORT: Writeback Scale Ratio And Taps Support : %s\n", mode_lib->ms.support.WritebackScaleRatioAndTapsSupport == true ? "Supported" : "NOT Supported"); 400 dml_print("DML: MODE SUPPORT: Cursor Support : %s\n", mode_lib->ms.support.CursorSupport == true ? "Supported" : "NOT Supported"); 401 dml_print("DML: MODE SUPPORT: Pitch Support : %s\n", mode_lib->ms.support.PitchSupport == true ? "Supported" : "NOT Supported"); 402 dml_print("DML: MODE SUPPORT: Viewport Exceeds Surface : %s\n", mode_lib->ms.support.ViewportExceedsSurface == false ? "Supported" : "NOT Supported"); 403 dml_print("DML: MODE SUPPORT: Prefetch Supported : %s\n", mode_lib->ms.support.PrefetchSupported[j] == true ? "Supported" : "NOT Supported"); 404 dml_print("DML: MODE SUPPORT: VActive Bandwith Support : %s\n", mode_lib->ms.support.VActiveBandwithSupport[j] == true ? "Supported" : "NOT Supported"); 405 dml_print("DML: MODE SUPPORT: Dynamic Metadata Supported : %s\n", mode_lib->ms.support.DynamicMetadataSupported[j] == true ? "Supported" : "NOT Supported"); 406 dml_print("DML: MODE SUPPORT: Total Vertical Active Bandwidth Support : %s\n", mode_lib->ms.support.TotalVerticalActiveBandwidthSupport[j] == true ? "Supported" : "NOT Supported"); 407 dml_print("DML: MODE SUPPORT: VRatio In Prefetch Supported : %s\n", mode_lib->ms.support.VRatioInPrefetchSupported[j] == true ? "Supported" : "NOT Supported"); 408 dml_print("DML: MODE SUPPORT: PTE Buffer Size Not Exceeded : %s\n", mode_lib->ms.support.PTEBufferSizeNotExceeded[j] == true ? "Supported" : "NOT Supported"); 409 dml_print("DML: MODE SUPPORT: DCC Meta Buffer Size Not Exceeded : %s\n", mode_lib->ms.support.DCCMetaBufferSizeNotExceeded[j] == true ? "Supported" : "NOT Supported"); 410 dml_print("DML: MODE SUPPORT: Non supported DSC Input BPC : %s\n", mode_lib->ms.support.NonsupportedDSCInputBPC == false ? "Supported" : "NOT Supported"); 411 dml_print("DML: MODE SUPPORT: Exceeded MALL Size : %s\n", mode_lib->ms.support.ExceededMALLSize == false ? "Supported" : "NOT Supported"); 412 dml_print("DML: MODE SUPPORT: Host VM or Immediate Flip Supported : %s\n", ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == false && !mode_lib->scratch.dml_core_mode_support_locals.ImmediateFlipRequiredFinal) || mode_lib->ms.support.ImmediateFlipSupportedForState[j]) ? "Supported" : "NOT Supported"); 413 dml_print("DML: MODE SUPPORT: dram clock change support : %s\n", mode_lib->scratch.dml_core_mode_support_locals.dram_clock_change_support == true ? "Supported" : "NOT Supported"); 414 dml_print("DML: MODE SUPPORT: f_clock change support : %s\n", mode_lib->scratch.dml_core_mode_support_locals.f_clock_change_support == true ? "Supported" : "NOT Supported"); 415 dml_print("DML: MODE SUPPORT: USR Retraining Support : %s\n", (!mode_lib->ms.policy.USRRetrainingRequiredFinal || &mode_lib->ms.support.USRRetrainingSupport[j]) ? "Supported" : "NOT Supported"); 416 dml_print("DML: MODE SUPPORT: ===============================================\n"); 417 } 418 419 void dml_print_dml_mode_support_info(const struct dml_mode_support_info_st *support, dml_bool_t fail_only) 420 { 421 dml_print("DML: ===================================== \n"); 422 dml_print("DML: DML_MODE_SUPPORT_INFO_ST\n"); 423 if (!fail_only || support->ModeIsSupported == 0) 424 dml_print("DML: support: ModeIsSupported = 0x%x\n", support->ModeIsSupported); 425 if (!fail_only || support->ImmediateFlipSupport == 0) 426 dml_print("DML: support: ImmediateFlipSupport = 0x%x\n", support->ImmediateFlipSupport); 427 if (!fail_only || support->WritebackLatencySupport == 0) 428 dml_print("DML: support: WritebackLatencySupport = 0x%x\n", support->WritebackLatencySupport); 429 if (!fail_only || support->ScaleRatioAndTapsSupport == 0) 430 dml_print("DML: support: ScaleRatioAndTapsSupport = 0x%x\n", support->ScaleRatioAndTapsSupport); 431 if (!fail_only || support->SourceFormatPixelAndScanSupport == 0) 432 dml_print("DML: support: SourceFormatPixelAndScanSupport = 0x%x\n", support->SourceFormatPixelAndScanSupport); 433 if (!fail_only || support->MPCCombineMethodIncompatible == 1) 434 dml_print("DML: support: MPCCombineMethodIncompatible = 0x%x\n", support->MPCCombineMethodIncompatible); 435 if (!fail_only || support->P2IWith420 == 1) 436 dml_print("DML: support: P2IWith420 = 0x%x\n", support->P2IWith420); 437 if (!fail_only || support->DSCOnlyIfNecessaryWithBPP == 1) 438 dml_print("DML: support: DSCOnlyIfNecessaryWithBPP = 0x%x\n", support->DSCOnlyIfNecessaryWithBPP); 439 if (!fail_only || support->DSC422NativeNotSupported == 1) 440 dml_print("DML: support: DSC422NativeNotSupported = 0x%x\n", support->DSC422NativeNotSupported); 441 if (!fail_only || support->LinkRateDoesNotMatchDPVersion == 1) 442 dml_print("DML: support: LinkRateDoesNotMatchDPVersion = 0x%x\n", support->LinkRateDoesNotMatchDPVersion); 443 if (!fail_only || support->LinkRateForMultistreamNotIndicated == 1) 444 dml_print("DML: support: LinkRateForMultistreamNotIndicated = 0x%x\n", support->LinkRateForMultistreamNotIndicated); 445 if (!fail_only || support->BPPForMultistreamNotIndicated == 1) 446 dml_print("DML: support: BPPForMultistreamNotIndicated = 0x%x\n", support->BPPForMultistreamNotIndicated); 447 if (!fail_only || support->MultistreamWithHDMIOreDP == 1) 448 dml_print("DML: support: MultistreamWithHDMIOreDP = 0x%x\n", support->MultistreamWithHDMIOreDP); 449 if (!fail_only || support->MSOOrODMSplitWithNonDPLink == 1) 450 dml_print("DML: support: MSOOrODMSplitWithNonDPLink = 0x%x\n", support->MSOOrODMSplitWithNonDPLink); 451 if (!fail_only || support->NotEnoughLanesForMSO == 1) 452 dml_print("DML: support: NotEnoughLanesForMSO = 0x%x\n", support->NotEnoughLanesForMSO); 453 if (!fail_only || support->NumberOfOTGSupport == 0) 454 dml_print("DML: support: NumberOfOTGSupport = 0x%x\n", support->NumberOfOTGSupport); 455 if (!fail_only || support->NumberOfHDMIFRLSupport == 0) 456 dml_print("DML: support: NumberOfHDMIFRLSupport = 0x%x\n", support->NumberOfHDMIFRLSupport); 457 if (!fail_only || support->NumberOfDP2p0Support == 0) 458 dml_print("DML: support: NumberOfDP2p0Support = 0x%x\n", support->NumberOfDP2p0Support); 459 if (!fail_only || support->NonsupportedDSCInputBPC == 1) 460 dml_print("DML: support: NonsupportedDSCInputBPC = 0x%x\n", support->NonsupportedDSCInputBPC); 461 if (!fail_only || support->WritebackScaleRatioAndTapsSupport == 0) 462 dml_print("DML: support: WritebackScaleRatioAndTapsSupport = 0x%x\n", support->WritebackScaleRatioAndTapsSupport); 463 if (!fail_only || support->CursorSupport == 0) 464 dml_print("DML: support: CursorSupport = 0x%x\n", support->CursorSupport); 465 if (!fail_only || support->PitchSupport == 0) 466 dml_print("DML: support: PitchSupport = 0x%x\n", support->PitchSupport); 467 if (!fail_only || support->ViewportExceedsSurface == 1) 468 dml_print("DML: support: ViewportExceedsSurface = 0x%x\n", support->ViewportExceedsSurface); 469 if (!fail_only || support->ExceededMALLSize == 1) 470 dml_print("DML: support: ExceededMALLSize = 0x%x\n", support->ExceededMALLSize); 471 if (!fail_only || support->EnoughWritebackUnits == 0) 472 dml_print("DML: support: EnoughWritebackUnits = 0x%x\n", support->EnoughWritebackUnits); 473 if (!fail_only || support->ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified == 1) 474 dml_print("DML: support: ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified = 0x%x\n", support->ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified); 475 if (!fail_only || support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == 1) 476 dml_print("DML: support: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = 0x%x\n", support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe); 477 if (!fail_only || support->InvalidCombinationOfMALLUseForPStateAndStaticScreen == 1) 478 dml_print("DML: support: InvalidCombinationOfMALLUseForPStateAndStaticScreen = 0x%x\n", support->InvalidCombinationOfMALLUseForPStateAndStaticScreen); 479 if (!fail_only || support->InvalidCombinationOfMALLUseForPState == 1) 480 dml_print("DML: support: InvalidCombinationOfMALLUseForPState = 0x%x\n", support->InvalidCombinationOfMALLUseForPState); 481 482 if (!fail_only || support->ExceededMultistreamSlots == 1) 483 dml_print("DML: support: ExceededMultistreamSlots = 0x%x\n", support->ExceededMultistreamSlots); 484 if (!fail_only || support->ODMCombineTwoToOneSupportCheckOK == 0) 485 dml_print("DML: support: ODMCombineTwoToOneSupportCheckOK = 0x%x\n", support->ODMCombineTwoToOneSupportCheckOK); 486 if (!fail_only || support->ODMCombineFourToOneSupportCheckOK == 0) 487 dml_print("DML: support: ODMCombineFourToOneSupportCheckOK = 0x%x\n", support->ODMCombineFourToOneSupportCheckOK); 488 if (!fail_only || support->NotEnoughDSCUnits == 1) 489 dml_print("DML: support: NotEnoughDSCUnits = 0x%x\n", support->NotEnoughDSCUnits); 490 if (!fail_only || support->NotEnoughDSCSlices == 1) 491 dml_print("DML: support: NotEnoughDSCSlices = 0x%x\n", support->NotEnoughDSCSlices); 492 if (!fail_only || support->PixelsPerLinePerDSCUnitSupport == 0) 493 dml_print("DML: support: PixelsPerLinePerDSCUnitSupport = 0x%x\n", support->PixelsPerLinePerDSCUnitSupport); 494 if (!fail_only || support->DSCCLKRequiredMoreThanSupported == 1) 495 dml_print("DML: support: DSCCLKRequiredMoreThanSupported = 0x%x\n", support->DSCCLKRequiredMoreThanSupported); 496 if (!fail_only || support->DTBCLKRequiredMoreThanSupported == 1) 497 dml_print("DML: support: DTBCLKRequiredMoreThanSupported = 0x%x\n", support->DTBCLKRequiredMoreThanSupported); 498 if (!fail_only || support->LinkCapacitySupport == 0) 499 dml_print("DML: support: LinkCapacitySupport = 0x%x\n", support->LinkCapacitySupport); 500 501 for (dml_uint_t j = 0; j < 2; j++) { 502 if (!fail_only || support->DRAMClockChangeSupport[j] == dml_dram_clock_change_unsupported) 503 dml_print("DML: support: combine=%d, DRAMClockChangeSupport = %d\n", j, support->DRAMClockChangeSupport[j]); 504 if (!fail_only || support->FCLKChangeSupport[j] == dml_fclock_change_unsupported) 505 dml_print("DML: support: combine=%d, FCLKChangeSupport = %d\n", j, support->FCLKChangeSupport[j]); 506 if (!fail_only || support->ROBSupport[j] == 0) 507 dml_print("DML: support: combine=%d, ROBSupport = %d\n", j, support->ROBSupport[j]); 508 if (!fail_only || support->PTEBufferSizeNotExceeded[j] == 0) 509 dml_print("DML: support: combine=%d, PTEBufferSizeNotExceeded = %d\n", j, support->PTEBufferSizeNotExceeded[j]); 510 if (!fail_only || support->DCCMetaBufferSizeNotExceeded[j] == 0) 511 dml_print("DML: support: combine=%d, DCCMetaBufferSizeNotExceeded = %d\n", j, support->DCCMetaBufferSizeNotExceeded[j]); 512 if (!fail_only || support->TotalVerticalActiveBandwidthSupport[j] == 0) 513 dml_print("DML: support: combine=%d, TotalVerticalActiveBandwidthSupport = %d\n", j, support->TotalVerticalActiveBandwidthSupport[j]); 514 if (!fail_only || support->USRRetrainingSupport[j] == 0) 515 dml_print("DML: support: combine=%d, USRRetrainingSupport = %d\n", j, support->USRRetrainingSupport[j]); 516 if (!fail_only || support->VActiveBandwithSupport[j] == 0) 517 dml_print("DML: support: combine=%d, VActiveBandwithSupport = %d\n", j, support->VActiveBandwithSupport[j]); 518 if (!fail_only || support->PrefetchSupported[j] == 0) 519 dml_print("DML: support: combine=%d, PrefetchSupported = %d\n", j, support->PrefetchSupported[j]); 520 if (!fail_only || support->DynamicMetadataSupported[j] == 0) 521 dml_print("DML: support: combine=%d, DynamicMetadataSupported = %d\n", j, support->DynamicMetadataSupported[j]); 522 if (!fail_only || support->VRatioInPrefetchSupported[j] == 0) 523 dml_print("DML: support: combine=%d, VRatioInPrefetchSupported = %d\n", j, support->VRatioInPrefetchSupported[j]); 524 if (!fail_only || support->DISPCLK_DPPCLK_Support[j] == 0) 525 dml_print("DML: support: combine=%d, DISPCLK_DPPCLK_Support = %d\n", j, support->DISPCLK_DPPCLK_Support[j]); 526 if (!fail_only || support->TotalAvailablePipesSupport[j] == 0) 527 dml_print("DML: support: combine=%d, TotalAvailablePipesSupport = %d\n", j, support->TotalAvailablePipesSupport[j]); 528 if (!fail_only || support->ModeSupport[j] == 0) 529 dml_print("DML: support: combine=%d, ModeSupport = %d\n", j, support->ModeSupport[j]); 530 if (!fail_only || support->ViewportSizeSupport[j] == 0) 531 dml_print("DML: support: combine=%d, ViewportSizeSupport = %d\n", j, support->ViewportSizeSupport[j]); 532 if (!fail_only || support->ImmediateFlipSupportedForState[j] == 0) 533 dml_print("DML: support: combine=%d, ImmediateFlipSupportedForState = %d\n", j, support->ImmediateFlipSupportedForState[j]); 534 } 535 } 536 537 void dml_print_dml_display_cfg_timing(const struct dml_timing_cfg_st *timing, dml_uint_t num_plane) 538 { 539 (void)timing; 540 for (dml_uint_t i = 0; i < num_plane; i++) { 541 dml_print("DML: timing_cfg: plane=%d, HTotal = %d\n", i, timing->HTotal[i]); 542 dml_print("DML: timing_cfg: plane=%d, VTotal = %d\n", i, timing->VTotal[i]); 543 dml_print("DML: timing_cfg: plane=%d, HActive = %d\n", i, timing->HActive[i]); 544 dml_print("DML: timing_cfg: plane=%d, VActive = %d\n", i, timing->VActive[i]); 545 dml_print("DML: timing_cfg: plane=%d, VFrontPorch = %d\n", i, timing->VFrontPorch[i]); 546 dml_print("DML: timing_cfg: plane=%d, VBlankNom = %d\n", i, timing->VBlankNom[i]); 547 dml_print("DML: timing_cfg: plane=%d, RefreshRate = %d\n", i, timing->RefreshRate[i]); 548 dml_print("DML: timing_cfg: plane=%d, PixelClock = %f\n", i, timing->PixelClock[i]); 549 dml_print("DML: timing_cfg: plane=%d, Interlace = %d\n", i, timing->Interlace[i]); 550 dml_print("DML: timing_cfg: plane=%d, DRRDisplay = %d\n", i, timing->DRRDisplay[i]); 551 } 552 } 553 554 void dml_print_dml_display_cfg_plane(const struct dml_plane_cfg_st *plane, dml_uint_t num_plane) 555 { 556 (void)plane; 557 dml_print("DML: plane_cfg: num_plane = %d\n", num_plane); 558 dml_print("DML: plane_cfg: GPUVMEnable = %d\n", plane->GPUVMEnable); 559 dml_print("DML: plane_cfg: HostVMEnable = %d\n", plane->HostVMEnable); 560 dml_print("DML: plane_cfg: GPUVMMaxPageTableLevels = %d\n", plane->GPUVMMaxPageTableLevels); 561 dml_print("DML: plane_cfg: HostVMMaxPageTableLevels = %d\n", plane->HostVMMaxPageTableLevels); 562 563 for (dml_uint_t i = 0; i < num_plane; i++) { 564 dml_print("DML: plane_cfg: plane=%d, GPUVMMinPageSizeKBytes = %d\n", i, plane->GPUVMMinPageSizeKBytes[i]); 565 dml_print("DML: plane_cfg: plane=%d, ForceOneRowForFrame = %d\n", i, plane->ForceOneRowForFrame[i]); 566 dml_print("DML: plane_cfg: plane=%d, PTEBufferModeOverrideEn = %d\n", i, plane->PTEBufferModeOverrideEn[i]); 567 dml_print("DML: plane_cfg: plane=%d, PTEBufferMode = %d\n", i, plane->PTEBufferMode[i]); 568 dml_print("DML: plane_cfg: plane=%d, DETSizeOverride = %d\n", i, plane->DETSizeOverride[i]); 569 dml_print("DML: plane_cfg: plane=%d, UseMALLForStaticScreen = %d\n", i, plane->UseMALLForStaticScreen[i]); 570 dml_print("DML: plane_cfg: plane=%d, UseMALLForPStateChange = %d\n", i, plane->UseMALLForPStateChange[i]); 571 dml_print("DML: plane_cfg: plane=%d, BlendingAndTiming = %d\n", i, plane->BlendingAndTiming[i]); 572 dml_print("DML: plane_cfg: plane=%d, ViewportWidth = %d\n", i, plane->ViewportWidth[i]); 573 dml_print("DML: plane_cfg: plane=%d, ViewportHeight = %d\n", i, plane->ViewportHeight[i]); 574 dml_print("DML: plane_cfg: plane=%d, ViewportWidthChroma = %d\n", i, plane->ViewportWidthChroma[i]); 575 dml_print("DML: plane_cfg: plane=%d, ViewportHeightChroma = %d\n", i, plane->ViewportHeightChroma[i]); 576 dml_print("DML: plane_cfg: plane=%d, ViewportXStart = %d\n", i, plane->ViewportXStart[i]); 577 dml_print("DML: plane_cfg: plane=%d, ViewportXStartC = %d\n", i, plane->ViewportXStartC[i]); 578 dml_print("DML: plane_cfg: plane=%d, ViewportYStart = %d\n", i, plane->ViewportYStart[i]); 579 dml_print("DML: plane_cfg: plane=%d, ViewportYStartC = %d\n", i, plane->ViewportYStartC[i]); 580 dml_print("DML: plane_cfg: plane=%d, ViewportStationary = %d\n", i, plane->ViewportStationary[i]); 581 dml_print("DML: plane_cfg: plane=%d, ScalerEnabled = %d\n", i, plane->ScalerEnabled[i]); 582 dml_print("DML: plane_cfg: plane=%d, HRatio = %3.2f\n", i, plane->HRatio[i]); 583 dml_print("DML: plane_cfg: plane=%d, VRatio = %3.2f\n", i, plane->VRatio[i]); 584 dml_print("DML: plane_cfg: plane=%d, HRatioChroma = %3.2f\n", i, plane->HRatioChroma[i]); 585 dml_print("DML: plane_cfg: plane=%d, VRatioChroma = %3.2f\n", i, plane->VRatioChroma[i]); 586 dml_print("DML: plane_cfg: plane=%d, HTaps = %d\n", i, plane->HTaps[i]); 587 dml_print("DML: plane_cfg: plane=%d, VTaps = %d\n", i, plane->VTaps[i]); 588 dml_print("DML: plane_cfg: plane=%d, HTapsChroma = %d\n", i, plane->HTapsChroma[i]); 589 dml_print("DML: plane_cfg: plane=%d, VTapsChroma = %d\n", i, plane->VTapsChroma[i]); 590 dml_print("DML: plane_cfg: plane=%d, LBBitPerPixel = %d\n", i, plane->LBBitPerPixel[i]); 591 dml_print("DML: plane_cfg: plane=%d, SourceScan = %d\n", i, plane->SourceScan[i]); 592 dml_print("DML: plane_cfg: plane=%d, ScalerRecoutWidth = %d\n", i, plane->ScalerRecoutWidth[i]); 593 dml_print("DML: plane_cfg: plane=%d, NumberOfCursors = %d\n", i, plane->NumberOfCursors[i]); 594 dml_print("DML: plane_cfg: plane=%d, CursorWidth = %d\n", i, plane->CursorWidth[i]); 595 dml_print("DML: plane_cfg: plane=%d, CursorBPP = %d\n", i, plane->CursorBPP[i]); 596 597 dml_print("DML: plane_cfg: plane=%d, DynamicMetadataEnable = %d\n", i, plane->DynamicMetadataEnable[i]); 598 dml_print("DML: plane_cfg: plane=%d, DynamicMetadataLinesBeforeActiveRequired = %d\n", i, plane->DynamicMetadataLinesBeforeActiveRequired[i]); 599 dml_print("DML: plane_cfg: plane=%d, DynamicMetadataTransmittedBytes = %d\n", i, plane->DynamicMetadataTransmittedBytes[i]); 600 } 601 } 602 603 void dml_print_dml_display_cfg_surface(const struct dml_surface_cfg_st *surface, dml_uint_t num_plane) 604 { 605 (void)surface; 606 for (dml_uint_t i = 0; i < num_plane; i++) { 607 dml_print("DML: surface_cfg: plane=%d, PitchY = %d\n", i, surface->PitchY[i]); 608 dml_print("DML: surface_cfg: plane=%d, SurfaceWidthY = %d\n", i, surface->SurfaceWidthY[i]); 609 dml_print("DML: surface_cfg: plane=%d, SurfaceHeightY = %d\n", i, surface->SurfaceHeightY[i]); 610 dml_print("DML: surface_cfg: plane=%d, PitchC = %d\n", i, surface->PitchC[i]); 611 dml_print("DML: surface_cfg: plane=%d, SurfaceWidthC = %d\n", i, surface->SurfaceWidthC[i]); 612 dml_print("DML: surface_cfg: plane=%d, SurfaceHeightC = %d\n", i, surface->SurfaceHeightC[i]); 613 dml_print("DML: surface_cfg: plane=%d, DCCEnable = %d\n", i, surface->DCCEnable[i]); 614 dml_print("DML: surface_cfg: plane=%d, DCCMetaPitchY = %d\n", i, surface->DCCMetaPitchY[i]); 615 dml_print("DML: surface_cfg: plane=%d, DCCMetaPitchC = %d\n", i, surface->DCCMetaPitchC[i]); 616 dml_print("DML: surface_cfg: plane=%d, DCCRateLuma = %f\n", i, surface->DCCRateLuma[i]); 617 dml_print("DML: surface_cfg: plane=%d, DCCRateChroma = %f\n", i, surface->DCCRateChroma[i]); 618 dml_print("DML: surface_cfg: plane=%d, DCCFractionOfZeroSizeRequestsLuma = %f\n", i, surface->DCCFractionOfZeroSizeRequestsLuma[i]); 619 dml_print("DML: surface_cfg: plane=%d, DCCFractionOfZeroSizeRequestsChroma= %f\n", i, surface->DCCFractionOfZeroSizeRequestsChroma[i]); 620 } 621 } 622 623 void dml_print_dml_display_cfg_hw_resource(const struct dml_hw_resource_st *hw, dml_uint_t num_plane) 624 { 625 (void)hw; 626 for (dml_uint_t i = 0; i < num_plane; i++) { 627 dml_print("DML: hw_resource: plane=%d, ODMMode = %d\n", i, hw->ODMMode[i]); 628 dml_print("DML: hw_resource: plane=%d, DPPPerSurface = %d\n", i, hw->DPPPerSurface[i]); 629 dml_print("DML: hw_resource: plane=%d, DSCEnabled = %d\n", i, hw->DSCEnabled[i]); 630 dml_print("DML: hw_resource: plane=%d, NumberOfDSCSlices = %d\n", i, hw->NumberOfDSCSlices[i]); 631 } 632 dml_print("DML: hw_resource: DLGRefClkFreqMHz = %f\n", hw->DLGRefClkFreqMHz); 633 } 634 635 __DML_DLL_EXPORT__ void dml_print_soc_state_bounding_box(const struct soc_state_bounding_box_st *state) 636 { 637 (void)state; 638 dml_print("DML: state_bbox: socclk_mhz = %f\n", state->socclk_mhz); 639 dml_print("DML: state_bbox: dscclk_mhz = %f\n", state->dscclk_mhz); 640 dml_print("DML: state_bbox: phyclk_mhz = %f\n", state->phyclk_mhz); 641 dml_print("DML: state_bbox: phyclk_d18_mhz = %f\n", state->phyclk_d18_mhz); 642 dml_print("DML: state_bbox: phyclk_d32_mhz = %f\n", state->phyclk_d32_mhz); 643 dml_print("DML: state_bbox: dtbclk_mhz = %f\n", state->dtbclk_mhz); 644 dml_print("DML: state_bbox: dispclk_mhz = %f\n", state->dispclk_mhz); 645 dml_print("DML: state_bbox: dppclk_mhz = %f\n", state->dppclk_mhz); 646 dml_print("DML: state_bbox: fabricclk_mhz = %f\n", state->fabricclk_mhz); 647 dml_print("DML: state_bbox: dcfclk_mhz = %f\n", state->dcfclk_mhz); 648 dml_print("DML: state_bbox: dram_speed_mts = %f\n", state->dram_speed_mts); 649 dml_print("DML: state_bbox: urgent_latency_pixel_data_only_us = %f\n", state->urgent_latency_pixel_data_only_us); 650 dml_print("DML: state_bbox: urgent_latency_pixel_mixed_with_vm_data_us = %f\n", state->urgent_latency_pixel_mixed_with_vm_data_us); 651 dml_print("DML: state_bbox: urgent_latency_vm_data_only_us = %f\n", state->urgent_latency_vm_data_only_us); 652 dml_print("DML: state_bbox: writeback_latency_us = %f\n", state->writeback_latency_us); 653 dml_print("DML: state_bbox: urgent_latency_adjustment_fabric_clock_component_us = %f\n", state->urgent_latency_adjustment_fabric_clock_component_us); 654 dml_print("DML: state_bbox: urgent_latency_adjustment_fabric_clock_reference_mhz= %f\n", state->urgent_latency_adjustment_fabric_clock_reference_mhz); 655 dml_print("DML: state_bbox: sr_exit_time_us = %f\n", state->sr_exit_time_us); 656 dml_print("DML: state_bbox: sr_enter_plus_exit_time_us = %f\n", state->sr_enter_plus_exit_time_us); 657 dml_print("DML: state_bbox: sr_exit_z8_time_us = %f\n", state->sr_exit_z8_time_us); 658 dml_print("DML: state_bbox: sr_enter_plus_exit_z8_time_us = %f\n", state->sr_enter_plus_exit_z8_time_us); 659 dml_print("DML: state_bbox: dram_clock_change_latency_us = %f\n", state->dram_clock_change_latency_us); 660 dml_print("DML: state_bbox: fclk_change_latency_us = %f\n", state->fclk_change_latency_us); 661 dml_print("DML: state_bbox: usr_retraining_latency_us = %f\n", state->usr_retraining_latency_us); 662 dml_print("DML: state_bbox: use_ideal_dram_bw_strobe = %d\n", state->use_ideal_dram_bw_strobe); 663 } 664 665 __DML_DLL_EXPORT__ void dml_print_soc_bounding_box(const struct soc_bounding_box_st *soc) 666 { 667 (void)soc; 668 dml_print("DML: soc_bbox: dprefclk_mhz = %f\n", soc->dprefclk_mhz); 669 dml_print("DML: soc_bbox: xtalclk_mhz = %f\n", soc->xtalclk_mhz); 670 dml_print("DML: soc_bbox: pcierefclk_mhz = %f\n", soc->pcierefclk_mhz); 671 dml_print("DML: soc_bbox: refclk_mhz = %f\n", soc->refclk_mhz); 672 dml_print("DML: soc_bbox: amclk_mhz = %f\n", soc->amclk_mhz); 673 674 dml_print("DML: soc_bbox: max_outstanding_reqs = %d\n", soc->max_outstanding_reqs); 675 dml_print("DML: soc_bbox: pct_ideal_sdp_bw_after_urgent = %f\n", soc->pct_ideal_sdp_bw_after_urgent); 676 dml_print("DML: soc_bbox: pct_ideal_fabric_bw_after_urgent = %f\n", soc->pct_ideal_fabric_bw_after_urgent); 677 dml_print("DML: soc_bbox: pct_ideal_dram_bw_after_urgent_pixel_only = %f\n", soc->pct_ideal_dram_bw_after_urgent_pixel_only); 678 dml_print("DML: soc_bbox: pct_ideal_dram_bw_after_urgent_pixel_and_vm = %f\n", soc->pct_ideal_dram_bw_after_urgent_pixel_and_vm); 679 dml_print("DML: soc_bbox: pct_ideal_dram_bw_after_urgent_vm_only = %f\n", soc->pct_ideal_dram_bw_after_urgent_vm_only); 680 dml_print("DML: soc_bbox: pct_ideal_dram_bw_after_urgent_strobe = %f\n", soc->pct_ideal_dram_bw_after_urgent_strobe); 681 dml_print("DML: soc_bbox: max_avg_sdp_bw_use_normal_percent = %f\n", soc->max_avg_sdp_bw_use_normal_percent); 682 dml_print("DML: soc_bbox: max_avg_fabric_bw_use_normal_percent = %f\n", soc->max_avg_fabric_bw_use_normal_percent); 683 dml_print("DML: soc_bbox: max_avg_dram_bw_use_normal_percent = %f\n", soc->max_avg_dram_bw_use_normal_percent); 684 dml_print("DML: soc_bbox: max_avg_dram_bw_use_normal_strobe_percent = %f\n", soc->max_avg_dram_bw_use_normal_strobe_percent); 685 dml_print("DML: soc_bbox: round_trip_ping_latency_dcfclk_cycles = %d\n", soc->round_trip_ping_latency_dcfclk_cycles); 686 dml_print("DML: soc_bbox: urgent_out_of_order_return_per_channel_pixel_only_bytes = %d\n", soc->urgent_out_of_order_return_per_channel_pixel_only_bytes); 687 dml_print("DML: soc_bbox: urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = %d\n", soc->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes); 688 dml_print("DML: soc_bbox: urgent_out_of_order_return_per_channel_vm_only_bytes = %d\n", soc->urgent_out_of_order_return_per_channel_vm_only_bytes); 689 dml_print("DML: soc_bbox: num_chans = %d\n", soc->num_chans); 690 dml_print("DML: soc_bbox: return_bus_width_bytes = %d\n", soc->return_bus_width_bytes); 691 dml_print("DML: soc_bbox: dram_channel_width_bytes = %d\n", soc->dram_channel_width_bytes); 692 dml_print("DML: soc_bbox: fabric_datapath_to_dcn_data_return_bytes = %d\n", soc->fabric_datapath_to_dcn_data_return_bytes); 693 dml_print("DML: soc_bbox: hostvm_min_page_size_kbytes = %d\n", soc->hostvm_min_page_size_kbytes); 694 dml_print("DML: soc_bbox: gpuvm_min_page_size_kbytes = %d\n", soc->gpuvm_min_page_size_kbytes); 695 dml_print("DML: soc_bbox: phy_downspread_percent = %f\n", soc->phy_downspread_percent); 696 dml_print("DML: soc_bbox: dcn_downspread_percent = %f\n", soc->dcn_downspread_percent); 697 dml_print("DML: soc_bbox: smn_latency_us = %f\n", soc->smn_latency_us); 698 dml_print("DML: soc_bbox: mall_allocated_for_dcn_mbytes = %d\n", soc->mall_allocated_for_dcn_mbytes); 699 dml_print("DML: soc_bbox: dispclk_dppclk_vco_speed_mhz = %f\n", soc->dispclk_dppclk_vco_speed_mhz); 700 dml_print("DML: soc_bbox: do_urgent_latency_adjustment = %d\n", soc->do_urgent_latency_adjustment); 701 } 702 703 __DML_DLL_EXPORT__ void dml_print_clk_cfg(const struct dml_clk_cfg_st *clk_cfg) 704 { 705 (void)clk_cfg; 706 dml_print("DML: clk_cfg: 0-use_required, 1-use pipe.clks_cfg, 2-use state bbox\n"); 707 dml_print("DML: clk_cfg: dcfclk_option = %d\n", clk_cfg->dcfclk_option); 708 dml_print("DML: clk_cfg: dispclk_option = %d\n", clk_cfg->dispclk_option); 709 710 dml_print("DML: clk_cfg: dcfclk_mhz = %f\n", clk_cfg->dcfclk_mhz); 711 dml_print("DML: clk_cfg: dispclk_mhz = %f\n", clk_cfg->dispclk_mhz); 712 713 for (dml_uint_t i = 0; i < DCN_DML__NUM_PLANE; i++) { 714 dml_print("DML: clk_cfg: i=%d, dppclk_option = %d\n", i, clk_cfg->dppclk_option[i]); 715 dml_print("DML: clk_cfg: i=%d, dppclk_mhz = %f\n", i, clk_cfg->dppclk_mhz[i]); 716 } 717 } 718 719 dml_bool_t dml_is_vertical_rotation(enum dml_rotation_angle Scan) 720 { 721 dml_bool_t is_vert = false; 722 if (Scan == dml_rotation_90 || Scan == dml_rotation_90m || Scan == dml_rotation_270 || Scan == dml_rotation_270m) { 723 is_vert = true; 724 } else { 725 is_vert = false; 726 } 727 return is_vert; 728 } // dml_is_vertical_rotation 729 730 dml_uint_t dml_get_cursor_bit_per_pixel(enum dml_cursor_bpp ebpp) 731 { 732 switch (ebpp) { 733 case dml_cur_2bit: 734 return 2; 735 case dml_cur_32bit: 736 return 32; 737 case dml_cur_64bit: 738 return 64; 739 default: 740 return 0; 741 } 742 } 743 744 /// @brief Determine the physical pipe to logical plane mapping using the display_cfg 745 dml_uint_t dml_get_num_active_planes(const struct dml_display_cfg_st *display_cfg) 746 { 747 dml_uint_t num_active_planes = 0; 748 749 for (dml_uint_t k = 0; k < __DML_NUM_PLANES__; k++) { 750 if (display_cfg->plane.ViewportWidth[k] > 0) 751 num_active_planes = num_active_planes + 1; 752 } 753 #ifdef __DML_VBA_DEBUG__ 754 dml_print("DML::%s: num_active_planes = %d\n", __func__, num_active_planes); 755 #endif 756 return num_active_planes; 757 } 758 759 /// @brief Determine the physical pipe to logical plane mapping using the display_cfg 760 dml_uint_t dml_get_num_active_pipes(const struct dml_display_cfg_st *display_cfg) 761 { 762 dml_uint_t num_active_pipes = 0; 763 764 for (dml_uint_t j = 0; j < dml_get_num_active_planes(display_cfg); j++) { 765 num_active_pipes = num_active_pipes + display_cfg->hw.DPPPerSurface[j]; 766 } 767 768 #ifdef __DML_VBA_DEBUG__ 769 dml_print("DML::%s: num_active_pipes = %d\n", __func__, num_active_pipes); 770 #endif 771 return num_active_pipes; 772 } 773 774 dml_uint_t dml_get_plane_idx(const struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx) 775 { 776 dml_uint_t plane_idx = mode_lib->mp.pipe_plane[pipe_idx]; 777 return plane_idx; 778 } 779 780 dml_uint_t dml_get_pipe_idx(const struct display_mode_lib_st *mode_lib, dml_uint_t plane_idx) 781 { 782 dml_uint_t pipe_idx = 0; 783 dml_bool_t pipe_found = 0; 784 785 ASSERT(plane_idx < __DML_NUM_PLANES__); 786 787 for (dml_uint_t i = 0; i < __DML_NUM_PLANES__; i++) { 788 if (plane_idx == mode_lib->mp.pipe_plane[i]) { 789 pipe_idx = i; 790 pipe_found = 1; 791 break; 792 } 793 } 794 ASSERT(pipe_found != 0); 795 796 return pipe_idx; 797 } 798 799 void dml_calc_pipe_plane_mapping(const struct dml_hw_resource_st *hw, dml_uint_t *pipe_plane) 800 { 801 dml_uint_t pipe_idx = 0; 802 803 for (dml_uint_t k = 0; k < __DML_NUM_PLANES__; ++k) { 804 pipe_plane[k] = __DML_PIPE_NO_PLANE__; 805 } 806 807 for (dml_uint_t plane_idx = 0; plane_idx < __DML_NUM_PLANES__; plane_idx++) { 808 for (dml_uint_t i = 0; i < hw->DPPPerSurface[plane_idx]; i++) { 809 pipe_plane[pipe_idx] = plane_idx; 810 pipe_idx++; 811 } 812 } 813 } 814 815 816