xref: /linux/drivers/pinctrl/pinctrl-falcon.c (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  linux/drivers/pinctrl/pinmux-falcon.c
4  *  based on linux/drivers/pinctrl/pinmux-pxa910.c
5  *
6  *  Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
7  *  Copyright (C) 2012 John Crispin <john@phrozen.org>
8  */
9 
10 #include <linux/err.h>
11 #include <linux/export.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include <linux/platform_device.h>
19 #include <linux/seq_file.h>
20 #include <linux/slab.h>
21 
22 #include "pinctrl-lantiq.h"
23 
24 #include <lantiq_soc.h>
25 
26 /* Multiplexer Control Register */
27 #define LTQ_PADC_MUX(x)         (x * 0x4)
28 /* Pull Up Enable Register */
29 #define LTQ_PADC_PUEN		0x80
30 /* Pull Down Enable Register */
31 #define LTQ_PADC_PDEN		0x84
32 /* Slew Rate Control Register */
33 #define LTQ_PADC_SRC		0x88
34 /* Drive Current Control Register */
35 #define LTQ_PADC_DCC		0x8C
36 /* Pad Control Availability Register */
37 #define LTQ_PADC_AVAIL          0xF0
38 
39 #define pad_r32(p, reg)		ltq_r32(p + reg)
40 #define pad_w32(p, val, reg)	ltq_w32(val, p + reg)
41 #define pad_w32_mask(c, clear, set, reg) \
42 		pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg)
43 
44 #define pad_getbit(m, r, p)	(!!(ltq_r32(m + r) & (1 << p)))
45 
46 #define PORTS			5
47 #define PINS			32
48 #define PORT(x)                 (x / PINS)
49 #define PORT_PIN(x)             (x % PINS)
50 
51 #define MFP_FALCON(a, f0, f1, f2, f3)		\
52 {						\
53 	.name = #a,				\
54 	.pin = a,				\
55 	.func = {				\
56 		FALCON_MUX_##f0,		\
57 		FALCON_MUX_##f1,		\
58 		FALCON_MUX_##f2,		\
59 		FALCON_MUX_##f3,		\
60 	},					\
61 }
62 
63 #define GRP_MUX(a, m, p)	\
64 {				\
65 	.name = a,		\
66 	.mux = FALCON_MUX_##m,	\
67 	.pins = p,		\
68 	.npins = ARRAY_SIZE(p),	\
69 }
70 
71 enum falcon_mux {
72 	FALCON_MUX_GPIO = 0,
73 	FALCON_MUX_RST,
74 	FALCON_MUX_NTR,
75 	FALCON_MUX_PPS,
76 	FALCON_MUX_MDIO,
77 	FALCON_MUX_LED,
78 	FALCON_MUX_SPI,
79 	FALCON_MUX_ASC,
80 	FALCON_MUX_I2C,
81 	FALCON_MUX_HOSTIF,
82 	FALCON_MUX_SLIC,
83 	FALCON_MUX_JTAG,
84 	FALCON_MUX_PCM,
85 	FALCON_MUX_MII,
86 	FALCON_MUX_PHY,
87 	FALCON_MUX_NONE = 0xffff,
88 };
89 
90 static struct pinctrl_pin_desc falcon_pads[PORTS * PINS];
91 static int pad_count[PORTS];
92 
lantiq_load_pin_desc(struct pinctrl_pin_desc * d,int bank,int len)93 static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len)
94 {
95 	int base = bank * PINS;
96 	int i;
97 
98 	for (i = 0; i < len; i++) {
99 		d[i].number = base + i;
100 		d[i].name = kasprintf(GFP_KERNEL, "io%d", base + i);
101 	}
102 	pad_count[bank] = len;
103 }
104 
105 static struct ltq_mfp_pin falcon_mfp[] = {
106 	/*	pin		f0	f1	f2	f3 */
107 	MFP_FALCON(GPIO0,	RST,	GPIO,   NONE,   NONE),
108 	MFP_FALCON(GPIO1,	GPIO,	GPIO,   NONE,   NONE),
109 	MFP_FALCON(GPIO2,	GPIO,	GPIO,   NONE,   NONE),
110 	MFP_FALCON(GPIO3,	GPIO,	GPIO,   NONE,   NONE),
111 	MFP_FALCON(GPIO4,	NTR,	GPIO,   NONE,   NONE),
112 	MFP_FALCON(GPIO5,	NTR,	GPIO,   PPS,    NONE),
113 	MFP_FALCON(GPIO6,	RST,	GPIO,   NONE,   NONE),
114 	MFP_FALCON(GPIO7,	MDIO,	GPIO,   NONE,   NONE),
115 	MFP_FALCON(GPIO8,	MDIO,	GPIO,   NONE,   NONE),
116 	MFP_FALCON(GPIO9,	LED,	GPIO,   NONE,   NONE),
117 	MFP_FALCON(GPIO10,	LED,	GPIO,   NONE,   NONE),
118 	MFP_FALCON(GPIO11,	LED,	GPIO,   NONE,   NONE),
119 	MFP_FALCON(GPIO12,	LED,	GPIO,   NONE,   NONE),
120 	MFP_FALCON(GPIO13,	LED,	GPIO,   NONE,   NONE),
121 	MFP_FALCON(GPIO14,	LED,	GPIO,   NONE,   NONE),
122 	MFP_FALCON(GPIO32,	ASC,	GPIO,   NONE,   NONE),
123 	MFP_FALCON(GPIO33,	ASC,	GPIO,   NONE,   NONE),
124 	MFP_FALCON(GPIO34,	SPI,	GPIO,	NONE,	NONE),
125 	MFP_FALCON(GPIO35,	SPI,	GPIO,	NONE,	NONE),
126 	MFP_FALCON(GPIO36,	SPI,	GPIO,	NONE,	NONE),
127 	MFP_FALCON(GPIO37,	SPI,	GPIO,	NONE,	NONE),
128 	MFP_FALCON(GPIO38,	SPI,	GPIO,	NONE,	NONE),
129 	MFP_FALCON(GPIO39,	I2C,	GPIO,	NONE,	NONE),
130 	MFP_FALCON(GPIO40,	I2C,	GPIO,	NONE,	NONE),
131 	MFP_FALCON(GPIO41,	HOSTIF,	GPIO,	HOSTIF,	JTAG),
132 	MFP_FALCON(GPIO42,	HOSTIF,	GPIO,	HOSTIF,	NONE),
133 	MFP_FALCON(GPIO43,	SLIC,	GPIO,	NONE,	NONE),
134 	MFP_FALCON(GPIO44,	SLIC,	GPIO,	PCM,	ASC),
135 	MFP_FALCON(GPIO45,	SLIC,	GPIO,	PCM,	ASC),
136 	MFP_FALCON(GPIO64,	MII,	GPIO,	NONE,	NONE),
137 	MFP_FALCON(GPIO65,	MII,	GPIO,	NONE,	NONE),
138 	MFP_FALCON(GPIO66,	MII,	GPIO,	NONE,	NONE),
139 	MFP_FALCON(GPIO67,	MII,	GPIO,	NONE,	NONE),
140 	MFP_FALCON(GPIO68,	MII,	GPIO,	NONE,	NONE),
141 	MFP_FALCON(GPIO69,	MII,	GPIO,	NONE,	NONE),
142 	MFP_FALCON(GPIO70,	MII,	GPIO,	NONE,	NONE),
143 	MFP_FALCON(GPIO71,	MII,	GPIO,	NONE,	NONE),
144 	MFP_FALCON(GPIO72,	MII,	GPIO,	NONE,	NONE),
145 	MFP_FALCON(GPIO73,	MII,	GPIO,	NONE,	NONE),
146 	MFP_FALCON(GPIO74,	MII,	GPIO,	NONE,	NONE),
147 	MFP_FALCON(GPIO75,	MII,	GPIO,	NONE,	NONE),
148 	MFP_FALCON(GPIO76,	MII,	GPIO,	NONE,	NONE),
149 	MFP_FALCON(GPIO77,	MII,	GPIO,	NONE,	NONE),
150 	MFP_FALCON(GPIO78,	MII,	GPIO,	NONE,	NONE),
151 	MFP_FALCON(GPIO79,	MII,	GPIO,	NONE,	NONE),
152 	MFP_FALCON(GPIO80,	MII,	GPIO,	NONE,	NONE),
153 	MFP_FALCON(GPIO81,	MII,	GPIO,	NONE,	NONE),
154 	MFP_FALCON(GPIO82,	MII,	GPIO,	NONE,	NONE),
155 	MFP_FALCON(GPIO83,	MII,	GPIO,	NONE,	NONE),
156 	MFP_FALCON(GPIO84,	MII,	GPIO,	NONE,	NONE),
157 	MFP_FALCON(GPIO85,	MII,	GPIO,	NONE,	NONE),
158 	MFP_FALCON(GPIO86,	MII,	GPIO,	NONE,	NONE),
159 	MFP_FALCON(GPIO87,	MII,	GPIO,	NONE,	NONE),
160 	MFP_FALCON(GPIO88,	PHY,	GPIO,	NONE,	NONE),
161 };
162 
163 static const unsigned pins_por[] = {GPIO0};
164 static const unsigned pins_ntr[] = {GPIO4};
165 static const unsigned pins_ntr8k[] = {GPIO5};
166 static const unsigned pins_pps[] = {GPIO5};
167 static const unsigned pins_hrst[] = {GPIO6};
168 static const unsigned pins_mdio[] = {GPIO7, GPIO8};
169 static const unsigned pins_bled[] = {GPIO9, GPIO10, GPIO11,
170 					GPIO12, GPIO13, GPIO14};
171 static const unsigned pins_asc0[] = {GPIO32, GPIO33};
172 static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36};
173 static const unsigned pins_spi_cs0[] = {GPIO37};
174 static const unsigned pins_spi_cs1[] = {GPIO38};
175 static const unsigned pins_i2c[] = {GPIO39, GPIO40};
176 static const unsigned pins_jtag[] = {GPIO41};
177 static const unsigned pins_slic[] = {GPIO43, GPIO44, GPIO45};
178 static const unsigned pins_pcm[] = {GPIO44, GPIO45};
179 static const unsigned pins_asc1[] = {GPIO44, GPIO45};
180 
181 static struct ltq_pin_group falcon_grps[] = {
182 	GRP_MUX("por", RST, pins_por),
183 	GRP_MUX("ntr", NTR, pins_ntr),
184 	GRP_MUX("ntr8k", NTR, pins_ntr8k),
185 	GRP_MUX("pps", PPS, pins_pps),
186 	GRP_MUX("hrst", RST, pins_hrst),
187 	GRP_MUX("mdio", MDIO, pins_mdio),
188 	GRP_MUX("bootled", LED, pins_bled),
189 	GRP_MUX("asc0", ASC, pins_asc0),
190 	GRP_MUX("spi", SPI, pins_spi),
191 	GRP_MUX("spi cs0", SPI, pins_spi_cs0),
192 	GRP_MUX("spi cs1", SPI, pins_spi_cs1),
193 	GRP_MUX("i2c", I2C, pins_i2c),
194 	GRP_MUX("jtag", JTAG, pins_jtag),
195 	GRP_MUX("slic", SLIC, pins_slic),
196 	GRP_MUX("pcm", PCM, pins_pcm),
197 	GRP_MUX("asc1", ASC, pins_asc1),
198 };
199 
200 static const char * const ltq_rst_grps[] = {"por", "hrst"};
201 static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k", "pps"};
202 static const char * const ltq_mdio_grps[] = {"mdio"};
203 static const char * const ltq_bled_grps[] = {"bootled"};
204 static const char * const ltq_asc_grps[] = {"asc0", "asc1"};
205 static const char * const ltq_spi_grps[] = {"spi", "spi cs0", "spi cs1"};
206 static const char * const ltq_i2c_grps[] = {"i2c"};
207 static const char * const ltq_jtag_grps[] = {"jtag"};
208 static const char * const ltq_slic_grps[] = {"slic"};
209 static const char * const ltq_pcm_grps[] = {"pcm"};
210 
211 static struct ltq_pmx_func falcon_funcs[] = {
212 	{"rst",		ARRAY_AND_SIZE(ltq_rst_grps)},
213 	{"ntr",		ARRAY_AND_SIZE(ltq_ntr_grps)},
214 	{"mdio",	ARRAY_AND_SIZE(ltq_mdio_grps)},
215 	{"led",		ARRAY_AND_SIZE(ltq_bled_grps)},
216 	{"asc",		ARRAY_AND_SIZE(ltq_asc_grps)},
217 	{"spi",		ARRAY_AND_SIZE(ltq_spi_grps)},
218 	{"i2c",		ARRAY_AND_SIZE(ltq_i2c_grps)},
219 	{"jtag",	ARRAY_AND_SIZE(ltq_jtag_grps)},
220 	{"slic",	ARRAY_AND_SIZE(ltq_slic_grps)},
221 	{"pcm",		ARRAY_AND_SIZE(ltq_pcm_grps)},
222 };
223 
224 
225 
226 
227 /* ---------  pinconf related code --------- */
falcon_pinconf_group_get(struct pinctrl_dev * pctrldev,unsigned group,unsigned long * config)228 static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev,
229 				unsigned group, unsigned long *config)
230 {
231 	return -ENOTSUPP;
232 }
233 
falcon_pinconf_group_set(struct pinctrl_dev * pctrldev,unsigned group,unsigned long * configs,unsigned num_configs)234 static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev,
235 				unsigned group, unsigned long *configs,
236 				unsigned num_configs)
237 {
238 	return -ENOTSUPP;
239 }
240 
falcon_pinconf_get(struct pinctrl_dev * pctrldev,unsigned pin,unsigned long * config)241 static int falcon_pinconf_get(struct pinctrl_dev *pctrldev,
242 				unsigned pin, unsigned long *config)
243 {
244 	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
245 	enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
246 	void __iomem *mem = info->membase[PORT(pin)];
247 
248 	switch (param) {
249 	case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
250 		*config = LTQ_PINCONF_PACK(param,
251 			!!pad_getbit(mem, LTQ_PADC_DCC, PORT_PIN(pin)));
252 		break;
253 
254 	case LTQ_PINCONF_PARAM_SLEW_RATE:
255 		*config = LTQ_PINCONF_PACK(param,
256 			!!pad_getbit(mem, LTQ_PADC_SRC, PORT_PIN(pin)));
257 		break;
258 
259 	case LTQ_PINCONF_PARAM_PULL:
260 		if (pad_getbit(mem, LTQ_PADC_PDEN, PORT_PIN(pin)))
261 			*config = LTQ_PINCONF_PACK(param, 1);
262 		else if (pad_getbit(mem, LTQ_PADC_PUEN, PORT_PIN(pin)))
263 			*config = LTQ_PINCONF_PACK(param, 2);
264 		else
265 			*config = LTQ_PINCONF_PACK(param, 0);
266 
267 		break;
268 
269 	default:
270 		return -ENOTSUPP;
271 	}
272 
273 	return 0;
274 }
275 
falcon_pinconf_set(struct pinctrl_dev * pctrldev,unsigned pin,unsigned long * configs,unsigned num_configs)276 static int falcon_pinconf_set(struct pinctrl_dev *pctrldev,
277 			unsigned pin, unsigned long *configs,
278 			unsigned num_configs)
279 {
280 	enum ltq_pinconf_param param;
281 	int arg;
282 	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
283 	void __iomem *mem = info->membase[PORT(pin)];
284 	u32 reg;
285 	int i;
286 
287 	for (i = 0; i < num_configs; i++) {
288 		param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
289 		arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
290 
291 		switch (param) {
292 		case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
293 			reg = LTQ_PADC_DCC;
294 			break;
295 
296 		case LTQ_PINCONF_PARAM_SLEW_RATE:
297 			reg = LTQ_PADC_SRC;
298 			break;
299 
300 		case LTQ_PINCONF_PARAM_PULL:
301 			if (arg == 1)
302 				reg = LTQ_PADC_PDEN;
303 			else
304 				reg = LTQ_PADC_PUEN;
305 			break;
306 
307 		default:
308 			pr_err("%s: Invalid config param %04x\n",
309 			pinctrl_dev_get_name(pctrldev), param);
310 			return -ENOTSUPP;
311 		}
312 
313 		pad_w32(mem, BIT(PORT_PIN(pin)), reg);
314 		if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin))))
315 			return -ENOTSUPP;
316 	} /* for each config */
317 
318 	return 0;
319 }
320 
falcon_pinconf_dbg_show(struct pinctrl_dev * pctrldev,struct seq_file * s,unsigned offset)321 static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev,
322 			struct seq_file *s, unsigned offset)
323 {
324 	unsigned long config;
325 	struct pin_desc *desc;
326 
327 	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
328 	int port = PORT(offset);
329 
330 	seq_printf(s, " (port %d) mux %d -- ", port,
331 		pad_r32(info->membase[port], LTQ_PADC_MUX(PORT_PIN(offset))));
332 
333 	config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_PULL, 0);
334 	if (!falcon_pinconf_get(pctrldev, offset, &config))
335 		seq_printf(s, "pull %d ",
336 			(int)LTQ_PINCONF_UNPACK_ARG(config));
337 
338 	config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_DRIVE_CURRENT, 0);
339 	if (!falcon_pinconf_get(pctrldev, offset, &config))
340 		seq_printf(s, "drive-current %d ",
341 			(int)LTQ_PINCONF_UNPACK_ARG(config));
342 
343 	config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_SLEW_RATE, 0);
344 	if (!falcon_pinconf_get(pctrldev, offset, &config))
345 		seq_printf(s, "slew-rate %d ",
346 			(int)LTQ_PINCONF_UNPACK_ARG(config));
347 
348 	desc = pin_desc_get(pctrldev, offset);
349 	if (desc) {
350 		if (desc->gpio_owner)
351 			seq_printf(s, " owner: %s", desc->gpio_owner);
352 	} else {
353 		seq_printf(s, " not registered");
354 	}
355 }
356 
falcon_pinconf_group_dbg_show(struct pinctrl_dev * pctrldev,struct seq_file * s,unsigned selector)357 static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
358 			struct seq_file *s, unsigned selector)
359 {
360 }
361 
362 static const struct pinconf_ops falcon_pinconf_ops = {
363 	.pin_config_get			= falcon_pinconf_get,
364 	.pin_config_set			= falcon_pinconf_set,
365 	.pin_config_group_get		= falcon_pinconf_group_get,
366 	.pin_config_group_set		= falcon_pinconf_group_set,
367 	.pin_config_dbg_show		= falcon_pinconf_dbg_show,
368 	.pin_config_group_dbg_show	= falcon_pinconf_group_dbg_show,
369 };
370 
371 static struct pinctrl_desc falcon_pctrl_desc = {
372 	.owner		= THIS_MODULE,
373 	.pins		= falcon_pads,
374 	.confops	= &falcon_pinconf_ops,
375 };
376 
falcon_mux_apply(struct pinctrl_dev * pctrldev,int mfp,int mux)377 static inline int falcon_mux_apply(struct pinctrl_dev *pctrldev,
378 			int mfp, int mux)
379 {
380 	struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
381 	int port = PORT(info->mfp[mfp].pin);
382 
383 	if ((port >= PORTS) || (!info->membase[port]))
384 		return -ENODEV;
385 
386 	pad_w32(info->membase[port], mux,
387 		LTQ_PADC_MUX(PORT_PIN(info->mfp[mfp].pin)));
388 	return 0;
389 }
390 
391 static const struct ltq_cfg_param falcon_cfg_params[] = {
392 	{"lantiq,pull",			LTQ_PINCONF_PARAM_PULL},
393 	{"lantiq,drive-current",	LTQ_PINCONF_PARAM_DRIVE_CURRENT},
394 	{"lantiq,slew-rate",		LTQ_PINCONF_PARAM_SLEW_RATE},
395 };
396 
397 static struct ltq_pinmux_info falcon_info = {
398 	.desc		= &falcon_pctrl_desc,
399 	.apply_mux	= falcon_mux_apply,
400 	.params		= falcon_cfg_params,
401 	.num_params	= ARRAY_SIZE(falcon_cfg_params),
402 };
403 
404 
405 
406 
407 /* --------- register the pinctrl layer --------- */
408 
pinctrl_falcon_get_range_size(int id)409 int pinctrl_falcon_get_range_size(int id)
410 {
411 	u32 avail;
412 
413 	if ((id >= PORTS) || (!falcon_info.membase[id]))
414 		return -EINVAL;
415 
416 	avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL);
417 
418 	return fls(avail);
419 }
420 
pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range * range)421 void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range)
422 {
423 	pinctrl_add_gpio_range(falcon_info.pctrl, range);
424 }
425 
pinctrl_falcon_probe(struct platform_device * pdev)426 static int pinctrl_falcon_probe(struct platform_device *pdev)
427 {
428 	struct device_node *np;
429 	int pad_count = 0;
430 	int ret = 0;
431 
432 	/* load and remap the pad resources of the different banks */
433 	for_each_compatible_node(np, NULL, "lantiq,pad-falcon") {
434 		const __be32 *bank = of_get_property(np, "lantiq,bank", NULL);
435 		struct resource res;
436 		struct platform_device *ppdev;
437 		u32 avail;
438 		int pins;
439 
440 		if (!of_device_is_available(np))
441 			continue;
442 
443 		if (!bank || *bank >= PORTS)
444 			continue;
445 		if (of_address_to_resource(np, 0, &res))
446 			continue;
447 
448 		ppdev = of_find_device_by_node(np);
449 		if (!ppdev) {
450 			dev_err(&pdev->dev, "failed to find pad pdev\n");
451 			continue;
452 		}
453 
454 		falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);
455 		put_device(&ppdev->dev);
456 		if (IS_ERR(falcon_info.clk[*bank])) {
457 			dev_err(&ppdev->dev, "failed to get clock\n");
458 			of_node_put(np);
459 			return PTR_ERR(falcon_info.clk[*bank]);
460 		}
461 		falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev,
462 								   &res);
463 		if (IS_ERR(falcon_info.membase[*bank])) {
464 			of_node_put(np);
465 			return PTR_ERR(falcon_info.membase[*bank]);
466 		}
467 
468 		avail = pad_r32(falcon_info.membase[*bank],
469 					LTQ_PADC_AVAIL);
470 		pins = fls(avail);
471 		lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins);
472 		pad_count += pins;
473 		clk_enable(falcon_info.clk[*bank]);
474 		dev_dbg(&pdev->dev, "found %s with %d pads\n",
475 				res.name, pins);
476 	}
477 	dev_dbg(&pdev->dev, "found a total of %d pads\n", pad_count);
478 	falcon_pctrl_desc.name	= dev_name(&pdev->dev);
479 	falcon_pctrl_desc.npins	= pad_count;
480 
481 	falcon_info.mfp		= falcon_mfp;
482 	falcon_info.num_mfp	= ARRAY_SIZE(falcon_mfp);
483 	falcon_info.grps	= falcon_grps;
484 	falcon_info.num_grps	= ARRAY_SIZE(falcon_grps);
485 	falcon_info.funcs	= falcon_funcs;
486 	falcon_info.num_funcs	= ARRAY_SIZE(falcon_funcs);
487 
488 	ret = ltq_pinctrl_register(pdev, &falcon_info);
489 	if (!ret)
490 		dev_info(&pdev->dev, "Init done\n");
491 	return ret;
492 }
493 
494 static const struct of_device_id falcon_match[] = {
495 	{ .compatible = "lantiq,pinctrl-falcon" },
496 	{},
497 };
498 MODULE_DEVICE_TABLE(of, falcon_match);
499 
500 static struct platform_driver pinctrl_falcon_driver = {
501 	.probe = pinctrl_falcon_probe,
502 	.driver = {
503 		.name = "pinctrl-falcon",
504 		.of_match_table = falcon_match,
505 	},
506 };
507 
pinctrl_falcon_init(void)508 int __init pinctrl_falcon_init(void)
509 {
510 	return platform_driver_register(&pinctrl_falcon_driver);
511 }
512 
513 core_initcall_sync(pinctrl_falcon_init);
514