1 /*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23 #ifndef _DRM_DP_HELPER_H_
24 #define _DRM_DP_HELPER_H_
25
26 #include <linux/delay.h>
27 #include <linux/i2c.h>
28
29 #include <drm/display/drm_dp.h>
30 #include <drm/drm_connector.h>
31
32 struct drm_device;
33 struct drm_dp_aux;
34 struct drm_panel;
35
36 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
37 int lane_count);
38 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
39 int lane_count);
40 bool drm_dp_post_lt_adj_req_in_progress(const u8 link_status[DP_LINK_STATUS_SIZE]);
41 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
42 int lane);
43 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
44 int lane);
45 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
46 int lane);
47
48 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
49 enum drm_dp_phy dp_phy, bool uhbr);
50 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
51 enum drm_dp_phy dp_phy, bool uhbr);
52
53 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
54 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
55 void drm_dp_lttpr_link_train_clock_recovery_delay(void);
56 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
57 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
58 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
59 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
60
61 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);
62 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
63 int lane_count);
64 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
65 int lane_count);
66 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
67 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
68 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]);
69
70 u8 drm_dp_link_rate_to_bw_code(int link_rate);
71 int drm_dp_bw_code_to_link_rate(u8 link_bw);
72
73 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
74
75 /**
76 * struct drm_dp_vsc_sdp - drm DP VSC SDP
77 *
78 * This structure represents a DP VSC SDP of drm
79 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
80 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
81 *
82 * @sdp_type: secondary-data packet type
83 * @revision: revision number
84 * @length: number of valid data bytes
85 * @pixelformat: pixel encoding format
86 * @colorimetry: colorimetry format
87 * @bpc: bit per color
88 * @dynamic_range: dynamic range information
89 * @content_type: CTA-861-G defines content types and expected processing by a sink device
90 */
91 struct drm_dp_vsc_sdp {
92 unsigned char sdp_type;
93 unsigned char revision;
94 unsigned char length;
95 enum dp_pixelformat pixelformat;
96 enum dp_colorimetry colorimetry;
97 int bpc;
98 enum dp_dynamic_range dynamic_range;
99 enum dp_content_type content_type;
100 };
101
102 /**
103 * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP
104 *
105 * This structure represents a DP AS SDP of drm
106 * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes] and
107 * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8]
108 *
109 * @sdp_type: Secondary-data packet type
110 * @revision: Revision Number
111 * @length: Number of valid data bytes
112 * @vtotal: Minimum Vertical Vtotal
113 * @target_rr: Target Refresh
114 * @duration_incr_ms: Successive frame duration increase
115 * @duration_decr_ms: Successive frame duration decrease
116 * @target_rr_divider: Target refresh rate divider
117 * @mode: Adaptive Sync Operation Mode
118 * @coasting_vtotal: Coasting vtotal
119 */
120 struct drm_dp_as_sdp {
121 unsigned char sdp_type;
122 unsigned char revision;
123 unsigned char length;
124 int vtotal;
125 int target_rr;
126 int duration_incr_ms;
127 int duration_decr_ms;
128 bool target_rr_divider;
129 enum operation_mode mode;
130 int coasting_vtotal;
131 };
132
133 void drm_dp_as_sdp_log(struct drm_printer *p,
134 const struct drm_dp_as_sdp *as_sdp);
135 void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc);
136
137 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
138 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
139
140 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
141
142 static inline int
drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])143 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
144 {
145 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
146 }
147
148 static inline u8
drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])149 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
150 {
151 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
152 }
153
154 static inline bool
drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])155 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
156 {
157 return dpcd[DP_DPCD_REV] >= 0x11 &&
158 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
159 }
160
161 static inline bool
drm_dp_post_lt_adj_req_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])162 drm_dp_post_lt_adj_req_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
163 {
164 return dpcd[DP_DPCD_REV] >= 0x13 &&
165 (dpcd[DP_MAX_LANE_COUNT] & DP_POST_LT_ADJ_REQ_SUPPORTED);
166 }
167
168 static inline bool
drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])169 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
170 {
171 return dpcd[DP_DPCD_REV] >= 0x11 &&
172 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
173 }
174
175 static inline bool
drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])176 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
177 {
178 return dpcd[DP_DPCD_REV] >= 0x12 &&
179 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
180 }
181
182 static inline bool
drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])183 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
184 {
185 return dpcd[DP_DPCD_REV] >= 0x11 ||
186 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5;
187 }
188
189 static inline bool
drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])190 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
191 {
192 return dpcd[DP_DPCD_REV] >= 0x14 &&
193 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
194 }
195
196 static inline u8
drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])197 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
198 {
199 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
200 DP_TRAINING_PATTERN_MASK;
201 }
202
203 static inline bool
drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])204 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
205 {
206 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
207 }
208
209 /* DP/eDP DSC support */
210 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
211 u32 drm_dp_dsc_slice_count_to_mask(int slice_count);
212 u32 drm_dp_dsc_sink_slice_count_mask(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
213 bool is_edp);
214 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
215 bool is_edp);
216 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
217 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
218 u8 dsc_bpc[3]);
219 int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
220 int peak_pixel_rate, bool is_rgb_yuv444);
221 int drm_dp_dsc_branch_max_overall_throughput(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE],
222 bool is_rgb_yuv444);
223 int drm_dp_dsc_branch_max_line_width(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE]);
224
225 static inline bool
drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])226 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
227 {
228 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
229 DP_DSC_DECOMPRESSION_IS_SUPPORTED;
230 }
231
232 static inline u16
drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])233 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
234 {
235 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
236 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
237 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8);
238 }
239
240 static inline u32
drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])241 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
242 {
243 /* Max Slicewidth = Number of Pixels * 320 */
244 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
245 DP_DSC_SLICE_WIDTH_MULTIPLIER;
246 }
247
248 /**
249 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format
250 * @dsc_dpcd : DSC-capability DPCDs of the sink
251 * @output_format: output_format which is to be checked
252 *
253 * Returns true if the sink supports DSC with the given output_format, false otherwise.
254 */
255 static inline bool
drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],u8 output_format)256 drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format)
257 {
258 return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format;
259 }
260
261 /* Forward Error Correction Support on DP 1.4 */
262 static inline bool
drm_dp_sink_supports_fec(const u8 fec_capable)263 drm_dp_sink_supports_fec(const u8 fec_capable)
264 {
265 return fec_capable & DP_FEC_CAPABLE;
266 }
267
268 static inline bool
drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])269 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
270 {
271 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
272 }
273
274 static inline bool
drm_dp_128b132b_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])275 drm_dp_128b132b_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
276 {
277 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B;
278 }
279
280 static inline bool
drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])281 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
282 {
283 return dpcd[DP_EDP_CONFIGURATION_CAP] &
284 DP_ALTERNATE_SCRAMBLER_RESET_CAP;
285 }
286
287 /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
288 static inline bool
drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])289 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
290 {
291 return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
292 DP_MSA_TIMING_PAR_IGNORED;
293 }
294
295 /**
296 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
297 * @edp_dpcd: The DPCD to check
298 *
299 * Note that currently this function will return %false for panels which support various DPCD
300 * backlight features but which require the brightness be set through PWM, and don't support setting
301 * the brightness level via the DPCD.
302 *
303 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
304 * otherwise
305 */
306 static inline bool
drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])307 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
308 {
309 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP);
310 }
311
312 /**
313 * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR
314 * @link_rate: link rate in 10kbits/s units
315 *
316 * Determine if the provided link rate is an UHBR rate.
317 *
318 * Returns: %True if @link_rate is an UHBR rate.
319 */
drm_dp_is_uhbr_rate(int link_rate)320 static inline bool drm_dp_is_uhbr_rate(int link_rate)
321 {
322 return link_rate >= 1000000;
323 }
324
325 /*
326 * DisplayPort AUX channel
327 */
328
329 /**
330 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
331 * @address: address of the (first) register to access
332 * @request: contains the type of transaction (see DP_AUX_* macros)
333 * @reply: upon completion, contains the reply type of the transaction
334 * @buffer: pointer to a transmission or reception buffer
335 * @size: size of @buffer
336 */
337 struct drm_dp_aux_msg {
338 unsigned int address;
339 u8 request;
340 u8 reply;
341 void *buffer;
342 size_t size;
343 };
344
345 struct cec_adapter;
346 struct drm_connector;
347 struct drm_edid;
348
349 /**
350 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
351 * @lock: mutex protecting this struct
352 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
353 * @connector: the connector this CEC adapter is associated with
354 * @unregister_work: unregister the CEC adapter
355 */
356 struct drm_dp_aux_cec {
357 struct mutex lock;
358 struct cec_adapter *adap;
359 struct drm_connector *connector;
360 struct delayed_work unregister_work;
361 };
362
363 /**
364 * struct drm_dp_aux - DisplayPort AUX channel
365 *
366 * An AUX channel can also be used to transport I2C messages to a sink. A
367 * typical application of that is to access an EDID that's present in the sink
368 * device. The @transfer() function can also be used to execute such
369 * transactions. The drm_dp_aux_register() function registers an I2C adapter
370 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call
371 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long
372 * transfers by default; if a partial response is received, the adapter will
373 * drop down to the size given by the partial response for this transaction
374 * only.
375 */
376 struct drm_dp_aux {
377 /**
378 * @name: user-visible name of this AUX channel and the
379 * I2C-over-AUX adapter.
380 *
381 * It's also used to specify the name of the I2C adapter. If set
382 * to %NULL, dev_name() of @dev will be used.
383 */
384 const char *name;
385
386 /**
387 * @ddc: I2C adapter that can be used for I2C-over-AUX
388 * communication
389 */
390 struct i2c_adapter ddc;
391
392 /**
393 * @dev: pointer to struct device that is the parent for this
394 * AUX channel.
395 */
396 struct device *dev;
397
398 /**
399 * @drm_dev: pointer to the &drm_device that owns this AUX channel.
400 * Beware, this may be %NULL before drm_dp_aux_register() has been
401 * called.
402 *
403 * It should be set to the &drm_device that will be using this AUX
404 * channel as early as possible. For many graphics drivers this should
405 * happen before drm_dp_aux_init(), however it's perfectly fine to set
406 * this field later so long as it's assigned before calling
407 * drm_dp_aux_register().
408 */
409 struct drm_device *drm_dev;
410
411 /**
412 * @crtc: backpointer to the crtc that is currently using this
413 * AUX channel
414 */
415 struct drm_crtc *crtc;
416
417 /**
418 * @hw_mutex: internal mutex used for locking transfers.
419 *
420 * Note that if the underlying hardware is shared among multiple
421 * channels, the driver needs to do additional locking to
422 * prevent concurrent access.
423 */
424 struct mutex hw_mutex;
425
426 /**
427 * @crc_work: worker that captures CRCs for each frame
428 */
429 struct work_struct crc_work;
430
431 /**
432 * @crc_count: counter of captured frame CRCs
433 */
434 u8 crc_count;
435
436 /**
437 * @transfer: transfers a message representing a single AUX
438 * transaction.
439 *
440 * This is a hardware-specific implementation of how
441 * transactions are executed that the drivers must provide.
442 *
443 * A pointer to a &drm_dp_aux_msg structure describing the
444 * transaction is passed into this function. Upon success, the
445 * implementation should return the number of payload bytes that
446 * were transferred, or a negative error-code on failure.
447 *
448 * Helpers will propagate these errors, with the exception of
449 * the %-EBUSY error, which causes a transaction to be retried.
450 * On a short, helpers will return %-EPROTO to make it simpler
451 * to check for failure.
452 *
453 * The @transfer() function must only modify the reply field of
454 * the &drm_dp_aux_msg structure. The retry logic and i2c
455 * helpers assume this is the case.
456 *
457 * Also note that this callback can be called no matter the
458 * state @dev is in and also no matter what state the panel is
459 * in. It's expected:
460 *
461 * - If the @dev providing the AUX bus is currently unpowered then
462 * it will power itself up for the transfer.
463 *
464 * - If we're on eDP (using a drm_panel) and the panel is not in a
465 * state where it can respond (it's not powered or it's in a
466 * low power state) then this function may return an error, but
467 * not crash. It's up to the caller of this code to make sure that
468 * the panel is powered on if getting an error back is not OK. If a
469 * drm_panel driver is initiating a DP AUX transfer it may power
470 * itself up however it wants. All other code should ensure that
471 * the pre_enable() bridge chain (which eventually calls the
472 * drm_panel prepare function) has powered the panel.
473 */
474 ssize_t (*transfer)(struct drm_dp_aux *aux,
475 struct drm_dp_aux_msg *msg);
476
477 /**
478 * @wait_hpd_asserted: wait for HPD to be asserted
479 *
480 * This is mainly useful for eDP panels drivers to wait for an eDP
481 * panel to finish powering on. It is optional for DP AUX controllers
482 * to implement this function. It is required for DP AUX endpoints
483 * (panel drivers) to call this function after powering up but before
484 * doing AUX transfers unless the DP AUX endpoint driver knows that
485 * we're not using the AUX controller's HPD. One example of the panel
486 * driver not needing to call this is if HPD is hooked up to a GPIO
487 * that the panel driver can read directly.
488 *
489 * If a DP AUX controller does not implement this function then it
490 * may still support eDP panels that use the AUX controller's built-in
491 * HPD signal by implementing a long wait for HPD in the transfer()
492 * callback, though this is deprecated.
493 *
494 * This function will efficiently wait for the HPD signal to be
495 * asserted. The `wait_us` parameter that is passed in says that we
496 * know that the HPD signal is expected to be asserted within `wait_us`
497 * microseconds. This function could wait for longer than `wait_us` if
498 * the logic in the DP controller has a long debouncing time. The
499 * important thing is that if this function returns success that the
500 * DP controller is ready to send AUX transactions.
501 *
502 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time
503 * expired and HPD wasn't asserted. This function should not print
504 * timeout errors to the log.
505 *
506 * The semantics of this function are designed to match the
507 * readx_poll_timeout() function. That means a `wait_us` of 0 means
508 * to wait forever. Like readx_poll_timeout(), this function may sleep.
509 *
510 * NOTE: this function specifically reports the state of the HPD pin
511 * that's associated with the DP AUX channel. This is different from
512 * the HPD concept in much of the rest of DRM which is more about
513 * physical presence of a display. For eDP, for instance, a display is
514 * assumed always present even if the HPD pin is deasserted.
515 */
516 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us);
517
518 /**
519 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
520 */
521 unsigned i2c_nack_count;
522 /**
523 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
524 */
525 unsigned i2c_defer_count;
526 /**
527 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
528 */
529 struct drm_dp_aux_cec cec;
530 /**
531 * @is_remote: Is this AUX CH actually using sideband messaging.
532 */
533 bool is_remote;
534
535 /**
536 * @powered_down: If true then the remote endpoint is powered down.
537 */
538 bool powered_down;
539
540 /**
541 * @no_zero_sized: If the hw can't use zero sized transfers (NVIDIA)
542 */
543 bool no_zero_sized;
544
545 /**
546 * @dpcd_probe_disabled: If probing before a DPCD access is disabled.
547 */
548 bool dpcd_probe_disabled;
549 };
550
551 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset);
552 void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered);
553 void drm_dp_dpcd_set_probe(struct drm_dp_aux *aux, bool enable);
554 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
555 void *buffer, size_t size);
556 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
557 void *buffer, size_t size);
558
559 /**
560 * drm_dp_dpcd_readb() - read a single byte from the DPCD
561 * @aux: DisplayPort AUX channel
562 * @offset: address of the register to read
563 * @valuep: location where the value of the register will be stored
564 *
565 * Returns the number of bytes transferred (1) on success, or a negative
566 * error code on failure. In most of the cases you should be using
567 * drm_dp_dpcd_read_byte() instead.
568 */
drm_dp_dpcd_readb(struct drm_dp_aux * aux,unsigned int offset,u8 * valuep)569 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
570 unsigned int offset, u8 *valuep)
571 {
572 return drm_dp_dpcd_read(aux, offset, valuep, 1);
573 }
574
575 /**
576 * drm_dp_dpcd_read_data() - read a series of bytes from the DPCD
577 * @aux: DisplayPort AUX channel (SST or MST)
578 * @offset: address of the (first) register to read
579 * @buffer: buffer to store the register values
580 * @size: number of bytes in @buffer
581 *
582 * Returns zero (0) on success, or a negative error
583 * code on failure. -EIO is returned if the request was NAKed by the sink or
584 * if the retry count was exceeded. If not all bytes were transferred, this
585 * function returns -EPROTO. Errors from the underlying AUX channel transfer
586 * function, with the exception of -EBUSY (which causes the transaction to
587 * be retried), are propagated to the caller.
588 */
drm_dp_dpcd_read_data(struct drm_dp_aux * aux,unsigned int offset,void * buffer,size_t size)589 static inline int drm_dp_dpcd_read_data(struct drm_dp_aux *aux,
590 unsigned int offset,
591 void *buffer, size_t size)
592 {
593 int ret;
594 size_t i;
595 u8 *buf = buffer;
596
597 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
598 if (ret >= 0) {
599 if (ret < size)
600 return -EPROTO;
601 return 0;
602 }
603
604 /*
605 * Workaround for USB-C hubs/adapters with buggy firmware that fail
606 * multi-byte AUX reads but work with single-byte reads.
607 * Known affected devices:
608 * - Lenovo USB-C to VGA adapter (VIA VL817, idVendor=17ef, idProduct=7217)
609 * - Dell DA310 USB-C hub (idVendor=413c, idProduct=c010)
610 * Attempt byte-by-byte reading as a fallback.
611 */
612 for (i = 0; i < size; i++) {
613 ret = drm_dp_dpcd_readb(aux, offset + i, &buf[i]);
614 if (ret < 0)
615 return ret;
616 }
617
618 return 0;
619 }
620
621 /**
622 * drm_dp_dpcd_write_data() - write a series of bytes to the DPCD
623 * @aux: DisplayPort AUX channel (SST or MST)
624 * @offset: address of the (first) register to write
625 * @buffer: buffer containing the values to write
626 * @size: number of bytes in @buffer
627 *
628 * Returns zero (0) on success, or a negative error
629 * code on failure. -EIO is returned if the request was NAKed by the sink or
630 * if the retry count was exceeded. If not all bytes were transferred, this
631 * function returns -EPROTO. Errors from the underlying AUX channel transfer
632 * function, with the exception of -EBUSY (which causes the transaction to
633 * be retried), are propagated to the caller.
634 */
drm_dp_dpcd_write_data(struct drm_dp_aux * aux,unsigned int offset,void * buffer,size_t size)635 static inline int drm_dp_dpcd_write_data(struct drm_dp_aux *aux,
636 unsigned int offset,
637 void *buffer, size_t size)
638 {
639 int ret;
640
641 ret = drm_dp_dpcd_write(aux, offset, buffer, size);
642 if (ret < 0)
643 return ret;
644 if (ret < size)
645 return -EPROTO;
646
647 return 0;
648 }
649
650 /**
651 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
652 * @aux: DisplayPort AUX channel
653 * @offset: address of the register to write
654 * @value: value to write to the register
655 *
656 * Returns the number of bytes transferred (1) on success, or a negative
657 * error code on failure. In most of the cases you should be using
658 * drm_dp_dpcd_write_byte() instead.
659 */
drm_dp_dpcd_writeb(struct drm_dp_aux * aux,unsigned int offset,u8 value)660 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
661 unsigned int offset, u8 value)
662 {
663 return drm_dp_dpcd_write(aux, offset, &value, 1);
664 }
665
666 /**
667 * drm_dp_dpcd_read_byte() - read a single byte from the DPCD
668 * @aux: DisplayPort AUX channel
669 * @offset: address of the register to read
670 * @valuep: location where the value of the register will be stored
671 *
672 * Returns zero (0) on success, or a negative error code on failure.
673 */
drm_dp_dpcd_read_byte(struct drm_dp_aux * aux,unsigned int offset,u8 * valuep)674 static inline int drm_dp_dpcd_read_byte(struct drm_dp_aux *aux,
675 unsigned int offset, u8 *valuep)
676 {
677 return drm_dp_dpcd_read_data(aux, offset, valuep, 1);
678 }
679
680 /**
681 * drm_dp_dpcd_write_byte() - write a single byte to the DPCD
682 * @aux: DisplayPort AUX channel
683 * @offset: address of the register to write
684 * @value: value to write to the register
685 *
686 * Returns zero (0) on success, or a negative error code on failure.
687 */
drm_dp_dpcd_write_byte(struct drm_dp_aux * aux,unsigned int offset,u8 value)688 static inline int drm_dp_dpcd_write_byte(struct drm_dp_aux *aux,
689 unsigned int offset, u8 value)
690 {
691 return drm_dp_dpcd_write_data(aux, offset, &value, 1);
692 }
693
694 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
695 u8 dpcd[DP_RECEIVER_CAP_SIZE]);
696
697 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
698 u8 status[DP_LINK_STATUS_SIZE]);
699
700 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
701 enum drm_dp_phy dp_phy,
702 u8 link_status[DP_LINK_STATUS_SIZE]);
703 int drm_dp_link_power_up(struct drm_dp_aux *aux, unsigned char revision);
704 int drm_dp_link_power_down(struct drm_dp_aux *aux, unsigned char revision);
705
706 int drm_dp_dpcd_write_payload(struct drm_dp_aux *aux,
707 int vcpid, u8 start_time_slot, u8 time_slot_count);
708 int drm_dp_dpcd_clear_payload(struct drm_dp_aux *aux);
709 int drm_dp_dpcd_poll_act_handled(struct drm_dp_aux *aux, int timeout_ms);
710
711 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
712 u8 real_edid_checksum);
713
714 int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
715 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
716 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
717 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
718 const u8 port_cap[4], u8 type);
719 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
720 const u8 port_cap[4],
721 const struct drm_edid *drm_edid);
722 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
723 const u8 port_cap[4]);
724 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
725 const u8 port_cap[4],
726 const struct drm_edid *drm_edid);
727 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
728 const u8 port_cap[4],
729 const struct drm_edid *drm_edid);
730 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
731 const u8 port_cap[4],
732 const struct drm_edid *drm_edid);
733 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
734 const u8 port_cap[4]);
735 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
736 const u8 port_cap[4]);
737 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
738 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
739 const u8 port_cap[4]);
740 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
741 void drm_dp_downstream_debug(struct seq_file *m,
742 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
743 const u8 port_cap[4],
744 const struct drm_edid *drm_edid,
745 struct drm_dp_aux *aux);
746 enum drm_mode_subconnector
747 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
748 const u8 port_cap[4]);
749 void drm_dp_set_subconnector_property(struct drm_connector *connector,
750 enum drm_connector_status status,
751 const u8 *dpcd,
752 const u8 port_cap[4]);
753
754 struct drm_dp_desc;
755 bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
756 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
757 const struct drm_dp_desc *desc);
758 int drm_dp_read_sink_count(struct drm_dp_aux *aux);
759
760 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
761 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
762 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
763 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
764 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
765 enum drm_dp_phy dp_phy,
766 u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
767 int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
768 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
769 int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable);
770 int drm_dp_lttpr_init(struct drm_dp_aux *aux, int lttpr_count);
771 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
772 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
773 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
774 void drm_dp_lttpr_wake_timeout_setup(struct drm_dp_aux *aux, bool transparent_mode);
775
776 void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
777 void drm_dp_aux_init(struct drm_dp_aux *aux);
778 int drm_dp_aux_register(struct drm_dp_aux *aux);
779 void drm_dp_aux_unregister(struct drm_dp_aux *aux);
780
781 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
782 int drm_dp_stop_crc(struct drm_dp_aux *aux);
783
784 struct drm_dp_dpcd_ident {
785 u8 oui[3];
786 u8 device_id[6];
787 u8 hw_rev;
788 u8 sw_major_rev;
789 u8 sw_minor_rev;
790 } __packed;
791
792 /**
793 * struct drm_dp_desc - DP branch/sink device descriptor
794 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
795 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
796 */
797 struct drm_dp_desc {
798 struct drm_dp_dpcd_ident ident;
799 u32 quirks;
800 };
801
802 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
803 bool is_branch);
804
805 int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy);
806
807 /**
808 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
809 *
810 * Display Port sink and branch devices in the wild have a variety of bugs, try
811 * to collect them here. The quirks are shared, but it's up to the drivers to
812 * implement workarounds for them.
813 */
814 enum drm_dp_quirk {
815 /**
816 * @DP_DPCD_QUIRK_CONSTANT_N:
817 *
818 * The device requires main link attributes Mvid and Nvid to be limited
819 * to 16 bits. So will give a constant value (0x8000) for compatability.
820 */
821 DP_DPCD_QUIRK_CONSTANT_N,
822 /**
823 * @DP_DPCD_QUIRK_NO_PSR:
824 *
825 * The device does not support PSR even if reports that it supports or
826 * driver still need to implement proper handling for such device.
827 */
828 DP_DPCD_QUIRK_NO_PSR,
829 /**
830 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
831 *
832 * The device does not set SINK_COUNT to a non-zero value.
833 * The driver should ignore SINK_COUNT during detection. Note that
834 * drm_dp_read_sink_count_cap() automatically checks for this quirk.
835 */
836 DP_DPCD_QUIRK_NO_SINK_COUNT,
837 /**
838 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
839 *
840 * The device supports MST DSC despite not supporting Virtual DPCD.
841 * The DSC caps can be read from the physical aux instead.
842 */
843 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
844 /**
845 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
846 *
847 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
848 * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
849 */
850 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
851 /**
852 * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC:
853 *
854 * The device applies HBLANK expansion for some modes, but this
855 * requires enabling DSC.
856 */
857 DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC,
858 /**
859 * @DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT:
860 *
861 * The device doesn't support DSC decompression at the maximum DSC
862 * pixel throughput and compressed bpp it indicates via its DPCD DSC
863 * capabilities. The compressed bpp must be limited above a device
864 * specific DSC pixel throughput.
865 */
866 DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT,
867 };
868
869 /**
870 * drm_dp_has_quirk() - does the DP device have a specific quirk
871 * @desc: Device descriptor filled by drm_dp_read_desc()
872 * @quirk: Quirk to query for
873 *
874 * Return true if DP device identified by @desc has @quirk.
875 */
876 static inline bool
drm_dp_has_quirk(const struct drm_dp_desc * desc,enum drm_dp_quirk quirk)877 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
878 {
879 return desc->quirks & BIT(quirk);
880 }
881
882 /**
883 * struct drm_edp_backlight_info - Probed eDP backlight info struct
884 * @pwmgen_bit_count: The pwmgen bit count
885 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
886 * @max: The maximum backlight level that may be set
887 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
888 * @aux_enable: Does the panel support the AUX enable cap?
889 * @aux_set: Does the panel support setting the brightness through AUX?
890 * @luminance_set: Does the panel support setting the brightness through AUX using luminance values?
891 *
892 * This structure contains various data about an eDP backlight, which can be populated by using
893 * drm_edp_backlight_init().
894 */
895 struct drm_edp_backlight_info {
896 u8 pwmgen_bit_count;
897 u8 pwm_freq_pre_divider;
898 u32 max;
899
900 bool lsb_reg_used : 1;
901 bool aux_enable : 1;
902 bool aux_set : 1;
903 bool luminance_set : 1;
904 };
905
906 int
907 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
908 u32 max_luminance,
909 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
910 u32 *current_level, u8 *current_mode, bool need_luminance);
911 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
912 u32 level);
913 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
914 u32 level);
915 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
916
917 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
918 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)))
919
920 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux);
921
922 #else
923
drm_panel_dp_aux_backlight(struct drm_panel * panel,struct drm_dp_aux * aux)924 static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel,
925 struct drm_dp_aux *aux)
926 {
927 return 0;
928 }
929
930 #endif
931
932 #ifdef CONFIG_DRM_DISPLAY_DP_AUX_CEC
933 void drm_dp_cec_irq(struct drm_dp_aux *aux);
934 void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
935 struct drm_connector *connector);
936 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
937 void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address);
938 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
939 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
940 #else
drm_dp_cec_irq(struct drm_dp_aux * aux)941 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
942 {
943 }
944
945 static inline void
drm_dp_cec_register_connector(struct drm_dp_aux * aux,struct drm_connector * connector)946 drm_dp_cec_register_connector(struct drm_dp_aux *aux,
947 struct drm_connector *connector)
948 {
949 }
950
drm_dp_cec_unregister_connector(struct drm_dp_aux * aux)951 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
952 {
953 }
954
drm_dp_cec_attach(struct drm_dp_aux * aux,u16 source_physical_address)955 static inline void drm_dp_cec_attach(struct drm_dp_aux *aux,
956 u16 source_physical_address)
957 {
958 }
959
drm_dp_cec_set_edid(struct drm_dp_aux * aux,const struct edid * edid)960 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
961 const struct edid *edid)
962 {
963 }
964
drm_dp_cec_unset_edid(struct drm_dp_aux * aux)965 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
966 {
967 }
968
969 #endif
970
971 /**
972 * struct drm_dp_phy_test_params - DP Phy Compliance parameters
973 * @link_rate: Requested Link rate from DPCD 0x219
974 * @num_lanes: Number of lanes requested by sing through DPCD 0x220
975 * @phy_pattern: DP Phy test pattern from DPCD 0x248
976 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
977 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
978 * @enhanced_frame_cap: flag for enhanced frame capability.
979 */
980 struct drm_dp_phy_test_params {
981 int link_rate;
982 u8 num_lanes;
983 u8 phy_pattern;
984 u8 hbr2_reset[2];
985 u8 custom80[10];
986 bool enhanced_frame_cap;
987 };
988
989 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
990 struct drm_dp_phy_test_params *data);
991 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
992 struct drm_dp_phy_test_params *data, u8 dp_rev);
993 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
994 const u8 port_cap[4]);
995 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
996 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
997 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
998 u8 frl_mode);
999 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
1000 u8 frl_type);
1001 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
1002 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
1003
1004 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
1005 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
1006 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
1007 struct drm_connector *connector);
1008 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
1009 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
1010 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
1011 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
1012 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux);
1013 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
1014 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);
1015 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1016 const u8 port_cap[4], u8 color_spc);
1017 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
1018
1019 #define DRM_DP_BW_OVERHEAD_MST BIT(0)
1020 #define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
1021 #define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
1022 #define DRM_DP_BW_OVERHEAD_FEC BIT(3)
1023 #define DRM_DP_BW_OVERHEAD_DSC BIT(4)
1024
1025 int drm_dp_bw_overhead(int lane_count, int hactive,
1026 int dsc_slice_count,
1027 int bpp_x16, unsigned long flags);
1028 int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
1029 int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes);
1030
1031 ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp);
1032 int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count,
1033 int bpp_x16, int symbol_size, bool is_mst);
1034
1035 #endif /* _DRM_DP_HELPER_H_ */
1036