1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2020 NXP
4 * Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/bits.h>
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/iopoll.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16
17 #define PHY_REG(reg) (reg * 4)
18
19 #define REG01_PMS_P_MASK GENMASK(3, 0)
20 #define REG03_PMS_S_MASK GENMASK(7, 4)
21 #define REG12_CK_DIV_MASK GENMASK(5, 4)
22
23 #define REG13_TG_CODE_LOW_MASK GENMASK(7, 0)
24
25 #define REG14_TOL_MASK GENMASK(7, 4)
26 #define REG14_RP_CODE_MASK GENMASK(3, 1)
27 #define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0)
28
29 #define REG21_SEL_TX_CK_INV BIT(7)
30 #define REG21_PMS_S_MASK GENMASK(3, 0)
31 /*
32 * REG33 does not match the ref manual. According to Sandor Yu from NXP,
33 * "There is a doc issue on the i.MX8MP latest RM"
34 * REG33 is being used per guidance from Sandor
35 */
36 #define REG33_MODE_SET_DONE BIT(7)
37 #define REG33_FIX_DA BIT(1)
38
39 #define REG34_PHY_READY BIT(7)
40 #define REG34_PLL_LOCK BIT(6)
41 #define REG34_PHY_CLK_READY BIT(5)
42
43 #ifndef MHZ
44 #define MHZ (1000UL * 1000UL)
45 #endif
46
47 #define PHY_PLL_DIV_REGS_NUM 7
48
49 struct phy_config {
50 u32 pixclk;
51 u8 pll_div_regs[PHY_PLL_DIV_REGS_NUM];
52 };
53
54 /*
55 * The calculated_phy_pll_cfg only handles integer divider for PMS,
56 * meaning the last four entries will be fixed, but the first three will
57 * be calculated by the PMS calculator.
58 */
59 static struct phy_config calculated_phy_pll_cfg = {
60 .pixclk = 0,
61 .pll_div_regs = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00 },
62 };
63
64 /* The lookup table contains values for which the fractional divder is used */
65 static const struct phy_config phy_pll_cfg[] = {
66 {
67 .pixclk = 22250000,
68 .pll_div_regs = { 0xd1, 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40 },
69 }, {
70 .pixclk = 23750000,
71 .pll_div_regs = { 0xd1, 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 },
72 }, {
73 .pixclk = 24024000,
74 .pll_div_regs = { 0xd1, 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 },
75 }, {
76 .pixclk = 25175000,
77 .pll_div_regs = { 0xd1, 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 },
78 }, {
79 .pixclk = 26750000,
80 .pll_div_regs = { 0xd1, 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 },
81 }, {
82 .pixclk = 27027000,
83 .pll_div_regs = { 0xd1, 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 },
84 }, {
85 .pixclk = 29500000,
86 .pll_div_regs = { 0xd1, 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 },
87 }, {
88 .pixclk = 30750000,
89 .pll_div_regs = { 0xd1, 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 },
90 }, {
91 .pixclk = 30888000,
92 .pll_div_regs = { 0xd1, 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 },
93 }, {
94 .pixclk = 33750000,
95 .pll_div_regs = { 0xd1, 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 },
96 }, {
97 .pixclk = 35000000,
98 .pll_div_regs = { 0xd1, 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 },
99 }, {
100 .pixclk = 36036000,
101 .pll_div_regs = { 0xd1, 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 },
102 }, {
103 .pixclk = 43243200,
104 .pll_div_regs = { 0xd1, 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 },
105 }, {
106 .pixclk = 44500000,
107 .pll_div_regs = { 0xd1, 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 },
108 }, {
109 .pixclk = 47000000,
110 .pll_div_regs = { 0xd1, 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 },
111 }, {
112 .pixclk = 47500000,
113 .pll_div_regs = { 0xd1, 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 },
114 }, {
115 .pixclk = 50349650,
116 .pll_div_regs = { 0xd1, 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 },
117 }, {
118 .pixclk = 53250000,
119 .pll_div_regs = { 0xd1, 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 },
120 }, {
121 .pixclk = 53500000,
122 .pll_div_regs = { 0xd1, 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 },
123 }, {
124 .pixclk = 54054000,
125 .pll_div_regs = { 0xd1, 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 },
126 }, {
127 .pixclk = 59000000,
128 .pll_div_regs = { 0xd1, 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 },
129 }, {
130 .pixclk = 59340659,
131 .pll_div_regs = { 0xd1, 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 },
132 }, {
133 .pixclk = 61500000,
134 .pll_div_regs = { 0xd1, 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 },
135 }, {
136 .pixclk = 63500000,
137 .pll_div_regs = { 0xd1, 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 },
138 }, {
139 .pixclk = 67500000,
140 .pll_div_regs = { 0xd1, 0x54, 0x52, 0x87, 0x03, 0x80, 0x40 },
141 }, {
142 .pixclk = 70000000,
143 .pll_div_regs = { 0xd1, 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 },
144 }, {
145 .pixclk = 72072000,
146 .pll_div_regs = { 0xd1, 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 },
147 }, {
148 .pixclk = 74176000,
149 .pll_div_regs = { 0xd1, 0x5d, 0x58, 0xdb, 0xA2, 0x88, 0x41 },
150 }, {
151 .pixclk = 74250000,
152 .pll_div_regs = { 0xd1, 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 },
153 }, {
154 .pixclk = 78500000,
155 .pll_div_regs = { 0xd1, 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 },
156 }, {
157 .pixclk = 82000000,
158 .pll_div_regs = { 0xd1, 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 },
159 }, {
160 .pixclk = 82500000,
161 .pll_div_regs = { 0xd1, 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 },
162 }, {
163 .pixclk = 89000000,
164 .pll_div_regs = { 0xd1, 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 },
165 }, {
166 .pixclk = 90000000,
167 .pll_div_regs = { 0xd1, 0x70, 0x54, 0x82, 0x01, 0x80, 0x40 },
168 }, {
169 .pixclk = 94000000,
170 .pll_div_regs = { 0xd1, 0x4e, 0x32, 0xa7, 0x10, 0x80, 0x40 },
171 }, {
172 .pixclk = 95000000,
173 .pll_div_regs = { 0xd1, 0x50, 0x31, 0x86, 0x85, 0x80, 0x40 },
174 }, {
175 .pixclk = 98901099,
176 .pll_div_regs = { 0xd1, 0x52, 0x3a, 0xdb, 0x4c, 0x88, 0x47 },
177 }, {
178 .pixclk = 99000000,
179 .pll_div_regs = { 0xd1, 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 },
180 }, {
181 .pixclk = 100699300,
182 .pll_div_regs = { 0xd1, 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 },
183 }, {
184 .pixclk = 102500000,
185 .pll_div_regs = { 0xd1, 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b },
186 }, {
187 .pixclk = 104750000,
188 .pll_div_regs = { 0xd1, 0x57, 0x32, 0x98, 0x07, 0x90, 0x49 },
189 }, {
190 .pixclk = 106500000,
191 .pll_div_regs = { 0xd1, 0x58, 0x32, 0x84, 0x03, 0x82, 0x41 },
192 }, {
193 .pixclk = 107000000,
194 .pll_div_regs = { 0xd1, 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 },
195 }, {
196 .pixclk = 108108000,
197 .pll_div_regs = { 0xd1, 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 },
198 }, {
199 .pixclk = 118000000,
200 .pll_div_regs = { 0xd1, 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 },
201 }, {
202 .pixclk = 123000000,
203 .pll_div_regs = { 0xd1, 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 },
204 }, {
205 .pixclk = 127000000,
206 .pll_div_regs = { 0xd1, 0x69, 0x34, 0x89, 0x08, 0x80, 0x40 },
207 }, {
208 .pixclk = 135000000,
209 .pll_div_regs = { 0xd1, 0x70, 0x34, 0x82, 0x01, 0x80, 0x40 },
210 }, {
211 .pixclk = 135580000,
212 .pll_div_regs = { 0xd1, 0x71, 0x39, 0xe9, 0x82, 0x9c, 0x5b },
213 }, {
214 .pixclk = 137520000,
215 .pll_div_regs = { 0xd1, 0x72, 0x38, 0x99, 0x10, 0x85, 0x41 },
216 }, {
217 .pixclk = 138750000,
218 .pll_div_regs = { 0xd1, 0x73, 0x35, 0x88, 0x05, 0x90, 0x4d },
219 }, {
220 .pixclk = 140000000,
221 .pll_div_regs = { 0xd1, 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 },
222 }, {
223 .pixclk = 148352000,
224 .pll_div_regs = { 0xd1, 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 },
225 }, {
226 .pixclk = 148500000,
227 .pll_div_regs = { 0xd1, 0x7b, 0x35, 0x84, 0x03, 0x90, 0x45 },
228 }, {
229 .pixclk = 154000000,
230 .pll_div_regs = { 0xd1, 0x40, 0x18, 0x83, 0x01, 0x00, 0x40 },
231 }, {
232 .pixclk = 157000000,
233 .pll_div_regs = { 0xd1, 0x41, 0x11, 0xa7, 0x14, 0x80, 0x40 },
234 }, {
235 .pixclk = 160000000,
236 .pll_div_regs = { 0xd1, 0x42, 0x12, 0xa1, 0x20, 0x80, 0x40 },
237 }, {
238 .pixclk = 162000000,
239 .pll_div_regs = { 0xd1, 0x43, 0x18, 0x8b, 0x08, 0x96, 0x55 },
240 }, {
241 .pixclk = 164000000,
242 .pll_div_regs = { 0xd1, 0x45, 0x11, 0x83, 0x82, 0x90, 0x4b },
243 }, {
244 .pixclk = 165000000,
245 .pll_div_regs = { 0xd1, 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b },
246 }, {
247 .pixclk = 185625000,
248 .pll_div_regs = { 0xd1, 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 },
249 }, {
250 .pixclk = 188000000,
251 .pll_div_regs = { 0xd1, 0x4e, 0x12, 0xa7, 0x10, 0x80, 0x40 },
252 }, {
253 .pixclk = 198000000,
254 .pll_div_regs = { 0xd1, 0x52, 0x12, 0x82, 0x01, 0x88, 0x47 },
255 }, {
256 .pixclk = 205000000,
257 .pll_div_regs = { 0xd1, 0x55, 0x12, 0x8c, 0x05, 0x90, 0x4b },
258 }, {
259 .pixclk = 209500000,
260 .pll_div_regs = { 0xd1, 0x57, 0x12, 0x98, 0x07, 0x90, 0x49 },
261 }, {
262 .pixclk = 213000000,
263 .pll_div_regs = { 0xd1, 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 },
264 }, {
265 .pixclk = 216216000,
266 .pll_div_regs = { 0xd1, 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 },
267 }, {
268 .pixclk = 254000000,
269 .pll_div_regs = { 0xd1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 },
270 }, {
271 .pixclk = 277500000,
272 .pll_div_regs = { 0xd1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d },
273 }, {
274 .pixclk = 297000000,
275 .pll_div_regs = { 0xd1, 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 },
276 },
277 };
278
279 struct reg_settings {
280 u8 reg;
281 u8 val;
282 };
283
284 static const struct reg_settings common_phy_cfg[] = {
285 { PHY_REG(0), 0x00 },
286 /* PHY_REG(1-7) pix clk specific */
287 { PHY_REG(8), 0x4f }, { PHY_REG(9), 0x30 },
288 { PHY_REG(10), 0x33 }, { PHY_REG(11), 0x65 },
289 /* REG12 pixclk specific */
290 /* REG13 pixclk specific */
291 /* REG14 pixclk specific */
292 { PHY_REG(15), 0x80 }, { PHY_REG(16), 0x6c },
293 { PHY_REG(17), 0xf2 }, { PHY_REG(18), 0x67 },
294 { PHY_REG(19), 0x00 }, { PHY_REG(20), 0x10 },
295 /* REG21 pixclk specific */
296 { PHY_REG(22), 0x30 }, { PHY_REG(23), 0x32 },
297 { PHY_REG(24), 0x60 }, { PHY_REG(25), 0x8f },
298 { PHY_REG(26), 0x00 }, { PHY_REG(27), 0x00 },
299 { PHY_REG(28), 0x08 }, { PHY_REG(29), 0x00 },
300 { PHY_REG(30), 0x00 }, { PHY_REG(31), 0x00 },
301 { PHY_REG(32), 0x00 }, { PHY_REG(33), 0x80 },
302 { PHY_REG(34), 0x00 }, { PHY_REG(35), 0x00 },
303 { PHY_REG(36), 0x00 }, { PHY_REG(37), 0x00 },
304 { PHY_REG(38), 0x00 }, { PHY_REG(39), 0x00 },
305 { PHY_REG(40), 0x00 }, { PHY_REG(41), 0xe0 },
306 { PHY_REG(42), 0x83 }, { PHY_REG(43), 0x0f },
307 { PHY_REG(44), 0x3E }, { PHY_REG(45), 0xf8 },
308 { PHY_REG(46), 0x00 }, { PHY_REG(47), 0x00 }
309 };
310
311 struct fsl_samsung_hdmi_phy {
312 struct device *dev;
313 void __iomem *regs;
314 struct clk *apbclk;
315 struct clk *refclk;
316
317 /* clk provider */
318 struct clk_hw hw;
319 const struct phy_config *cur_cfg;
320 };
321
322 static inline struct fsl_samsung_hdmi_phy *
to_fsl_samsung_hdmi_phy(struct clk_hw * hw)323 to_fsl_samsung_hdmi_phy(struct clk_hw *hw)
324 {
325 return container_of(hw, struct fsl_samsung_hdmi_phy, hw);
326 }
327
328 static int
fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy * phy,const struct phy_config * cfg)329 fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy,
330 const struct phy_config *cfg)
331 {
332 u32 pclk = cfg->pixclk;
333 u32 fld_tg_code;
334 u32 int_pllclk;
335 u8 div;
336
337 /* Find int_pllclk speed */
338 for (div = 0; div < 4; div++) {
339 int_pllclk = pclk / (1 << div);
340 if (int_pllclk < (50 * MHZ))
341 break;
342 }
343
344 if (unlikely(div == 4))
345 return -EINVAL;
346
347 writeb(FIELD_PREP(REG12_CK_DIV_MASK, div), phy->regs + PHY_REG(12));
348
349 /*
350 * Calculation for the frequency lock detector target code (fld_tg_code)
351 * is based on reference manual register description of PHY_REG13
352 * (13.10.3.1.14.2):
353 * 1st) Calculate int_pllclk which is determinded by FLD_CK_DIV
354 * 2nd) Increase resolution to avoid rounding issues
355 * 3th) Do the div (256 / Freq. of int_pllclk) * 24
356 * 4th) Reduce the resolution and always round up since the NXP
357 * settings rounding up always too. TODO: Check if that is
358 * correct.
359 */
360
361 fld_tg_code = DIV_ROUND_UP(24 * MHZ * 256, int_pllclk);
362
363 /* FLD_TOL and FLD_RP_CODE taken from downstream driver */
364 writeb(FIELD_PREP(REG13_TG_CODE_LOW_MASK, fld_tg_code),
365 phy->regs + PHY_REG(13));
366 writeb(FIELD_PREP(REG14_TOL_MASK, 2) |
367 FIELD_PREP(REG14_RP_CODE_MASK, 2) |
368 FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8),
369 phy->regs + PHY_REG(14));
370
371 return 0;
372 }
373
fsl_samsung_hdmi_phy_find_pms(unsigned long fout,u8 * p,u16 * m,u8 * s)374 static unsigned long fsl_samsung_hdmi_phy_find_pms(unsigned long fout, u8 *p, u16 *m, u8 *s)
375 {
376 unsigned long best_freq = 0;
377 u32 min_delta = 0xffffffff;
378 u8 _p, best_p;
379 u16 _m, best_m;
380 u8 _s, best_s;
381
382 /*
383 * Figure 13-78 of the reference manual states the PLL should be TMDS x 5
384 * while the TMDS_CLKO should be the PLL / 5. So to calculate the PLL,
385 * take the pix clock x 5, then return the value of the PLL / 5.
386 */
387 fout *= 5;
388
389 /* The ref manual states the values of 'P' range from 1 to 11 */
390 for (_p = 1; _p <= 11; ++_p) {
391 for (_s = 1; _s <= 16; ++_s) {
392 u64 tmp;
393 u32 delta;
394
395 /* s must be one or even */
396 if (_s > 1 && (_s & 0x01) == 1)
397 _s++;
398
399 /* _s cannot be 14 per the TRM */
400 if (_s == 14)
401 continue;
402
403 /*
404 * The Ref manual doesn't explicitly state the range of M,
405 * but it does show it as an 8-bit value, so reject
406 * any value above 255.
407 */
408 tmp = (u64)fout * (_p * _s);
409 do_div(tmp, 24 * MHZ);
410 if (tmp > 255)
411 continue;
412 _m = tmp;
413
414 /*
415 * Rev 2 of the Ref Manual states the
416 * VCO can range between 750MHz and
417 * 3GHz. The VCO is assumed to be
418 * Fvco = (M * f_ref) / P,
419 * where f_ref is 24MHz.
420 */
421 tmp = div64_ul((u64)_m * 24 * MHZ, _p);
422 if (tmp < 750 * MHZ ||
423 tmp > 3000 * MHZ)
424 continue;
425
426 /* Final frequency after post-divider */
427 do_div(tmp, _s);
428
429 delta = abs(fout - tmp);
430 if (delta < min_delta) {
431 best_p = _p;
432 best_s = _s;
433 best_m = _m;
434 min_delta = delta;
435 best_freq = tmp;
436 }
437
438 /* If we have an exact match, stop looking for a better value */
439 if (!delta)
440 goto done;
441 }
442 }
443 done:
444 if (best_freq) {
445 *p = best_p;
446 *m = best_m;
447 *s = best_s;
448 }
449
450 return best_freq / 5;
451 }
452
fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy * phy,const struct phy_config * cfg)453 static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy,
454 const struct phy_config *cfg)
455 {
456 int i, ret;
457 u8 val;
458
459 /* HDMI PHY init */
460 writeb(REG33_FIX_DA, phy->regs + PHY_REG(33));
461
462 /* common PHY registers */
463 for (i = 0; i < ARRAY_SIZE(common_phy_cfg); i++)
464 writeb(common_phy_cfg[i].val, phy->regs + common_phy_cfg[i].reg);
465
466 /* set individual PLL registers PHY_REG1 ... PHY_REG7 */
467 for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++)
468 writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(1) + i * 4);
469
470 /* High nibble of PHY_REG3 and low nibble of PHY_REG21 both contain 'S' */
471 writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK,
472 cfg->pll_div_regs[2] >> 4), phy->regs + PHY_REG(21));
473
474 ret = fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg);
475 if (ret) {
476 dev_err(phy->dev, "pixclock too large\n");
477 return ret;
478 }
479
480 writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33));
481
482 ret = readb_poll_timeout(phy->regs + PHY_REG(34), val,
483 val & REG34_PLL_LOCK, 50, 20000);
484 if (ret)
485 dev_err(phy->dev, "PLL failed to lock\n");
486
487 return ret;
488 }
489
phy_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)490 static unsigned long phy_clk_recalc_rate(struct clk_hw *hw,
491 unsigned long parent_rate)
492 {
493 struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw);
494
495 if (!phy->cur_cfg)
496 return 74250000;
497
498 return phy->cur_cfg->pixclk;
499 }
500
501 /* Helper function to lookup the available fractional-divider rate */
fsl_samsung_hdmi_phy_lookup_rate(unsigned long rate)502 static const struct phy_config *fsl_samsung_hdmi_phy_lookup_rate(unsigned long rate)
503 {
504 int i;
505
506 /* Search the lookup table */
507 for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--)
508 if (phy_pll_cfg[i].pixclk <= rate)
509 break;
510
511 return &phy_pll_cfg[i];
512 }
513
fsl_samsung_hdmi_calculate_phy(struct phy_config * cal_phy,unsigned long rate,u8 p,u16 m,u8 s)514 static void fsl_samsung_hdmi_calculate_phy(struct phy_config *cal_phy, unsigned long rate,
515 u8 p, u16 m, u8 s)
516 {
517 cal_phy->pixclk = rate;
518 cal_phy->pll_div_regs[0] = FIELD_PREP(REG01_PMS_P_MASK, p);
519 cal_phy->pll_div_regs[1] = m;
520 cal_phy->pll_div_regs[2] = FIELD_PREP(REG03_PMS_S_MASK, s-1);
521 /* pll_div_regs 3-6 are fixed and pre-defined already */
522 }
523
fsl_samsung_hdmi_phy_get_closest_rate(unsigned long rate,u32 int_div_clk,u32 frac_div_clk)524 static u32 fsl_samsung_hdmi_phy_get_closest_rate(unsigned long rate,
525 u32 int_div_clk, u32 frac_div_clk)
526 {
527 /* Calculate the absolute value of the differences and return whichever is closest */
528 if (abs((long)rate - (long)int_div_clk) < abs((long)(rate - (long)frac_div_clk)))
529 return int_div_clk;
530
531 return frac_div_clk;
532 }
533
phy_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)534 static long phy_clk_round_rate(struct clk_hw *hw,
535 unsigned long rate, unsigned long *parent_rate)
536 {
537 const struct phy_config *fract_div_phy;
538 u32 int_div_clk;
539 u16 m;
540 u8 p, s;
541
542 /* If the clock is out of range return error instead of searching */
543 if (rate > 297000000 || rate < 22250000)
544 return -EINVAL;
545
546 /* Search the fractional divider lookup table */
547 fract_div_phy = fsl_samsung_hdmi_phy_lookup_rate(rate);
548
549 /* If the rate is an exact match, return that value */
550 if (rate == fract_div_phy->pixclk)
551 return fract_div_phy->pixclk;
552
553 /* If the exact match isn't found, calculate the integer divider */
554 int_div_clk = fsl_samsung_hdmi_phy_find_pms(rate, &p, &m, &s);
555
556 /* If the int_div_clk rate is an exact match, return that value */
557 if (int_div_clk == rate)
558 return int_div_clk;
559
560 /* If neither rate is an exact match, use the value from the LUT */
561 return fract_div_phy->pixclk;
562 }
563
phy_use_fract_div(struct fsl_samsung_hdmi_phy * phy,const struct phy_config * fract_div_phy)564 static int phy_use_fract_div(struct fsl_samsung_hdmi_phy *phy, const struct phy_config *fract_div_phy)
565 {
566 phy->cur_cfg = fract_div_phy;
567 dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: using fractional divider rate = %u\n",
568 phy->cur_cfg->pixclk);
569 return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);
570 }
571
phy_use_integer_div(struct fsl_samsung_hdmi_phy * phy,const struct phy_config * int_div_clk)572 static int phy_use_integer_div(struct fsl_samsung_hdmi_phy *phy,
573 const struct phy_config *int_div_clk)
574 {
575 phy->cur_cfg = &calculated_phy_pll_cfg;
576 dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: integer divider rate = %u\n",
577 phy->cur_cfg->pixclk);
578 return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);
579 }
580
phy_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)581 static int phy_clk_set_rate(struct clk_hw *hw,
582 unsigned long rate, unsigned long parent_rate)
583 {
584 struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw);
585 const struct phy_config *fract_div_phy;
586 u32 int_div_clk;
587 u16 m;
588 u8 p, s;
589
590 /* Search the fractional divider lookup table */
591 fract_div_phy = fsl_samsung_hdmi_phy_lookup_rate(rate);
592
593 /* If the rate is an exact match, use that value */
594 if (fract_div_phy->pixclk == rate)
595 return phy_use_fract_div(phy, fract_div_phy);
596
597 /*
598 * If the rate from the fractional divider is not exact, check the integer divider,
599 * and use it if that value is an exact match.
600 */
601 int_div_clk = fsl_samsung_hdmi_phy_find_pms(rate, &p, &m, &s);
602 fsl_samsung_hdmi_calculate_phy(&calculated_phy_pll_cfg, int_div_clk, p, m, s);
603 if (int_div_clk == rate)
604 return phy_use_integer_div(phy, &calculated_phy_pll_cfg);
605
606 /*
607 * Compare the difference between the integer clock and the fractional clock against
608 * the desired clock and which whichever is closest.
609 */
610 if (fsl_samsung_hdmi_phy_get_closest_rate(rate, int_div_clk,
611 fract_div_phy->pixclk) == fract_div_phy->pixclk)
612 return phy_use_fract_div(phy, fract_div_phy);
613 else
614 return phy_use_integer_div(phy, &calculated_phy_pll_cfg);
615 }
616
617 static const struct clk_ops phy_clk_ops = {
618 .recalc_rate = phy_clk_recalc_rate,
619 .round_rate = phy_clk_round_rate,
620 .set_rate = phy_clk_set_rate,
621 };
622
phy_clk_register(struct fsl_samsung_hdmi_phy * phy)623 static int phy_clk_register(struct fsl_samsung_hdmi_phy *phy)
624 {
625 struct device *dev = phy->dev;
626 struct device_node *np = dev->of_node;
627 struct clk_init_data init;
628 const char *parent_name;
629 struct clk *phyclk;
630 int ret;
631
632 parent_name = __clk_get_name(phy->refclk);
633
634 init.parent_names = &parent_name;
635 init.num_parents = 1;
636 init.flags = 0;
637 init.name = "hdmi_pclk";
638 init.ops = &phy_clk_ops;
639
640 phy->hw.init = &init;
641
642 phyclk = devm_clk_register(dev, &phy->hw);
643 if (IS_ERR(phyclk))
644 return dev_err_probe(dev, PTR_ERR(phyclk),
645 "failed to register clock\n");
646
647 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, phyclk);
648 if (ret)
649 return dev_err_probe(dev, ret,
650 "failed to register clock provider\n");
651
652 return 0;
653 }
654
fsl_samsung_hdmi_phy_probe(struct platform_device * pdev)655 static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev)
656 {
657 struct fsl_samsung_hdmi_phy *phy;
658 int ret;
659
660 phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
661 if (!phy)
662 return -ENOMEM;
663
664 platform_set_drvdata(pdev, phy);
665 phy->dev = &pdev->dev;
666
667 phy->regs = devm_platform_ioremap_resource(pdev, 0);
668 if (IS_ERR(phy->regs))
669 return PTR_ERR(phy->regs);
670
671 phy->apbclk = devm_clk_get(phy->dev, "apb");
672 if (IS_ERR(phy->apbclk))
673 return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk),
674 "failed to get apb clk\n");
675
676 phy->refclk = devm_clk_get(phy->dev, "ref");
677 if (IS_ERR(phy->refclk))
678 return dev_err_probe(phy->dev, PTR_ERR(phy->refclk),
679 "failed to get ref clk\n");
680
681 ret = clk_prepare_enable(phy->apbclk);
682 if (ret) {
683 dev_err(phy->dev, "failed to enable apbclk\n");
684 return ret;
685 }
686
687 pm_runtime_get_noresume(phy->dev);
688 pm_runtime_set_active(phy->dev);
689 pm_runtime_enable(phy->dev);
690
691 ret = phy_clk_register(phy);
692 if (ret) {
693 dev_err(&pdev->dev, "register clk failed\n");
694 goto register_clk_failed;
695 }
696
697 pm_runtime_put(phy->dev);
698
699 return 0;
700
701 register_clk_failed:
702 clk_disable_unprepare(phy->apbclk);
703
704 return ret;
705 }
706
fsl_samsung_hdmi_phy_remove(struct platform_device * pdev)707 static void fsl_samsung_hdmi_phy_remove(struct platform_device *pdev)
708 {
709 of_clk_del_provider(pdev->dev.of_node);
710 }
711
fsl_samsung_hdmi_phy_suspend(struct device * dev)712 static int __maybe_unused fsl_samsung_hdmi_phy_suspend(struct device *dev)
713 {
714 struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev);
715
716 clk_disable_unprepare(phy->apbclk);
717
718 return 0;
719 }
720
fsl_samsung_hdmi_phy_resume(struct device * dev)721 static int __maybe_unused fsl_samsung_hdmi_phy_resume(struct device *dev)
722 {
723 struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev);
724 int ret = 0;
725
726 ret = clk_prepare_enable(phy->apbclk);
727 if (ret) {
728 dev_err(phy->dev, "failed to enable apbclk\n");
729 return ret;
730 }
731
732 if (phy->cur_cfg)
733 ret = fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);
734
735 return ret;
736
737 }
738
739 static DEFINE_RUNTIME_DEV_PM_OPS(fsl_samsung_hdmi_phy_pm_ops,
740 fsl_samsung_hdmi_phy_suspend,
741 fsl_samsung_hdmi_phy_resume, NULL);
742
743 static const struct of_device_id fsl_samsung_hdmi_phy_of_match[] = {
744 {
745 .compatible = "fsl,imx8mp-hdmi-phy",
746 }, {
747 /* sentinel */
748 }
749 };
750 MODULE_DEVICE_TABLE(of, fsl_samsung_hdmi_phy_of_match);
751
752 static struct platform_driver fsl_samsung_hdmi_phy_driver = {
753 .probe = fsl_samsung_hdmi_phy_probe,
754 .remove = fsl_samsung_hdmi_phy_remove,
755 .driver = {
756 .name = "fsl-samsung-hdmi-phy",
757 .of_match_table = fsl_samsung_hdmi_phy_of_match,
758 .pm = pm_ptr(&fsl_samsung_hdmi_phy_pm_ops),
759 },
760 };
761 module_platform_driver(fsl_samsung_hdmi_phy_driver);
762
763 MODULE_AUTHOR("Sandor Yu <Sandor.yu@nxp.com>");
764 MODULE_DESCRIPTION("SAMSUNG HDMI 2.0 Transmitter PHY Driver");
765 MODULE_LICENSE("GPL");
766