1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2022, Intel Corporation. */
3
4 #ifndef _ICE_DPLL_H_
5 #define _ICE_DPLL_H_
6
7 #include "ice.h"
8
9 #define ICE_DPLL_RCLK_NUM_MAX 4
10
11 #define ICE_CGU_R10 0x28
12 #define ICE_CGU_R10_SYNCE_CLKO_SEL GENMASK(8, 5)
13 #define ICE_CGU_R10_SYNCE_CLKODIV_M1 GENMASK(13, 9)
14 #define ICE_CGU_R10_SYNCE_CLKODIV_LOAD BIT(14)
15 #define ICE_CGU_R10_SYNCE_DCK_RST BIT(15)
16 #define ICE_CGU_R10_SYNCE_ETHCLKO_SEL GENMASK(18, 16)
17 #define ICE_CGU_R10_SYNCE_ETHDIV_M1 GENMASK(23, 19)
18 #define ICE_CGU_R10_SYNCE_ETHDIV_LOAD BIT(24)
19 #define ICE_CGU_R10_SYNCE_DCK2_RST BIT(25)
20 #define ICE_CGU_R10_SYNCE_S_REF_CLK GENMASK(31, 27)
21
22 #define ICE_CGU_R11 0x2C
23 #define ICE_CGU_R11_SYNCE_S_BYP_CLK GENMASK(6, 1)
24
25 #define ICE_CGU_BYPASS_MUX_OFFSET_E825C 3
26
27 /**
28 * enum ice_dpll_pin_sw - enumerate ice software pin indices:
29 * @ICE_DPLL_PIN_SW_1_IDX: index of first SW pin
30 * @ICE_DPLL_PIN_SW_2_IDX: index of second SW pin
31 * @ICE_DPLL_PIN_SW_NUM: number of SW pins in pair
32 */
33 enum ice_dpll_pin_sw {
34 ICE_DPLL_PIN_SW_1_IDX,
35 ICE_DPLL_PIN_SW_2_IDX,
36 ICE_DPLL_PIN_SW_NUM
37 };
38
39 struct ice_dpll_pin_work {
40 struct work_struct work;
41 unsigned long action;
42 struct ice_dpll_pin *pin;
43 };
44
45 /** ice_dpll_pin - store info about pins
46 * @pin: dpll pin structure
47 * @pf: pointer to pf, which has registered the dpll_pin
48 * @tracker: reference count tracker
49 * @idx: ice pin private idx
50 * @num_parents: hols number of parent pins
51 * @parent_idx: hold indexes of parent pins
52 * @flags: pin flags returned from HW
53 * @state: state of a pin
54 * @prop: pin properties
55 * @freq: current frequency of a pin
56 * @phase_adjust: current phase adjust value
57 * @phase_offset: monitored phase offset value
58 * @ref_sync: store id of reference sync pin
59 */
60 struct ice_dpll_pin {
61 struct dpll_pin *pin;
62 struct ice_pf *pf;
63 dpll_tracker tracker;
64 struct fwnode_handle *fwnode;
65 struct notifier_block nb;
66 u8 idx;
67 u8 num_parents;
68 u8 parent_idx[ICE_DPLL_RCLK_NUM_MAX];
69 u8 flags[ICE_DPLL_RCLK_NUM_MAX];
70 u8 state[ICE_DPLL_RCLK_NUM_MAX];
71 struct dpll_pin_properties prop;
72 u32 freq;
73 s32 phase_adjust;
74 struct ice_dpll_pin *input;
75 struct ice_dpll_pin *output;
76 enum dpll_pin_direction direction;
77 s64 phase_offset;
78 u8 status;
79 u8 ref_sync;
80 bool active;
81 bool hidden;
82 };
83
84 /** ice_dpll - store info required for DPLL control
85 * @dpll: pointer to dpll dev
86 * @pf: pointer to pf, which has registered the dpll_device
87 * @tracker: reference count tracker
88 * @dpll_idx: index of dpll on the NIC
89 * @input_idx: currently selected input index
90 * @prev_input_idx: previously selected input index
91 * @ref_state: state of dpll reference signals
92 * @eec_mode: eec_mode dpll is configured for
93 * @phase_offset: phase offset of active pin vs dpll signal
94 * @prev_phase_offset: previous phase offset of active pin vs dpll signal
95 * @input_prio: priorities of each input
96 * @dpll_state: current dpll sync state
97 * @prev_dpll_state: last dpll sync state
98 * @phase_offset_monitor_period: period for phase offset monitor read frequency
99 * @active_input: pointer to active input pin
100 * @prev_input: pointer to previous active input pin
101 * @ops: holds the registered ops
102 */
103 struct ice_dpll {
104 struct dpll_device *dpll;
105 struct ice_pf *pf;
106 dpll_tracker tracker;
107 u8 dpll_idx;
108 u8 input_idx;
109 u8 prev_input_idx;
110 u8 ref_state;
111 u8 eec_mode;
112 s64 phase_offset;
113 s64 prev_phase_offset;
114 u8 *input_prio;
115 enum dpll_lock_status dpll_state;
116 enum dpll_lock_status prev_dpll_state;
117 enum dpll_mode mode;
118 u32 phase_offset_monitor_period;
119 struct dpll_pin *active_input;
120 struct dpll_pin *prev_input;
121 const struct dpll_device_ops *ops;
122 };
123
124 /** ice_dplls - store info required for CCU (clock controlling unit)
125 * @kworker: periodic worker
126 * @work: periodic work
127 * @lock: locks access to configuration of a dpll
128 * @eec: pointer to EEC dpll dev
129 * @pps: pointer to PPS dpll dev
130 * @inputs: input pins pointer
131 * @outputs: output pins pointer
132 * @rclk: recovered pins pointer
133 * @num_inputs: number of input pins available on dpll
134 * @num_outputs: number of output pins available on dpll
135 * @cgu_state_acq_err_num: number of errors returned during periodic work
136 * @base_rclk_idx: idx of first pin used for clock revocery pins
137 * @clock_id: clock_id of dplls
138 * @input_phase_adj_max: max phase adjust value for an input pins
139 * @output_phase_adj_max: max phase adjust value for an output pins
140 * @periodic_counter: counter of periodic work executions
141 */
142 struct ice_dplls {
143 struct kthread_worker *kworker;
144 struct kthread_delayed_work work;
145 struct workqueue_struct *wq;
146 struct mutex lock;
147 struct completion dpll_init;
148 struct ice_dpll eec;
149 struct ice_dpll pps;
150 struct ice_dpll_pin *inputs;
151 struct ice_dpll_pin *outputs;
152 struct ice_dpll_pin sma[ICE_DPLL_PIN_SW_NUM];
153 struct ice_dpll_pin ufl[ICE_DPLL_PIN_SW_NUM];
154 struct ice_dpll_pin rclk;
155 u8 num_inputs;
156 u8 num_outputs;
157 u8 sma_data;
158 u8 base_rclk_idx;
159 int cgu_state_acq_err_num;
160 u64 clock_id;
161 s32 input_phase_adj_max;
162 s32 output_phase_adj_max;
163 u32 periodic_counter;
164 bool generic;
165 };
166
167 #if IS_ENABLED(CONFIG_PTP_1588_CLOCK)
168 void ice_dpll_init(struct ice_pf *pf);
169 void ice_dpll_deinit(struct ice_pf *pf);
170 #else
ice_dpll_init(struct ice_pf * pf)171 static inline void ice_dpll_init(struct ice_pf *pf) { }
ice_dpll_deinit(struct ice_pf * pf)172 static inline void ice_dpll_deinit(struct ice_pf *pf) { }
173 #endif
174
175 #endif
176