xref: /linux/drivers/dpll/zl3073x/dpll.h (revision 91ec2035134982b98fab0609a9fd8480e8217dc1)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _ZL3073X_DPLL_H
4 #define _ZL3073X_DPLL_H
5 
6 #include <linux/dpll.h>
7 #include <linux/list.h>
8 #include <linux/ptp_clock_kernel.h>
9 
10 #include "core.h"
11 
12 /**
13  * struct zl3073x_dpll - ZL3073x DPLL sub-device structure
14  * @list: this DPLL list entry
15  * @dev: pointer to multi-function parent device
16  * @id: DPLL index
17  * @check_count: periodic check counter
18  * @phase_monitor: is phase offset monitor enabled
19  * @ops: DPLL device operations for this instance
20  * @dpll_dev: pointer to registered DPLL device
21  * @tracker: tracking object for the acquired reference
22  * @lock: per-DPLL mutex serializing all operations
23  * @type: DPLL type (PPS or EEC)
24  * @lock_status: last saved DPLL lock status
25  * @pins: list of pins
26  * @ptp_info: PTP clock info
27  * @ptp_clock: registered PTP clock (or NULL)
28  */
29 struct zl3073x_dpll {
30 	struct list_head		list;
31 	struct zl3073x_dev		*dev;
32 	u8				id;
33 	u8				check_count;
34 	bool				phase_monitor;
35 	struct dpll_device_ops		ops;
36 	struct dpll_device		*dpll_dev;
37 	dpll_tracker			tracker;
38 	struct mutex			lock;
39 	enum dpll_type			type;
40 	enum dpll_lock_status		lock_status;
41 	struct list_head		pins;
42 	struct ptp_clock_info		ptp_info;
43 	struct ptp_clock		*ptp_clock;
44 };
45 
46 struct zl3073x_dpll *zl3073x_dpll_alloc(struct zl3073x_dev *zldev, u8 ch);
47 void zl3073x_dpll_free(struct zl3073x_dpll *zldpll);
48 
49 int zl3073x_dpll_register(struct zl3073x_dpll *zldpll);
50 void zl3073x_dpll_unregister(struct zl3073x_dpll *zldpll);
51 
52 int zl3073x_dpll_init_fine_phase_adjust(struct zl3073x_dev *zldev);
53 void zl3073x_dpll_changes_check(struct zl3073x_dpll *zldpll);
54 
55 #endif /* _ZL3073X_DPLL_H */
56