1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Qualcomm PCIe Endpoint controller driver
4 *
5 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
6 * Author: Siddartha Mohanadoss <smohanad@codeaurora.org
7 *
8 * Copyright (c) 2021, Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org
10 */
11
12 #include <linux/clk.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/interconnect.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/phy/pcie.h>
19 #include <linux/phy/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_domain.h>
22 #include <linux/regmap.h>
23 #include <linux/reset.h>
24 #include <linux/module.h>
25
26 #include "../../pci.h"
27 #include "pcie-designware.h"
28 #include "pcie-qcom-common.h"
29
30 /* PARF registers */
31 #define PARF_SYS_CTRL 0x00
32 #define PARF_DB_CTRL 0x10
33 #define PARF_PM_CTRL 0x20
34 #define PARF_MHI_CLOCK_RESET_CTRL 0x174
35 #define PARF_MHI_BASE_ADDR_LOWER 0x178
36 #define PARF_MHI_BASE_ADDR_UPPER 0x17c
37 #define PARF_DEBUG_INT_EN 0x190
38 #define PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1a4
39 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x1a8
40 #define PARF_Q2A_FLUSH 0x1ac
41 #define PARF_LTSSM 0x1b0
42 #define PARF_CFG_BITS 0x210
43 #define PARF_INT_ALL_STATUS 0x224
44 #define PARF_INT_ALL_CLEAR 0x228
45 #define PARF_INT_ALL_MASK 0x22c
46 #define PARF_SLV_ADDR_MSB_CTRL 0x2c0
47 #define PARF_DBI_BASE_ADDR 0x350
48 #define PARF_DBI_BASE_ADDR_HI 0x354
49 #define PARF_SLV_ADDR_SPACE_SIZE 0x358
50 #define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c
51 #define PARF_NO_SNOOP_OVERRIDE 0x3d4
52 #define PARF_ATU_BASE_ADDR 0x634
53 #define PARF_ATU_BASE_ADDR_HI 0x638
54 #define PARF_SRIS_MODE 0x644
55 #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04
56 #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c
57 #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10
58 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84
59 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88
60 #define PARF_DEVICE_TYPE 0x1000
61 #define PARF_BDF_TO_SID_CFG 0x2c00
62 #define PARF_INT_ALL_5_MASK 0x2dcc
63 #define PARF_INT_ALL_3_MASK 0x2e18
64
65 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
66 #define PARF_INT_ALL_LINK_DOWN BIT(1)
67 #define PARF_INT_ALL_BME BIT(2)
68 #define PARF_INT_ALL_PM_TURNOFF BIT(3)
69 #define PARF_INT_ALL_DEBUG BIT(4)
70 #define PARF_INT_ALL_LTR BIT(5)
71 #define PARF_INT_ALL_MHI_Q6 BIT(6)
72 #define PARF_INT_ALL_MHI_A7 BIT(7)
73 #define PARF_INT_ALL_DSTATE_CHANGE BIT(8)
74 #define PARF_INT_ALL_L1SUB_TIMEOUT BIT(9)
75 #define PARF_INT_ALL_MMIO_WRITE BIT(10)
76 #define PARF_INT_ALL_CFG_WRITE BIT(11)
77 #define PARF_INT_ALL_BRIDGE_FLUSH_N BIT(12)
78 #define PARF_INT_ALL_LINK_UP BIT(13)
79 #define PARF_INT_ALL_AER_LEGACY BIT(14)
80 #define PARF_INT_ALL_PLS_ERR BIT(15)
81 #define PARF_INT_ALL_PME_LEGACY BIT(16)
82 #define PARF_INT_ALL_PLS_PME BIT(17)
83 #define PARF_INT_ALL_EDMA BIT(22)
84
85 /* PARF_BDF_TO_SID_CFG register fields */
86 #define PARF_BDF_TO_SID_BYPASS BIT(0)
87
88 /* PARF_DEBUG_INT_EN register fields */
89 #define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1)
90 #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2)
91 #define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3)
92
93 /* PARF_NO_SNOOP_OVERRIDE register fields */
94 #define WR_NO_SNOOP_OVERRIDE_EN BIT(1)
95 #define RD_NO_SNOOP_OVERRIDE_EN BIT(3)
96
97 /* PARF_DEVICE_TYPE register fields */
98 #define PARF_DEVICE_TYPE_EP 0x0
99
100 /* PARF_PM_CTRL register fields */
101 #define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1)
102 #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2)
103 #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5)
104
105 /* PARF_MHI_CLOCK_RESET_CTRL fields */
106 #define PARF_MSTR_AXI_CLK_EN BIT(1)
107
108 /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */
109 #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0)
110
111 /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
112 #define PARF_AXI_MSTR_WR_ADDR_HALT_EN BIT(31)
113
114 /* PARF_Q2A_FLUSH register fields */
115 #define PARF_Q2A_FLUSH_EN BIT(16)
116
117 /* PARF_SYS_CTRL register fields */
118 #define PARF_SYS_CTRL_AUX_PWR_DET BIT(4)
119 #define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6)
120 #define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS BIT(10)
121 #define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11)
122
123 /* PARF_DB_CTRL register fields */
124 #define PARF_DB_CTRL_INSR_DBNCR_BLOCK BIT(0)
125 #define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1)
126 #define PARF_DB_CTRL_DBI_WKP_BLOCK BIT(4)
127 #define PARF_DB_CTRL_SLV_WKP_BLOCK BIT(5)
128 #define PARF_DB_CTRL_MST_WKP_BLOCK BIT(6)
129
130 /* PARF_CFG_BITS register fields */
131 #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1)
132
133 /* PARF_INT_ALL_5_MASK fields */
134 #define PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR BIT(0)
135
136 /* PARF_INT_ALL_3_MASK fields */
137 #define PARF_INT_ALL_3_PTM_UPDATING BIT(4)
138
139 /* ELBI registers */
140 #define ELBI_SYS_STTS 0x08
141 #define ELBI_CS2_ENABLE 0xa4
142
143 /* DBI registers */
144 #define DBI_CON_STATUS 0x44
145
146 /* DBI register fields */
147 #define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0)
148
149 #define XMLH_LINK_UP 0x400
150 #define CORE_RESET_TIME_US_MIN 1000
151 #define CORE_RESET_TIME_US_MAX 1005
152 #define WAKE_DELAY_US 2000 /* 2 ms */
153
154 #define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \
155 Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]))
156
157 #define to_pcie_ep(x) dev_get_drvdata((x)->dev)
158
159 enum qcom_pcie_ep_link_status {
160 QCOM_PCIE_EP_LINK_DISABLED,
161 QCOM_PCIE_EP_LINK_ENABLED,
162 QCOM_PCIE_EP_LINK_UP,
163 QCOM_PCIE_EP_LINK_DOWN,
164 };
165
166 /**
167 * struct qcom_pcie_ep_cfg - Per SoC config struct
168 * @hdma_support: HDMA support on this SoC
169 * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache snooping
170 * @disable_mhi_ram_parity_check: Disable MHI RAM data parity error check
171 */
172 struct qcom_pcie_ep_cfg {
173 bool hdma_support;
174 bool override_no_snoop;
175 bool disable_mhi_ram_parity_check;
176 };
177
178 /**
179 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller
180 * @pci: Designware PCIe controller struct
181 * @parf: Qualcomm PCIe specific PARF register base
182 * @elbi: Designware PCIe specific ELBI register base
183 * @mmio: MMIO register base
184 * @perst_map: PERST regmap
185 * @mmio_res: MMIO region resource
186 * @core_reset: PCIe Endpoint core reset
187 * @reset: PERST# GPIO
188 * @wake: WAKE# GPIO
189 * @phy: PHY controller block
190 * @debugfs: PCIe Endpoint Debugfs directory
191 * @icc_mem: Handle to an interconnect path between PCIe and MEM
192 * @clks: PCIe clocks
193 * @num_clks: PCIe clocks count
194 * @perst_en: Flag for PERST enable
195 * @perst_sep_en: Flag for PERST separation enable
196 * @cfg: PCIe EP config struct
197 * @link_status: PCIe Link status
198 * @global_irq: Qualcomm PCIe specific Global IRQ
199 * @perst_irq: PERST# IRQ
200 */
201 struct qcom_pcie_ep {
202 struct dw_pcie pci;
203
204 void __iomem *parf;
205 void __iomem *elbi;
206 void __iomem *mmio;
207 struct regmap *perst_map;
208 struct resource *mmio_res;
209
210 struct reset_control *core_reset;
211 struct gpio_desc *reset;
212 struct gpio_desc *wake;
213 struct phy *phy;
214 struct dentry *debugfs;
215
216 struct icc_path *icc_mem;
217
218 struct clk_bulk_data *clks;
219 int num_clks;
220
221 u32 perst_en;
222 u32 perst_sep_en;
223
224 const struct qcom_pcie_ep_cfg *cfg;
225 enum qcom_pcie_ep_link_status link_status;
226 int global_irq;
227 int perst_irq;
228 };
229
qcom_pcie_ep_core_reset(struct qcom_pcie_ep * pcie_ep)230 static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep)
231 {
232 struct dw_pcie *pci = &pcie_ep->pci;
233 struct device *dev = pci->dev;
234 int ret;
235
236 ret = reset_control_assert(pcie_ep->core_reset);
237 if (ret) {
238 dev_err(dev, "Cannot assert core reset\n");
239 return ret;
240 }
241
242 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);
243
244 ret = reset_control_deassert(pcie_ep->core_reset);
245 if (ret) {
246 dev_err(dev, "Cannot de-assert core reset\n");
247 return ret;
248 }
249
250 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);
251
252 return 0;
253 }
254
255 /*
256 * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid
257 * device reset during host reboot and hibernation. The driver is
258 * expected to handle this situation.
259 */
qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep * pcie_ep)260 static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep)
261 {
262 if (pcie_ep->perst_map) {
263 regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0);
264 regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0);
265 }
266 }
267
qcom_pcie_dw_link_up(struct dw_pcie * pci)268 static bool qcom_pcie_dw_link_up(struct dw_pcie *pci)
269 {
270 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
271 u32 reg;
272
273 reg = readl_relaxed(pcie_ep->elbi + ELBI_SYS_STTS);
274
275 return reg & XMLH_LINK_UP;
276 }
277
qcom_pcie_dw_start_link(struct dw_pcie * pci)278 static int qcom_pcie_dw_start_link(struct dw_pcie *pci)
279 {
280 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
281
282 enable_irq(pcie_ep->perst_irq);
283
284 return 0;
285 }
286
qcom_pcie_dw_stop_link(struct dw_pcie * pci)287 static void qcom_pcie_dw_stop_link(struct dw_pcie *pci)
288 {
289 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
290
291 disable_irq(pcie_ep->perst_irq);
292 }
293
qcom_pcie_dw_write_dbi2(struct dw_pcie * pci,void __iomem * base,u32 reg,size_t size,u32 val)294 static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base,
295 u32 reg, size_t size, u32 val)
296 {
297 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
298 int ret;
299
300 writel(1, pcie_ep->elbi + ELBI_CS2_ENABLE);
301
302 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
303 if (ret)
304 dev_err(pci->dev, "Failed to write DBI2 register (0x%x): %d\n", reg, ret);
305
306 writel(0, pcie_ep->elbi + ELBI_CS2_ENABLE);
307 }
308
qcom_pcie_ep_icc_update(struct qcom_pcie_ep * pcie_ep)309 static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)
310 {
311 struct dw_pcie *pci = &pcie_ep->pci;
312 u32 offset, status;
313 int speed, width;
314 int ret;
315
316 if (!pcie_ep->icc_mem)
317 return;
318
319 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
320 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
321
322 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
323 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
324
325 ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
326 if (ret)
327 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
328 ret);
329 }
330
qcom_pcie_enable_resources(struct qcom_pcie_ep * pcie_ep)331 static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
332 {
333 struct dw_pcie *pci = &pcie_ep->pci;
334 int ret;
335
336 ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks);
337 if (ret)
338 return ret;
339
340 ret = qcom_pcie_ep_core_reset(pcie_ep);
341 if (ret)
342 goto err_disable_clk;
343
344 ret = phy_init(pcie_ep->phy);
345 if (ret)
346 goto err_disable_clk;
347
348 ret = phy_set_mode_ext(pcie_ep->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_EP);
349 if (ret)
350 goto err_phy_exit;
351
352 ret = phy_power_on(pcie_ep->phy);
353 if (ret)
354 goto err_phy_exit;
355
356 /*
357 * Some Qualcomm platforms require interconnect bandwidth constraints
358 * to be set before enabling interconnect clocks.
359 *
360 * Set an initial peak bandwidth corresponding to single-lane Gen 1
361 * for the pcie-mem path.
362 */
363 ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
364 if (ret) {
365 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
366 ret);
367 goto err_phy_off;
368 }
369
370 return 0;
371
372 err_phy_off:
373 phy_power_off(pcie_ep->phy);
374 err_phy_exit:
375 phy_exit(pcie_ep->phy);
376 err_disable_clk:
377 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
378
379 return ret;
380 }
381
qcom_pcie_disable_resources(struct qcom_pcie_ep * pcie_ep)382 static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep)
383 {
384 icc_set_bw(pcie_ep->icc_mem, 0, 0);
385 phy_power_off(pcie_ep->phy);
386 phy_exit(pcie_ep->phy);
387 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
388 }
389
qcom_pcie_perst_deassert(struct dw_pcie * pci)390 static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
391 {
392 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
393 struct device *dev = pci->dev;
394 u32 val, offset;
395 int ret;
396
397 ret = qcom_pcie_enable_resources(pcie_ep);
398 if (ret) {
399 dev_err(dev, "Failed to enable resources: %d\n", ret);
400 return ret;
401 }
402
403 /* Perform cleanup that requires refclk */
404 pci_epc_deinit_notify(pci->ep.epc);
405 dw_pcie_ep_cleanup(&pci->ep);
406
407 /* Assert WAKE# to RC to indicate device is ready */
408 gpiod_set_value_cansleep(pcie_ep->wake, 1);
409 usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500);
410 gpiod_set_value_cansleep(pcie_ep->wake, 0);
411
412 qcom_pcie_ep_configure_tcsr(pcie_ep);
413
414 /* Disable BDF to SID mapping */
415 val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG);
416 val |= PARF_BDF_TO_SID_BYPASS;
417 writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG);
418
419 /* Enable debug IRQ */
420 val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN);
421 val |= PARF_DEBUG_INT_RADM_PM_TURNOFF |
422 PARF_DEBUG_INT_CFG_BUS_MASTER_EN |
423 PARF_DEBUG_INT_PM_DSTATE_CHANGE;
424 writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN);
425
426 /* Configure PCIe to endpoint mode */
427 writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE);
428
429 /* Allow entering L1 state */
430 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
431 val &= ~PARF_PM_CTRL_REQ_NOT_ENTR_L1;
432 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
433
434 /* Read halts write */
435 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
436 val &= ~PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN;
437 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
438
439 /* Write after write halt */
440 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
441 val |= PARF_AXI_MSTR_WR_ADDR_HALT_EN;
442 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
443
444 /* Q2A flush disable */
445 val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH);
446 val &= ~PARF_Q2A_FLUSH_EN;
447 writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH);
448
449 /*
450 * Disable Master AXI clock during idle. Do not allow DBI access
451 * to take the core out of L1. Disable core clock gating that
452 * gates PIPE clock from propagating to core clock. Report to the
453 * host that Vaux is present.
454 */
455 val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL);
456 val &= ~PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS;
457 val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE |
458 PARF_SYS_CTRL_CORE_CLK_CGC_DIS |
459 PARF_SYS_CTRL_AUX_PWR_DET;
460 writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL);
461
462 /* Disable the debouncers */
463 val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL);
464 val |= PARF_DB_CTRL_INSR_DBNCR_BLOCK | PARF_DB_CTRL_RMVL_DBNCR_BLOCK |
465 PARF_DB_CTRL_DBI_WKP_BLOCK | PARF_DB_CTRL_SLV_WKP_BLOCK |
466 PARF_DB_CTRL_MST_WKP_BLOCK;
467 writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL);
468
469 /* Request to exit from L1SS for MSI and LTR MSG */
470 val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS);
471 val |= PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN;
472 writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS);
473
474 dw_pcie_dbi_ro_wr_en(pci);
475
476 /* Set the L0s Exit Latency to 2us-4us = 0x6 */
477 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
478 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
479 val &= ~PCI_EXP_LNKCAP_L0SEL;
480 val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6);
481 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
482
483 /* Set the L1 Exit Latency to be 32us-64 us = 0x6 */
484 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
485 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
486 val &= ~PCI_EXP_LNKCAP_L1EL;
487 val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6);
488 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
489
490 dw_pcie_dbi_ro_wr_dis(pci);
491
492 writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK);
493 val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME |
494 PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE |
495 PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA;
496 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);
497
498 if (pcie_ep->cfg && pcie_ep->cfg->disable_mhi_ram_parity_check) {
499 val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_5_MASK);
500 val &= ~PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR;
501 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_5_MASK);
502 }
503
504 val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_3_MASK);
505 val &= ~PARF_INT_ALL_3_PTM_UPDATING;
506 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_3_MASK);
507
508 ret = dw_pcie_ep_init_registers(&pcie_ep->pci.ep);
509 if (ret) {
510 dev_err(dev, "Failed to complete initialization: %d\n", ret);
511 goto err_disable_resources;
512 }
513
514 if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) {
515 qcom_pcie_common_set_16gt_equalization(pci);
516 qcom_pcie_common_set_16gt_lane_margining(pci);
517 }
518
519 /*
520 * The physical address of the MMIO region which is exposed as the BAR
521 * should be written to MHI BASE registers.
522 */
523 writel_relaxed(pcie_ep->mmio_res->start,
524 pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
525 writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
526
527 /* Gate Master AXI clock to MHI bus during L1SS */
528 val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
529 val &= ~PARF_MSTR_AXI_CLK_EN;
530 writel_relaxed(val, pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
531
532 pci_epc_init_notify(pcie_ep->pci.ep.epc);
533
534 /* Enable LTSSM */
535 val = readl_relaxed(pcie_ep->parf + PARF_LTSSM);
536 val |= BIT(8);
537 writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);
538
539 if (pcie_ep->cfg && pcie_ep->cfg->override_no_snoop)
540 writel_relaxed(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
541 pcie_ep->parf + PARF_NO_SNOOP_OVERRIDE);
542
543 return 0;
544
545 err_disable_resources:
546 qcom_pcie_disable_resources(pcie_ep);
547
548 return ret;
549 }
550
qcom_pcie_perst_assert(struct dw_pcie * pci)551 static void qcom_pcie_perst_assert(struct dw_pcie *pci)
552 {
553 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
554
555 qcom_pcie_disable_resources(pcie_ep);
556 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED;
557 }
558
559 /* Common DWC controller ops */
560 static const struct dw_pcie_ops pci_ops = {
561 .link_up = qcom_pcie_dw_link_up,
562 .start_link = qcom_pcie_dw_start_link,
563 .stop_link = qcom_pcie_dw_stop_link,
564 .write_dbi2 = qcom_pcie_dw_write_dbi2,
565 };
566
qcom_pcie_ep_get_io_resources(struct platform_device * pdev,struct qcom_pcie_ep * pcie_ep)567 static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev,
568 struct qcom_pcie_ep *pcie_ep)
569 {
570 struct device *dev = &pdev->dev;
571 struct dw_pcie *pci = &pcie_ep->pci;
572 struct device_node *syscon;
573 struct resource *res;
574 int ret;
575
576 pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
577 if (IS_ERR(pcie_ep->parf))
578 return PTR_ERR(pcie_ep->parf);
579
580 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
581 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
582 if (IS_ERR(pci->dbi_base))
583 return PTR_ERR(pci->dbi_base);
584 pci->dbi_base2 = pci->dbi_base;
585
586 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
587 pcie_ep->elbi = devm_pci_remap_cfg_resource(dev, res);
588 if (IS_ERR(pcie_ep->elbi))
589 return PTR_ERR(pcie_ep->elbi);
590
591 pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
592 "mmio");
593 if (!pcie_ep->mmio_res) {
594 dev_err(dev, "Failed to get mmio resource\n");
595 return -EINVAL;
596 }
597
598 pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res);
599 if (IS_ERR(pcie_ep->mmio))
600 return PTR_ERR(pcie_ep->mmio);
601
602 syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0);
603 if (!syscon) {
604 dev_dbg(dev, "PERST separation not available\n");
605 return 0;
606 }
607
608 pcie_ep->perst_map = syscon_node_to_regmap(syscon);
609 of_node_put(syscon);
610 if (IS_ERR(pcie_ep->perst_map))
611 return PTR_ERR(pcie_ep->perst_map);
612
613 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",
614 1, &pcie_ep->perst_en);
615 if (ret < 0) {
616 dev_err(dev, "No Perst Enable offset in syscon\n");
617 return ret;
618 }
619
620 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",
621 2, &pcie_ep->perst_sep_en);
622 if (ret < 0) {
623 dev_err(dev, "No Perst Separation Enable offset in syscon\n");
624 return ret;
625 }
626
627 return 0;
628 }
629
qcom_pcie_ep_get_resources(struct platform_device * pdev,struct qcom_pcie_ep * pcie_ep)630 static int qcom_pcie_ep_get_resources(struct platform_device *pdev,
631 struct qcom_pcie_ep *pcie_ep)
632 {
633 struct device *dev = &pdev->dev;
634 int ret;
635
636 ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep);
637 if (ret) {
638 dev_err(dev, "Failed to get io resources %d\n", ret);
639 return ret;
640 }
641
642 pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks);
643 if (pcie_ep->num_clks < 0) {
644 dev_err(dev, "Failed to get clocks\n");
645 return pcie_ep->num_clks;
646 }
647
648 pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core");
649 if (IS_ERR(pcie_ep->core_reset))
650 return PTR_ERR(pcie_ep->core_reset);
651
652 pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN);
653 if (IS_ERR(pcie_ep->reset))
654 return PTR_ERR(pcie_ep->reset);
655
656 pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW);
657 if (IS_ERR(pcie_ep->wake))
658 return PTR_ERR(pcie_ep->wake);
659
660 pcie_ep->phy = devm_phy_optional_get(dev, "pciephy");
661 if (IS_ERR(pcie_ep->phy))
662 ret = PTR_ERR(pcie_ep->phy);
663
664 pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem");
665 if (IS_ERR(pcie_ep->icc_mem))
666 ret = PTR_ERR(pcie_ep->icc_mem);
667
668 return ret;
669 }
670
671 /* TODO: Notify clients about PCIe state change */
qcom_pcie_ep_global_irq_thread(int irq,void * data)672 static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data)
673 {
674 struct qcom_pcie_ep *pcie_ep = data;
675 struct dw_pcie *pci = &pcie_ep->pci;
676 struct device *dev = pci->dev;
677 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS);
678 u32 dstate, val;
679
680 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR);
681
682 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) {
683 dev_dbg(dev, "Received Linkdown event\n");
684 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN;
685 dw_pcie_ep_linkdown(&pci->ep);
686 } else if (FIELD_GET(PARF_INT_ALL_BME, status)) {
687 dev_dbg(dev, "Received Bus Master Enable event\n");
688 pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED;
689 qcom_pcie_ep_icc_update(pcie_ep);
690 pci_epc_bus_master_enable_notify(pci->ep.epc);
691 } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) {
692 dev_dbg(dev, "Received PM Turn-off event! Entering L23\n");
693 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
694 val |= PARF_PM_CTRL_READY_ENTR_L23;
695 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
696 } else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) {
697 dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) &
698 DBI_CON_STATUS_POWER_STATE_MASK;
699 dev_dbg(dev, "Received D%d state event\n", dstate);
700 if (dstate == 3) {
701 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
702 val |= PARF_PM_CTRL_REQ_EXIT_L1;
703 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
704 }
705 } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) {
706 dev_dbg(dev, "Received Linkup event. Enumeration complete!\n");
707 dw_pcie_ep_linkup(&pci->ep);
708 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP;
709 } else {
710 dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n",
711 status);
712 }
713
714 return IRQ_HANDLED;
715 }
716
qcom_pcie_ep_perst_irq_thread(int irq,void * data)717 static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data)
718 {
719 struct qcom_pcie_ep *pcie_ep = data;
720 struct dw_pcie *pci = &pcie_ep->pci;
721 struct device *dev = pci->dev;
722 u32 perst;
723
724 perst = gpiod_get_value(pcie_ep->reset);
725 if (perst) {
726 dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link!\n");
727 qcom_pcie_perst_assert(pci);
728 } else {
729 dev_dbg(dev, "PERST de-asserted by host. Starting link training!\n");
730 qcom_pcie_perst_deassert(pci);
731 }
732
733 irq_set_irq_type(gpiod_to_irq(pcie_ep->reset),
734 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW));
735
736 return IRQ_HANDLED;
737 }
738
qcom_pcie_ep_enable_irq_resources(struct platform_device * pdev,struct qcom_pcie_ep * pcie_ep)739 static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,
740 struct qcom_pcie_ep *pcie_ep)
741 {
742 struct device *dev = pcie_ep->pci.dev;
743 char *name;
744 int ret;
745
746 name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_global_irq%d",
747 pcie_ep->pci.ep.epc->domain_nr);
748 if (!name)
749 return -ENOMEM;
750
751 pcie_ep->global_irq = platform_get_irq_byname(pdev, "global");
752 if (pcie_ep->global_irq < 0)
753 return pcie_ep->global_irq;
754
755 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL,
756 qcom_pcie_ep_global_irq_thread,
757 IRQF_ONESHOT,
758 name, pcie_ep);
759 if (ret) {
760 dev_err(&pdev->dev, "Failed to request Global IRQ\n");
761 return ret;
762 }
763
764 name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_perst_irq%d",
765 pcie_ep->pci.ep.epc->domain_nr);
766 if (!name)
767 return -ENOMEM;
768
769 pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset);
770 irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN);
771 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL,
772 qcom_pcie_ep_perst_irq_thread,
773 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
774 name, pcie_ep);
775 if (ret) {
776 dev_err(&pdev->dev, "Failed to request PERST IRQ\n");
777 disable_irq(pcie_ep->global_irq);
778 return ret;
779 }
780
781 return 0;
782 }
783
qcom_pcie_ep_raise_irq(struct dw_pcie_ep * ep,u8 func_no,unsigned int type,u16 interrupt_num)784 static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
785 unsigned int type, u16 interrupt_num)
786 {
787 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
788
789 switch (type) {
790 case PCI_IRQ_INTX:
791 return dw_pcie_ep_raise_intx_irq(ep, func_no);
792 case PCI_IRQ_MSI:
793 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
794 default:
795 dev_err(pci->dev, "Unknown IRQ type\n");
796 return -EINVAL;
797 }
798 }
799
qcom_pcie_ep_link_transition_count(struct seq_file * s,void * data)800 static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data)
801 {
802 struct qcom_pcie_ep *pcie_ep = (struct qcom_pcie_ep *)
803 dev_get_drvdata(s->private);
804
805 seq_printf(s, "L0s transition count: %u\n",
806 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S));
807
808 seq_printf(s, "L1 transition count: %u\n",
809 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1));
810
811 seq_printf(s, "L1.1 transition count: %u\n",
812 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1));
813
814 seq_printf(s, "L1.2 transition count: %u\n",
815 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2));
816
817 seq_printf(s, "L2 transition count: %u\n",
818 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2));
819
820 return 0;
821 }
822
qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep * pcie_ep)823 static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep)
824 {
825 struct dw_pcie *pci = &pcie_ep->pci;
826
827 debugfs_create_devm_seqfile(pci->dev, "link_transition_count", pcie_ep->debugfs,
828 qcom_pcie_ep_link_transition_count);
829 }
830
831 static const struct pci_epc_features qcom_pcie_epc_features = {
832 .linkup_notifier = true,
833 .msi_capable = true,
834 .msix_capable = false,
835 .align = SZ_4K,
836 .bar[BAR_0] = { .only_64bit = true, },
837 .bar[BAR_1] = { .type = BAR_RESERVED, },
838 .bar[BAR_2] = { .only_64bit = true, },
839 .bar[BAR_3] = { .type = BAR_RESERVED, },
840 };
841
842 static const struct pci_epc_features *
qcom_pcie_epc_get_features(struct dw_pcie_ep * pci_ep)843 qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep)
844 {
845 return &qcom_pcie_epc_features;
846 }
847
qcom_pcie_ep_init(struct dw_pcie_ep * ep)848 static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)
849 {
850 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
851 enum pci_barno bar;
852
853 for (bar = BAR_0; bar <= BAR_5; bar++)
854 dw_pcie_ep_reset_bar(pci, bar);
855 }
856
857 static const struct dw_pcie_ep_ops pci_ep_ops = {
858 .init = qcom_pcie_ep_init,
859 .raise_irq = qcom_pcie_ep_raise_irq,
860 .get_features = qcom_pcie_epc_get_features,
861 };
862
qcom_pcie_ep_probe(struct platform_device * pdev)863 static int qcom_pcie_ep_probe(struct platform_device *pdev)
864 {
865 struct device *dev = &pdev->dev;
866 struct qcom_pcie_ep *pcie_ep;
867 char *name;
868 int ret;
869
870 pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
871 if (!pcie_ep)
872 return -ENOMEM;
873
874 pcie_ep->pci.dev = dev;
875 pcie_ep->pci.ops = &pci_ops;
876 pcie_ep->pci.ep.ops = &pci_ep_ops;
877 pcie_ep->pci.edma.nr_irqs = 1;
878
879 pcie_ep->cfg = of_device_get_match_data(dev);
880 if (pcie_ep->cfg && pcie_ep->cfg->hdma_support) {
881 pcie_ep->pci.edma.ll_wr_cnt = 8;
882 pcie_ep->pci.edma.ll_rd_cnt = 8;
883 pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE;
884 }
885
886 platform_set_drvdata(pdev, pcie_ep);
887
888 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep);
889 if (ret)
890 return ret;
891
892 ret = dw_pcie_ep_init(&pcie_ep->pci.ep);
893 if (ret) {
894 dev_err(dev, "Failed to initialize endpoint: %d\n", ret);
895 return ret;
896 }
897
898 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep);
899 if (ret)
900 goto err_ep_deinit;
901
902 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
903 if (!name) {
904 ret = -ENOMEM;
905 goto err_disable_irqs;
906 }
907
908 pcie_ep->debugfs = debugfs_create_dir(name, NULL);
909 qcom_pcie_ep_init_debugfs(pcie_ep);
910
911 return 0;
912
913 err_disable_irqs:
914 disable_irq(pcie_ep->global_irq);
915 disable_irq(pcie_ep->perst_irq);
916
917 err_ep_deinit:
918 dw_pcie_ep_deinit(&pcie_ep->pci.ep);
919
920 return ret;
921 }
922
qcom_pcie_ep_remove(struct platform_device * pdev)923 static void qcom_pcie_ep_remove(struct platform_device *pdev)
924 {
925 struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev);
926
927 disable_irq(pcie_ep->global_irq);
928 disable_irq(pcie_ep->perst_irq);
929
930 debugfs_remove_recursive(pcie_ep->debugfs);
931
932 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED)
933 return;
934
935 qcom_pcie_disable_resources(pcie_ep);
936 }
937
938 static const struct qcom_pcie_ep_cfg cfg_1_34_0 = {
939 .hdma_support = true,
940 .override_no_snoop = true,
941 .disable_mhi_ram_parity_check = true,
942 };
943
944 static const struct of_device_id qcom_pcie_ep_match[] = {
945 { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0},
946 { .compatible = "qcom,sdx55-pcie-ep", },
947 { .compatible = "qcom,sm8450-pcie-ep", },
948 { .compatible = "qcom,sar2130p-pcie-ep", },
949 { }
950 };
951 MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match);
952
953 static struct platform_driver qcom_pcie_ep_driver = {
954 .probe = qcom_pcie_ep_probe,
955 .remove = qcom_pcie_ep_remove,
956 .driver = {
957 .name = "qcom-pcie-ep",
958 .of_match_table = qcom_pcie_ep_match,
959 },
960 };
961 builtin_platform_driver(qcom_pcie_ep_driver);
962
963 MODULE_AUTHOR("Siddartha Mohanadoss <smohanad@codeaurora.org>");
964 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
965 MODULE_DESCRIPTION("Qualcomm PCIe Endpoint controller driver");
966 MODULE_LICENSE("GPL v2");
967