1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2021 Intel Corporation 3 4 #include <linux/auxiliary_bus.h> 5 #include <linux/bitfield.h> 6 #include <linux/bitops.h> 7 #include <linux/devm-helpers.h> 8 #include <linux/hwmon.h> 9 #include <linux/jiffies.h> 10 #include <linux/module.h> 11 #include <linux/peci.h> 12 #include <linux/peci-cpu.h> 13 #include <linux/units.h> 14 #include <linux/workqueue.h> 15 16 #include "common.h" 17 18 #define DIMM_MASK_CHECK_DELAY_JIFFIES msecs_to_jiffies(5000) 19 20 /* Max number of channel ranks and DIMM index per channel */ 21 #define CHAN_RANK_MAX_ON_HSX 8 22 #define DIMM_IDX_MAX_ON_HSX 3 23 #define CHAN_RANK_MAX_ON_BDX 4 24 #define DIMM_IDX_MAX_ON_BDX 3 25 #define CHAN_RANK_MAX_ON_BDXD 2 26 #define DIMM_IDX_MAX_ON_BDXD 2 27 #define CHAN_RANK_MAX_ON_SKX 6 28 #define DIMM_IDX_MAX_ON_SKX 2 29 #define CHAN_RANK_MAX_ON_ICX 8 30 #define DIMM_IDX_MAX_ON_ICX 2 31 #define CHAN_RANK_MAX_ON_ICXD 4 32 #define DIMM_IDX_MAX_ON_ICXD 2 33 #define CHAN_RANK_MAX_ON_SPR 8 34 #define DIMM_IDX_MAX_ON_SPR 2 35 #define CHAN_RANK_MAX_ON_EMR 8 36 #define DIMM_IDX_MAX_ON_EMR 2 37 38 #define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX 39 #define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX 40 #define DIMM_NUMS_MAX (CHAN_RANK_MAX * DIMM_IDX_MAX) 41 42 #define CPU_SEG_MASK GENMASK(23, 16) 43 #define GET_CPU_SEG(x) (((x) & CPU_SEG_MASK) >> 16) 44 #define CPU_BUS_MASK GENMASK(7, 0) 45 #define GET_CPU_BUS(x) ((x) & CPU_BUS_MASK) 46 47 #define DIMM_TEMP_MAX GENMASK(15, 8) 48 #define DIMM_TEMP_CRIT GENMASK(23, 16) 49 #define GET_TEMP_MAX(x) (((x) & DIMM_TEMP_MAX) >> 8) 50 #define GET_TEMP_CRIT(x) (((x) & DIMM_TEMP_CRIT) >> 16) 51 52 #define NO_DIMM_RETRY_COUNT_MAX 120 53 54 struct peci_dimmtemp; 55 56 struct dimm_info { 57 int chan_rank_max; 58 int dimm_idx_max; 59 u8 min_peci_revision; 60 int (*read_thresholds)(struct peci_dimmtemp *priv, int dimm_order, 61 int chan_rank, u32 *data); 62 }; 63 64 struct peci_dimm_thresholds { 65 long temp_max; 66 long temp_crit; 67 struct peci_sensor_state state; 68 }; 69 70 enum peci_dimm_threshold_type { 71 temp_max_type, 72 temp_crit_type, 73 }; 74 75 struct peci_dimmtemp { 76 struct peci_device *peci_dev; 77 struct device *dev; 78 const char *name; 79 const struct dimm_info *gen_info; 80 struct delayed_work detect_work; 81 struct { 82 struct peci_sensor_data temp; 83 struct peci_dimm_thresholds thresholds; 84 } dimm[DIMM_NUMS_MAX]; 85 char **dimmtemp_label; 86 DECLARE_BITMAP(dimm_mask, DIMM_NUMS_MAX); 87 u8 no_dimm_retry_count; 88 }; 89 90 static u8 __dimm_temp(u32 reg, int dimm_order) 91 { 92 return (reg >> (dimm_order * 8)) & 0xff; 93 } 94 95 static int get_dimm_temp(struct peci_dimmtemp *priv, int dimm_no, long *val) 96 { 97 int dimm_order = dimm_no % priv->gen_info->dimm_idx_max; 98 int chan_rank = dimm_no / priv->gen_info->dimm_idx_max; 99 u32 data; 100 int ret; 101 102 if (!peci_sensor_need_update(&priv->dimm[dimm_no].temp.state)) 103 goto skip_update; 104 105 ret = peci_pcs_read(priv->peci_dev, PECI_PCS_DDR_DIMM_TEMP, chan_rank, &data); 106 if (ret) 107 return ret; 108 109 priv->dimm[dimm_no].temp.value = __dimm_temp(data, dimm_order) * MILLIDEGREE_PER_DEGREE; 110 111 peci_sensor_mark_updated(&priv->dimm[dimm_no].temp.state); 112 113 skip_update: 114 *val = priv->dimm[dimm_no].temp.value; 115 return 0; 116 } 117 118 static int update_thresholds(struct peci_dimmtemp *priv, int dimm_no) 119 { 120 int dimm_order = dimm_no % priv->gen_info->dimm_idx_max; 121 int chan_rank = dimm_no / priv->gen_info->dimm_idx_max; 122 u32 data; 123 int ret; 124 125 if (!peci_sensor_need_update(&priv->dimm[dimm_no].thresholds.state)) 126 return 0; 127 128 ret = priv->gen_info->read_thresholds(priv, dimm_order, chan_rank, &data); 129 if (ret) 130 return ret; 131 132 priv->dimm[dimm_no].thresholds.temp_max = GET_TEMP_MAX(data) * MILLIDEGREE_PER_DEGREE; 133 priv->dimm[dimm_no].thresholds.temp_crit = GET_TEMP_CRIT(data) * MILLIDEGREE_PER_DEGREE; 134 135 peci_sensor_mark_updated(&priv->dimm[dimm_no].thresholds.state); 136 137 return 0; 138 } 139 140 static int get_dimm_thresholds(struct peci_dimmtemp *priv, enum peci_dimm_threshold_type type, 141 int dimm_no, long *val) 142 { 143 int ret; 144 145 ret = update_thresholds(priv, dimm_no); 146 if (ret) 147 return ret; 148 149 switch (type) { 150 case temp_max_type: 151 *val = priv->dimm[dimm_no].thresholds.temp_max; 152 break; 153 case temp_crit_type: 154 *val = priv->dimm[dimm_no].thresholds.temp_crit; 155 break; 156 default: 157 ret = -EOPNOTSUPP; 158 break; 159 } 160 return ret; 161 } 162 163 static int dimmtemp_read_string(struct device *dev, 164 enum hwmon_sensor_types type, 165 u32 attr, int channel, const char **str) 166 { 167 struct peci_dimmtemp *priv = dev_get_drvdata(dev); 168 169 if (attr != hwmon_temp_label) 170 return -EOPNOTSUPP; 171 172 *str = (const char *)priv->dimmtemp_label[channel]; 173 174 return 0; 175 } 176 177 static int dimmtemp_read(struct device *dev, enum hwmon_sensor_types type, 178 u32 attr, int channel, long *val) 179 { 180 struct peci_dimmtemp *priv = dev_get_drvdata(dev); 181 182 switch (attr) { 183 case hwmon_temp_input: 184 return get_dimm_temp(priv, channel, val); 185 case hwmon_temp_max: 186 return get_dimm_thresholds(priv, temp_max_type, channel, val); 187 case hwmon_temp_crit: 188 return get_dimm_thresholds(priv, temp_crit_type, channel, val); 189 default: 190 break; 191 } 192 193 return -EOPNOTSUPP; 194 } 195 196 static umode_t dimmtemp_is_visible(const void *data, enum hwmon_sensor_types type, 197 u32 attr, int channel) 198 { 199 const struct peci_dimmtemp *priv = data; 200 201 if (test_bit(channel, priv->dimm_mask)) 202 return 0444; 203 204 return 0; 205 } 206 207 static const struct hwmon_ops peci_dimmtemp_ops = { 208 .is_visible = dimmtemp_is_visible, 209 .read_string = dimmtemp_read_string, 210 .read = dimmtemp_read, 211 }; 212 213 static int check_populated_dimms(struct peci_dimmtemp *priv) 214 { 215 int chan_rank_max = priv->gen_info->chan_rank_max; 216 int dimm_idx_max = priv->gen_info->dimm_idx_max; 217 DECLARE_BITMAP(dimm_mask, DIMM_NUMS_MAX); 218 DECLARE_BITMAP(chan_rank_empty, CHAN_RANK_MAX); 219 220 int chan_rank, dimm_idx, ret, i; 221 u32 pcs; 222 223 if (chan_rank_max * dimm_idx_max > DIMM_NUMS_MAX) { 224 WARN_ONCE(1, "Unsupported number of DIMMs - chan_rank_max: %d, dimm_idx_max: %d", 225 chan_rank_max, dimm_idx_max); 226 return -EINVAL; 227 } 228 229 bitmap_zero(dimm_mask, DIMM_NUMS_MAX); 230 bitmap_zero(chan_rank_empty, CHAN_RANK_MAX); 231 232 for (chan_rank = 0; chan_rank < chan_rank_max; chan_rank++) { 233 ret = peci_pcs_read(priv->peci_dev, PECI_PCS_DDR_DIMM_TEMP, chan_rank, &pcs); 234 if (ret) { 235 /* 236 * Overall, we expect either success or -EINVAL in 237 * order to determine whether DIMM is populated or not. 238 * For anything else we fall back to deferring the 239 * detection to be performed at a later point in time. 240 */ 241 if (ret == -EINVAL) { 242 bitmap_set(chan_rank_empty, chan_rank, 1); 243 continue; 244 } 245 246 return -EAGAIN; 247 } 248 249 for (dimm_idx = 0; dimm_idx < dimm_idx_max; dimm_idx++) 250 if (__dimm_temp(pcs, dimm_idx)) 251 bitmap_set(dimm_mask, chan_rank * dimm_idx_max + dimm_idx, 1); 252 } 253 254 /* 255 * If we got all -EINVALs, it means that the CPU doesn't have any 256 * DIMMs. Unfortunately, it may also happen at the very start of 257 * host platform boot. Retrying a couple of times lets us make sure 258 * that the state is persistent. 259 */ 260 if (bitmap_full(chan_rank_empty, chan_rank_max)) { 261 if (priv->no_dimm_retry_count < NO_DIMM_RETRY_COUNT_MAX) { 262 priv->no_dimm_retry_count++; 263 264 return -EAGAIN; 265 } 266 267 return -ENODEV; 268 } 269 270 /* 271 * It's possible that memory training is not done yet. In this case we 272 * defer the detection to be performed at a later point in time. 273 */ 274 if (bitmap_empty(dimm_mask, DIMM_NUMS_MAX)) { 275 priv->no_dimm_retry_count = 0; 276 return -EAGAIN; 277 } 278 279 for_each_set_bit(i, dimm_mask, DIMM_NUMS_MAX) { 280 dev_dbg(priv->dev, "Found DIMM%#x\n", i); 281 } 282 283 bitmap_copy(priv->dimm_mask, dimm_mask, DIMM_NUMS_MAX); 284 285 return 0; 286 } 287 288 static int create_dimm_temp_label(struct peci_dimmtemp *priv, int chan) 289 { 290 int rank = chan / priv->gen_info->dimm_idx_max; 291 int idx = chan % priv->gen_info->dimm_idx_max; 292 293 priv->dimmtemp_label[chan] = devm_kasprintf(priv->dev, GFP_KERNEL, 294 "DIMM %c%d", 'A' + rank, 295 idx + 1); 296 if (!priv->dimmtemp_label[chan]) 297 return -ENOMEM; 298 299 return 0; 300 } 301 302 static const struct hwmon_channel_info * const peci_dimmtemp_temp_info[] = { 303 HWMON_CHANNEL_INFO(temp, 304 [0 ... DIMM_NUMS_MAX - 1] = HWMON_T_LABEL | 305 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT), 306 NULL 307 }; 308 309 static const struct hwmon_chip_info peci_dimmtemp_chip_info = { 310 .ops = &peci_dimmtemp_ops, 311 .info = peci_dimmtemp_temp_info, 312 }; 313 314 static int create_dimm_temp_info(struct peci_dimmtemp *priv) 315 { 316 int ret, i, channels; 317 struct device *dev; 318 319 /* 320 * We expect to either find populated DIMMs and carry on with creating 321 * sensors, or find out that there are no DIMMs populated. 322 * All other states mean that the platform never reached the state that 323 * allows to check DIMM state - causing us to retry later on. 324 */ 325 ret = check_populated_dimms(priv); 326 if (ret == -ENODEV) { 327 dev_dbg(priv->dev, "No DIMMs found\n"); 328 return 0; 329 } else if (ret) { 330 schedule_delayed_work(&priv->detect_work, DIMM_MASK_CHECK_DELAY_JIFFIES); 331 dev_dbg(priv->dev, "Deferred populating DIMM temp info\n"); 332 return ret; 333 } 334 335 channels = priv->gen_info->chan_rank_max * priv->gen_info->dimm_idx_max; 336 337 priv->dimmtemp_label = devm_kzalloc(priv->dev, channels * sizeof(char *), GFP_KERNEL); 338 if (!priv->dimmtemp_label) 339 return -ENOMEM; 340 341 for_each_set_bit(i, priv->dimm_mask, DIMM_NUMS_MAX) { 342 ret = create_dimm_temp_label(priv, i); 343 if (ret) 344 return ret; 345 } 346 347 dev = devm_hwmon_device_register_with_info(priv->dev, priv->name, priv, 348 &peci_dimmtemp_chip_info, NULL); 349 if (IS_ERR(dev)) { 350 dev_err(priv->dev, "Failed to register hwmon device\n"); 351 return PTR_ERR(dev); 352 } 353 354 dev_dbg(priv->dev, "%s: sensor '%s'\n", dev_name(dev), priv->name); 355 356 return 0; 357 } 358 359 static void create_dimm_temp_info_delayed(struct work_struct *work) 360 { 361 struct peci_dimmtemp *priv = container_of(to_delayed_work(work), 362 struct peci_dimmtemp, 363 detect_work); 364 int ret; 365 366 ret = create_dimm_temp_info(priv); 367 if (ret && ret != -EAGAIN) 368 dev_err(priv->dev, "Failed to populate DIMM temp info\n"); 369 } 370 371 static int peci_dimmtemp_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id) 372 { 373 struct device *dev = &adev->dev; 374 struct peci_device *peci_dev = to_peci_device(dev->parent); 375 struct peci_dimmtemp *priv; 376 int ret; 377 378 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 379 if (!priv) 380 return -ENOMEM; 381 382 priv->name = devm_kasprintf(dev, GFP_KERNEL, "peci_dimmtemp.cpu%d", 383 peci_dev->info.socket_id); 384 if (!priv->name) 385 return -ENOMEM; 386 387 priv->dev = dev; 388 priv->peci_dev = peci_dev; 389 priv->gen_info = (const struct dimm_info *)id->driver_data; 390 391 /* 392 * This is just a sanity check. Since we're using commands that are 393 * guaranteed to be supported on a given platform, we should never see 394 * revision lower than expected. 395 */ 396 if (peci_dev->info.peci_revision < priv->gen_info->min_peci_revision) 397 dev_warn(priv->dev, 398 "Unexpected PECI revision %#x, some features may be unavailable\n", 399 peci_dev->info.peci_revision); 400 401 ret = devm_delayed_work_autocancel(priv->dev, &priv->detect_work, 402 create_dimm_temp_info_delayed); 403 if (ret) 404 return ret; 405 406 ret = create_dimm_temp_info(priv); 407 if (ret && ret != -EAGAIN) { 408 dev_err(dev, "Failed to populate DIMM temp info\n"); 409 return ret; 410 } 411 412 return 0; 413 } 414 415 static int 416 read_thresholds_hsx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data) 417 { 418 u8 dev, func; 419 u16 reg; 420 int ret; 421 422 /* 423 * Device 20, Function 0: IMC 0 channel 0 -> rank 0 424 * Device 20, Function 1: IMC 0 channel 1 -> rank 1 425 * Device 21, Function 0: IMC 0 channel 2 -> rank 2 426 * Device 21, Function 1: IMC 0 channel 3 -> rank 3 427 * Device 23, Function 0: IMC 1 channel 0 -> rank 4 428 * Device 23, Function 1: IMC 1 channel 1 -> rank 5 429 * Device 24, Function 0: IMC 1 channel 2 -> rank 6 430 * Device 24, Function 1: IMC 1 channel 3 -> rank 7 431 */ 432 dev = 20 + chan_rank / 2 + chan_rank / 4; 433 func = chan_rank % 2; 434 reg = 0x120 + dimm_order * 4; 435 436 ret = peci_pci_local_read(priv->peci_dev, 1, dev, func, reg, data); 437 if (ret) 438 return ret; 439 440 return 0; 441 } 442 443 static int 444 read_thresholds_bdxd(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data) 445 { 446 u8 dev, func; 447 u16 reg; 448 int ret; 449 450 /* 451 * Device 10, Function 2: IMC 0 channel 0 -> rank 0 452 * Device 10, Function 6: IMC 0 channel 1 -> rank 1 453 * Device 12, Function 2: IMC 1 channel 0 -> rank 2 454 * Device 12, Function 6: IMC 1 channel 1 -> rank 3 455 */ 456 dev = 10 + chan_rank / 2 * 2; 457 func = (chan_rank % 2) ? 6 : 2; 458 reg = 0x120 + dimm_order * 4; 459 460 ret = peci_pci_local_read(priv->peci_dev, 2, dev, func, reg, data); 461 if (ret) 462 return ret; 463 464 return 0; 465 } 466 467 static int 468 read_thresholds_skx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data) 469 { 470 u8 dev, func; 471 u16 reg; 472 int ret; 473 474 /* 475 * Device 10, Function 2: IMC 0 channel 0 -> rank 0 476 * Device 10, Function 6: IMC 0 channel 1 -> rank 1 477 * Device 11, Function 2: IMC 0 channel 2 -> rank 2 478 * Device 12, Function 2: IMC 1 channel 0 -> rank 3 479 * Device 12, Function 6: IMC 1 channel 1 -> rank 4 480 * Device 13, Function 2: IMC 1 channel 2 -> rank 5 481 */ 482 dev = 10 + chan_rank / 3 * 2 + (chan_rank % 3 == 2 ? 1 : 0); 483 func = chan_rank % 3 == 1 ? 6 : 2; 484 reg = 0x120 + dimm_order * 4; 485 486 ret = peci_pci_local_read(priv->peci_dev, 2, dev, func, reg, data); 487 if (ret) 488 return ret; 489 490 return 0; 491 } 492 493 static int 494 read_thresholds_icx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data) 495 { 496 u32 reg_val; 497 u64 offset; 498 int ret; 499 u8 dev; 500 501 ret = peci_ep_pci_local_read(priv->peci_dev, 0, 13, 0, 2, 0xd4, ®_val); 502 if (ret || !(reg_val & BIT(31))) 503 return -ENODATA; 504 505 ret = peci_ep_pci_local_read(priv->peci_dev, 0, 13, 0, 2, 0xd0, ®_val); 506 if (ret) 507 return -ENODATA; 508 509 /* 510 * Device 26, Offset 224e0: IMC 0 channel 0 -> rank 0 511 * Device 26, Offset 264e0: IMC 0 channel 1 -> rank 1 512 * Device 27, Offset 224e0: IMC 1 channel 0 -> rank 2 513 * Device 27, Offset 264e0: IMC 1 channel 1 -> rank 3 514 * Device 28, Offset 224e0: IMC 2 channel 0 -> rank 4 515 * Device 28, Offset 264e0: IMC 2 channel 1 -> rank 5 516 * Device 29, Offset 224e0: IMC 3 channel 0 -> rank 6 517 * Device 29, Offset 264e0: IMC 3 channel 1 -> rank 7 518 */ 519 dev = 26 + chan_rank / 2; 520 offset = 0x224e0 + dimm_order * 4 + (chan_rank % 2) * 0x4000; 521 522 ret = peci_mmio_read(priv->peci_dev, 0, GET_CPU_SEG(reg_val), GET_CPU_BUS(reg_val), 523 dev, 0, offset, data); 524 if (ret) 525 return ret; 526 527 return 0; 528 } 529 530 static int 531 read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data) 532 { 533 u32 reg_val; 534 u64 offset; 535 int ret; 536 u8 dev; 537 538 ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd4, ®_val); 539 if (ret || !(reg_val & BIT(31))) 540 return -ENODATA; 541 542 ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd0, ®_val); 543 if (ret) 544 return -ENODATA; 545 546 /* 547 * Device 26, Offset 219a8: IMC 0 channel 0 -> rank 0 548 * Device 26, Offset 299a8: IMC 0 channel 1 -> rank 1 549 * Device 27, Offset 219a8: IMC 1 channel 0 -> rank 2 550 * Device 27, Offset 299a8: IMC 1 channel 1 -> rank 3 551 * Device 28, Offset 219a8: IMC 2 channel 0 -> rank 4 552 * Device 28, Offset 299a8: IMC 2 channel 1 -> rank 5 553 * Device 29, Offset 219a8: IMC 3 channel 0 -> rank 6 554 * Device 29, Offset 299a8: IMC 3 channel 1 -> rank 7 555 */ 556 dev = 26 + chan_rank / 2; 557 offset = 0x219a8 + dimm_order * 4 + (chan_rank % 2) * 0x8000; 558 559 ret = peci_mmio_read(priv->peci_dev, 0, GET_CPU_SEG(reg_val), GET_CPU_BUS(reg_val), 560 dev, 0, offset, data); 561 if (ret) 562 return ret; 563 564 return 0; 565 } 566 567 static int read_thresholds_emr(struct peci_dimmtemp *priv, int dimm_order, 568 int chan_rank, u32 *data) 569 { 570 return read_thresholds_spr(priv, dimm_order, chan_rank, data); 571 } 572 573 static const struct dimm_info dimm_hsx = { 574 .chan_rank_max = CHAN_RANK_MAX_ON_HSX, 575 .dimm_idx_max = DIMM_IDX_MAX_ON_HSX, 576 .min_peci_revision = 0x33, 577 .read_thresholds = &read_thresholds_hsx, 578 }; 579 580 static const struct dimm_info dimm_bdx = { 581 .chan_rank_max = CHAN_RANK_MAX_ON_BDX, 582 .dimm_idx_max = DIMM_IDX_MAX_ON_BDX, 583 .min_peci_revision = 0x33, 584 .read_thresholds = &read_thresholds_hsx, 585 }; 586 587 static const struct dimm_info dimm_bdxd = { 588 .chan_rank_max = CHAN_RANK_MAX_ON_BDXD, 589 .dimm_idx_max = DIMM_IDX_MAX_ON_BDXD, 590 .min_peci_revision = 0x33, 591 .read_thresholds = &read_thresholds_bdxd, 592 }; 593 594 static const struct dimm_info dimm_skx = { 595 .chan_rank_max = CHAN_RANK_MAX_ON_SKX, 596 .dimm_idx_max = DIMM_IDX_MAX_ON_SKX, 597 .min_peci_revision = 0x33, 598 .read_thresholds = &read_thresholds_skx, 599 }; 600 601 static const struct dimm_info dimm_icx = { 602 .chan_rank_max = CHAN_RANK_MAX_ON_ICX, 603 .dimm_idx_max = DIMM_IDX_MAX_ON_ICX, 604 .min_peci_revision = 0x40, 605 .read_thresholds = &read_thresholds_icx, 606 }; 607 608 static const struct dimm_info dimm_icxd = { 609 .chan_rank_max = CHAN_RANK_MAX_ON_ICXD, 610 .dimm_idx_max = DIMM_IDX_MAX_ON_ICXD, 611 .min_peci_revision = 0x40, 612 .read_thresholds = &read_thresholds_icx, 613 }; 614 615 static const struct dimm_info dimm_spr = { 616 .chan_rank_max = CHAN_RANK_MAX_ON_SPR, 617 .dimm_idx_max = DIMM_IDX_MAX_ON_SPR, 618 .min_peci_revision = 0x40, 619 .read_thresholds = &read_thresholds_spr, 620 }; 621 622 static const struct dimm_info dimm_emr = { 623 .chan_rank_max = CHAN_RANK_MAX_ON_EMR, 624 .dimm_idx_max = DIMM_IDX_MAX_ON_EMR, 625 .min_peci_revision = 0x40, 626 .read_thresholds = &read_thresholds_emr, 627 }; 628 629 static const struct auxiliary_device_id peci_dimmtemp_ids[] = { 630 { 631 .name = "peci_cpu.dimmtemp.hsx", 632 .driver_data = (kernel_ulong_t)&dimm_hsx, 633 }, 634 { 635 .name = "peci_cpu.dimmtemp.bdx", 636 .driver_data = (kernel_ulong_t)&dimm_bdx, 637 }, 638 { 639 .name = "peci_cpu.dimmtemp.bdxd", 640 .driver_data = (kernel_ulong_t)&dimm_bdxd, 641 }, 642 { 643 .name = "peci_cpu.dimmtemp.skx", 644 .driver_data = (kernel_ulong_t)&dimm_skx, 645 }, 646 { 647 .name = "peci_cpu.dimmtemp.icx", 648 .driver_data = (kernel_ulong_t)&dimm_icx, 649 }, 650 { 651 .name = "peci_cpu.dimmtemp.icxd", 652 .driver_data = (kernel_ulong_t)&dimm_icxd, 653 }, 654 { 655 .name = "peci_cpu.dimmtemp.spr", 656 .driver_data = (kernel_ulong_t)&dimm_spr, 657 }, 658 { 659 .name = "peci_cpu.dimmtemp.emr", 660 .driver_data = (kernel_ulong_t)&dimm_emr, 661 }, 662 { } 663 }; 664 MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids); 665 666 static struct auxiliary_driver peci_dimmtemp_driver = { 667 .probe = peci_dimmtemp_probe, 668 .id_table = peci_dimmtemp_ids, 669 }; 670 671 module_auxiliary_driver(peci_dimmtemp_driver); 672 673 MODULE_AUTHOR("Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>"); 674 MODULE_AUTHOR("Iwona Winiarska <iwona.winiarska@intel.com>"); 675 MODULE_DESCRIPTION("PECI dimmtemp driver"); 676 MODULE_LICENSE("GPL"); 677 MODULE_IMPORT_NS("PECI_CPU"); 678