xref: /linux/drivers/ata/pata_pdc2027x.c (revision 1ac731c529cd4d6adbce134754b51ff7d822b145)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
4  *
5  *  Ported to libata by:
6  *  Albert Lee <albertcc@tw.ibm.com> IBM Corporation
7  *
8  *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
9  *  Portions Copyright (C) 1999 Promise Technology, Inc.
10  *
11  *  Author: Frank Tiernan (frankt@promise.com)
12  *  Released under terms of General Public License
13  *
14  *  libata documentation is available via 'make {ps|pdf}docs',
15  *  as Documentation/driver-api/libata.rst
16  *
17  *  Hardware information only available under NDA.
18  */
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/ktime.h>
26 #include <scsi/scsi.h>
27 #include <scsi/scsi_host.h>
28 #include <scsi/scsi_cmnd.h>
29 #include <linux/libata.h>
30 
31 #define DRV_NAME	"pata_pdc2027x"
32 #define DRV_VERSION	"1.0"
33 
34 enum {
35 	PDC_MMIO_BAR		= 5,
36 
37 	PDC_UDMA_100		= 0,
38 	PDC_UDMA_133		= 1,
39 
40 	PDC_100_MHZ		= 100000000,
41 	PDC_133_MHZ		= 133333333,
42 
43 	PDC_SYS_CTL		= 0x1100,
44 	PDC_ATA_CTL		= 0x1104,
45 	PDC_GLOBAL_CTL		= 0x1108,
46 	PDC_CTCR0		= 0x110C,
47 	PDC_CTCR1		= 0x1110,
48 	PDC_BYTE_COUNT		= 0x1120,
49 	PDC_PLL_CTL		= 0x1202,
50 };
51 
52 static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
53 #ifdef CONFIG_PM_SLEEP
54 static int pdc2027x_reinit_one(struct pci_dev *pdev);
55 #endif
56 static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline);
57 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
58 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
59 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
60 static unsigned int pdc2027x_mode_filter(struct ata_device *adev, unsigned int mask);
61 static int pdc2027x_cable_detect(struct ata_port *ap);
62 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed);
63 
64 /*
65  * ATA Timing Tables based on 133MHz controller clock.
66  * These tables are only used when the controller is in 133MHz clock.
67  * If the controller is in 100MHz clock, the ASIC hardware will
68  * set the timing registers automatically when "set feature" command
69  * is issued to the device. However, if the controller clock is 133MHz,
70  * the following tables must be used.
71  */
72 static const struct pdc2027x_pio_timing {
73 	u8 value0, value1, value2;
74 } pdc2027x_pio_timing_tbl[] = {
75 	{ 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
76 	{ 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
77 	{ 0x23, 0x26, 0x64 }, /* PIO mode 2 */
78 	{ 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
79 	{ 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
80 };
81 
82 static const struct pdc2027x_mdma_timing {
83 	u8 value0, value1;
84 } pdc2027x_mdma_timing_tbl[] = {
85 	{ 0xdf, 0x5f }, /* MDMA mode 0 */
86 	{ 0x6b, 0x27 }, /* MDMA mode 1 */
87 	{ 0x69, 0x25 }, /* MDMA mode 2 */
88 };
89 
90 static const struct pdc2027x_udma_timing {
91 	u8 value0, value1, value2;
92 } pdc2027x_udma_timing_tbl[] = {
93 	{ 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
94 	{ 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
95 	{ 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
96 	{ 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
97 	{ 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
98 	{ 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
99 	{ 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
100 };
101 
102 static const struct pci_device_id pdc2027x_pci_tbl[] = {
103 	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
104 	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
105 	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
106 	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
107 	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
108 	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
109 	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
110 
111 	{ }	/* terminate list */
112 };
113 
114 static struct pci_driver pdc2027x_pci_driver = {
115 	.name			= DRV_NAME,
116 	.id_table		= pdc2027x_pci_tbl,
117 	.probe			= pdc2027x_init_one,
118 	.remove			= ata_pci_remove_one,
119 #ifdef CONFIG_PM_SLEEP
120 	.suspend		= ata_pci_device_suspend,
121 	.resume			= pdc2027x_reinit_one,
122 #endif
123 };
124 
125 static const struct scsi_host_template pdc2027x_sht = {
126 	ATA_BMDMA_SHT(DRV_NAME),
127 };
128 
129 static struct ata_port_operations pdc2027x_pata100_ops = {
130 	.inherits		= &ata_bmdma_port_ops,
131 	.check_atapi_dma	= pdc2027x_check_atapi_dma,
132 	.cable_detect		= pdc2027x_cable_detect,
133 	.prereset		= pdc2027x_prereset,
134 };
135 
136 static struct ata_port_operations pdc2027x_pata133_ops = {
137 	.inherits		= &pdc2027x_pata100_ops,
138 	.mode_filter		= pdc2027x_mode_filter,
139 	.set_piomode		= pdc2027x_set_piomode,
140 	.set_dmamode		= pdc2027x_set_dmamode,
141 	.set_mode		= pdc2027x_set_mode,
142 };
143 
144 static struct ata_port_info pdc2027x_port_info[] = {
145 	/* PDC_UDMA_100 */
146 	{
147 		.flags		= ATA_FLAG_SLAVE_POSS,
148 		.pio_mask	= ATA_PIO4,
149 		.mwdma_mask	= ATA_MWDMA2,
150 		.udma_mask	= ATA_UDMA5,
151 		.port_ops	= &pdc2027x_pata100_ops,
152 	},
153 	/* PDC_UDMA_133 */
154 	{
155 		.flags		= ATA_FLAG_SLAVE_POSS,
156 		.pio_mask	= ATA_PIO4,
157 		.mwdma_mask	= ATA_MWDMA2,
158 		.udma_mask	= ATA_UDMA6,
159 		.port_ops	= &pdc2027x_pata133_ops,
160 	},
161 };
162 
163 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
164 MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
165 MODULE_LICENSE("GPL");
166 MODULE_VERSION(DRV_VERSION);
167 MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
168 
169 /**
170  *	port_mmio - Get the MMIO address of PDC2027x extended registers
171  *	@ap: Port
172  *	@offset: offset from mmio base
173  */
port_mmio(struct ata_port * ap,unsigned int offset)174 static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
175 {
176 	return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;
177 }
178 
179 /**
180  *	dev_mmio - Get the MMIO address of PDC2027x extended registers
181  *	@ap: Port
182  *	@adev: device
183  *	@offset: offset from mmio base
184  */
dev_mmio(struct ata_port * ap,struct ata_device * adev,unsigned int offset)185 static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
186 {
187 	u8 adj = (adev->devno) ? 0x08 : 0x00;
188 	return port_mmio(ap, offset) + adj;
189 }
190 
191 /**
192  *	pdc2027x_cable_detect - Probe host controller cable detect info
193  *	@ap: Port for which cable detect info is desired
194  *
195  *	Read 80c cable indicator from Promise extended register.
196  *      This register is latched when the system is reset.
197  *
198  *	LOCKING:
199  *	None (inherited from caller).
200  */
pdc2027x_cable_detect(struct ata_port * ap)201 static int pdc2027x_cable_detect(struct ata_port *ap)
202 {
203 	u32 cgcr;
204 
205 	/* check cable detect results */
206 	cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL));
207 	if (cgcr & (1 << 26))
208 		goto cbl40;
209 
210 	ata_port_dbg(ap, "No cable or 80-conductor cable\n");
211 
212 	return ATA_CBL_PATA80;
213 cbl40:
214 	ata_port_info(ap, DRV_NAME ":40-conductor cable detected\n");
215 	return ATA_CBL_PATA40;
216 }
217 
218 /**
219  * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
220  * @ap: Port to check
221  */
pdc2027x_port_enabled(struct ata_port * ap)222 static inline int pdc2027x_port_enabled(struct ata_port *ap)
223 {
224 	return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
225 }
226 
227 /**
228  *	pdc2027x_prereset - prereset for PATA host controller
229  *	@link: Target link
230  *	@deadline: deadline jiffies for the operation
231  *
232  *	Probeinit including cable detection.
233  *
234  *	LOCKING:
235  *	None (inherited from caller).
236  */
237 
pdc2027x_prereset(struct ata_link * link,unsigned long deadline)238 static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline)
239 {
240 	/* Check whether port enabled */
241 	if (!pdc2027x_port_enabled(link->ap))
242 		return -ENOENT;
243 	return ata_sff_prereset(link, deadline);
244 }
245 
246 /**
247  *	pdc2027x_mode_filter	-	mode selection filter
248  *	@adev: ATA device
249  *	@mask: list of modes proposed
250  *
251  *	Block UDMA on devices that cause trouble with this controller.
252  */
253 
pdc2027x_mode_filter(struct ata_device * adev,unsigned int mask)254 static unsigned int pdc2027x_mode_filter(struct ata_device *adev, unsigned int mask)
255 {
256 	unsigned char model_num[ATA_ID_PROD_LEN + 1];
257 	struct ata_device *pair = ata_dev_pair(adev);
258 
259 	if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
260 		return mask;
261 
262 	/* Check for slave of a Maxtor at UDMA6 */
263 	ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
264 			  ATA_ID_PROD_LEN + 1);
265 	/* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
266 	if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6)
267 		mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
268 
269 	return mask;
270 }
271 
272 /**
273  *	pdc2027x_set_piomode - Initialize host controller PATA PIO timings
274  *	@ap: Port to configure
275  *	@adev: um
276  *
277  *	Set PIO mode for device.
278  *
279  *	LOCKING:
280  *	None (inherited from caller).
281  */
282 
pdc2027x_set_piomode(struct ata_port * ap,struct ata_device * adev)283 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
284 {
285 	unsigned int pio = adev->pio_mode - XFER_PIO_0;
286 	u32 ctcr0, ctcr1;
287 
288 	ata_port_dbg(ap, "adev->pio_mode[%X]\n", adev->pio_mode);
289 
290 	/* Sanity check */
291 	if (pio > 4) {
292 		ata_port_err(ap, "Unknown pio mode [%d] ignored\n", pio);
293 		return;
294 
295 	}
296 
297 	/* Set the PIO timing registers using value table for 133MHz */
298 	ata_port_dbg(ap, "Set pio regs... \n");
299 
300 	ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
301 	ctcr0 &= 0xffff0000;
302 	ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
303 		(pdc2027x_pio_timing_tbl[pio].value1 << 8);
304 	iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
305 
306 	ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
307 	ctcr1 &= 0x00ffffff;
308 	ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
309 	iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
310 
311 	ata_port_dbg(ap, "Set to pio mode[%u] \n", pio);
312 }
313 
314 /**
315  *	pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
316  *	@ap: Port to configure
317  *	@adev: um
318  *
319  *	Set UDMA mode for device.
320  *
321  *	LOCKING:
322  *	None (inherited from caller).
323  */
pdc2027x_set_dmamode(struct ata_port * ap,struct ata_device * adev)324 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
325 {
326 	unsigned int dma_mode = adev->dma_mode;
327 	u32 ctcr0, ctcr1;
328 
329 	if ((dma_mode >= XFER_UDMA_0) &&
330 	   (dma_mode <= XFER_UDMA_6)) {
331 		/* Set the UDMA timing registers with value table for 133MHz */
332 		unsigned int udma_mode = dma_mode & 0x07;
333 
334 		if (dma_mode == XFER_UDMA_2) {
335 			/*
336 			 * Turn off tHOLD.
337 			 * If tHOLD is '1', the hardware will add half clock for data hold time.
338 			 * This code segment seems to be no effect. tHOLD will be overwritten below.
339 			 */
340 			ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
341 			iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
342 		}
343 
344 		ata_port_dbg(ap, "Set udma regs... \n");
345 
346 		ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
347 		ctcr1 &= 0xff000000;
348 		ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
349 			(pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
350 			(pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
351 		iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
352 
353 		ata_port_dbg(ap, "Set to udma mode[%u] \n", udma_mode);
354 
355 	} else  if ((dma_mode >= XFER_MW_DMA_0) &&
356 		   (dma_mode <= XFER_MW_DMA_2)) {
357 		/* Set the MDMA timing registers with value table for 133MHz */
358 		unsigned int mdma_mode = dma_mode & 0x07;
359 
360 		ata_port_dbg(ap, "Set mdma regs... \n");
361 		ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
362 
363 		ctcr0 &= 0x0000ffff;
364 		ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
365 			(pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
366 
367 		iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
368 
369 		ata_port_dbg(ap, "Set to mdma mode[%u] \n", mdma_mode);
370 	} else {
371 		ata_port_err(ap, "Unknown dma mode [%u] ignored\n", dma_mode);
372 	}
373 }
374 
375 /**
376  *	pdc2027x_set_mode - Set the timing registers back to correct values.
377  *	@link: link to configure
378  *	@r_failed: Returned device for failure
379  *
380  *	The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
381  *	automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
382  *	This function overwrites the possibly incorrect values set by the hardware to be correct.
383  */
pdc2027x_set_mode(struct ata_link * link,struct ata_device ** r_failed)384 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed)
385 {
386 	struct ata_port *ap = link->ap;
387 	struct ata_device *dev;
388 	int rc;
389 
390 	rc = ata_do_set_mode(link, r_failed);
391 	if (rc < 0)
392 		return rc;
393 
394 	ata_for_each_dev(dev, link, ENABLED) {
395 		pdc2027x_set_piomode(ap, dev);
396 
397 		/*
398 		 * Enable prefetch if the device support PIO only.
399 		 */
400 		if (dev->xfer_shift == ATA_SHIFT_PIO) {
401 			u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1));
402 			ctcr1 |= (1 << 25);
403 			iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
404 
405 			ata_dev_dbg(dev, "Turn on prefetch\n");
406 		} else {
407 			pdc2027x_set_dmamode(ap, dev);
408 		}
409 	}
410 	return 0;
411 }
412 
413 /**
414  *	pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
415  *	@qc: Metadata associated with taskfile to check
416  *
417  *	LOCKING:
418  *	None (inherited from caller).
419  *
420  *	RETURNS: 0 when ATAPI DMA can be used
421  *		 1 otherwise
422  */
pdc2027x_check_atapi_dma(struct ata_queued_cmd * qc)423 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
424 {
425 	struct scsi_cmnd *cmd = qc->scsicmd;
426 	u8 *scsicmd = cmd->cmnd;
427 	int rc = 1; /* atapi dma off by default */
428 
429 	/*
430 	 * This workaround is from Promise's GPL driver.
431 	 * If ATAPI DMA is used for commands not in the
432 	 * following white list, say MODE_SENSE and REQUEST_SENSE,
433 	 * pdc2027x might hit the irq lost problem.
434 	 */
435 	switch (scsicmd[0]) {
436 	case READ_10:
437 	case WRITE_10:
438 	case READ_12:
439 	case WRITE_12:
440 	case READ_6:
441 	case WRITE_6:
442 	case 0xad: /* READ_DVD_STRUCTURE */
443 	case 0xbe: /* READ_CD */
444 		/* ATAPI DMA is ok */
445 		rc = 0;
446 		break;
447 	default:
448 		;
449 	}
450 
451 	return rc;
452 }
453 
454 /**
455  * pdc_read_counter - Read the ctr counter
456  * @host: target ATA host
457  */
458 
pdc_read_counter(struct ata_host * host)459 static long pdc_read_counter(struct ata_host *host)
460 {
461 	void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
462 	long counter;
463 	int retry = 1;
464 	u32 bccrl, bccrh, bccrlv, bccrhv;
465 
466 retry:
467 	bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
468 	bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
469 
470 	/* Read the counter values again for verification */
471 	bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
472 	bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
473 
474 	counter = (bccrh << 15) | bccrl;
475 
476 	dev_dbg(host->dev, "bccrh [%X] bccrl [%X]\n", bccrh,  bccrl);
477 	dev_dbg(host->dev, "bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
478 
479 	/*
480 	 * The 30-bit decreasing counter are read by 2 pieces.
481 	 * Incorrect value may be read when both bccrh and bccrl are changing.
482 	 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
483 	 */
484 	if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
485 		retry--;
486 		dev_dbg(host->dev, "rereading counter\n");
487 		goto retry;
488 	}
489 
490 	return counter;
491 }
492 
493 /**
494  * pdc_adjust_pll - Adjust the PLL input clock in Hz.
495  *
496  * @host: target ATA host
497  * @pll_clock: The input of PLL in HZ
498  * @board_idx: board identifier
499  */
pdc_adjust_pll(struct ata_host * host,long pll_clock,unsigned int board_idx)500 static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx)
501 {
502 	void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
503 	u16 pll_ctl;
504 	long pll_clock_khz = pll_clock / 1000;
505 	long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
506 	long ratio = pout_required / pll_clock_khz;
507 	int F, R;
508 
509 	/* Sanity check */
510 	if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
511 		dev_err(host->dev, "Invalid PLL input clock %ldkHz, give up!\n",
512 			pll_clock_khz);
513 		return;
514 	}
515 
516 	dev_dbg(host->dev, "pout_required is %ld\n", pout_required);
517 
518 	/* Show the current clock value of PLL control register
519 	 * (maybe already configured by the firmware)
520 	 */
521 	pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
522 
523 	dev_dbg(host->dev, "pll_ctl[%X]\n", pll_ctl);
524 
525 	/*
526 	 * Calculate the ratio of F, R and OD
527 	 * POUT = (F + 2) / (( R + 2) * NO)
528 	 */
529 	if (ratio < 8600L) { /* 8.6x */
530 		/* Using NO = 0x01, R = 0x0D */
531 		R = 0x0d;
532 	} else if (ratio < 12900L) { /* 12.9x */
533 		/* Using NO = 0x01, R = 0x08 */
534 		R = 0x08;
535 	} else if (ratio < 16100L) { /* 16.1x */
536 		/* Using NO = 0x01, R = 0x06 */
537 		R = 0x06;
538 	} else if (ratio < 64000L) { /* 64x */
539 		R = 0x00;
540 	} else {
541 		/* Invalid ratio */
542 		dev_err(host->dev, "Invalid ratio %ld, give up!\n", ratio);
543 		return;
544 	}
545 
546 	F = (ratio * (R+2)) / 1000 - 2;
547 
548 	if (unlikely(F < 0 || F > 127)) {
549 		/* Invalid F */
550 		dev_err(host->dev, "F[%d] invalid!\n", F);
551 		return;
552 	}
553 
554 	dev_dbg(host->dev, "F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
555 
556 	pll_ctl = (R << 8) | F;
557 
558 	dev_dbg(host->dev, "Writing pll_ctl[%X]\n", pll_ctl);
559 
560 	iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);
561 	ioread16(mmio_base + PDC_PLL_CTL); /* flush */
562 
563 	/* Wait the PLL circuit to be stable */
564 	msleep(30);
565 
566 	/*
567 	 *  Show the current clock value of PLL control register
568 	 * (maybe configured by the firmware)
569 	 */
570 	pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
571 
572 	dev_dbg(host->dev, "pll_ctl[%X]\n", pll_ctl);
573 
574 	return;
575 }
576 
577 /**
578  * pdc_detect_pll_input_clock - Detect the PLL input clock in Hz.
579  * @host: target ATA host
580  * Ex. 16949000 on 33MHz PCI bus for pdc20275.
581  *     Half of the PCI clock.
582  */
pdc_detect_pll_input_clock(struct ata_host * host)583 static long pdc_detect_pll_input_clock(struct ata_host *host)
584 {
585 	void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
586 	u32 scr;
587 	long start_count, end_count;
588 	ktime_t start_time, end_time;
589 	long pll_clock, usec_elapsed;
590 
591 	/* Start the test mode */
592 	scr = ioread32(mmio_base + PDC_SYS_CTL);
593 	dev_dbg(host->dev, "scr[%X]\n", scr);
594 	iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
595 	ioread32(mmio_base + PDC_SYS_CTL); /* flush */
596 
597 	/* Read current counter value */
598 	start_count = pdc_read_counter(host);
599 	start_time = ktime_get();
600 
601 	/* Let the counter run for 100 ms. */
602 	msleep(100);
603 
604 	/* Read the counter values again */
605 	end_count = pdc_read_counter(host);
606 	end_time = ktime_get();
607 
608 	/* Stop the test mode */
609 	scr = ioread32(mmio_base + PDC_SYS_CTL);
610 	dev_dbg(host->dev, "scr[%X]\n", scr);
611 	iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
612 	ioread32(mmio_base + PDC_SYS_CTL); /* flush */
613 
614 	/* calculate the input clock in Hz */
615 	usec_elapsed = (long) ktime_us_delta(end_time, start_time);
616 
617 	pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *
618 		(100000000 / usec_elapsed);
619 
620 	dev_dbg(host->dev, "start[%ld] end[%ld] PLL input clock[%ld]HZ\n",
621 		     start_count, end_count, pll_clock);
622 
623 	return pll_clock;
624 }
625 
626 /**
627  * pdc_hardware_init - Initialize the hardware.
628  * @host: target ATA host
629  * @board_idx: board identifier
630  */
pdc_hardware_init(struct ata_host * host,unsigned int board_idx)631 static void pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
632 {
633 	long pll_clock;
634 
635 	/*
636 	 * Detect PLL input clock rate.
637 	 * On some system, where PCI bus is running at non-standard clock rate.
638 	 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
639 	 * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
640 	 */
641 	pll_clock = pdc_detect_pll_input_clock(host);
642 
643 	dev_info(host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
644 
645 	/* Adjust PLL control register */
646 	pdc_adjust_pll(host, pll_clock, board_idx);
647 }
648 
649 /**
650  * pdc_ata_setup_port - setup the mmio address
651  * @port: ata ioports to setup
652  * @base: base address
653  */
pdc_ata_setup_port(struct ata_ioports * port,void __iomem * base)654 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
655 {
656 	port->cmd_addr		=
657 	port->data_addr		= base;
658 	port->feature_addr	=
659 	port->error_addr	= base + 0x05;
660 	port->nsect_addr	= base + 0x0a;
661 	port->lbal_addr		= base + 0x0f;
662 	port->lbam_addr		= base + 0x10;
663 	port->lbah_addr		= base + 0x15;
664 	port->device_addr	= base + 0x1a;
665 	port->command_addr	=
666 	port->status_addr	= base + 0x1f;
667 	port->altstatus_addr	=
668 	port->ctl_addr		= base + 0x81a;
669 }
670 
671 /**
672  * pdc2027x_init_one - PCI probe function
673  * Called when an instance of PCI adapter is inserted.
674  * This function checks whether the hardware is supported,
675  * initialize hardware and register an instance of ata_host to
676  * libata.  (implements struct pci_driver.probe() )
677  *
678  * @pdev: instance of pci_dev found
679  * @ent:  matching entry in the id_tbl[]
680  */
pdc2027x_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)681 static int pdc2027x_init_one(struct pci_dev *pdev,
682 			     const struct pci_device_id *ent)
683 {
684 	static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 };
685 	static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 };
686 	unsigned int board_idx = (unsigned int) ent->driver_data;
687 	const struct ata_port_info *ppi[] =
688 		{ &pdc2027x_port_info[board_idx], NULL };
689 	struct ata_host *host;
690 	void __iomem *mmio_base;
691 	int i, rc;
692 
693 	ata_print_version_once(&pdev->dev, DRV_VERSION);
694 
695 	/* alloc host */
696 	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
697 	if (!host)
698 		return -ENOMEM;
699 
700 	/* acquire resources and fill host */
701 	rc = pcim_enable_device(pdev);
702 	if (rc)
703 		return rc;
704 
705 	rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
706 	if (rc)
707 		return rc;
708 	host->iomap = pcim_iomap_table(pdev);
709 
710 	rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
711 	if (rc)
712 		return rc;
713 
714 	mmio_base = host->iomap[PDC_MMIO_BAR];
715 
716 	for (i = 0; i < 2; i++) {
717 		struct ata_port *ap = host->ports[i];
718 
719 		pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]);
720 		ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i];
721 
722 		ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
723 		ata_port_pbar_desc(ap, PDC_MMIO_BAR, cmd_offset[i], "cmd");
724 	}
725 
726 	//pci_enable_intx(pdev);
727 
728 	/* initialize adapter */
729 	pdc_hardware_init(host, board_idx);
730 
731 	pci_set_master(pdev);
732 	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
733 				 IRQF_SHARED, &pdc2027x_sht);
734 }
735 
736 #ifdef CONFIG_PM_SLEEP
pdc2027x_reinit_one(struct pci_dev * pdev)737 static int pdc2027x_reinit_one(struct pci_dev *pdev)
738 {
739 	struct ata_host *host = pci_get_drvdata(pdev);
740 	unsigned int board_idx;
741 	int rc;
742 
743 	rc = ata_pci_device_do_resume(pdev);
744 	if (rc)
745 		return rc;
746 
747 	if (pdev->device == PCI_DEVICE_ID_PROMISE_20268 ||
748 	    pdev->device == PCI_DEVICE_ID_PROMISE_20270)
749 		board_idx = PDC_UDMA_100;
750 	else
751 		board_idx = PDC_UDMA_133;
752 
753 	pdc_hardware_init(host, board_idx);
754 
755 	ata_host_resume(host);
756 	return 0;
757 }
758 #endif
759 
760 module_pci_driver(pdc2027x_pci_driver);
761