1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for the Microchip PD692X0 PoE PSE Controller driver (I2C bus)
4 *
5 * Copyright (c) 2023 Bootlin, Kory Maincent <kory.maincent@bootlin.com>
6 */
7
8 #include <linux/delay.h>
9 #include <linux/firmware.h>
10 #include <linux/i2c.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14 #include <linux/pse-pd/pse.h>
15 #include <linux/regulator/driver.h>
16 #include <linux/regulator/machine.h>
17
18 #define PD692X0_PSE_NAME "pd692x0_pse"
19
20 #define PD692X0_MAX_PIS 48
21 #define PD692X0_MAX_MANAGERS 12
22 #define PD692X0_MAX_MANAGER_PORTS 8
23 #define PD692X0_MAX_HW_PORTS (PD692X0_MAX_MANAGERS * PD692X0_MAX_MANAGER_PORTS)
24
25 #define PD69200_BT_PROD_VER 24
26 #define PD69210_BT_PROD_VER 26
27 #define PD69220_BT_PROD_VER 29
28
29 #define PD692X0_FW_MAJ_VER 3
30 #define PD692X0_FW_MIN_VER 5
31 #define PD692X0_FW_PATCH_VER 5
32
33 enum pd692x0_fw_state {
34 PD692X0_FW_UNKNOWN,
35 PD692X0_FW_OK,
36 PD692X0_FW_BROKEN,
37 PD692X0_FW_NEED_UPDATE,
38 PD692X0_FW_PREPARE,
39 PD692X0_FW_WRITE,
40 PD692X0_FW_COMPLETE,
41 };
42
43 struct pd692x0_msg {
44 u8 key;
45 u8 echo;
46 u8 sub[3];
47 u8 data[8];
48 __be16 chksum;
49 } __packed;
50
51 struct pd692x0_msg_ver {
52 u8 prod;
53 u8 maj_sw_ver;
54 u8 min_sw_ver;
55 u8 pa_sw_ver;
56 u8 param;
57 u8 build;
58 };
59
60 enum {
61 PD692X0_KEY_CMD,
62 PD692X0_KEY_PRG,
63 PD692X0_KEY_REQ,
64 PD692X0_KEY_TLM,
65 PD692X0_KEY_TEST,
66 PD692X0_KEY_REPORT = 0x52
67 };
68
69 enum {
70 PD692X0_MSG_RESET,
71 PD692X0_MSG_GET_SYS_STATUS,
72 PD692X0_MSG_GET_SW_VER,
73 PD692X0_MSG_SET_TMP_PORT_MATRIX,
74 PD692X0_MSG_PRG_PORT_MATRIX,
75 PD692X0_MSG_SET_PORT_PARAM,
76 PD692X0_MSG_GET_PORT_STATUS,
77 PD692X0_MSG_DOWNLOAD_CMD,
78 PD692X0_MSG_GET_PORT_CLASS,
79 PD692X0_MSG_GET_PORT_MEAS,
80 PD692X0_MSG_GET_PORT_PARAM,
81 PD692X0_MSG_GET_POWER_BANK,
82 PD692X0_MSG_SET_POWER_BANK,
83
84 /* add new message above here */
85 PD692X0_MSG_CNT
86 };
87
88 struct pd692x0_priv {
89 struct i2c_client *client;
90 struct pse_controller_dev pcdev;
91 struct device_node *np;
92
93 enum pd692x0_fw_state fw_state;
94 struct fw_upload *fwl;
95 bool cancel_request;
96
97 u8 msg_id;
98 bool last_cmd_key;
99 unsigned long last_cmd_key_time;
100
101 enum ethtool_c33_pse_admin_state admin_state[PD692X0_MAX_PIS];
102 struct regulator_dev *manager_reg[PD692X0_MAX_MANAGERS];
103 int manager_pw_budget[PD692X0_MAX_MANAGERS];
104 };
105
106 /* Template list of communication messages. The non-null bytes defined here
107 * constitute the fixed portion of the messages. The remaining bytes will
108 * be configured later within the functions. Refer to the "PD692x0 BT Serial
109 * Communication Protocol User Guide" for comprehensive details on messages
110 * content.
111 */
112 static const struct pd692x0_msg pd692x0_msg_template_list[PD692X0_MSG_CNT] = {
113 [PD692X0_MSG_RESET] = {
114 .key = PD692X0_KEY_CMD,
115 .sub = {0x07, 0x55, 0x00},
116 .data = {0x55, 0x00, 0x55, 0x4e,
117 0x4e, 0x4e, 0x4e, 0x4e},
118 },
119 [PD692X0_MSG_GET_SYS_STATUS] = {
120 .key = PD692X0_KEY_REQ,
121 .sub = {0x07, 0xd0, 0x4e},
122 .data = {0x4e, 0x4e, 0x4e, 0x4e,
123 0x4e, 0x4e, 0x4e, 0x4e},
124 },
125 [PD692X0_MSG_GET_SW_VER] = {
126 .key = PD692X0_KEY_REQ,
127 .sub = {0x07, 0x1e, 0x21},
128 .data = {0x4e, 0x4e, 0x4e, 0x4e,
129 0x4e, 0x4e, 0x4e, 0x4e},
130 },
131 [PD692X0_MSG_SET_TMP_PORT_MATRIX] = {
132 .key = PD692X0_KEY_CMD,
133 .sub = {0x05, 0x43},
134 .data = { 0, 0x4e, 0x4e, 0x4e,
135 0x4e, 0x4e, 0x4e, 0x4e},
136 },
137 [PD692X0_MSG_PRG_PORT_MATRIX] = {
138 .key = PD692X0_KEY_CMD,
139 .sub = {0x07, 0x43, 0x4e},
140 .data = {0x4e, 0x4e, 0x4e, 0x4e,
141 0x4e, 0x4e, 0x4e, 0x4e},
142 },
143 [PD692X0_MSG_SET_PORT_PARAM] = {
144 .key = PD692X0_KEY_CMD,
145 .sub = {0x05, 0xc0},
146 .data = { 0xf, 0xff, 0xff, 0xff,
147 0x4e, 0x4e, 0x4e, 0x4e},
148 },
149 [PD692X0_MSG_GET_PORT_STATUS] = {
150 .key = PD692X0_KEY_REQ,
151 .sub = {0x05, 0xc1},
152 .data = {0x4e, 0x4e, 0x4e, 0x4e,
153 0x4e, 0x4e, 0x4e, 0x4e},
154 },
155 [PD692X0_MSG_DOWNLOAD_CMD] = {
156 .key = PD692X0_KEY_PRG,
157 .sub = {0xff, 0x99, 0x15},
158 .data = {0x16, 0x16, 0x99, 0x4e,
159 0x4e, 0x4e, 0x4e, 0x4e},
160 },
161 [PD692X0_MSG_GET_PORT_CLASS] = {
162 .key = PD692X0_KEY_REQ,
163 .sub = {0x05, 0xc4},
164 .data = {0x4e, 0x4e, 0x4e, 0x4e,
165 0x4e, 0x4e, 0x4e, 0x4e},
166 },
167 [PD692X0_MSG_GET_PORT_MEAS] = {
168 .key = PD692X0_KEY_REQ,
169 .sub = {0x05, 0xc5},
170 .data = {0x4e, 0x4e, 0x4e, 0x4e,
171 0x4e, 0x4e, 0x4e, 0x4e},
172 },
173 [PD692X0_MSG_GET_PORT_PARAM] = {
174 .key = PD692X0_KEY_REQ,
175 .sub = {0x05, 0xc0},
176 .data = {0x4e, 0x4e, 0x4e, 0x4e,
177 0x4e, 0x4e, 0x4e, 0x4e},
178 },
179 [PD692X0_MSG_GET_POWER_BANK] = {
180 .key = PD692X0_KEY_REQ,
181 .sub = {0x07, 0x0b, 0x57},
182 .data = { 0, 0x4e, 0x4e, 0x4e,
183 0x4e, 0x4e, 0x4e, 0x4e},
184 },
185 [PD692X0_MSG_SET_POWER_BANK] = {
186 .key = PD692X0_KEY_CMD,
187 .sub = {0x07, 0x0b, 0x57},
188 },
189 };
190
pd692x0_build_msg(struct pd692x0_msg * msg,u8 echo)191 static u8 pd692x0_build_msg(struct pd692x0_msg *msg, u8 echo)
192 {
193 u8 *data = (u8 *)msg;
194 u16 chksum = 0;
195 int i;
196
197 msg->echo = echo++;
198 if (echo == 0xff)
199 echo = 0;
200
201 for (i = 0; i < sizeof(*msg) - sizeof(msg->chksum); i++)
202 chksum += data[i];
203
204 msg->chksum = cpu_to_be16(chksum);
205
206 return echo;
207 }
208
pd692x0_send_msg(struct pd692x0_priv * priv,struct pd692x0_msg * msg)209 static int pd692x0_send_msg(struct pd692x0_priv *priv, struct pd692x0_msg *msg)
210 {
211 const struct i2c_client *client = priv->client;
212 int ret;
213
214 if (msg->key == PD692X0_KEY_CMD && priv->last_cmd_key) {
215 int cmd_msleep;
216
217 cmd_msleep = 30 - jiffies_to_msecs(jiffies - priv->last_cmd_key_time);
218 if (cmd_msleep > 0)
219 msleep(cmd_msleep);
220 }
221
222 /* Add echo and checksum bytes to the message */
223 priv->msg_id = pd692x0_build_msg(msg, priv->msg_id);
224
225 ret = i2c_master_send(client, (u8 *)msg, sizeof(*msg));
226 if (ret != sizeof(*msg))
227 return -EIO;
228
229 return 0;
230 }
231
pd692x0_reset(struct pd692x0_priv * priv)232 static int pd692x0_reset(struct pd692x0_priv *priv)
233 {
234 const struct i2c_client *client = priv->client;
235 struct pd692x0_msg msg, buf = {0};
236 int ret;
237
238 msg = pd692x0_msg_template_list[PD692X0_MSG_RESET];
239 ret = pd692x0_send_msg(priv, &msg);
240 if (ret) {
241 dev_err(&client->dev,
242 "Failed to reset the controller (%pe)\n", ERR_PTR(ret));
243 return ret;
244 }
245
246 msleep(30);
247
248 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf));
249 if (ret != sizeof(buf))
250 return ret < 0 ? ret : -EIO;
251
252 /* Is the reply a successful report message */
253 if (buf.key != PD692X0_KEY_REPORT || buf.sub[0] || buf.sub[1])
254 return -EIO;
255
256 msleep(300);
257
258 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf));
259 if (ret != sizeof(buf))
260 return ret < 0 ? ret : -EIO;
261
262 /* Is the boot status without error */
263 if (buf.key != 0x03 || buf.echo != 0xff || buf.sub[0] & 0x1) {
264 dev_err(&client->dev, "PSE controller error\n");
265 return -EIO;
266 }
267
268 return 0;
269 }
270
pd692x0_try_recv_msg(const struct i2c_client * client,struct pd692x0_msg * msg,struct pd692x0_msg * buf)271 static bool pd692x0_try_recv_msg(const struct i2c_client *client,
272 struct pd692x0_msg *msg,
273 struct pd692x0_msg *buf)
274 {
275 /* Wait 30ms before readback as mandated by the protocol */
276 msleep(30);
277
278 memset(buf, 0, sizeof(*buf));
279 i2c_master_recv(client, (u8 *)buf, sizeof(*buf));
280 if (buf->key)
281 return 0;
282
283 msleep(100);
284
285 memset(buf, 0, sizeof(*buf));
286 i2c_master_recv(client, (u8 *)buf, sizeof(*buf));
287 if (buf->key)
288 return 0;
289
290 return 1;
291 }
292
293 /* Implementation of I2C communication, specifically addressing scenarios
294 * involving communication loss. Refer to the "Synchronization During
295 * Communication Loss" section in the Communication Protocol document for
296 * further details.
297 */
pd692x0_recv_msg(struct pd692x0_priv * priv,struct pd692x0_msg * msg,struct pd692x0_msg * buf)298 static int pd692x0_recv_msg(struct pd692x0_priv *priv,
299 struct pd692x0_msg *msg,
300 struct pd692x0_msg *buf)
301 {
302 const struct i2c_client *client = priv->client;
303 int ret;
304
305 ret = pd692x0_try_recv_msg(client, msg, buf);
306 if (!ret)
307 goto out_success;
308
309 dev_warn(&client->dev,
310 "Communication lost, rtnl is locked until communication is back!");
311
312 ret = pd692x0_send_msg(priv, msg);
313 if (ret)
314 return ret;
315
316 ret = pd692x0_try_recv_msg(client, msg, buf);
317 if (!ret)
318 goto out_success2;
319
320 msleep(10000);
321
322 ret = pd692x0_send_msg(priv, msg);
323 if (ret)
324 return ret;
325
326 ret = pd692x0_try_recv_msg(client, msg, buf);
327 if (!ret)
328 goto out_success2;
329
330 return pd692x0_reset(priv);
331
332 out_success2:
333 dev_warn(&client->dev, "Communication is back, rtnl is unlocked!");
334 out_success:
335 if (msg->key == PD692X0_KEY_CMD) {
336 priv->last_cmd_key = true;
337 priv->last_cmd_key_time = jiffies;
338 } else {
339 priv->last_cmd_key = false;
340 }
341
342 return 0;
343 }
344
pd692x0_sendrecv_msg(struct pd692x0_priv * priv,struct pd692x0_msg * msg,struct pd692x0_msg * buf)345 static int pd692x0_sendrecv_msg(struct pd692x0_priv *priv,
346 struct pd692x0_msg *msg,
347 struct pd692x0_msg *buf)
348 {
349 struct device *dev = &priv->client->dev;
350 int ret;
351
352 ret = pd692x0_send_msg(priv, msg);
353 if (ret)
354 return ret;
355
356 ret = pd692x0_recv_msg(priv, msg, buf);
357 if (ret)
358 return ret;
359
360 if (msg->echo != buf->echo) {
361 dev_err(dev,
362 "Wrong match in message ID, expect %d received %d.\n",
363 msg->echo, buf->echo);
364 return -EIO;
365 }
366
367 /* If the reply is a report message is it successful */
368 if (buf->key == PD692X0_KEY_REPORT &&
369 (buf->sub[0] || buf->sub[1])) {
370 return -EIO;
371 }
372
373 return 0;
374 }
375
to_pd692x0_priv(struct pse_controller_dev * pcdev)376 static struct pd692x0_priv *to_pd692x0_priv(struct pse_controller_dev *pcdev)
377 {
378 return container_of(pcdev, struct pd692x0_priv, pcdev);
379 }
380
pd692x0_fw_unavailable(struct pd692x0_priv * priv)381 static int pd692x0_fw_unavailable(struct pd692x0_priv *priv)
382 {
383 switch (priv->fw_state) {
384 case PD692X0_FW_OK:
385 return 0;
386 case PD692X0_FW_PREPARE:
387 case PD692X0_FW_WRITE:
388 case PD692X0_FW_COMPLETE:
389 dev_err(&priv->client->dev, "Firmware update in progress!\n");
390 return -EBUSY;
391 case PD692X0_FW_BROKEN:
392 case PD692X0_FW_NEED_UPDATE:
393 default:
394 dev_err(&priv->client->dev,
395 "Firmware issue. Please update it!\n");
396 return -EOPNOTSUPP;
397 }
398 }
399
pd692x0_pi_enable(struct pse_controller_dev * pcdev,int id)400 static int pd692x0_pi_enable(struct pse_controller_dev *pcdev, int id)
401 {
402 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
403 struct pd692x0_msg msg, buf = {0};
404 int ret;
405
406 ret = pd692x0_fw_unavailable(priv);
407 if (ret)
408 return ret;
409
410 if (priv->admin_state[id] == ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED)
411 return 0;
412
413 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM];
414 msg.data[0] = 0x1;
415 msg.sub[2] = id;
416 ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
417 if (ret < 0)
418 return ret;
419
420 priv->admin_state[id] = ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED;
421
422 return 0;
423 }
424
pd692x0_pi_disable(struct pse_controller_dev * pcdev,int id)425 static int pd692x0_pi_disable(struct pse_controller_dev *pcdev, int id)
426 {
427 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
428 struct pd692x0_msg msg, buf = {0};
429 int ret;
430
431 ret = pd692x0_fw_unavailable(priv);
432 if (ret)
433 return ret;
434
435 if (priv->admin_state[id] == ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED)
436 return 0;
437
438 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM];
439 msg.data[0] = 0x0;
440 msg.sub[2] = id;
441 ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
442 if (ret < 0)
443 return ret;
444
445 priv->admin_state[id] = ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED;
446
447 return 0;
448 }
449
450 struct pd692x0_pse_ext_state_mapping {
451 u32 status_code;
452 enum ethtool_c33_pse_ext_state pse_ext_state;
453 u32 pse_ext_substate;
454 };
455
456 static const struct pd692x0_pse_ext_state_mapping
457 pd692x0_pse_ext_state_map[] = {
458 {0x06, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM,
459 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE},
460 {0x07, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM,
461 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE},
462 {0x08, ETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE,
463 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE},
464 {0x0C, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
465 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT},
466 {0x11, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
467 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT},
468 {0x12, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
469 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT},
470 {0x1B, ETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED,
471 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS},
472 {0x1C, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
473 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS},
474 {0x1E, ETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID,
475 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_DETECTED_UNDERLOAD},
476 {0x1F, ETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED,
477 ETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD},
478 {0x20, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE,
479 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED},
480 {0x21, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
481 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT},
482 {0x22, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
483 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE},
484 {0x24, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM,
485 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION},
486 {0x25, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
487 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS},
488 {0x34, ETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED,
489 ETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION},
490 {0x35, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
491 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP},
492 {0x36, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
493 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP},
494 {0x37, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
495 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS},
496 {0x3C, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE,
497 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET},
498 {0x3D, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE,
499 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT},
500 {0x41, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE,
501 ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT},
502 {0x43, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
503 ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS},
504 {0xA7, ETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED,
505 ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR},
506 {0xA8, ETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID,
507 ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_CONNECTION_OPEN},
508 { /* sentinel */ }
509 };
510
511 static int
pd692x0_pi_get_ext_state(struct pse_controller_dev * pcdev,int id,struct pse_ext_state_info * ext_state_info)512 pd692x0_pi_get_ext_state(struct pse_controller_dev *pcdev, int id,
513 struct pse_ext_state_info *ext_state_info)
514 {
515 struct ethtool_c33_pse_ext_state_info *c33_ext_state_info;
516 const struct pd692x0_pse_ext_state_mapping *ext_state_map;
517 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
518 struct pd692x0_msg msg, buf = {0};
519 int ret;
520
521 ret = pd692x0_fw_unavailable(priv);
522 if (ret)
523 return ret;
524
525 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS];
526 msg.sub[2] = id;
527 ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
528 if (ret < 0)
529 return ret;
530
531 c33_ext_state_info = &ext_state_info->c33_ext_state_info;
532 ext_state_map = pd692x0_pse_ext_state_map;
533 while (ext_state_map->status_code) {
534 if (ext_state_map->status_code == buf.sub[0]) {
535 c33_ext_state_info->c33_pse_ext_state = ext_state_map->pse_ext_state;
536 c33_ext_state_info->__c33_pse_ext_substate = ext_state_map->pse_ext_substate;
537 return 0;
538 }
539 ext_state_map++;
540 }
541
542 return 0;
543 }
544
545 struct pd692x0_class_pw {
546 int class;
547 int class_cfg_value;
548 int class_pw;
549 int max_added_class_pw;
550 };
551
552 #define PD692X0_CLASS_PW_TABLE_SIZE 4
553 /* 4/2 pairs class configuration power table in compliance mode.
554 * Need to be arranged in ascending order of power support.
555 */
556 static const struct pd692x0_class_pw
557 pd692x0_class_pw_table[PD692X0_CLASS_PW_TABLE_SIZE] = {
558 {.class = 3, .class_cfg_value = 0x3, .class_pw = 15000, .max_added_class_pw = 3100},
559 {.class = 4, .class_cfg_value = 0x2, .class_pw = 30000, .max_added_class_pw = 8000},
560 {.class = 6, .class_cfg_value = 0x1, .class_pw = 60000, .max_added_class_pw = 5000},
561 {.class = 8, .class_cfg_value = 0x0, .class_pw = 90000, .max_added_class_pw = 7500},
562 };
563
pd692x0_pi_get_pw_from_table(int op_mode,int added_pw)564 static int pd692x0_pi_get_pw_from_table(int op_mode, int added_pw)
565 {
566 const struct pd692x0_class_pw *pw_table;
567 int i;
568
569 pw_table = pd692x0_class_pw_table;
570 for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) {
571 if (pw_table->class_cfg_value == op_mode)
572 return pw_table->class_pw + added_pw * 100;
573 }
574
575 return -ERANGE;
576 }
577
pd692x0_pi_set_pw_from_table(struct device * dev,struct pd692x0_msg * msg,int pw)578 static int pd692x0_pi_set_pw_from_table(struct device *dev,
579 struct pd692x0_msg *msg, int pw)
580 {
581 const struct pd692x0_class_pw *pw_table;
582 int i;
583
584 pw_table = pd692x0_class_pw_table;
585 if (pw < pw_table->class_pw) {
586 dev_err(dev,
587 "Power limit %dmW not supported. Ranges minimal available: [%d-%d]\n",
588 pw,
589 pw_table->class_pw,
590 pw_table->class_pw + pw_table->max_added_class_pw);
591 return -ERANGE;
592 }
593
594 for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) {
595 if (pw > (pw_table->class_pw + pw_table->max_added_class_pw))
596 continue;
597
598 if (pw < pw_table->class_pw) {
599 dev_err(dev,
600 "Power limit %dmW not supported. Ranges available: [%d-%d] or [%d-%d]\n",
601 pw,
602 (pw_table - 1)->class_pw,
603 (pw_table - 1)->class_pw + (pw_table - 1)->max_added_class_pw,
604 pw_table->class_pw,
605 pw_table->class_pw + pw_table->max_added_class_pw);
606 return -ERANGE;
607 }
608
609 msg->data[2] = pw_table->class_cfg_value;
610 msg->data[3] = (pw - pw_table->class_pw) / 100;
611 return 0;
612 }
613
614 pw_table--;
615 dev_warn(dev,
616 "Power limit %dmW not supported. Set to highest power limit %dmW\n",
617 pw, pw_table->class_pw + pw_table->max_added_class_pw);
618 msg->data[2] = pw_table->class_cfg_value;
619 msg->data[3] = pw_table->max_added_class_pw / 100;
620 return 0;
621 }
622
623 static int
pd692x0_pi_get_pw_limit_ranges(struct pse_controller_dev * pcdev,int id,struct pse_pw_limit_ranges * pw_limit_ranges)624 pd692x0_pi_get_pw_limit_ranges(struct pse_controller_dev *pcdev, int id,
625 struct pse_pw_limit_ranges *pw_limit_ranges)
626 {
627 struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;
628 const struct pd692x0_class_pw *pw_table;
629 int i;
630
631 pw_table = pd692x0_class_pw_table;
632 c33_pw_limit_ranges = kcalloc(PD692X0_CLASS_PW_TABLE_SIZE,
633 sizeof(*c33_pw_limit_ranges),
634 GFP_KERNEL);
635 if (!c33_pw_limit_ranges)
636 return -ENOMEM;
637
638 for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) {
639 c33_pw_limit_ranges[i].min = pw_table->class_pw;
640 c33_pw_limit_ranges[i].max = pw_table->class_pw +
641 pw_table->max_added_class_pw;
642 }
643
644 pw_limit_ranges->c33_pw_limit_ranges = c33_pw_limit_ranges;
645 return i;
646 }
647
648 static int
pd692x0_pi_get_admin_state(struct pse_controller_dev * pcdev,int id,struct pse_admin_state * admin_state)649 pd692x0_pi_get_admin_state(struct pse_controller_dev *pcdev, int id,
650 struct pse_admin_state *admin_state)
651 {
652 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
653 struct pd692x0_msg msg, buf = {0};
654 int ret;
655
656 ret = pd692x0_fw_unavailable(priv);
657 if (ret)
658 return ret;
659
660 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS];
661 msg.sub[2] = id;
662 ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
663 if (ret < 0)
664 return ret;
665
666 if (buf.sub[1])
667 admin_state->c33_admin_state =
668 ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED;
669 else
670 admin_state->c33_admin_state =
671 ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED;
672
673 priv->admin_state[id] = admin_state->c33_admin_state;
674
675 return 0;
676 }
677
678 static int
pd692x0_pi_get_pw_status(struct pse_controller_dev * pcdev,int id,struct pse_pw_status * pw_status)679 pd692x0_pi_get_pw_status(struct pse_controller_dev *pcdev, int id,
680 struct pse_pw_status *pw_status)
681 {
682 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
683 struct pd692x0_msg msg, buf = {0};
684 int ret;
685
686 ret = pd692x0_fw_unavailable(priv);
687 if (ret)
688 return ret;
689
690 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS];
691 msg.sub[2] = id;
692 ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
693 if (ret < 0)
694 return ret;
695
696 /* Compare Port Status (Communication Protocol Document par. 7.1) */
697 if ((buf.sub[0] & 0xf0) == 0x80 || (buf.sub[0] & 0xf0) == 0x90)
698 pw_status->c33_pw_status =
699 ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING;
700 else if (buf.sub[0] == 0x1b || buf.sub[0] == 0x22)
701 pw_status->c33_pw_status =
702 ETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING;
703 else if (buf.sub[0] == 0x12)
704 pw_status->c33_pw_status =
705 ETHTOOL_C33_PSE_PW_D_STATUS_FAULT;
706 else
707 pw_status->c33_pw_status =
708 ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED;
709
710 return 0;
711 }
712
713 static int
pd692x0_pi_get_pw_class(struct pse_controller_dev * pcdev,int id)714 pd692x0_pi_get_pw_class(struct pse_controller_dev *pcdev, int id)
715 {
716 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
717 struct pd692x0_msg msg, buf = {0};
718 u32 class;
719 int ret;
720
721 ret = pd692x0_fw_unavailable(priv);
722 if (ret)
723 return ret;
724
725 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_CLASS];
726 msg.sub[2] = id;
727 ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
728 if (ret < 0)
729 return ret;
730
731 class = buf.data[3] >> 4;
732 if (class <= 8)
733 return class;
734
735 return 0;
736 }
737
738 static int
pd692x0_pi_get_actual_pw(struct pse_controller_dev * pcdev,int id)739 pd692x0_pi_get_actual_pw(struct pse_controller_dev *pcdev, int id)
740 {
741 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
742 struct pd692x0_msg msg, buf = {0};
743 int ret;
744
745 ret = pd692x0_fw_unavailable(priv);
746 if (ret)
747 return ret;
748
749 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS];
750 msg.sub[2] = id;
751 ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
752 if (ret < 0)
753 return ret;
754
755 return (buf.data[0] << 4 | buf.data[1]) * 100;
756 }
757
758 static int
pd692x0_pi_get_prio(struct pse_controller_dev * pcdev,int id)759 pd692x0_pi_get_prio(struct pse_controller_dev *pcdev, int id)
760 {
761 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
762 struct pd692x0_msg msg, buf = {0};
763 int ret;
764
765 ret = pd692x0_fw_unavailable(priv);
766 if (ret)
767 return ret;
768
769 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_PARAM];
770 msg.sub[2] = id;
771 ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
772 if (ret < 0)
773 return ret;
774 if (!buf.data[2] || buf.data[2] > pcdev->pis_prio_max + 1)
775 return -ERANGE;
776
777 /* PSE core priority start at 0 */
778 return buf.data[2] - 1;
779 }
780
pd692x0_get_sw_version(struct pd692x0_priv * priv)781 static struct pd692x0_msg_ver pd692x0_get_sw_version(struct pd692x0_priv *priv)
782 {
783 struct device *dev = &priv->client->dev;
784 struct pd692x0_msg msg, buf = {0};
785 struct pd692x0_msg_ver ver = {0};
786 int ret;
787
788 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_SW_VER];
789 ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
790 if (ret < 0) {
791 dev_err(dev, "Failed to get PSE version (%pe)\n", ERR_PTR(ret));
792 return ver;
793 }
794
795 /* Extract version from the message */
796 ver.prod = buf.sub[2];
797 ver.maj_sw_ver = (buf.data[0] << 8 | buf.data[1]) / 100;
798 ver.min_sw_ver = ((buf.data[0] << 8 | buf.data[1]) / 10) % 10;
799 ver.pa_sw_ver = (buf.data[0] << 8 | buf.data[1]) % 10;
800 ver.param = buf.data[2];
801 ver.build = buf.data[3];
802
803 return ver;
804 }
805
806 struct pd692x0_manager {
807 struct device_node *port_node[PD692X0_MAX_MANAGER_PORTS];
808 struct device_node *node;
809 int nports;
810 };
811
812 struct pd692x0_matrix {
813 u8 hw_port_a;
814 u8 hw_port_b;
815 };
816
817 static int
pd692x0_of_get_ports_manager(struct pd692x0_priv * priv,struct pd692x0_manager * manager,struct device_node * np)818 pd692x0_of_get_ports_manager(struct pd692x0_priv *priv,
819 struct pd692x0_manager *manager,
820 struct device_node *np)
821 {
822 struct device_node *node;
823 int ret, nports, i;
824
825 nports = 0;
826 for_each_child_of_node(np, node) {
827 u32 port;
828
829 if (!of_node_name_eq(node, "port"))
830 continue;
831
832 ret = of_property_read_u32(node, "reg", &port);
833 if (ret)
834 goto out;
835
836 if (port >= PD692X0_MAX_MANAGER_PORTS || port != nports) {
837 dev_err(&priv->client->dev,
838 "wrong number or order of manager ports (%d)\n",
839 port);
840 ret = -EINVAL;
841 goto out;
842 }
843
844 of_node_get(node);
845 manager->port_node[port] = node;
846 nports++;
847 }
848
849 manager->nports = nports;
850 return 0;
851
852 out:
853 for (i = 0; i < nports; i++) {
854 of_node_put(manager->port_node[i]);
855 manager->port_node[i] = NULL;
856 }
857 of_node_put(node);
858 return ret;
859 }
860
861 static int
pd692x0_of_get_managers(struct pd692x0_priv * priv,struct pd692x0_manager * manager)862 pd692x0_of_get_managers(struct pd692x0_priv *priv,
863 struct pd692x0_manager *manager)
864 {
865 struct device_node *managers_node, *node;
866 int ret, nmanagers, i, j;
867
868 if (!priv->np)
869 return -EINVAL;
870
871 nmanagers = 0;
872 managers_node = of_get_child_by_name(priv->np, "managers");
873 if (!managers_node)
874 return -EINVAL;
875
876 for_each_child_of_node(managers_node, node) {
877 u32 manager_id;
878
879 if (!of_node_name_eq(node, "manager"))
880 continue;
881
882 ret = of_property_read_u32(node, "reg", &manager_id);
883 if (ret)
884 goto out;
885
886 if (manager_id >= PD692X0_MAX_MANAGERS ||
887 manager_id != nmanagers) {
888 dev_err(&priv->client->dev,
889 "wrong number or order of managers (%d)\n",
890 manager_id);
891 ret = -EINVAL;
892 goto out;
893 }
894
895 ret = pd692x0_of_get_ports_manager(priv, &manager[manager_id],
896 node);
897 if (ret)
898 goto out;
899
900 of_node_get(node);
901 manager[manager_id].node = node;
902 nmanagers++;
903 }
904
905 of_node_put(managers_node);
906 return nmanagers;
907
908 out:
909 for (i = 0; i < nmanagers; i++) {
910 for (j = 0; j < manager[i].nports; j++) {
911 of_node_put(manager[i].port_node[j]);
912 manager[i].port_node[j] = NULL;
913 }
914 of_node_put(manager[i].node);
915 manager[i].node = NULL;
916 }
917
918 of_node_put(node);
919 of_node_put(managers_node);
920 return ret;
921 }
922
923 static const struct regulator_ops dummy_ops;
924
925 static struct regulator_dev *
pd692x0_register_manager_regulator(struct device * dev,char * reg_name,struct device_node * node)926 pd692x0_register_manager_regulator(struct device *dev, char *reg_name,
927 struct device_node *node)
928 {
929 struct regulator_init_data *rinit_data;
930 struct regulator_config rconfig = {0};
931 struct regulator_desc *rdesc;
932 struct regulator_dev *rdev;
933
934 rinit_data = devm_kzalloc(dev, sizeof(*rinit_data),
935 GFP_KERNEL);
936 if (!rinit_data)
937 return ERR_PTR(-ENOMEM);
938
939 rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL);
940 if (!rdesc)
941 return ERR_PTR(-ENOMEM);
942
943 rdesc->name = reg_name;
944 rdesc->type = REGULATOR_VOLTAGE;
945 rdesc->ops = &dummy_ops;
946 rdesc->owner = THIS_MODULE;
947
948 rinit_data->supply_regulator = "vmain";
949
950 rconfig.dev = dev;
951 rconfig.init_data = rinit_data;
952 rconfig.of_node = node;
953
954 rdev = devm_regulator_register(dev, rdesc, &rconfig);
955 if (IS_ERR(rdev)) {
956 dev_err_probe(dev, PTR_ERR(rdev),
957 "Failed to register regulator\n");
958 return rdev;
959 }
960
961 return rdev;
962 }
963
964 static int
pd692x0_register_managers_regulator(struct pd692x0_priv * priv,const struct pd692x0_manager * manager,int nmanagers)965 pd692x0_register_managers_regulator(struct pd692x0_priv *priv,
966 const struct pd692x0_manager *manager,
967 int nmanagers)
968 {
969 struct device *dev = &priv->client->dev;
970 size_t reg_name_len;
971 int i;
972
973 /* Each regulator name len is dev name + 12 char +
974 * int max digit number (10) + 1
975 */
976 reg_name_len = strlen(dev_name(dev)) + 23;
977
978 for (i = 0; i < nmanagers; i++) {
979 static const char * const regulators[] = { "vaux5", "vaux3p3" };
980 struct regulator_dev *rdev;
981 char *reg_name;
982 int ret;
983
984 reg_name = devm_kzalloc(dev, reg_name_len, GFP_KERNEL);
985 if (!reg_name)
986 return -ENOMEM;
987 snprintf(reg_name, 26, "pse-%s-manager%d", dev_name(dev), i);
988 rdev = pd692x0_register_manager_regulator(dev, reg_name,
989 manager[i].node);
990 if (IS_ERR(rdev))
991 return PTR_ERR(rdev);
992
993 /* VMAIN is described as main supply for the manager.
994 * Add other VAUX power supplies and link them to the
995 * virtual device rdev->dev.
996 */
997 ret = devm_regulator_bulk_get_enable(&rdev->dev,
998 ARRAY_SIZE(regulators),
999 regulators);
1000 if (ret)
1001 return dev_err_probe(&rdev->dev, ret,
1002 "Failed to enable regulators\n");
1003
1004 priv->manager_reg[i] = rdev;
1005 }
1006
1007 return 0;
1008 }
1009
1010 static int
pd692x0_conf_manager_power_budget(struct pd692x0_priv * priv,int id,int pw)1011 pd692x0_conf_manager_power_budget(struct pd692x0_priv *priv, int id, int pw)
1012 {
1013 struct pd692x0_msg msg, buf;
1014 int ret, pw_mW = pw / 1000;
1015
1016 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_POWER_BANK];
1017 msg.data[0] = id;
1018 ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
1019 if (ret < 0)
1020 return ret;
1021
1022 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_POWER_BANK];
1023 msg.data[0] = id;
1024 msg.data[1] = pw_mW >> 8;
1025 msg.data[2] = pw_mW & 0xff;
1026 msg.data[3] = buf.sub[2];
1027 msg.data[4] = buf.data[0];
1028 msg.data[5] = buf.data[1];
1029 msg.data[6] = buf.data[2];
1030 msg.data[7] = buf.data[3];
1031 return pd692x0_sendrecv_msg(priv, &msg, &buf);
1032 }
1033
1034 static int
pd692x0_configure_managers(struct pd692x0_priv * priv,int nmanagers)1035 pd692x0_configure_managers(struct pd692x0_priv *priv, int nmanagers)
1036 {
1037 int i, ret;
1038
1039 for (i = 0; i < nmanagers; i++) {
1040 struct regulator *supply = priv->manager_reg[i]->supply;
1041 int pw_budget;
1042
1043 pw_budget = regulator_get_unclaimed_power_budget(supply);
1044 /* Max power budget per manager */
1045 if (pw_budget > 6000000)
1046 pw_budget = 6000000;
1047 ret = regulator_request_power_budget(supply, pw_budget);
1048 if (ret < 0)
1049 return ret;
1050
1051 priv->manager_pw_budget[i] = pw_budget;
1052 ret = pd692x0_conf_manager_power_budget(priv, i, pw_budget);
1053 if (ret < 0)
1054 return ret;
1055 }
1056
1057 return 0;
1058 }
1059
1060 static int
pd692x0_set_port_matrix(const struct pse_pi_pairset * pairset,const struct pd692x0_manager * manager,int nmanagers,struct pd692x0_matrix * port_matrix)1061 pd692x0_set_port_matrix(const struct pse_pi_pairset *pairset,
1062 const struct pd692x0_manager *manager,
1063 int nmanagers, struct pd692x0_matrix *port_matrix)
1064 {
1065 int i, j, port_cnt;
1066 bool found = false;
1067
1068 if (!pairset->np)
1069 return 0;
1070
1071 /* Look on every managers */
1072 port_cnt = 0;
1073 for (i = 0; i < nmanagers; i++) {
1074 /* Look on every ports of the manager */
1075 for (j = 0; j < manager[i].nports; j++) {
1076 if (pairset->np == manager[i].port_node[j]) {
1077 found = true;
1078 break;
1079 }
1080 }
1081 port_cnt += j;
1082
1083 if (found)
1084 break;
1085 }
1086
1087 if (!found)
1088 return -ENODEV;
1089
1090 if (pairset->pinout == ALTERNATIVE_A)
1091 port_matrix->hw_port_a = port_cnt;
1092 else if (pairset->pinout == ALTERNATIVE_B)
1093 port_matrix->hw_port_b = port_cnt;
1094
1095 return 0;
1096 }
1097
1098 static int
pd692x0_set_ports_matrix(struct pd692x0_priv * priv,const struct pd692x0_manager * manager,int nmanagers,struct pd692x0_matrix port_matrix[PD692X0_MAX_PIS])1099 pd692x0_set_ports_matrix(struct pd692x0_priv *priv,
1100 const struct pd692x0_manager *manager,
1101 int nmanagers,
1102 struct pd692x0_matrix port_matrix[PD692X0_MAX_PIS])
1103 {
1104 struct pse_controller_dev *pcdev = &priv->pcdev;
1105 int i, ret;
1106
1107 /* Init Matrix */
1108 for (i = 0; i < PD692X0_MAX_PIS; i++) {
1109 port_matrix[i].hw_port_a = 0xff;
1110 port_matrix[i].hw_port_b = 0xff;
1111 }
1112
1113 /* Update with values for every PSE PIs */
1114 for (i = 0; i < pcdev->nr_lines; i++) {
1115 ret = pd692x0_set_port_matrix(&pcdev->pi[i].pairset[0],
1116 manager, nmanagers,
1117 &port_matrix[i]);
1118 if (ret) {
1119 dev_err(&priv->client->dev,
1120 "unable to configure pi %d pairset 0", i);
1121 return ret;
1122 }
1123
1124 ret = pd692x0_set_port_matrix(&pcdev->pi[i].pairset[1],
1125 manager, nmanagers,
1126 &port_matrix[i]);
1127 if (ret) {
1128 dev_err(&priv->client->dev,
1129 "unable to configure pi %d pairset 1", i);
1130 return ret;
1131 }
1132 }
1133
1134 return 0;
1135 }
1136
1137 static int
pd692x0_write_ports_matrix(struct pd692x0_priv * priv,const struct pd692x0_matrix port_matrix[PD692X0_MAX_PIS])1138 pd692x0_write_ports_matrix(struct pd692x0_priv *priv,
1139 const struct pd692x0_matrix port_matrix[PD692X0_MAX_PIS])
1140 {
1141 struct pd692x0_msg msg, buf;
1142 int ret, i;
1143
1144 /* Write temporary Matrix */
1145 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_TMP_PORT_MATRIX];
1146 for (i = 0; i < PD692X0_MAX_PIS; i++) {
1147 msg.sub[2] = i;
1148 msg.data[0] = port_matrix[i].hw_port_b;
1149 msg.data[1] = port_matrix[i].hw_port_a;
1150
1151 ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
1152 if (ret < 0)
1153 return ret;
1154 }
1155
1156 /* Program Matrix */
1157 msg = pd692x0_msg_template_list[PD692X0_MSG_PRG_PORT_MATRIX];
1158 ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
1159 if (ret < 0)
1160 return ret;
1161
1162 return 0;
1163 }
1164
pd692x0_setup_pi_matrix(struct pse_controller_dev * pcdev)1165 static int pd692x0_setup_pi_matrix(struct pse_controller_dev *pcdev)
1166 {
1167 struct pd692x0_manager *manager __free(kfree) = NULL;
1168 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
1169 struct pd692x0_matrix port_matrix[PD692X0_MAX_PIS];
1170 int ret, i, j, nmanagers;
1171
1172 /* Should we flash the port matrix */
1173 if (priv->fw_state != PD692X0_FW_OK &&
1174 priv->fw_state != PD692X0_FW_COMPLETE)
1175 return 0;
1176
1177 manager = kcalloc(PD692X0_MAX_MANAGERS, sizeof(*manager), GFP_KERNEL);
1178 if (!manager)
1179 return -ENOMEM;
1180
1181 ret = pd692x0_of_get_managers(priv, manager);
1182 if (ret < 0)
1183 return ret;
1184
1185 nmanagers = ret;
1186 ret = pd692x0_register_managers_regulator(priv, manager, nmanagers);
1187 if (ret)
1188 goto out;
1189
1190 ret = pd692x0_configure_managers(priv, nmanagers);
1191 if (ret)
1192 goto out;
1193
1194 ret = pd692x0_set_ports_matrix(priv, manager, nmanagers, port_matrix);
1195 if (ret)
1196 goto out;
1197
1198 ret = pd692x0_write_ports_matrix(priv, port_matrix);
1199 if (ret)
1200 goto out;
1201
1202 out:
1203 for (i = 0; i < nmanagers; i++) {
1204 struct regulator *supply = priv->manager_reg[i]->supply;
1205
1206 regulator_free_power_budget(supply,
1207 priv->manager_pw_budget[i]);
1208
1209 for (j = 0; j < manager[i].nports; j++)
1210 of_node_put(manager[i].port_node[j]);
1211 of_node_put(manager[i].node);
1212 }
1213 return ret;
1214 }
1215
pd692x0_pi_get_voltage(struct pse_controller_dev * pcdev,int id)1216 static int pd692x0_pi_get_voltage(struct pse_controller_dev *pcdev, int id)
1217 {
1218 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
1219 struct pd692x0_msg msg, buf = {0};
1220 int ret;
1221
1222 ret = pd692x0_fw_unavailable(priv);
1223 if (ret)
1224 return ret;
1225
1226 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_MEAS];
1227 msg.sub[2] = id;
1228 ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
1229 if (ret < 0)
1230 return ret;
1231
1232 /* Convert 0.1V unit to uV */
1233 return (buf.sub[0] << 8 | buf.sub[1]) * 100000;
1234 }
1235
pd692x0_pi_get_pw_limit(struct pse_controller_dev * pcdev,int id)1236 static int pd692x0_pi_get_pw_limit(struct pse_controller_dev *pcdev,
1237 int id)
1238 {
1239 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
1240 struct pd692x0_msg msg, buf = {0};
1241 int ret;
1242
1243 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_PARAM];
1244 msg.sub[2] = id;
1245 ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
1246 if (ret < 0)
1247 return ret;
1248
1249 return pd692x0_pi_get_pw_from_table(buf.data[0], buf.data[1]);
1250 }
1251
pd692x0_pi_set_pw_limit(struct pse_controller_dev * pcdev,int id,int max_mW)1252 static int pd692x0_pi_set_pw_limit(struct pse_controller_dev *pcdev,
1253 int id, int max_mW)
1254 {
1255 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
1256 struct device *dev = &priv->client->dev;
1257 struct pd692x0_msg msg, buf = {0};
1258 int ret;
1259
1260 ret = pd692x0_fw_unavailable(priv);
1261 if (ret)
1262 return ret;
1263
1264 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM];
1265 msg.sub[2] = id;
1266 ret = pd692x0_pi_set_pw_from_table(dev, &msg, max_mW);
1267 if (ret)
1268 return ret;
1269
1270 return pd692x0_sendrecv_msg(priv, &msg, &buf);
1271 }
1272
pd692x0_pi_set_prio(struct pse_controller_dev * pcdev,int id,unsigned int prio)1273 static int pd692x0_pi_set_prio(struct pse_controller_dev *pcdev, int id,
1274 unsigned int prio)
1275 {
1276 struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
1277 struct pd692x0_msg msg, buf = {0};
1278 int ret;
1279
1280 ret = pd692x0_fw_unavailable(priv);
1281 if (ret)
1282 return ret;
1283
1284 msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM];
1285 msg.sub[2] = id;
1286 /* Controller priority from 1 to 3 */
1287 msg.data[4] = prio + 1;
1288
1289 return pd692x0_sendrecv_msg(priv, &msg, &buf);
1290 }
1291
1292 static const struct pse_controller_ops pd692x0_ops = {
1293 .setup_pi_matrix = pd692x0_setup_pi_matrix,
1294 .pi_get_admin_state = pd692x0_pi_get_admin_state,
1295 .pi_get_pw_status = pd692x0_pi_get_pw_status,
1296 .pi_get_ext_state = pd692x0_pi_get_ext_state,
1297 .pi_get_pw_class = pd692x0_pi_get_pw_class,
1298 .pi_get_actual_pw = pd692x0_pi_get_actual_pw,
1299 .pi_enable = pd692x0_pi_enable,
1300 .pi_disable = pd692x0_pi_disable,
1301 .pi_get_voltage = pd692x0_pi_get_voltage,
1302 .pi_get_pw_limit = pd692x0_pi_get_pw_limit,
1303 .pi_set_pw_limit = pd692x0_pi_set_pw_limit,
1304 .pi_get_pw_limit_ranges = pd692x0_pi_get_pw_limit_ranges,
1305 .pi_get_prio = pd692x0_pi_get_prio,
1306 .pi_set_prio = pd692x0_pi_set_prio,
1307 };
1308
1309 #define PD692X0_FW_LINE_MAX_SZ 0xff
pd692x0_fw_get_next_line(const u8 * data,char * line,size_t size)1310 static int pd692x0_fw_get_next_line(const u8 *data,
1311 char *line, size_t size)
1312 {
1313 size_t line_size;
1314 int i;
1315
1316 line_size = min_t(size_t, size, PD692X0_FW_LINE_MAX_SZ);
1317
1318 memset(line, 0, PD692X0_FW_LINE_MAX_SZ);
1319 for (i = 0; i < line_size - 1; i++) {
1320 if (*data == '\r' && *(data + 1) == '\n') {
1321 line[i] = '\r';
1322 line[i + 1] = '\n';
1323 return i + 2;
1324 }
1325 line[i] = *data;
1326 data++;
1327 }
1328
1329 return -EIO;
1330 }
1331
1332 static enum fw_upload_err
pd692x0_fw_recv_resp(const struct i2c_client * client,unsigned long ms_timeout,const char * msg_ok,unsigned int msg_size)1333 pd692x0_fw_recv_resp(const struct i2c_client *client, unsigned long ms_timeout,
1334 const char *msg_ok, unsigned int msg_size)
1335 {
1336 /* Maximum controller response size */
1337 char fw_msg_buf[5] = {0};
1338 unsigned long timeout;
1339 int ret;
1340
1341 if (msg_size > sizeof(fw_msg_buf))
1342 return FW_UPLOAD_ERR_RW_ERROR;
1343
1344 /* Read until we get something */
1345 timeout = msecs_to_jiffies(ms_timeout) + jiffies;
1346 while (true) {
1347 if (time_is_before_jiffies(timeout))
1348 return FW_UPLOAD_ERR_TIMEOUT;
1349
1350 ret = i2c_master_recv(client, fw_msg_buf, 1);
1351 if (ret < 0 || *fw_msg_buf == 0) {
1352 usleep_range(1000, 2000);
1353 continue;
1354 } else {
1355 break;
1356 }
1357 }
1358
1359 /* Read remaining characters */
1360 ret = i2c_master_recv(client, fw_msg_buf + 1, msg_size - 1);
1361 if (strncmp(fw_msg_buf, msg_ok, msg_size)) {
1362 dev_err(&client->dev,
1363 "Wrong FW download process answer (%*pE)\n",
1364 msg_size, fw_msg_buf);
1365 return FW_UPLOAD_ERR_HW_ERROR;
1366 }
1367
1368 return FW_UPLOAD_ERR_NONE;
1369 }
1370
pd692x0_fw_write_line(const struct i2c_client * client,const char line[PD692X0_FW_LINE_MAX_SZ],const bool last_line)1371 static int pd692x0_fw_write_line(const struct i2c_client *client,
1372 const char line[PD692X0_FW_LINE_MAX_SZ],
1373 const bool last_line)
1374 {
1375 int ret;
1376
1377 while (*line != 0) {
1378 ret = i2c_master_send(client, line, 1);
1379 if (ret < 0)
1380 return FW_UPLOAD_ERR_RW_ERROR;
1381 line++;
1382 }
1383
1384 if (last_line) {
1385 ret = pd692x0_fw_recv_resp(client, 100, "TP\r\n",
1386 sizeof("TP\r\n") - 1);
1387 if (ret)
1388 return ret;
1389 } else {
1390 ret = pd692x0_fw_recv_resp(client, 100, "T*\r\n",
1391 sizeof("T*\r\n") - 1);
1392 if (ret)
1393 return ret;
1394 }
1395
1396 return FW_UPLOAD_ERR_NONE;
1397 }
1398
pd692x0_fw_reset(const struct i2c_client * client)1399 static enum fw_upload_err pd692x0_fw_reset(const struct i2c_client *client)
1400 {
1401 const struct pd692x0_msg zero = {0};
1402 struct pd692x0_msg buf = {0};
1403 unsigned long timeout;
1404 char cmd[] = "RST";
1405 int ret;
1406
1407 ret = i2c_master_send(client, cmd, strlen(cmd));
1408 if (ret < 0) {
1409 dev_err(&client->dev,
1410 "Failed to reset the controller (%pe)\n",
1411 ERR_PTR(ret));
1412 return ret;
1413 }
1414
1415 timeout = msecs_to_jiffies(10000) + jiffies;
1416 while (true) {
1417 if (time_is_before_jiffies(timeout))
1418 return FW_UPLOAD_ERR_TIMEOUT;
1419
1420 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf));
1421 if (ret < 0 ||
1422 !memcmp(&buf, &zero, sizeof(buf)))
1423 usleep_range(1000, 2000);
1424 else
1425 break;
1426 }
1427
1428 /* Is the reply a successful report message */
1429 if (buf.key != PD692X0_KEY_TLM || buf.echo != 0xff ||
1430 buf.sub[0] & 0x01) {
1431 dev_err(&client->dev, "PSE controller error\n");
1432 return FW_UPLOAD_ERR_HW_ERROR;
1433 }
1434
1435 /* Is the firmware operational */
1436 if (buf.sub[0] & 0x02) {
1437 dev_err(&client->dev,
1438 "PSE firmware error. Please update it.\n");
1439 return FW_UPLOAD_ERR_HW_ERROR;
1440 }
1441
1442 return FW_UPLOAD_ERR_NONE;
1443 }
1444
pd692x0_fw_prepare(struct fw_upload * fwl,const u8 * data,u32 size)1445 static enum fw_upload_err pd692x0_fw_prepare(struct fw_upload *fwl,
1446 const u8 *data, u32 size)
1447 {
1448 struct pd692x0_priv *priv = fwl->dd_handle;
1449 const struct i2c_client *client = priv->client;
1450 enum pd692x0_fw_state last_fw_state;
1451 int ret;
1452
1453 priv->cancel_request = false;
1454 last_fw_state = priv->fw_state;
1455
1456 priv->fw_state = PD692X0_FW_PREPARE;
1457
1458 /* Enter program mode */
1459 if (last_fw_state == PD692X0_FW_BROKEN) {
1460 const char *msg = "ENTR";
1461 const char *c;
1462
1463 c = msg;
1464 do {
1465 ret = i2c_master_send(client, c, 1);
1466 if (ret < 0)
1467 return FW_UPLOAD_ERR_RW_ERROR;
1468 if (*(c + 1))
1469 usleep_range(10000, 20000);
1470 } while (*(++c));
1471 } else {
1472 struct pd692x0_msg msg, buf;
1473
1474 msg = pd692x0_msg_template_list[PD692X0_MSG_DOWNLOAD_CMD];
1475 ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
1476 if (ret < 0) {
1477 dev_err(&client->dev,
1478 "Failed to enter programming mode (%pe)\n",
1479 ERR_PTR(ret));
1480 return FW_UPLOAD_ERR_RW_ERROR;
1481 }
1482 }
1483
1484 ret = pd692x0_fw_recv_resp(client, 100, "TPE\r\n", sizeof("TPE\r\n") - 1);
1485 if (ret)
1486 goto err_out;
1487
1488 if (priv->cancel_request) {
1489 ret = FW_UPLOAD_ERR_CANCELED;
1490 goto err_out;
1491 }
1492
1493 return FW_UPLOAD_ERR_NONE;
1494
1495 err_out:
1496 pd692x0_fw_reset(priv->client);
1497 priv->fw_state = last_fw_state;
1498 return ret;
1499 }
1500
pd692x0_fw_write(struct fw_upload * fwl,const u8 * data,u32 offset,u32 size,u32 * written)1501 static enum fw_upload_err pd692x0_fw_write(struct fw_upload *fwl,
1502 const u8 *data, u32 offset,
1503 u32 size, u32 *written)
1504 {
1505 struct pd692x0_priv *priv = fwl->dd_handle;
1506 char line[PD692X0_FW_LINE_MAX_SZ];
1507 const struct i2c_client *client;
1508 int ret, i;
1509 char cmd;
1510
1511 client = priv->client;
1512 priv->fw_state = PD692X0_FW_WRITE;
1513
1514 /* Erase */
1515 cmd = 'E';
1516 ret = i2c_master_send(client, &cmd, 1);
1517 if (ret < 0) {
1518 dev_err(&client->dev,
1519 "Failed to boot programming mode (%pe)\n",
1520 ERR_PTR(ret));
1521 return FW_UPLOAD_ERR_RW_ERROR;
1522 }
1523
1524 ret = pd692x0_fw_recv_resp(client, 100, "TOE\r\n", sizeof("TOE\r\n") - 1);
1525 if (ret)
1526 return ret;
1527
1528 ret = pd692x0_fw_recv_resp(client, 5000, "TE\r\n", sizeof("TE\r\n") - 1);
1529 if (ret)
1530 dev_warn(&client->dev,
1531 "Failed to erase internal memory, however still try to write Firmware\n");
1532
1533 ret = pd692x0_fw_recv_resp(client, 100, "TPE\r\n", sizeof("TPE\r\n") - 1);
1534 if (ret)
1535 dev_warn(&client->dev,
1536 "Failed to erase internal memory, however still try to write Firmware\n");
1537
1538 if (priv->cancel_request)
1539 return FW_UPLOAD_ERR_CANCELED;
1540
1541 /* Program */
1542 cmd = 'P';
1543 ret = i2c_master_send(client, &cmd, sizeof(char));
1544 if (ret < 0) {
1545 dev_err(&client->dev,
1546 "Failed to boot programming mode (%pe)\n",
1547 ERR_PTR(ret));
1548 return ret;
1549 }
1550
1551 ret = pd692x0_fw_recv_resp(client, 100, "TOP\r\n", sizeof("TOP\r\n") - 1);
1552 if (ret)
1553 return ret;
1554
1555 i = 0;
1556 while (i < size) {
1557 ret = pd692x0_fw_get_next_line(data, line, size - i);
1558 if (ret < 0) {
1559 ret = FW_UPLOAD_ERR_FW_INVALID;
1560 goto err;
1561 }
1562
1563 i += ret;
1564 data += ret;
1565 if (line[0] == 'S' && line[1] == '0') {
1566 continue;
1567 } else if (line[0] == 'S' && line[1] == '7') {
1568 ret = pd692x0_fw_write_line(client, line, true);
1569 if (ret)
1570 goto err;
1571 } else {
1572 ret = pd692x0_fw_write_line(client, line, false);
1573 if (ret)
1574 goto err;
1575 }
1576
1577 if (priv->cancel_request) {
1578 ret = FW_UPLOAD_ERR_CANCELED;
1579 goto err;
1580 }
1581 }
1582 *written = i;
1583
1584 msleep(400);
1585
1586 return FW_UPLOAD_ERR_NONE;
1587
1588 err:
1589 strscpy_pad(line, "S7\r\n", sizeof(line));
1590 pd692x0_fw_write_line(client, line, true);
1591 return ret;
1592 }
1593
pd692x0_fw_poll_complete(struct fw_upload * fwl)1594 static enum fw_upload_err pd692x0_fw_poll_complete(struct fw_upload *fwl)
1595 {
1596 struct pd692x0_priv *priv = fwl->dd_handle;
1597 const struct i2c_client *client = priv->client;
1598 struct pd692x0_msg_ver ver;
1599 int ret;
1600
1601 priv->fw_state = PD692X0_FW_COMPLETE;
1602
1603 ret = pd692x0_fw_reset(client);
1604 if (ret)
1605 return ret;
1606
1607 ver = pd692x0_get_sw_version(priv);
1608 if (ver.maj_sw_ver < PD692X0_FW_MAJ_VER) {
1609 dev_err(&client->dev,
1610 "Too old firmware version. Please update it\n");
1611 priv->fw_state = PD692X0_FW_NEED_UPDATE;
1612 return FW_UPLOAD_ERR_FW_INVALID;
1613 }
1614
1615 ret = pd692x0_setup_pi_matrix(&priv->pcdev);
1616 if (ret < 0) {
1617 dev_err(&client->dev, "Error configuring ports matrix (%pe)\n",
1618 ERR_PTR(ret));
1619 priv->fw_state = PD692X0_FW_NEED_UPDATE;
1620 return FW_UPLOAD_ERR_HW_ERROR;
1621 }
1622
1623 priv->fw_state = PD692X0_FW_OK;
1624 return FW_UPLOAD_ERR_NONE;
1625 }
1626
pd692x0_fw_cancel(struct fw_upload * fwl)1627 static void pd692x0_fw_cancel(struct fw_upload *fwl)
1628 {
1629 struct pd692x0_priv *priv = fwl->dd_handle;
1630
1631 priv->cancel_request = true;
1632 }
1633
pd692x0_fw_cleanup(struct fw_upload * fwl)1634 static void pd692x0_fw_cleanup(struct fw_upload *fwl)
1635 {
1636 struct pd692x0_priv *priv = fwl->dd_handle;
1637
1638 switch (priv->fw_state) {
1639 case PD692X0_FW_WRITE:
1640 pd692x0_fw_reset(priv->client);
1641 fallthrough;
1642 case PD692X0_FW_COMPLETE:
1643 priv->fw_state = PD692X0_FW_BROKEN;
1644 break;
1645 default:
1646 break;
1647 }
1648 }
1649
1650 static const struct fw_upload_ops pd692x0_fw_ops = {
1651 .prepare = pd692x0_fw_prepare,
1652 .write = pd692x0_fw_write,
1653 .poll_complete = pd692x0_fw_poll_complete,
1654 .cancel = pd692x0_fw_cancel,
1655 .cleanup = pd692x0_fw_cleanup,
1656 };
1657
pd692x0_i2c_probe(struct i2c_client * client)1658 static int pd692x0_i2c_probe(struct i2c_client *client)
1659 {
1660 static const char * const regulators[] = { "vdd", "vdda" };
1661 struct pd692x0_msg msg, buf = {0}, zero = {0};
1662 struct device *dev = &client->dev;
1663 struct pd692x0_msg_ver ver;
1664 struct pd692x0_priv *priv;
1665 struct fw_upload *fwl;
1666 int ret;
1667
1668 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulators),
1669 regulators);
1670 if (ret)
1671 return dev_err_probe(dev, ret,
1672 "Failed to enable regulators\n");
1673
1674 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1675 dev_err(dev, "i2c check functionality failed\n");
1676 return -ENXIO;
1677 }
1678
1679 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1680 if (!priv)
1681 return -ENOMEM;
1682
1683 priv->client = client;
1684 i2c_set_clientdata(client, priv);
1685
1686 ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf));
1687 if (ret != sizeof(buf)) {
1688 dev_err(dev, "Failed to get device status\n");
1689 return -EIO;
1690 }
1691
1692 /* Probe has been already run and the status dumped */
1693 if (!memcmp(&buf, &zero, sizeof(buf))) {
1694 /* Ask again the controller status */
1695 msg = pd692x0_msg_template_list[PD692X0_MSG_GET_SYS_STATUS];
1696 ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
1697 if (ret < 0) {
1698 dev_err(dev, "Failed to get device status\n");
1699 return ret;
1700 }
1701 }
1702
1703 if (buf.key != 0x03 || buf.sub[0] & 0x01) {
1704 dev_err(dev, "PSE controller error\n");
1705 return -EIO;
1706 }
1707 if (buf.sub[0] & 0x02) {
1708 dev_err(dev, "PSE firmware error. Please update it.\n");
1709 priv->fw_state = PD692X0_FW_BROKEN;
1710 } else {
1711 ver = pd692x0_get_sw_version(priv);
1712 dev_info(&client->dev, "Software version %d.%02d.%d.%d\n",
1713 ver.prod, ver.maj_sw_ver, ver.min_sw_ver,
1714 ver.pa_sw_ver);
1715
1716 if (ver.maj_sw_ver < PD692X0_FW_MAJ_VER) {
1717 dev_err(dev, "Too old firmware version. Please update it\n");
1718 priv->fw_state = PD692X0_FW_NEED_UPDATE;
1719 } else {
1720 priv->fw_state = PD692X0_FW_OK;
1721 }
1722 }
1723
1724 priv->np = dev->of_node;
1725 priv->pcdev.nr_lines = PD692X0_MAX_PIS;
1726 priv->pcdev.owner = THIS_MODULE;
1727 priv->pcdev.ops = &pd692x0_ops;
1728 priv->pcdev.dev = dev;
1729 priv->pcdev.types = ETHTOOL_PSE_C33;
1730 priv->pcdev.supp_budget_eval_strategies = PSE_BUDGET_EVAL_STRAT_DYNAMIC;
1731 priv->pcdev.pis_prio_max = 2;
1732 ret = devm_pse_controller_register(dev, &priv->pcdev);
1733 if (ret)
1734 return dev_err_probe(dev, ret,
1735 "failed to register PSE controller\n");
1736
1737 fwl = firmware_upload_register(THIS_MODULE, dev, dev_name(dev),
1738 &pd692x0_fw_ops, priv);
1739 if (IS_ERR(fwl))
1740 return dev_err_probe(dev, PTR_ERR(fwl),
1741 "failed to register to the Firmware Upload API\n");
1742 priv->fwl = fwl;
1743
1744 return 0;
1745 }
1746
pd692x0_i2c_remove(struct i2c_client * client)1747 static void pd692x0_i2c_remove(struct i2c_client *client)
1748 {
1749 struct pd692x0_priv *priv = i2c_get_clientdata(client);
1750
1751 firmware_upload_unregister(priv->fwl);
1752 }
1753
1754 static const struct i2c_device_id pd692x0_id[] = {
1755 { PD692X0_PSE_NAME },
1756 { }
1757 };
1758 MODULE_DEVICE_TABLE(i2c, pd692x0_id);
1759
1760 static const struct of_device_id pd692x0_of_match[] = {
1761 { .compatible = "microchip,pd69200", },
1762 { .compatible = "microchip,pd69210", },
1763 { .compatible = "microchip,pd69220", },
1764 { },
1765 };
1766 MODULE_DEVICE_TABLE(of, pd692x0_of_match);
1767
1768 static struct i2c_driver pd692x0_driver = {
1769 .probe = pd692x0_i2c_probe,
1770 .remove = pd692x0_i2c_remove,
1771 .id_table = pd692x0_id,
1772 .driver = {
1773 .name = PD692X0_PSE_NAME,
1774 .of_match_table = pd692x0_of_match,
1775 },
1776 };
1777 module_i2c_driver(pd692x0_driver);
1778
1779 MODULE_AUTHOR("Kory Maincent <kory.maincent@bootlin.com>");
1780 MODULE_DESCRIPTION("Microchip PD692x0 PoE PSE Controller driver");
1781 MODULE_LICENSE("GPL");
1782