1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2023, Linaro Limited
5 *
6 */
7
8 #include <linux/device.h>
9 #include <linux/interconnect.h>
10 #include <linux/interconnect-provider.h>
11 #include <linux/module.h>
12 #include <linux/of_platform.h>
13 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
14
15 #include "bcm-voter.h"
16 #include "icc-common.h"
17 #include "icc-rpmh.h"
18
19 static struct qcom_icc_node qhm_qspi;
20 static struct qcom_icc_node qhm_qup1;
21 static struct qcom_icc_node xm_sdc4;
22 static struct qcom_icc_node xm_ufs_mem;
23 static struct qcom_icc_node qhm_qup0;
24 static struct qcom_icc_node qhm_qup2;
25 static struct qcom_icc_node qxm_crypto;
26 static struct qcom_icc_node qxm_sp;
27 static struct qcom_icc_node xm_qdss_etr_0;
28 static struct qcom_icc_node xm_qdss_etr_1;
29 static struct qcom_icc_node xm_sdc2;
30 static struct qcom_icc_node qup0_core_master;
31 static struct qcom_icc_node qup1_core_master;
32 static struct qcom_icc_node qup2_core_master;
33 static struct qcom_icc_node qsm_cfg;
34 static struct qcom_icc_node qnm_gemnoc_cnoc;
35 static struct qcom_icc_node qnm_gemnoc_pcie;
36 static struct qcom_icc_node alm_gpu_tcu;
37 static struct qcom_icc_node alm_pcie_tcu;
38 static struct qcom_icc_node alm_sys_tcu;
39 static struct qcom_icc_node chm_apps;
40 static struct qcom_icc_node qnm_gpu;
41 static struct qcom_icc_node qnm_lpass;
42 static struct qcom_icc_node qnm_mnoc_hf;
43 static struct qcom_icc_node qnm_mnoc_sf;
44 static struct qcom_icc_node qnm_nsp_noc;
45 static struct qcom_icc_node qnm_pcie;
46 static struct qcom_icc_node qnm_snoc_sf;
47 static struct qcom_icc_node xm_gic;
48 static struct qcom_icc_node qnm_lpiaon_noc;
49 static struct qcom_icc_node qnm_lpass_lpinoc;
50 static struct qcom_icc_node qxm_lpinoc_dsp_axim;
51 static struct qcom_icc_node llcc_mc;
52 static struct qcom_icc_node qnm_av1_enc;
53 static struct qcom_icc_node qnm_camnoc_hf;
54 static struct qcom_icc_node qnm_camnoc_icp;
55 static struct qcom_icc_node qnm_camnoc_sf;
56 static struct qcom_icc_node qnm_eva;
57 static struct qcom_icc_node qnm_mdp;
58 static struct qcom_icc_node qnm_video;
59 static struct qcom_icc_node qnm_video_cv_cpu;
60 static struct qcom_icc_node qnm_video_v_cpu;
61 static struct qcom_icc_node qsm_mnoc_cfg;
62 static struct qcom_icc_node qxm_nsp;
63 static struct qcom_icc_node qnm_pcie_north_gem_noc;
64 static struct qcom_icc_node qnm_pcie_south_gem_noc;
65 static struct qcom_icc_node xm_pcie_3;
66 static struct qcom_icc_node xm_pcie_4;
67 static struct qcom_icc_node xm_pcie_5;
68 static struct qcom_icc_node xm_pcie_0;
69 static struct qcom_icc_node xm_pcie_1;
70 static struct qcom_icc_node xm_pcie_2;
71 static struct qcom_icc_node xm_pcie_6a;
72 static struct qcom_icc_node xm_pcie_6b;
73 static struct qcom_icc_node qnm_aggre1_noc;
74 static struct qcom_icc_node qnm_aggre2_noc;
75 static struct qcom_icc_node qnm_gic;
76 static struct qcom_icc_node qnm_usb_anoc;
77 static struct qcom_icc_node qnm_aggre_usb_north_snoc;
78 static struct qcom_icc_node qnm_aggre_usb_south_snoc;
79 static struct qcom_icc_node xm_usb2_0;
80 static struct qcom_icc_node xm_usb3_mp;
81 static struct qcom_icc_node xm_usb3_0;
82 static struct qcom_icc_node xm_usb3_1;
83 static struct qcom_icc_node xm_usb3_2;
84 static struct qcom_icc_node xm_usb4_0;
85 static struct qcom_icc_node xm_usb4_1;
86 static struct qcom_icc_node xm_usb4_2;
87 static struct qcom_icc_node qns_a1noc_snoc;
88 static struct qcom_icc_node qns_a2noc_snoc;
89 static struct qcom_icc_node qup0_core_slave;
90 static struct qcom_icc_node qup1_core_slave;
91 static struct qcom_icc_node qup2_core_slave;
92 static struct qcom_icc_node qhs_ahb2phy0;
93 static struct qcom_icc_node qhs_ahb2phy1;
94 static struct qcom_icc_node qhs_ahb2phy2;
95 static struct qcom_icc_node qhs_av1_enc_cfg;
96 static struct qcom_icc_node qhs_camera_cfg;
97 static struct qcom_icc_node qhs_clk_ctl;
98 static struct qcom_icc_node qhs_crypto0_cfg;
99 static struct qcom_icc_node qhs_display_cfg;
100 static struct qcom_icc_node qhs_gpuss_cfg;
101 static struct qcom_icc_node qhs_imem_cfg;
102 static struct qcom_icc_node qhs_ipc_router;
103 static struct qcom_icc_node qhs_pcie0_cfg;
104 static struct qcom_icc_node qhs_pcie1_cfg;
105 static struct qcom_icc_node qhs_pcie2_cfg;
106 static struct qcom_icc_node qhs_pcie3_cfg;
107 static struct qcom_icc_node qhs_pcie4_cfg;
108 static struct qcom_icc_node qhs_pcie5_cfg;
109 static struct qcom_icc_node qhs_pcie6a_cfg;
110 static struct qcom_icc_node qhs_pcie6b_cfg;
111 static struct qcom_icc_node qhs_pcie_rsc_cfg;
112 static struct qcom_icc_node qhs_pdm;
113 static struct qcom_icc_node qhs_prng;
114 static struct qcom_icc_node qhs_qdss_cfg;
115 static struct qcom_icc_node qhs_qspi;
116 static struct qcom_icc_node qhs_qup0;
117 static struct qcom_icc_node qhs_qup1;
118 static struct qcom_icc_node qhs_qup2;
119 static struct qcom_icc_node qhs_sdc2;
120 static struct qcom_icc_node qhs_sdc4;
121 static struct qcom_icc_node qhs_smmuv3_cfg;
122 static struct qcom_icc_node qhs_tcsr;
123 static struct qcom_icc_node qhs_tlmm;
124 static struct qcom_icc_node qhs_ufs_mem_cfg;
125 static struct qcom_icc_node qhs_usb2_0_cfg;
126 static struct qcom_icc_node qhs_usb3_0_cfg;
127 static struct qcom_icc_node qhs_usb3_1_cfg;
128 static struct qcom_icc_node qhs_usb3_2_cfg;
129 static struct qcom_icc_node qhs_usb3_mp_cfg;
130 static struct qcom_icc_node qhs_usb4_0_cfg;
131 static struct qcom_icc_node qhs_usb4_1_cfg;
132 static struct qcom_icc_node qhs_usb4_2_cfg;
133 static struct qcom_icc_node qhs_venus_cfg;
134 static struct qcom_icc_node qss_lpass_qtb_cfg;
135 static struct qcom_icc_node qss_mnoc_cfg;
136 static struct qcom_icc_node qss_nsp_qtb_cfg;
137 static struct qcom_icc_node xs_qdss_stm;
138 static struct qcom_icc_node xs_sys_tcu_cfg;
139 static struct qcom_icc_node qhs_aoss;
140 static struct qcom_icc_node qhs_tme_cfg;
141 static struct qcom_icc_node qns_apss;
142 static struct qcom_icc_node qss_cfg;
143 static struct qcom_icc_node qxs_boot_imem;
144 static struct qcom_icc_node qxs_imem;
145 static struct qcom_icc_node xs_pcie_0;
146 static struct qcom_icc_node xs_pcie_1;
147 static struct qcom_icc_node xs_pcie_2;
148 static struct qcom_icc_node xs_pcie_3;
149 static struct qcom_icc_node xs_pcie_4;
150 static struct qcom_icc_node xs_pcie_5;
151 static struct qcom_icc_node xs_pcie_6a;
152 static struct qcom_icc_node xs_pcie_6b;
153 static struct qcom_icc_node qns_gem_noc_cnoc;
154 static struct qcom_icc_node qns_llcc;
155 static struct qcom_icc_node qns_pcie;
156 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc;
157 static struct qcom_icc_node qns_lpass_aggnoc;
158 static struct qcom_icc_node qns_lpi_aon_noc;
159 static struct qcom_icc_node ebi;
160 static struct qcom_icc_node qns_mem_noc_hf;
161 static struct qcom_icc_node qns_mem_noc_sf;
162 static struct qcom_icc_node srvc_mnoc;
163 static struct qcom_icc_node qns_nsp_gemnoc;
164 static struct qcom_icc_node qns_pcie_mem_noc;
165 static struct qcom_icc_node qns_pcie_north_gem_noc;
166 static struct qcom_icc_node qns_pcie_south_gem_noc;
167 static struct qcom_icc_node qns_gemnoc_sf;
168 static struct qcom_icc_node qns_aggre_usb_snoc;
169 static struct qcom_icc_node qns_aggre_usb_north_snoc;
170 static struct qcom_icc_node qns_aggre_usb_south_snoc;
171
172 static struct qcom_icc_node qhm_qspi = {
173 .name = "qhm_qspi",
174 .channels = 1,
175 .buswidth = 4,
176 .num_links = 1,
177 .link_nodes = { &qns_a1noc_snoc },
178 };
179
180 static struct qcom_icc_node qhm_qup1 = {
181 .name = "qhm_qup1",
182 .channels = 1,
183 .buswidth = 4,
184 .num_links = 1,
185 .link_nodes = { &qns_a1noc_snoc },
186 };
187
188 static struct qcom_icc_node xm_sdc4 = {
189 .name = "xm_sdc4",
190 .channels = 1,
191 .buswidth = 8,
192 .num_links = 1,
193 .link_nodes = { &qns_a1noc_snoc },
194 };
195
196 static struct qcom_icc_node xm_ufs_mem = {
197 .name = "xm_ufs_mem",
198 .channels = 1,
199 .buswidth = 16,
200 .num_links = 1,
201 .link_nodes = { &qns_a1noc_snoc },
202 };
203
204 static struct qcom_icc_node qhm_qup0 = {
205 .name = "qhm_qup0",
206 .channels = 1,
207 .buswidth = 4,
208 .num_links = 1,
209 .link_nodes = { &qns_a2noc_snoc },
210 };
211
212 static struct qcom_icc_node qhm_qup2 = {
213 .name = "qhm_qup2",
214 .channels = 1,
215 .buswidth = 4,
216 .num_links = 1,
217 .link_nodes = { &qns_a2noc_snoc },
218 };
219
220 static struct qcom_icc_node qxm_crypto = {
221 .name = "qxm_crypto",
222 .channels = 1,
223 .buswidth = 8,
224 .num_links = 1,
225 .link_nodes = { &qns_a2noc_snoc },
226 };
227
228 static struct qcom_icc_node qxm_sp = {
229 .name = "qxm_sp",
230 .channels = 1,
231 .buswidth = 8,
232 .num_links = 1,
233 .link_nodes = { &qns_a2noc_snoc },
234 };
235
236 static struct qcom_icc_node xm_qdss_etr_0 = {
237 .name = "xm_qdss_etr_0",
238 .channels = 1,
239 .buswidth = 8,
240 .num_links = 1,
241 .link_nodes = { &qns_a2noc_snoc },
242 };
243
244 static struct qcom_icc_node xm_qdss_etr_1 = {
245 .name = "xm_qdss_etr_1",
246 .channels = 1,
247 .buswidth = 8,
248 .num_links = 1,
249 .link_nodes = { &qns_a2noc_snoc },
250 };
251
252 static struct qcom_icc_node xm_sdc2 = {
253 .name = "xm_sdc2",
254 .channels = 1,
255 .buswidth = 8,
256 .num_links = 1,
257 .link_nodes = { &qns_a2noc_snoc },
258 };
259
260 static struct qcom_icc_node qup0_core_master = {
261 .name = "qup0_core_master",
262 .channels = 1,
263 .buswidth = 4,
264 .num_links = 1,
265 .link_nodes = { &qup0_core_slave },
266 };
267
268 static struct qcom_icc_node qup1_core_master = {
269 .name = "qup1_core_master",
270 .channels = 1,
271 .buswidth = 4,
272 .num_links = 1,
273 .link_nodes = { &qup1_core_slave },
274 };
275
276 static struct qcom_icc_node qup2_core_master = {
277 .name = "qup2_core_master",
278 .channels = 1,
279 .buswidth = 4,
280 .num_links = 1,
281 .link_nodes = { &qup2_core_slave },
282 };
283
284 static struct qcom_icc_node qsm_cfg = {
285 .name = "qsm_cfg",
286 .channels = 1,
287 .buswidth = 4,
288 .num_links = 47,
289 .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
290 &qhs_ahb2phy2, &qhs_av1_enc_cfg,
291 &qhs_camera_cfg, &qhs_clk_ctl,
292 &qhs_crypto0_cfg, &qhs_display_cfg,
293 &qhs_gpuss_cfg, &qhs_imem_cfg,
294 &qhs_ipc_router, &qhs_pcie0_cfg,
295 &qhs_pcie1_cfg, &qhs_pcie2_cfg,
296 &qhs_pcie3_cfg, &qhs_pcie4_cfg,
297 &qhs_pcie5_cfg, &qhs_pcie6a_cfg,
298 &qhs_pcie6b_cfg, &qhs_pcie_rsc_cfg,
299 &qhs_pdm, &qhs_prng,
300 &qhs_qdss_cfg, &qhs_qspi,
301 &qhs_qup0, &qhs_qup1,
302 &qhs_qup2, &qhs_sdc2,
303 &qhs_sdc4, &qhs_smmuv3_cfg,
304 &qhs_tcsr, &qhs_tlmm,
305 &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg,
306 &qhs_usb3_0_cfg, &qhs_usb3_1_cfg,
307 &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg,
308 &qhs_usb4_0_cfg, &qhs_usb4_1_cfg,
309 &qhs_usb4_2_cfg, &qhs_venus_cfg,
310 &qss_lpass_qtb_cfg, &qss_mnoc_cfg,
311 &qss_nsp_qtb_cfg, &xs_qdss_stm,
312 &xs_sys_tcu_cfg },
313 };
314
315 static struct qcom_icc_node qnm_gemnoc_cnoc = {
316 .name = "qnm_gemnoc_cnoc",
317 .channels = 1,
318 .buswidth = 16,
319 .num_links = 6,
320 .link_nodes = { &qhs_aoss, &qhs_tme_cfg,
321 &qns_apss, &qss_cfg,
322 &qxs_boot_imem, &qxs_imem },
323 };
324
325 static struct qcom_icc_node qnm_gemnoc_pcie = {
326 .name = "qnm_gemnoc_pcie",
327 .channels = 1,
328 .buswidth = 32,
329 .num_links = 8,
330 .link_nodes = { &xs_pcie_0, &xs_pcie_1,
331 &xs_pcie_2, &xs_pcie_3,
332 &xs_pcie_4, &xs_pcie_5,
333 &xs_pcie_6a, &xs_pcie_6b },
334 };
335
336 static struct qcom_icc_node alm_gpu_tcu = {
337 .name = "alm_gpu_tcu",
338 .channels = 1,
339 .buswidth = 8,
340 .num_links = 2,
341 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
342 };
343
344 static struct qcom_icc_node alm_pcie_tcu = {
345 .name = "alm_pcie_tcu",
346 .channels = 1,
347 .buswidth = 8,
348 .num_links = 2,
349 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
350 };
351
352 static struct qcom_icc_node alm_sys_tcu = {
353 .name = "alm_sys_tcu",
354 .channels = 1,
355 .buswidth = 8,
356 .num_links = 2,
357 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
358 };
359
360 static struct qcom_icc_node chm_apps = {
361 .name = "chm_apps",
362 .channels = 6,
363 .buswidth = 32,
364 .num_links = 3,
365 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
366 &qns_pcie },
367 };
368
369 static struct qcom_icc_node qnm_gpu = {
370 .name = "qnm_gpu",
371 .channels = 4,
372 .buswidth = 32,
373 .num_links = 2,
374 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
375 };
376
377 static struct qcom_icc_node qnm_lpass = {
378 .name = "qnm_lpass",
379 .channels = 1,
380 .buswidth = 16,
381 .num_links = 3,
382 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
383 &qns_pcie },
384 };
385
386 static struct qcom_icc_node qnm_mnoc_hf = {
387 .name = "qnm_mnoc_hf",
388 .channels = 2,
389 .buswidth = 32,
390 .num_links = 2,
391 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
392 };
393
394 static struct qcom_icc_node qnm_mnoc_sf = {
395 .name = "qnm_mnoc_sf",
396 .channels = 2,
397 .buswidth = 32,
398 .num_links = 2,
399 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
400 };
401
402 static struct qcom_icc_node qnm_nsp_noc = {
403 .name = "qnm_nsp_noc",
404 .channels = 2,
405 .buswidth = 32,
406 .num_links = 3,
407 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
408 &qns_pcie },
409 };
410
411 static struct qcom_icc_node qnm_pcie = {
412 .name = "qnm_pcie",
413 .channels = 1,
414 .buswidth = 64,
415 .num_links = 2,
416 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
417 };
418
419 static struct qcom_icc_node qnm_snoc_sf = {
420 .name = "qnm_snoc_sf",
421 .channels = 1,
422 .buswidth = 64,
423 .num_links = 3,
424 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
425 &qns_pcie },
426 };
427
428 static struct qcom_icc_node xm_gic = {
429 .name = "xm_gic",
430 .channels = 1,
431 .buswidth = 8,
432 .num_links = 1,
433 .link_nodes = { &qns_llcc },
434 };
435
436 static struct qcom_icc_node qnm_lpiaon_noc = {
437 .name = "qnm_lpiaon_noc",
438 .channels = 1,
439 .buswidth = 16,
440 .num_links = 1,
441 .link_nodes = { &qns_lpass_ag_noc_gemnoc },
442 };
443
444 static struct qcom_icc_node qnm_lpass_lpinoc = {
445 .name = "qnm_lpass_lpinoc",
446 .channels = 1,
447 .buswidth = 16,
448 .num_links = 1,
449 .link_nodes = { &qns_lpass_aggnoc },
450 };
451
452 static struct qcom_icc_node qxm_lpinoc_dsp_axim = {
453 .name = "qxm_lpinoc_dsp_axim",
454 .channels = 1,
455 .buswidth = 16,
456 .num_links = 1,
457 .link_nodes = { &qns_lpi_aon_noc },
458 };
459
460 static struct qcom_icc_node llcc_mc = {
461 .name = "llcc_mc",
462 .channels = 8,
463 .buswidth = 4,
464 .num_links = 1,
465 .link_nodes = { &ebi },
466 };
467
468 static struct qcom_icc_node qnm_av1_enc = {
469 .name = "qnm_av1_enc",
470 .channels = 1,
471 .buswidth = 32,
472 .num_links = 1,
473 .link_nodes = { &qns_mem_noc_sf },
474 };
475
476 static struct qcom_icc_node qnm_camnoc_hf = {
477 .name = "qnm_camnoc_hf",
478 .channels = 2,
479 .buswidth = 32,
480 .num_links = 1,
481 .link_nodes = { &qns_mem_noc_hf },
482 };
483
484 static struct qcom_icc_node qnm_camnoc_icp = {
485 .name = "qnm_camnoc_icp",
486 .channels = 1,
487 .buswidth = 8,
488 .num_links = 1,
489 .link_nodes = { &qns_mem_noc_sf },
490 };
491
492 static struct qcom_icc_node qnm_camnoc_sf = {
493 .name = "qnm_camnoc_sf",
494 .channels = 2,
495 .buswidth = 32,
496 .num_links = 1,
497 .link_nodes = { &qns_mem_noc_sf },
498 };
499
500 static struct qcom_icc_node qnm_eva = {
501 .name = "qnm_eva",
502 .channels = 1,
503 .buswidth = 32,
504 .num_links = 1,
505 .link_nodes = { &qns_mem_noc_sf },
506 };
507
508 static struct qcom_icc_node qnm_mdp = {
509 .name = "qnm_mdp",
510 .channels = 2,
511 .buswidth = 32,
512 .num_links = 1,
513 .link_nodes = { &qns_mem_noc_hf },
514 };
515
516 static struct qcom_icc_node qnm_video = {
517 .name = "qnm_video",
518 .channels = 2,
519 .buswidth = 32,
520 .num_links = 1,
521 .link_nodes = { &qns_mem_noc_sf },
522 };
523
524 static struct qcom_icc_node qnm_video_cv_cpu = {
525 .name = "qnm_video_cv_cpu",
526 .channels = 1,
527 .buswidth = 8,
528 .num_links = 1,
529 .link_nodes = { &qns_mem_noc_sf },
530 };
531
532 static struct qcom_icc_node qnm_video_v_cpu = {
533 .name = "qnm_video_v_cpu",
534 .channels = 1,
535 .buswidth = 8,
536 .num_links = 1,
537 .link_nodes = { &qns_mem_noc_sf },
538 };
539
540 static struct qcom_icc_node qsm_mnoc_cfg = {
541 .name = "qsm_mnoc_cfg",
542 .channels = 1,
543 .buswidth = 4,
544 .num_links = 1,
545 .link_nodes = { &srvc_mnoc },
546 };
547
548 static struct qcom_icc_node qxm_nsp = {
549 .name = "qxm_nsp",
550 .channels = 2,
551 .buswidth = 32,
552 .num_links = 1,
553 .link_nodes = { &qns_nsp_gemnoc },
554 };
555
556 static struct qcom_icc_node qnm_pcie_north_gem_noc = {
557 .name = "qnm_pcie_north_gem_noc",
558 .channels = 1,
559 .buswidth = 64,
560 .num_links = 1,
561 .link_nodes = { &qns_pcie_mem_noc },
562 };
563
564 static struct qcom_icc_node qnm_pcie_south_gem_noc = {
565 .name = "qnm_pcie_south_gem_noc",
566 .channels = 1,
567 .buswidth = 64,
568 .num_links = 1,
569 .link_nodes = { &qns_pcie_mem_noc },
570 };
571
572 static struct qcom_icc_node xm_pcie_3 = {
573 .name = "xm_pcie_3",
574 .channels = 1,
575 .buswidth = 64,
576 .num_links = 1,
577 .link_nodes = { &qns_pcie_north_gem_noc },
578 };
579
580 static struct qcom_icc_node xm_pcie_4 = {
581 .name = "xm_pcie_4",
582 .channels = 1,
583 .buswidth = 8,
584 .num_links = 1,
585 .link_nodes = { &qns_pcie_north_gem_noc },
586 };
587
588 static struct qcom_icc_node xm_pcie_5 = {
589 .name = "xm_pcie_5",
590 .channels = 1,
591 .buswidth = 8,
592 .num_links = 1,
593 .link_nodes = { &qns_pcie_north_gem_noc },
594 };
595
596 static struct qcom_icc_node xm_pcie_0 = {
597 .name = "xm_pcie_0",
598 .channels = 1,
599 .buswidth = 16,
600 .num_links = 1,
601 .link_nodes = { &qns_pcie_south_gem_noc },
602 };
603
604 static struct qcom_icc_node xm_pcie_1 = {
605 .name = "xm_pcie_1",
606 .channels = 1,
607 .buswidth = 16,
608 .num_links = 1,
609 .link_nodes = { &qns_pcie_south_gem_noc },
610 };
611
612 static struct qcom_icc_node xm_pcie_2 = {
613 .name = "xm_pcie_2",
614 .channels = 1,
615 .buswidth = 16,
616 .num_links = 1,
617 .link_nodes = { &qns_pcie_south_gem_noc },
618 };
619
620 static struct qcom_icc_node xm_pcie_6a = {
621 .name = "xm_pcie_6a",
622 .channels = 1,
623 .buswidth = 32,
624 .num_links = 1,
625 .link_nodes = { &qns_pcie_south_gem_noc },
626 };
627
628 static struct qcom_icc_node xm_pcie_6b = {
629 .name = "xm_pcie_6b",
630 .channels = 1,
631 .buswidth = 16,
632 .num_links = 1,
633 .link_nodes = { &qns_pcie_south_gem_noc },
634 };
635
636 static struct qcom_icc_node qnm_aggre1_noc = {
637 .name = "qnm_aggre1_noc",
638 .channels = 1,
639 .buswidth = 16,
640 .num_links = 1,
641 .link_nodes = { &qns_gemnoc_sf },
642 };
643
644 static struct qcom_icc_node qnm_aggre2_noc = {
645 .name = "qnm_aggre2_noc",
646 .channels = 1,
647 .buswidth = 16,
648 .num_links = 1,
649 .link_nodes = { &qns_gemnoc_sf },
650 };
651
652 static struct qcom_icc_node qnm_gic = {
653 .name = "qnm_gic",
654 .channels = 1,
655 .buswidth = 8,
656 .num_links = 1,
657 .link_nodes = { &qns_gemnoc_sf },
658 };
659
660 static struct qcom_icc_node qnm_usb_anoc = {
661 .name = "qnm_usb_anoc",
662 .channels = 1,
663 .buswidth = 64,
664 .num_links = 1,
665 .link_nodes = { &qns_gemnoc_sf },
666 };
667
668 static struct qcom_icc_node qnm_aggre_usb_north_snoc = {
669 .name = "qnm_aggre_usb_north_snoc",
670 .channels = 1,
671 .buswidth = 64,
672 .num_links = 1,
673 .link_nodes = { &qns_aggre_usb_snoc },
674 };
675
676 static struct qcom_icc_node qnm_aggre_usb_south_snoc = {
677 .name = "qnm_aggre_usb_south_snoc",
678 .channels = 1,
679 .buswidth = 64,
680 .num_links = 1,
681 .link_nodes = { &qns_aggre_usb_snoc },
682 };
683
684 static struct qcom_icc_node xm_usb2_0 = {
685 .name = "xm_usb2_0",
686 .channels = 1,
687 .buswidth = 8,
688 .num_links = 1,
689 .link_nodes = { &qns_aggre_usb_north_snoc },
690 };
691
692 static struct qcom_icc_node xm_usb3_mp = {
693 .name = "xm_usb3_mp",
694 .channels = 1,
695 .buswidth = 16,
696 .num_links = 1,
697 .link_nodes = { &qns_aggre_usb_north_snoc },
698 };
699
700 static struct qcom_icc_node xm_usb3_0 = {
701 .name = "xm_usb3_0",
702 .channels = 1,
703 .buswidth = 8,
704 .num_links = 1,
705 .link_nodes = { &qns_aggre_usb_south_snoc },
706 };
707
708 static struct qcom_icc_node xm_usb3_1 = {
709 .name = "xm_usb3_1",
710 .channels = 1,
711 .buswidth = 8,
712 .num_links = 1,
713 .link_nodes = { &qns_aggre_usb_south_snoc },
714 };
715
716 static struct qcom_icc_node xm_usb3_2 = {
717 .name = "xm_usb3_2",
718 .channels = 1,
719 .buswidth = 8,
720 .num_links = 1,
721 .link_nodes = { &qns_aggre_usb_south_snoc },
722 };
723
724 static struct qcom_icc_node xm_usb4_0 = {
725 .name = "xm_usb4_0",
726 .channels = 1,
727 .buswidth = 16,
728 .num_links = 1,
729 .link_nodes = { &qns_aggre_usb_south_snoc },
730 };
731
732 static struct qcom_icc_node xm_usb4_1 = {
733 .name = "xm_usb4_1",
734 .channels = 1,
735 .buswidth = 16,
736 .num_links = 1,
737 .link_nodes = { &qns_aggre_usb_south_snoc },
738 };
739
740 static struct qcom_icc_node xm_usb4_2 = {
741 .name = "xm_usb4_2",
742 .channels = 1,
743 .buswidth = 16,
744 .num_links = 1,
745 .link_nodes = { &qns_aggre_usb_south_snoc },
746 };
747
748 static struct qcom_icc_node qns_a1noc_snoc = {
749 .name = "qns_a1noc_snoc",
750 .channels = 1,
751 .buswidth = 16,
752 .num_links = 1,
753 .link_nodes = { &qnm_aggre1_noc },
754 };
755
756 static struct qcom_icc_node qns_a2noc_snoc = {
757 .name = "qns_a2noc_snoc",
758 .channels = 1,
759 .buswidth = 16,
760 .num_links = 1,
761 .link_nodes = { &qnm_aggre2_noc },
762 };
763
764 static struct qcom_icc_node qup0_core_slave = {
765 .name = "qup0_core_slave",
766 .channels = 1,
767 .buswidth = 4,
768 };
769
770 static struct qcom_icc_node qup1_core_slave = {
771 .name = "qup1_core_slave",
772 .channels = 1,
773 .buswidth = 4,
774 };
775
776 static struct qcom_icc_node qup2_core_slave = {
777 .name = "qup2_core_slave",
778 .channels = 1,
779 .buswidth = 4,
780 };
781
782 static struct qcom_icc_node qhs_ahb2phy0 = {
783 .name = "qhs_ahb2phy0",
784 .channels = 1,
785 .buswidth = 4,
786 };
787
788 static struct qcom_icc_node qhs_ahb2phy1 = {
789 .name = "qhs_ahb2phy1",
790 .channels = 1,
791 .buswidth = 4,
792 };
793
794 static struct qcom_icc_node qhs_ahb2phy2 = {
795 .name = "qhs_ahb2phy2",
796 .channels = 1,
797 .buswidth = 4,
798 };
799
800 static struct qcom_icc_node qhs_av1_enc_cfg = {
801 .name = "qhs_av1_enc_cfg",
802 .channels = 1,
803 .buswidth = 4,
804 };
805
806 static struct qcom_icc_node qhs_camera_cfg = {
807 .name = "qhs_camera_cfg",
808 .channels = 1,
809 .buswidth = 4,
810 };
811
812 static struct qcom_icc_node qhs_clk_ctl = {
813 .name = "qhs_clk_ctl",
814 .channels = 1,
815 .buswidth = 4,
816 };
817
818 static struct qcom_icc_node qhs_crypto0_cfg = {
819 .name = "qhs_crypto0_cfg",
820 .channels = 1,
821 .buswidth = 4,
822 };
823
824 static struct qcom_icc_node qhs_display_cfg = {
825 .name = "qhs_display_cfg",
826 .channels = 1,
827 .buswidth = 4,
828 };
829
830 static struct qcom_icc_node qhs_gpuss_cfg = {
831 .name = "qhs_gpuss_cfg",
832 .channels = 1,
833 .buswidth = 8,
834 };
835
836 static struct qcom_icc_node qhs_imem_cfg = {
837 .name = "qhs_imem_cfg",
838 .channels = 1,
839 .buswidth = 4,
840 };
841
842 static struct qcom_icc_node qhs_ipc_router = {
843 .name = "qhs_ipc_router",
844 .channels = 1,
845 .buswidth = 4,
846 };
847
848 static struct qcom_icc_node qhs_pcie0_cfg = {
849 .name = "qhs_pcie0_cfg",
850 .channels = 1,
851 .buswidth = 4,
852 };
853
854 static struct qcom_icc_node qhs_pcie1_cfg = {
855 .name = "qhs_pcie1_cfg",
856 .channels = 1,
857 .buswidth = 4,
858 };
859
860 static struct qcom_icc_node qhs_pcie2_cfg = {
861 .name = "qhs_pcie2_cfg",
862 .channels = 1,
863 .buswidth = 4,
864 };
865
866 static struct qcom_icc_node qhs_pcie3_cfg = {
867 .name = "qhs_pcie3_cfg",
868 .channels = 1,
869 .buswidth = 4,
870 };
871
872 static struct qcom_icc_node qhs_pcie4_cfg = {
873 .name = "qhs_pcie4_cfg",
874 .channels = 1,
875 .buswidth = 4,
876 };
877
878 static struct qcom_icc_node qhs_pcie5_cfg = {
879 .name = "qhs_pcie5_cfg",
880 .channels = 1,
881 .buswidth = 4,
882 };
883
884 static struct qcom_icc_node qhs_pcie6a_cfg = {
885 .name = "qhs_pcie6a_cfg",
886 .channels = 1,
887 .buswidth = 4,
888 };
889
890 static struct qcom_icc_node qhs_pcie6b_cfg = {
891 .name = "qhs_pcie6b_cfg",
892 .channels = 1,
893 .buswidth = 4,
894 };
895
896 static struct qcom_icc_node qhs_pcie_rsc_cfg = {
897 .name = "qhs_pcie_rsc_cfg",
898 .channels = 1,
899 .buswidth = 4,
900 };
901
902 static struct qcom_icc_node qhs_pdm = {
903 .name = "qhs_pdm",
904 .channels = 1,
905 .buswidth = 4,
906 };
907
908 static struct qcom_icc_node qhs_prng = {
909 .name = "qhs_prng",
910 .channels = 1,
911 .buswidth = 4,
912 };
913
914 static struct qcom_icc_node qhs_qdss_cfg = {
915 .name = "qhs_qdss_cfg",
916 .channels = 1,
917 .buswidth = 4,
918 };
919
920 static struct qcom_icc_node qhs_qspi = {
921 .name = "qhs_qspi",
922 .channels = 1,
923 .buswidth = 4,
924 };
925
926 static struct qcom_icc_node qhs_qup0 = {
927 .name = "qhs_qup0",
928 .channels = 1,
929 .buswidth = 4,
930 };
931
932 static struct qcom_icc_node qhs_qup1 = {
933 .name = "qhs_qup1",
934 .channels = 1,
935 .buswidth = 4,
936 };
937
938 static struct qcom_icc_node qhs_qup2 = {
939 .name = "qhs_qup2",
940 .channels = 1,
941 .buswidth = 4,
942 };
943
944 static struct qcom_icc_node qhs_sdc2 = {
945 .name = "qhs_sdc2",
946 .channels = 1,
947 .buswidth = 4,
948 };
949
950 static struct qcom_icc_node qhs_sdc4 = {
951 .name = "qhs_sdc4",
952 .channels = 1,
953 .buswidth = 4,
954 };
955
956 static struct qcom_icc_node qhs_smmuv3_cfg = {
957 .name = "qhs_smmuv3_cfg",
958 .channels = 1,
959 .buswidth = 8,
960 };
961
962 static struct qcom_icc_node qhs_tcsr = {
963 .name = "qhs_tcsr",
964 .channels = 1,
965 .buswidth = 4,
966 };
967
968 static struct qcom_icc_node qhs_tlmm = {
969 .name = "qhs_tlmm",
970 .channels = 1,
971 .buswidth = 4,
972 };
973
974 static struct qcom_icc_node qhs_ufs_mem_cfg = {
975 .name = "qhs_ufs_mem_cfg",
976 .channels = 1,
977 .buswidth = 4,
978 };
979
980 static struct qcom_icc_node qhs_usb2_0_cfg = {
981 .name = "qhs_usb2_0_cfg",
982 .channels = 1,
983 .buswidth = 4,
984 };
985
986 static struct qcom_icc_node qhs_usb3_0_cfg = {
987 .name = "qhs_usb3_0_cfg",
988 .channels = 1,
989 .buswidth = 4,
990 };
991
992 static struct qcom_icc_node qhs_usb3_1_cfg = {
993 .name = "qhs_usb3_1_cfg",
994 .channels = 1,
995 .buswidth = 4,
996 };
997
998 static struct qcom_icc_node qhs_usb3_2_cfg = {
999 .name = "qhs_usb3_2_cfg",
1000 .channels = 1,
1001 .buswidth = 4,
1002 };
1003
1004 static struct qcom_icc_node qhs_usb3_mp_cfg = {
1005 .name = "qhs_usb3_mp_cfg",
1006 .channels = 1,
1007 .buswidth = 4,
1008 };
1009
1010 static struct qcom_icc_node qhs_usb4_0_cfg = {
1011 .name = "qhs_usb4_0_cfg",
1012 .channels = 1,
1013 .buswidth = 4,
1014 };
1015
1016 static struct qcom_icc_node qhs_usb4_1_cfg = {
1017 .name = "qhs_usb4_1_cfg",
1018 .channels = 1,
1019 .buswidth = 4,
1020 };
1021
1022 static struct qcom_icc_node qhs_usb4_2_cfg = {
1023 .name = "qhs_usb4_2_cfg",
1024 .channels = 1,
1025 .buswidth = 4,
1026 };
1027
1028 static struct qcom_icc_node qhs_venus_cfg = {
1029 .name = "qhs_venus_cfg",
1030 .channels = 1,
1031 .buswidth = 4,
1032 };
1033
1034 static struct qcom_icc_node qss_lpass_qtb_cfg = {
1035 .name = "qss_lpass_qtb_cfg",
1036 .channels = 1,
1037 .buswidth = 4,
1038 };
1039
1040 static struct qcom_icc_node qss_mnoc_cfg = {
1041 .name = "qss_mnoc_cfg",
1042 .channels = 1,
1043 .buswidth = 4,
1044 .num_links = 1,
1045 .link_nodes = { &qsm_mnoc_cfg },
1046 };
1047
1048 static struct qcom_icc_node qss_nsp_qtb_cfg = {
1049 .name = "qss_nsp_qtb_cfg",
1050 .channels = 1,
1051 .buswidth = 4,
1052 };
1053
1054 static struct qcom_icc_node xs_qdss_stm = {
1055 .name = "xs_qdss_stm",
1056 .channels = 1,
1057 .buswidth = 4,
1058 };
1059
1060 static struct qcom_icc_node xs_sys_tcu_cfg = {
1061 .name = "xs_sys_tcu_cfg",
1062 .channels = 1,
1063 .buswidth = 8,
1064 };
1065
1066 static struct qcom_icc_node qhs_aoss = {
1067 .name = "qhs_aoss",
1068 .channels = 1,
1069 .buswidth = 4,
1070 };
1071
1072 static struct qcom_icc_node qhs_tme_cfg = {
1073 .name = "qhs_tme_cfg",
1074 .channels = 1,
1075 .buswidth = 4,
1076 };
1077
1078 static struct qcom_icc_node qns_apss = {
1079 .name = "qns_apss",
1080 .channels = 1,
1081 .buswidth = 8,
1082 };
1083
1084 static struct qcom_icc_node qss_cfg = {
1085 .name = "qss_cfg",
1086 .channels = 1,
1087 .buswidth = 4,
1088 .num_links = 1,
1089 .link_nodes = { &qsm_cfg },
1090 };
1091
1092 static struct qcom_icc_node qxs_boot_imem = {
1093 .name = "qxs_boot_imem",
1094 .channels = 1,
1095 .buswidth = 16,
1096 };
1097
1098 static struct qcom_icc_node qxs_imem = {
1099 .name = "qxs_imem",
1100 .channels = 1,
1101 .buswidth = 8,
1102 };
1103
1104 static struct qcom_icc_node xs_pcie_0 = {
1105 .name = "xs_pcie_0",
1106 .channels = 1,
1107 .buswidth = 16,
1108 };
1109
1110 static struct qcom_icc_node xs_pcie_1 = {
1111 .name = "xs_pcie_1",
1112 .channels = 1,
1113 .buswidth = 16,
1114 };
1115
1116 static struct qcom_icc_node xs_pcie_2 = {
1117 .name = "xs_pcie_2",
1118 .channels = 1,
1119 .buswidth = 16,
1120 };
1121
1122 static struct qcom_icc_node xs_pcie_3 = {
1123 .name = "xs_pcie_3",
1124 .channels = 1,
1125 .buswidth = 64,
1126 };
1127
1128 static struct qcom_icc_node xs_pcie_4 = {
1129 .name = "xs_pcie_4",
1130 .channels = 1,
1131 .buswidth = 8,
1132 };
1133
1134 static struct qcom_icc_node xs_pcie_5 = {
1135 .name = "xs_pcie_5",
1136 .channels = 1,
1137 .buswidth = 8,
1138 };
1139
1140 static struct qcom_icc_node xs_pcie_6a = {
1141 .name = "xs_pcie_6a",
1142 .channels = 1,
1143 .buswidth = 32,
1144 };
1145
1146 static struct qcom_icc_node xs_pcie_6b = {
1147 .name = "xs_pcie_6b",
1148 .channels = 1,
1149 .buswidth = 16,
1150 };
1151
1152 static struct qcom_icc_node qns_gem_noc_cnoc = {
1153 .name = "qns_gem_noc_cnoc",
1154 .channels = 1,
1155 .buswidth = 16,
1156 .num_links = 1,
1157 .link_nodes = { &qnm_gemnoc_cnoc },
1158 };
1159
1160 static struct qcom_icc_node qns_llcc = {
1161 .name = "qns_llcc",
1162 .channels = 8,
1163 .buswidth = 16,
1164 .num_links = 1,
1165 .link_nodes = { &llcc_mc },
1166 };
1167
1168 static struct qcom_icc_node qns_pcie = {
1169 .name = "qns_pcie",
1170 .channels = 1,
1171 .buswidth = 32,
1172 .num_links = 1,
1173 .link_nodes = { &qnm_gemnoc_pcie },
1174 };
1175
1176 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
1177 .name = "qns_lpass_ag_noc_gemnoc",
1178 .channels = 1,
1179 .buswidth = 16,
1180 .num_links = 1,
1181 .link_nodes = { &qnm_lpass },
1182 };
1183
1184 static struct qcom_icc_node qns_lpass_aggnoc = {
1185 .name = "qns_lpass_aggnoc",
1186 .channels = 1,
1187 .buswidth = 16,
1188 .num_links = 1,
1189 .link_nodes = { &qnm_lpiaon_noc },
1190 };
1191
1192 static struct qcom_icc_node qns_lpi_aon_noc = {
1193 .name = "qns_lpi_aon_noc",
1194 .channels = 1,
1195 .buswidth = 16,
1196 .num_links = 1,
1197 .link_nodes = { &qnm_lpass_lpinoc },
1198 };
1199
1200 static struct qcom_icc_node ebi = {
1201 .name = "ebi",
1202 .channels = 8,
1203 .buswidth = 4,
1204 };
1205
1206 static struct qcom_icc_node qns_mem_noc_hf = {
1207 .name = "qns_mem_noc_hf",
1208 .channels = 2,
1209 .buswidth = 32,
1210 .num_links = 1,
1211 .link_nodes = { &qnm_mnoc_hf },
1212 };
1213
1214 static struct qcom_icc_node qns_mem_noc_sf = {
1215 .name = "qns_mem_noc_sf",
1216 .channels = 2,
1217 .buswidth = 32,
1218 .num_links = 1,
1219 .link_nodes = { &qnm_mnoc_sf },
1220 };
1221
1222 static struct qcom_icc_node srvc_mnoc = {
1223 .name = "srvc_mnoc",
1224 .channels = 1,
1225 .buswidth = 4,
1226 };
1227
1228 static struct qcom_icc_node qns_nsp_gemnoc = {
1229 .name = "qns_nsp_gemnoc",
1230 .channels = 2,
1231 .buswidth = 32,
1232 .num_links = 1,
1233 .link_nodes = { &qnm_nsp_noc },
1234 };
1235
1236 static struct qcom_icc_node qns_pcie_mem_noc = {
1237 .name = "qns_pcie_mem_noc",
1238 .channels = 1,
1239 .buswidth = 64,
1240 .num_links = 1,
1241 .link_nodes = { &qnm_pcie },
1242 };
1243
1244 static struct qcom_icc_node qns_pcie_north_gem_noc = {
1245 .name = "qns_pcie_north_gem_noc",
1246 .channels = 1,
1247 .buswidth = 64,
1248 .num_links = 1,
1249 .link_nodes = { &qnm_pcie_north_gem_noc },
1250 };
1251
1252 static struct qcom_icc_node qns_pcie_south_gem_noc = {
1253 .name = "qns_pcie_south_gem_noc",
1254 .channels = 1,
1255 .buswidth = 64,
1256 .num_links = 1,
1257 .link_nodes = { &qnm_pcie_south_gem_noc },
1258 };
1259
1260 static struct qcom_icc_node qns_gemnoc_sf = {
1261 .name = "qns_gemnoc_sf",
1262 .channels = 1,
1263 .buswidth = 64,
1264 .num_links = 1,
1265 .link_nodes = { &qnm_snoc_sf },
1266 };
1267
1268 static struct qcom_icc_node qns_aggre_usb_snoc = {
1269 .name = "qns_aggre_usb_snoc",
1270 .channels = 1,
1271 .buswidth = 64,
1272 .num_links = 1,
1273 .link_nodes = { &qnm_usb_anoc },
1274 };
1275
1276 static struct qcom_icc_node qns_aggre_usb_north_snoc = {
1277 .name = "qns_aggre_usb_north_snoc",
1278 .channels = 1,
1279 .buswidth = 64,
1280 .num_links = 1,
1281 .link_nodes = { &qnm_aggre_usb_north_snoc },
1282 };
1283
1284 static struct qcom_icc_node qns_aggre_usb_south_snoc = {
1285 .name = "qns_aggre_usb_south_snoc",
1286 .channels = 1,
1287 .buswidth = 64,
1288 .num_links = 1,
1289 .link_nodes = { &qnm_aggre_usb_south_snoc },
1290 };
1291
1292 static struct qcom_icc_bcm bcm_acv = {
1293 .name = "ACV",
1294 .enable_mask = BIT(3),
1295 .num_nodes = 1,
1296 .nodes = { &ebi },
1297 };
1298
1299 static struct qcom_icc_bcm bcm_ce0 = {
1300 .name = "CE0",
1301 .num_nodes = 1,
1302 .nodes = { &qxm_crypto },
1303 };
1304
1305 static struct qcom_icc_bcm bcm_cn0 = {
1306 .name = "CN0",
1307 .keepalive = true,
1308 .num_nodes = 63,
1309 .nodes = { &qsm_cfg, &qhs_ahb2phy0,
1310 &qhs_ahb2phy1, &qhs_ahb2phy2,
1311 &qhs_av1_enc_cfg, &qhs_camera_cfg,
1312 &qhs_clk_ctl, &qhs_crypto0_cfg,
1313 &qhs_gpuss_cfg, &qhs_imem_cfg,
1314 &qhs_ipc_router, &qhs_pcie0_cfg,
1315 &qhs_pcie1_cfg, &qhs_pcie2_cfg,
1316 &qhs_pcie3_cfg, &qhs_pcie4_cfg,
1317 &qhs_pcie5_cfg, &qhs_pcie6a_cfg,
1318 &qhs_pcie6b_cfg, &qhs_pcie_rsc_cfg,
1319 &qhs_pdm, &qhs_prng,
1320 &qhs_qdss_cfg, &qhs_qspi,
1321 &qhs_qup0, &qhs_qup1,
1322 &qhs_qup2, &qhs_sdc2,
1323 &qhs_sdc4, &qhs_smmuv3_cfg,
1324 &qhs_tcsr, &qhs_tlmm,
1325 &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg,
1326 &qhs_usb3_0_cfg, &qhs_usb3_1_cfg,
1327 &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg,
1328 &qhs_usb4_0_cfg, &qhs_usb4_1_cfg,
1329 &qhs_usb4_2_cfg, &qhs_venus_cfg,
1330 &qss_lpass_qtb_cfg, &qss_mnoc_cfg,
1331 &qss_nsp_qtb_cfg, &xs_qdss_stm,
1332 &xs_sys_tcu_cfg, &qnm_gemnoc_cnoc,
1333 &qnm_gemnoc_pcie, &qhs_aoss,
1334 &qhs_tme_cfg, &qns_apss,
1335 &qss_cfg, &qxs_boot_imem,
1336 &qxs_imem, &xs_pcie_0,
1337 &xs_pcie_1, &xs_pcie_2,
1338 &xs_pcie_3, &xs_pcie_4,
1339 &xs_pcie_5, &xs_pcie_6a,
1340 &xs_pcie_6b },
1341 };
1342
1343 static struct qcom_icc_bcm bcm_cn1 = {
1344 .name = "CN1",
1345 .num_nodes = 1,
1346 .nodes = { &qhs_display_cfg },
1347 };
1348
1349 static struct qcom_icc_bcm bcm_co0 = {
1350 .name = "CO0",
1351 .num_nodes = 2,
1352 .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
1353 };
1354
1355 static struct qcom_icc_bcm bcm_lp0 = {
1356 .name = "LP0",
1357 .num_nodes = 2,
1358 .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc },
1359 };
1360
1361 static struct qcom_icc_bcm bcm_mc0 = {
1362 .name = "MC0",
1363 .keepalive = true,
1364 .num_nodes = 1,
1365 .nodes = { &ebi },
1366 };
1367
1368 static struct qcom_icc_bcm bcm_mm0 = {
1369 .name = "MM0",
1370 .num_nodes = 1,
1371 .nodes = { &qns_mem_noc_hf },
1372 };
1373
1374 static struct qcom_icc_bcm bcm_mm1 = {
1375 .name = "MM1",
1376 .num_nodes = 10,
1377 .nodes = { &qnm_av1_enc, &qnm_camnoc_hf,
1378 &qnm_camnoc_icp, &qnm_camnoc_sf,
1379 &qnm_eva, &qnm_mdp,
1380 &qnm_video, &qnm_video_cv_cpu,
1381 &qnm_video_v_cpu, &qns_mem_noc_sf },
1382 };
1383
1384 static struct qcom_icc_bcm bcm_pc0 = {
1385 .name = "PC0",
1386 .num_nodes = 1,
1387 .nodes = { &qns_pcie_mem_noc },
1388 };
1389
1390 static struct qcom_icc_bcm bcm_qup0 = {
1391 .name = "QUP0",
1392 .keepalive = true,
1393 .vote_scale = 1,
1394 .num_nodes = 1,
1395 .nodes = { &qup0_core_slave },
1396 };
1397
1398 static struct qcom_icc_bcm bcm_qup1 = {
1399 .name = "QUP1",
1400 .keepalive = true,
1401 .vote_scale = 1,
1402 .num_nodes = 1,
1403 .nodes = { &qup1_core_slave },
1404 };
1405
1406 static struct qcom_icc_bcm bcm_qup2 = {
1407 .name = "QUP2",
1408 .keepalive = true,
1409 .vote_scale = 1,
1410 .num_nodes = 1,
1411 .nodes = { &qup2_core_slave },
1412 };
1413
1414 static struct qcom_icc_bcm bcm_sh0 = {
1415 .name = "SH0",
1416 .keepalive = true,
1417 .num_nodes = 1,
1418 .nodes = { &qns_llcc },
1419 };
1420
1421 static struct qcom_icc_bcm bcm_sh1 = {
1422 .name = "SH1",
1423 .num_nodes = 13,
1424 .nodes = { &alm_gpu_tcu, &alm_pcie_tcu,
1425 &alm_sys_tcu, &chm_apps,
1426 &qnm_gpu, &qnm_lpass,
1427 &qnm_mnoc_hf, &qnm_mnoc_sf,
1428 &qnm_nsp_noc, &qnm_pcie,
1429 &xm_gic, &qns_gem_noc_cnoc,
1430 &qns_pcie },
1431 };
1432
1433 static struct qcom_icc_bcm bcm_sn0 = {
1434 .name = "SN0",
1435 .keepalive = true,
1436 .num_nodes = 1,
1437 .nodes = { &qns_gemnoc_sf },
1438 };
1439
1440 static struct qcom_icc_bcm bcm_sn2 = {
1441 .name = "SN2",
1442 .num_nodes = 1,
1443 .nodes = { &qnm_aggre1_noc },
1444 };
1445
1446 static struct qcom_icc_bcm bcm_sn3 = {
1447 .name = "SN3",
1448 .num_nodes = 1,
1449 .nodes = { &qnm_aggre2_noc },
1450 };
1451
1452 static struct qcom_icc_bcm bcm_sn4 = {
1453 .name = "SN4",
1454 .num_nodes = 1,
1455 .nodes = { &qnm_usb_anoc },
1456 };
1457
1458 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1459 };
1460
1461 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1462 [MASTER_QSPI_0] = &qhm_qspi,
1463 [MASTER_QUP_1] = &qhm_qup1,
1464 [MASTER_SDCC_4] = &xm_sdc4,
1465 [MASTER_UFS_MEM] = &xm_ufs_mem,
1466 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1467 };
1468
1469 static const struct qcom_icc_desc x1e80100_aggre1_noc = {
1470 .nodes = aggre1_noc_nodes,
1471 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1472 .bcms = aggre1_noc_bcms,
1473 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1474 };
1475
1476 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1477 &bcm_ce0,
1478 };
1479
1480 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1481 [MASTER_QUP_0] = &qhm_qup0,
1482 [MASTER_QUP_2] = &qhm_qup2,
1483 [MASTER_CRYPTO] = &qxm_crypto,
1484 [MASTER_SP] = &qxm_sp,
1485 [MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1486 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1487 [MASTER_SDCC_2] = &xm_sdc2,
1488 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1489 };
1490
1491 static const struct qcom_icc_desc x1e80100_aggre2_noc = {
1492 .nodes = aggre2_noc_nodes,
1493 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1494 .bcms = aggre2_noc_bcms,
1495 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1496 };
1497
1498 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1499 &bcm_qup0,
1500 &bcm_qup1,
1501 &bcm_qup2,
1502 };
1503
1504 static struct qcom_icc_node * const clk_virt_nodes[] = {
1505 [MASTER_QUP_CORE_0] = &qup0_core_master,
1506 [MASTER_QUP_CORE_1] = &qup1_core_master,
1507 [MASTER_QUP_CORE_2] = &qup2_core_master,
1508 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1509 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1510 [SLAVE_QUP_CORE_2] = &qup2_core_slave,
1511 };
1512
1513 static const struct qcom_icc_desc x1e80100_clk_virt = {
1514 .nodes = clk_virt_nodes,
1515 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1516 .bcms = clk_virt_bcms,
1517 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1518 };
1519
1520 static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = {
1521 &bcm_cn0,
1522 &bcm_cn1,
1523 };
1524
1525 static struct qcom_icc_node * const cnoc_cfg_nodes[] = {
1526 [MASTER_CNOC_CFG] = &qsm_cfg,
1527 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1528 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1529 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
1530 [SLAVE_AV1_ENC_CFG] = &qhs_av1_enc_cfg,
1531 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1532 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1533 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1534 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1535 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1536 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1537 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1538 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1539 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1540 [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg,
1541 [SLAVE_PCIE_3_CFG] = &qhs_pcie3_cfg,
1542 [SLAVE_PCIE_4_CFG] = &qhs_pcie4_cfg,
1543 [SLAVE_PCIE_5_CFG] = &qhs_pcie5_cfg,
1544 [SLAVE_PCIE_6A_CFG] = &qhs_pcie6a_cfg,
1545 [SLAVE_PCIE_6B_CFG] = &qhs_pcie6b_cfg,
1546 [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg,
1547 [SLAVE_PDM] = &qhs_pdm,
1548 [SLAVE_PRNG] = &qhs_prng,
1549 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1550 [SLAVE_QSPI_0] = &qhs_qspi,
1551 [SLAVE_QUP_0] = &qhs_qup0,
1552 [SLAVE_QUP_1] = &qhs_qup1,
1553 [SLAVE_QUP_2] = &qhs_qup2,
1554 [SLAVE_SDCC_2] = &qhs_sdc2,
1555 [SLAVE_SDCC_4] = &qhs_sdc4,
1556 [SLAVE_SMMUV3_CFG] = &qhs_smmuv3_cfg,
1557 [SLAVE_TCSR] = &qhs_tcsr,
1558 [SLAVE_TLMM] = &qhs_tlmm,
1559 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1560 [SLAVE_USB2] = &qhs_usb2_0_cfg,
1561 [SLAVE_USB3_0] = &qhs_usb3_0_cfg,
1562 [SLAVE_USB3_1] = &qhs_usb3_1_cfg,
1563 [SLAVE_USB3_2] = &qhs_usb3_2_cfg,
1564 [SLAVE_USB3_MP] = &qhs_usb3_mp_cfg,
1565 [SLAVE_USB4_0] = &qhs_usb4_0_cfg,
1566 [SLAVE_USB4_1] = &qhs_usb4_1_cfg,
1567 [SLAVE_USB4_2] = &qhs_usb4_2_cfg,
1568 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1569 [SLAVE_LPASS_QTB_CFG] = &qss_lpass_qtb_cfg,
1570 [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg,
1571 [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg,
1572 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1573 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1574 };
1575
1576 static const struct qcom_icc_desc x1e80100_cnoc_cfg = {
1577 .nodes = cnoc_cfg_nodes,
1578 .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes),
1579 .bcms = cnoc_cfg_bcms,
1580 .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms),
1581 };
1582
1583 static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
1584 &bcm_cn0,
1585 };
1586
1587 static struct qcom_icc_node * const cnoc_main_nodes[] = {
1588 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1589 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1590 [SLAVE_AOSS] = &qhs_aoss,
1591 [SLAVE_TME_CFG] = &qhs_tme_cfg,
1592 [SLAVE_APPSS] = &qns_apss,
1593 [SLAVE_CNOC_CFG] = &qss_cfg,
1594 [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1595 [SLAVE_IMEM] = &qxs_imem,
1596 [SLAVE_PCIE_0] = &xs_pcie_0,
1597 [SLAVE_PCIE_1] = &xs_pcie_1,
1598 [SLAVE_PCIE_2] = &xs_pcie_2,
1599 [SLAVE_PCIE_3] = &xs_pcie_3,
1600 [SLAVE_PCIE_4] = &xs_pcie_4,
1601 [SLAVE_PCIE_5] = &xs_pcie_5,
1602 [SLAVE_PCIE_6A] = &xs_pcie_6a,
1603 [SLAVE_PCIE_6B] = &xs_pcie_6b,
1604 };
1605
1606 static const struct qcom_icc_desc x1e80100_cnoc_main = {
1607 .nodes = cnoc_main_nodes,
1608 .num_nodes = ARRAY_SIZE(cnoc_main_nodes),
1609 .bcms = cnoc_main_bcms,
1610 .num_bcms = ARRAY_SIZE(cnoc_main_bcms),
1611 };
1612
1613 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1614 &bcm_sh0,
1615 &bcm_sh1,
1616 };
1617
1618 static struct qcom_icc_node * const gem_noc_nodes[] = {
1619 [MASTER_GPU_TCU] = &alm_gpu_tcu,
1620 [MASTER_PCIE_TCU] = &alm_pcie_tcu,
1621 [MASTER_SYS_TCU] = &alm_sys_tcu,
1622 [MASTER_APPSS_PROC] = &chm_apps,
1623 [MASTER_GFX3D] = &qnm_gpu,
1624 [MASTER_LPASS_GEM_NOC] = &qnm_lpass,
1625 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1626 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1627 [MASTER_COMPUTE_NOC] = &qnm_nsp_noc,
1628 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1629 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1630 [MASTER_GIC2] = &xm_gic,
1631 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1632 [SLAVE_LLCC] = &qns_llcc,
1633 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1634 };
1635
1636 static const struct qcom_icc_desc x1e80100_gem_noc = {
1637 .nodes = gem_noc_nodes,
1638 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1639 .bcms = gem_noc_bcms,
1640 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1641 };
1642
1643 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1644 };
1645
1646 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1647 [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
1648 [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
1649 };
1650
1651 static const struct qcom_icc_desc x1e80100_lpass_ag_noc = {
1652 .nodes = lpass_ag_noc_nodes,
1653 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1654 .bcms = lpass_ag_noc_bcms,
1655 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1656 };
1657
1658 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
1659 &bcm_lp0,
1660 };
1661
1662 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
1663 [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc,
1664 [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
1665 };
1666
1667 static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc = {
1668 .nodes = lpass_lpiaon_noc_nodes,
1669 .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
1670 .bcms = lpass_lpiaon_noc_bcms,
1671 .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
1672 };
1673
1674 static struct qcom_icc_bcm * const lpass_lpicx_noc_bcms[] = {
1675 };
1676
1677 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
1678 [MASTER_LPASS_PROC] = &qxm_lpinoc_dsp_axim,
1679 [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
1680 };
1681
1682 static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = {
1683 .nodes = lpass_lpicx_noc_nodes,
1684 .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
1685 .bcms = lpass_lpicx_noc_bcms,
1686 .num_bcms = ARRAY_SIZE(lpass_lpicx_noc_bcms),
1687 };
1688
1689 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1690 &bcm_acv,
1691 &bcm_mc0,
1692 };
1693
1694 static struct qcom_icc_node * const mc_virt_nodes[] = {
1695 [MASTER_LLCC] = &llcc_mc,
1696 [SLAVE_EBI1] = &ebi,
1697 };
1698
1699 static const struct qcom_icc_desc x1e80100_mc_virt = {
1700 .nodes = mc_virt_nodes,
1701 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1702 .bcms = mc_virt_bcms,
1703 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1704 };
1705
1706 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1707 &bcm_mm0,
1708 &bcm_mm1,
1709 };
1710
1711 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1712 [MASTER_AV1_ENC] = &qnm_av1_enc,
1713 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1714 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1715 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1716 [MASTER_EVA] = &qnm_eva,
1717 [MASTER_MDP] = &qnm_mdp,
1718 [MASTER_VIDEO] = &qnm_video,
1719 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
1720 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
1721 [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg,
1722 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1723 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1724 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1725 };
1726
1727 static const struct qcom_icc_desc x1e80100_mmss_noc = {
1728 .nodes = mmss_noc_nodes,
1729 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1730 .bcms = mmss_noc_bcms,
1731 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1732 };
1733
1734 static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1735 &bcm_co0,
1736 };
1737
1738 static struct qcom_icc_node * const nsp_noc_nodes[] = {
1739 [MASTER_CDSP_PROC] = &qxm_nsp,
1740 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1741 };
1742
1743 static const struct qcom_icc_desc x1e80100_nsp_noc = {
1744 .nodes = nsp_noc_nodes,
1745 .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1746 .bcms = nsp_noc_bcms,
1747 .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1748 };
1749
1750 static struct qcom_icc_bcm * const pcie_center_anoc_bcms[] = {
1751 &bcm_pc0,
1752 };
1753
1754 static struct qcom_icc_node * const pcie_center_anoc_nodes[] = {
1755 [MASTER_PCIE_NORTH] = &qnm_pcie_north_gem_noc,
1756 [MASTER_PCIE_SOUTH] = &qnm_pcie_south_gem_noc,
1757 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1758 };
1759
1760 static const struct qcom_icc_desc x1e80100_pcie_center_anoc = {
1761 .nodes = pcie_center_anoc_nodes,
1762 .num_nodes = ARRAY_SIZE(pcie_center_anoc_nodes),
1763 .bcms = pcie_center_anoc_bcms,
1764 .num_bcms = ARRAY_SIZE(pcie_center_anoc_bcms),
1765 };
1766
1767 static struct qcom_icc_bcm * const pcie_north_anoc_bcms[] = {
1768 };
1769
1770 static struct qcom_icc_node * const pcie_north_anoc_nodes[] = {
1771 [MASTER_PCIE_3] = &xm_pcie_3,
1772 [MASTER_PCIE_4] = &xm_pcie_4,
1773 [MASTER_PCIE_5] = &xm_pcie_5,
1774 [SLAVE_PCIE_NORTH] = &qns_pcie_north_gem_noc,
1775 };
1776
1777 static const struct qcom_icc_desc x1e80100_pcie_north_anoc = {
1778 .nodes = pcie_north_anoc_nodes,
1779 .num_nodes = ARRAY_SIZE(pcie_north_anoc_nodes),
1780 .bcms = pcie_north_anoc_bcms,
1781 .num_bcms = ARRAY_SIZE(pcie_north_anoc_bcms),
1782 };
1783
1784 static struct qcom_icc_bcm * const pcie_south_anoc_bcms[] = {
1785 };
1786
1787 static struct qcom_icc_node * const pcie_south_anoc_nodes[] = {
1788 [MASTER_PCIE_0] = &xm_pcie_0,
1789 [MASTER_PCIE_1] = &xm_pcie_1,
1790 [MASTER_PCIE_2] = &xm_pcie_2,
1791 [MASTER_PCIE_6A] = &xm_pcie_6a,
1792 [MASTER_PCIE_6B] = &xm_pcie_6b,
1793 [SLAVE_PCIE_SOUTH] = &qns_pcie_south_gem_noc,
1794 };
1795
1796 static const struct qcom_icc_desc x1e80100_pcie_south_anoc = {
1797 .nodes = pcie_south_anoc_nodes,
1798 .num_nodes = ARRAY_SIZE(pcie_south_anoc_nodes),
1799 .bcms = pcie_south_anoc_bcms,
1800 .num_bcms = ARRAY_SIZE(pcie_south_anoc_bcms),
1801 };
1802
1803 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1804 &bcm_sn0,
1805 &bcm_sn2,
1806 &bcm_sn3,
1807 &bcm_sn4,
1808 };
1809
1810 static struct qcom_icc_node * const system_noc_nodes[] = {
1811 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1812 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1813 [MASTER_GIC1] = &qnm_gic,
1814 [MASTER_USB_NOC_SNOC] = &qnm_usb_anoc,
1815 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1816 };
1817
1818 static const struct qcom_icc_desc x1e80100_system_noc = {
1819 .nodes = system_noc_nodes,
1820 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1821 .bcms = system_noc_bcms,
1822 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1823 };
1824
1825 static struct qcom_icc_bcm * const usb_center_anoc_bcms[] = {
1826 };
1827
1828 static struct qcom_icc_node * const usb_center_anoc_nodes[] = {
1829 [MASTER_AGGRE_USB_NORTH] = &qnm_aggre_usb_north_snoc,
1830 [MASTER_AGGRE_USB_SOUTH] = &qnm_aggre_usb_south_snoc,
1831 [SLAVE_USB_NOC_SNOC] = &qns_aggre_usb_snoc,
1832 };
1833
1834 static const struct qcom_icc_desc x1e80100_usb_center_anoc = {
1835 .nodes = usb_center_anoc_nodes,
1836 .num_nodes = ARRAY_SIZE(usb_center_anoc_nodes),
1837 .bcms = usb_center_anoc_bcms,
1838 .num_bcms = ARRAY_SIZE(usb_center_anoc_bcms),
1839 };
1840
1841 static struct qcom_icc_bcm * const usb_north_anoc_bcms[] = {
1842 };
1843
1844 static struct qcom_icc_node * const usb_north_anoc_nodes[] = {
1845 [MASTER_USB2] = &xm_usb2_0,
1846 [MASTER_USB3_MP] = &xm_usb3_mp,
1847 [SLAVE_AGGRE_USB_NORTH] = &qns_aggre_usb_north_snoc,
1848 };
1849
1850 static const struct qcom_icc_desc x1e80100_usb_north_anoc = {
1851 .nodes = usb_north_anoc_nodes,
1852 .num_nodes = ARRAY_SIZE(usb_north_anoc_nodes),
1853 .bcms = usb_north_anoc_bcms,
1854 .num_bcms = ARRAY_SIZE(usb_north_anoc_bcms),
1855 };
1856
1857 static struct qcom_icc_bcm * const usb_south_anoc_bcms[] = {
1858 };
1859
1860 static struct qcom_icc_node * const usb_south_anoc_nodes[] = {
1861 [MASTER_USB3_0] = &xm_usb3_0,
1862 [MASTER_USB3_1] = &xm_usb3_1,
1863 [MASTER_USB3_2] = &xm_usb3_2,
1864 [MASTER_USB4_0] = &xm_usb4_0,
1865 [MASTER_USB4_1] = &xm_usb4_1,
1866 [MASTER_USB4_2] = &xm_usb4_2,
1867 [SLAVE_AGGRE_USB_SOUTH] = &qns_aggre_usb_south_snoc,
1868 };
1869
1870 static const struct qcom_icc_desc x1e80100_usb_south_anoc = {
1871 .nodes = usb_south_anoc_nodes,
1872 .num_nodes = ARRAY_SIZE(usb_south_anoc_nodes),
1873 .bcms = usb_south_anoc_bcms,
1874 .num_bcms = ARRAY_SIZE(usb_south_anoc_bcms),
1875 };
1876
1877 static const struct of_device_id qnoc_of_match[] = {
1878 { .compatible = "qcom,x1e80100-aggre1-noc", .data = &x1e80100_aggre1_noc},
1879 { .compatible = "qcom,x1e80100-aggre2-noc", .data = &x1e80100_aggre2_noc},
1880 { .compatible = "qcom,x1e80100-clk-virt", .data = &x1e80100_clk_virt},
1881 { .compatible = "qcom,x1e80100-cnoc-cfg", .data = &x1e80100_cnoc_cfg},
1882 { .compatible = "qcom,x1e80100-cnoc-main", .data = &x1e80100_cnoc_main},
1883 { .compatible = "qcom,x1e80100-gem-noc", .data = &x1e80100_gem_noc},
1884 { .compatible = "qcom,x1e80100-lpass-ag-noc", .data = &x1e80100_lpass_ag_noc},
1885 { .compatible = "qcom,x1e80100-lpass-lpiaon-noc", .data = &x1e80100_lpass_lpiaon_noc},
1886 { .compatible = "qcom,x1e80100-lpass-lpicx-noc", .data = &x1e80100_lpass_lpicx_noc},
1887 { .compatible = "qcom,x1e80100-mc-virt", .data = &x1e80100_mc_virt},
1888 { .compatible = "qcom,x1e80100-mmss-noc", .data = &x1e80100_mmss_noc},
1889 { .compatible = "qcom,x1e80100-nsp-noc", .data = &x1e80100_nsp_noc},
1890 { .compatible = "qcom,x1e80100-pcie-center-anoc", .data = &x1e80100_pcie_center_anoc},
1891 { .compatible = "qcom,x1e80100-pcie-north-anoc", .data = &x1e80100_pcie_north_anoc},
1892 { .compatible = "qcom,x1e80100-pcie-south-anoc", .data = &x1e80100_pcie_south_anoc},
1893 { .compatible = "qcom,x1e80100-system-noc", .data = &x1e80100_system_noc},
1894 { .compatible = "qcom,x1e80100-usb-center-anoc", .data = &x1e80100_usb_center_anoc},
1895 { .compatible = "qcom,x1e80100-usb-north-anoc", .data = &x1e80100_usb_north_anoc},
1896 { .compatible = "qcom,x1e80100-usb-south-anoc", .data = &x1e80100_usb_south_anoc},
1897 { }
1898 };
1899 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1900
1901 static struct platform_driver qnoc_driver = {
1902 .probe = qcom_icc_rpmh_probe,
1903 .remove = qcom_icc_rpmh_remove,
1904 .driver = {
1905 .name = "qnoc-x1e80100",
1906 .of_match_table = qnoc_of_match,
1907 .sync_state = icc_sync_state,
1908 },
1909 };
1910
qnoc_driver_init(void)1911 static int __init qnoc_driver_init(void)
1912 {
1913 return platform_driver_register(&qnoc_driver);
1914 }
1915 core_initcall(qnoc_driver_init);
1916
qnoc_driver_exit(void)1917 static void __exit qnoc_driver_exit(void)
1918 {
1919 platform_driver_unregister(&qnoc_driver);
1920 }
1921 module_exit(qnoc_driver_exit);
1922
1923 MODULE_DESCRIPTION("x1e80100 NoC driver");
1924 MODULE_LICENSE("GPL");
1925