1 /*
2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41 #include <linux/slab.h>
42 #include "pm8001_sas.h"
43 #include "pm8001_chips.h"
44 #include "pm80xx_hwi.h"
45
46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING |
47 PM8001_EVENT_LOGGING | PM8001_INIT_LOGGING;
48 module_param(logging_level, ulong, 0644);
49 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
50
51 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
52 module_param(link_rate, ulong, 0644);
53 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
54 " 1: Link rate 1.5G\n"
55 " 2: Link rate 3.0G\n"
56 " 4: Link rate 6.0G\n"
57 " 8: Link rate 12.0G\n");
58
59 bool pm8001_use_msix = true;
60 module_param_named(use_msix, pm8001_use_msix, bool, 0444);
61 MODULE_PARM_DESC(zoned, "Use MSIX interrupts. Default: true");
62
63 static bool pm8001_use_tasklet = true;
64 module_param_named(use_tasklet, pm8001_use_tasklet, bool, 0444);
65 MODULE_PARM_DESC(zoned, "Use MSIX interrupts. Default: true");
66
67 static bool pm8001_read_wwn = true;
68 module_param_named(read_wwn, pm8001_read_wwn, bool, 0444);
69 MODULE_PARM_DESC(zoned, "Get WWN from the controller. Default: true");
70
71 uint pcs_event_log_severity = 0x03;
72 module_param(pcs_event_log_severity, int, 0644);
73 MODULE_PARM_DESC(pcs_event_log_severity, "PCS event log severity level");
74
75 static struct scsi_transport_template *pm8001_stt;
76 static int pm8001_init_ccb_tag(struct pm8001_hba_info *);
77
78 /*
79 * chip info structure to identify chip key functionality as
80 * encryption available/not, no of ports, hw specific function ref
81 */
82 static const struct pm8001_chip_info pm8001_chips[] = {
83 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
84 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
85 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
86 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
87 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
88 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
89 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
90 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
91 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
92 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
93 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
94 };
95 static int pm8001_id;
96
97 LIST_HEAD(hba_list);
98
99 struct workqueue_struct *pm8001_wq;
100
pm8001_map_queues(struct Scsi_Host * shost)101 static void pm8001_map_queues(struct Scsi_Host *shost)
102 {
103 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
104 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
105 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
106
107 if (pm8001_ha->number_of_intr > 1) {
108 blk_mq_map_hw_queues(qmap, &pm8001_ha->pdev->dev, 1);
109 return;
110 }
111
112 blk_mq_map_queues(qmap);
113 }
114
115 /*
116 * The main structure which LLDD must register for scsi core.
117 */
118 static const struct scsi_host_template pm8001_sht = {
119 LIBSAS_SHT_BASE
120 .scan_finished = pm8001_scan_finished,
121 .scan_start = pm8001_scan_start,
122 .can_queue = 1,
123 .sg_tablesize = PM8001_MAX_DMA_SG,
124 .max_sectors = PM8001_MAX_SECTORS,
125 .shost_groups = pm8001_host_groups,
126 .sdev_groups = pm8001_sdev_groups,
127 .track_queue_depth = 1,
128 .cmd_per_lun = 32,
129 .map_queues = pm8001_map_queues,
130 };
131
132 /*
133 * Sas layer call this function to execute specific task.
134 */
135 static struct sas_domain_function_template pm8001_transport_ops = {
136 .lldd_dev_found = pm8001_dev_found,
137 .lldd_dev_gone = pm8001_dev_gone,
138
139 .lldd_execute_task = pm8001_queue_command,
140 .lldd_control_phy = pm8001_phy_control,
141
142 .lldd_abort_task = pm8001_abort_task,
143 .lldd_abort_task_set = sas_abort_task_set,
144 .lldd_clear_task_set = pm8001_clear_task_set,
145 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
146 .lldd_lu_reset = pm8001_lu_reset,
147 .lldd_query_task = pm8001_query_task,
148 .lldd_port_formed = pm8001_port_formed,
149 .lldd_tmf_exec_complete = pm8001_setds_completion,
150 .lldd_tmf_aborted = pm8001_tmf_aborted,
151 };
152
153 /**
154 * pm8001_phy_init - initiate our adapter phys
155 * @pm8001_ha: our hba structure.
156 * @phy_id: phy id.
157 */
pm8001_phy_init(struct pm8001_hba_info * pm8001_ha,int phy_id)158 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
159 {
160 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
161 struct asd_sas_phy *sas_phy = &phy->sas_phy;
162 phy->phy_state = PHY_LINK_DISABLE;
163 phy->pm8001_ha = pm8001_ha;
164 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
165 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
166 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
167 sas_phy->iproto = SAS_PROTOCOL_ALL;
168 sas_phy->tproto = 0;
169 sas_phy->role = PHY_ROLE_INITIATOR;
170 sas_phy->oob_mode = OOB_NOT_CONNECTED;
171 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
172 sas_phy->id = phy_id;
173 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
174 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
175 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
176 sas_phy->lldd_phy = phy;
177 }
178
179 /**
180 * pm8001_free - free hba
181 * @pm8001_ha: our hba structure.
182 */
pm8001_free(struct pm8001_hba_info * pm8001_ha)183 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
184 {
185 int i;
186
187 if (!pm8001_ha)
188 return;
189
190 for (i = 0; i < USI_MAX_MEMCNT; i++) {
191 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
192 dma_free_coherent(&pm8001_ha->pdev->dev,
193 (pm8001_ha->memoryMap.region[i].total_len +
194 pm8001_ha->memoryMap.region[i].alignment),
195 pm8001_ha->memoryMap.region[i].virt_ptr,
196 pm8001_ha->memoryMap.region[i].phys_addr);
197 }
198 }
199 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
200 flush_workqueue(pm8001_wq);
201 bitmap_free(pm8001_ha->rsvd_tags);
202 kfree(pm8001_ha);
203 }
204
205 /**
206 * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler
207 * @opaque: the passed general host adapter struct
208 * Note: pm8001_tasklet is common for pm8001 & pm80xx
209 */
pm8001_tasklet(unsigned long opaque)210 static void pm8001_tasklet(unsigned long opaque)
211 {
212 struct isr_param *irq_vector = (struct isr_param *)opaque;
213 struct pm8001_hba_info *pm8001_ha = irq_vector->drv_inst;
214
215 if (WARN_ON_ONCE(!pm8001_ha))
216 return;
217
218 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
219 }
220
pm8001_init_tasklet(struct pm8001_hba_info * pm8001_ha)221 static void pm8001_init_tasklet(struct pm8001_hba_info *pm8001_ha)
222 {
223 int i;
224
225 if (!pm8001_use_tasklet)
226 return;
227
228 /* Tasklet for non msi-x interrupt handler */
229 if ((!pm8001_ha->pdev->msix_cap || !pci_msi_enabled()) ||
230 (pm8001_ha->chip_id == chip_8001)) {
231 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
232 (unsigned long)&(pm8001_ha->irq_vector[0]));
233 return;
234 }
235 for (i = 0; i < PM8001_MAX_MSIX_VEC; i++)
236 tasklet_init(&pm8001_ha->tasklet[i], pm8001_tasklet,
237 (unsigned long)&(pm8001_ha->irq_vector[i]));
238 }
239
pm8001_kill_tasklet(struct pm8001_hba_info * pm8001_ha)240 static void pm8001_kill_tasklet(struct pm8001_hba_info *pm8001_ha)
241 {
242 int i;
243
244 if (!pm8001_use_tasklet)
245 return;
246
247 /* For non-msix and msix interrupts */
248 if ((!pm8001_ha->pdev->msix_cap || !pci_msi_enabled()) ||
249 (pm8001_ha->chip_id == chip_8001)) {
250 tasklet_kill(&pm8001_ha->tasklet[0]);
251 return;
252 }
253
254 for (i = 0; i < PM8001_MAX_MSIX_VEC; i++)
255 tasklet_kill(&pm8001_ha->tasklet[i]);
256 }
257
pm8001_handle_irq(struct pm8001_hba_info * pm8001_ha,int irq)258 static irqreturn_t pm8001_handle_irq(struct pm8001_hba_info *pm8001_ha,
259 int irq)
260 {
261 if (unlikely(!pm8001_ha))
262 return IRQ_NONE;
263
264 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
265 return IRQ_NONE;
266
267 if (!pm8001_use_tasklet)
268 return PM8001_CHIP_DISP->isr(pm8001_ha, irq);
269
270 tasklet_schedule(&pm8001_ha->tasklet[irq]);
271 return IRQ_HANDLED;
272 }
273
274 /**
275 * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
276 * It obtains the vector number and calls the equivalent bottom
277 * half or services directly.
278 * @irq: interrupt number
279 * @opaque: the passed outbound queue/vector. Host structure is
280 * retrieved from the same.
281 */
pm8001_interrupt_handler_msix(int irq,void * opaque)282 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
283 {
284 struct isr_param *irq_vector = (struct isr_param *)opaque;
285 struct pm8001_hba_info *pm8001_ha = irq_vector->drv_inst;
286
287 return pm8001_handle_irq(pm8001_ha, irq_vector->irq_id);
288 }
289
290 /**
291 * pm8001_interrupt_handler_intx - main INTx interrupt handler.
292 * @irq: interrupt number
293 * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure.
294 */
295
pm8001_interrupt_handler_intx(int irq,void * dev_id)296 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
297 {
298 struct sas_ha_struct *sha = dev_id;
299 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
300
301 return pm8001_handle_irq(pm8001_ha, 0);
302 }
303
304 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
305 static void pm8001_free_irq(struct pm8001_hba_info *pm8001_ha);
306
307 /**
308 * pm8001_alloc - initiate our hba structure and 6 DMAs area.
309 * @pm8001_ha: our hba structure.
310 * @ent: PCI device ID structure to match on
311 */
pm8001_alloc(struct pm8001_hba_info * pm8001_ha,const struct pci_device_id * ent)312 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
313 const struct pci_device_id *ent)
314 {
315 int i, count = 0, rc = 0;
316 u32 ci_offset, ib_offset, ob_offset, pi_offset;
317 struct inbound_queue_table *ibq;
318 struct outbound_queue_table *obq;
319
320 spin_lock_init(&pm8001_ha->lock);
321 spin_lock_init(&pm8001_ha->bitmap_lock);
322 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
323 pm8001_ha->chip->n_phy);
324
325 /* Request Interrupt */
326 rc = pm8001_request_irq(pm8001_ha);
327 if (rc)
328 goto err_out;
329
330 count = pm8001_ha->max_q_num;
331 /* Queues are chosen based on the number of cores/msix availability */
332 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE;
333 ci_offset = pm8001_ha->ci_offset = ib_offset + count;
334 ob_offset = pm8001_ha->ob_offset = ci_offset + count;
335 pi_offset = pm8001_ha->pi_offset = ob_offset + count;
336 pm8001_ha->max_memcnt = pi_offset + count;
337
338 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
339 pm8001_phy_init(pm8001_ha, i);
340 pm8001_ha->port[i].wide_port_phymap = 0;
341 pm8001_ha->port[i].port_attached = 0;
342 pm8001_ha->port[i].port_state = 0;
343 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
344 }
345
346 /* MPI Memory region 1 for AAP Event Log for fw */
347 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
348 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
349 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
350 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
351
352 /* MPI Memory region 2 for IOP Event Log for fw */
353 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
354 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
355 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
356 pm8001_ha->memoryMap.region[IOP].alignment = 32;
357
358 for (i = 0; i < count; i++) {
359 ibq = &pm8001_ha->inbnd_q_tbl[i];
360 spin_lock_init(&ibq->iq_lock);
361 /* MPI Memory region 3 for consumer Index of inbound queues */
362 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
363 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
364 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
365 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
366
367 if ((ent->driver_data) != chip_8001) {
368 /* MPI Memory region 5 inbound queues */
369 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
370 PM8001_MPI_QUEUE;
371 pm8001_ha->memoryMap.region[ib_offset+i].element_size
372 = 128;
373 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
374 PM8001_MPI_QUEUE * 128;
375 pm8001_ha->memoryMap.region[ib_offset+i].alignment
376 = 128;
377 } else {
378 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
379 PM8001_MPI_QUEUE;
380 pm8001_ha->memoryMap.region[ib_offset+i].element_size
381 = 64;
382 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
383 PM8001_MPI_QUEUE * 64;
384 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
385 }
386 }
387
388 for (i = 0; i < count; i++) {
389 obq = &pm8001_ha->outbnd_q_tbl[i];
390 spin_lock_init(&obq->oq_lock);
391 /* MPI Memory region 4 for producer Index of outbound queues */
392 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
393 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
394 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
395 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
396
397 if (ent->driver_data != chip_8001) {
398 /* MPI Memory region 6 Outbound queues */
399 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
400 PM8001_MPI_QUEUE;
401 pm8001_ha->memoryMap.region[ob_offset+i].element_size
402 = 128;
403 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
404 PM8001_MPI_QUEUE * 128;
405 pm8001_ha->memoryMap.region[ob_offset+i].alignment
406 = 128;
407 } else {
408 /* MPI Memory region 6 Outbound queues */
409 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
410 PM8001_MPI_QUEUE;
411 pm8001_ha->memoryMap.region[ob_offset+i].element_size
412 = 64;
413 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
414 PM8001_MPI_QUEUE * 64;
415 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
416 }
417
418 }
419 /* Memory region write DMA*/
420 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
421 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
422 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
423
424 /* Memory region for fw flash */
425 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
426
427 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
428 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
429 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
430 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
431 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
432 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];
433
434 if (pm8001_mem_alloc(pm8001_ha->pdev,
435 ®ion->virt_ptr,
436 ®ion->phys_addr,
437 ®ion->phys_addr_hi,
438 ®ion->phys_addr_lo,
439 region->total_len,
440 region->alignment) != 0) {
441 pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);
442 goto err_out;
443 }
444 }
445
446 /* Memory region for devices*/
447 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
448 * sizeof(struct pm8001_device), GFP_KERNEL);
449 if (!pm8001_ha->devices) {
450 rc = -ENOMEM;
451 goto err_out_nodev;
452 }
453 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
454 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
455 }
456 pm8001_ha->flags = PM8001F_INIT_TIME;
457 return 0;
458
459 err_out_nodev:
460 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
461 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
462 dma_free_coherent(&pm8001_ha->pdev->dev,
463 (pm8001_ha->memoryMap.region[i].total_len +
464 pm8001_ha->memoryMap.region[i].alignment),
465 pm8001_ha->memoryMap.region[i].virt_ptr,
466 pm8001_ha->memoryMap.region[i].phys_addr);
467 }
468 }
469 err_out:
470 return 1;
471 }
472
473 /**
474 * pm8001_ioremap - remap the pci high physical address to kernel virtual
475 * address so that we can access them.
476 * @pm8001_ha: our hba structure.
477 */
pm8001_ioremap(struct pm8001_hba_info * pm8001_ha)478 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
479 {
480 u32 bar;
481 u32 logicalBar = 0;
482 struct pci_dev *pdev;
483
484 pdev = pm8001_ha->pdev;
485 /* map pci mem (PMC pci base 0-3)*/
486 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
487 /*
488 ** logical BARs for SPC:
489 ** bar 0 and 1 - logical BAR0
490 ** bar 2 and 3 - logical BAR1
491 ** bar4 - logical BAR2
492 ** bar5 - logical BAR3
493 ** Skip the appropriate assignments:
494 */
495 if ((bar == 1) || (bar == 3))
496 continue;
497 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
498 pm8001_ha->io_mem[logicalBar].membase =
499 pci_resource_start(pdev, bar);
500 pm8001_ha->io_mem[logicalBar].memsize =
501 pci_resource_len(pdev, bar);
502 pm8001_ha->io_mem[logicalBar].memvirtaddr =
503 ioremap(pm8001_ha->io_mem[logicalBar].membase,
504 pm8001_ha->io_mem[logicalBar].memsize);
505 if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) {
506 pm8001_dbg(pm8001_ha, INIT,
507 "Failed to ioremap bar %d, logicalBar %d",
508 bar, logicalBar);
509 return -ENOMEM;
510 }
511 pm8001_dbg(pm8001_ha, INIT,
512 "base addr %llx virt_addr=%llx len=%d\n",
513 (u64)pm8001_ha->io_mem[logicalBar].membase,
514 (u64)(unsigned long)
515 pm8001_ha->io_mem[logicalBar].memvirtaddr,
516 pm8001_ha->io_mem[logicalBar].memsize);
517 } else {
518 pm8001_ha->io_mem[logicalBar].membase = 0;
519 pm8001_ha->io_mem[logicalBar].memsize = 0;
520 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
521 }
522 logicalBar++;
523 }
524 return 0;
525 }
526
527 /**
528 * pm8001_pci_alloc - initialize our ha card structure
529 * @pdev: pci device.
530 * @ent: ent
531 * @shost: scsi host struct which has been initialized before.
532 */
pm8001_pci_alloc(struct pci_dev * pdev,const struct pci_device_id * ent,struct Scsi_Host * shost)533 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
534 const struct pci_device_id *ent,
535 struct Scsi_Host *shost)
536
537 {
538 struct pm8001_hba_info *pm8001_ha;
539 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
540
541 pm8001_ha = sha->lldd_ha;
542 if (!pm8001_ha)
543 return NULL;
544
545 pm8001_ha->pdev = pdev;
546 pm8001_ha->dev = &pdev->dev;
547 pm8001_ha->chip_id = ent->driver_data;
548 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
549 pm8001_ha->irq = pdev->irq;
550 pm8001_ha->sas = sha;
551 pm8001_ha->shost = shost;
552 pm8001_ha->id = pm8001_id++;
553 pm8001_ha->logging_level = logging_level;
554 pm8001_ha->non_fatal_count = 0;
555 mutex_init(&pm8001_ha->iop_log_lock);
556 if (link_rate >= 1 && link_rate <= 15)
557 pm8001_ha->link_rate = (link_rate << 8);
558 else {
559 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
560 LINKRATE_60 | LINKRATE_120;
561 pm8001_dbg(pm8001_ha, FAIL,
562 "Setting link rate to default value\n");
563 }
564 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
565 /* IOMB size is 128 for 8088/89 controllers */
566 if (pm8001_ha->chip_id != chip_8001)
567 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
568 else
569 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
570
571 pm8001_init_tasklet(pm8001_ha);
572
573 if (pm8001_ioremap(pm8001_ha))
574 goto failed_pci_alloc;
575 if (!pm8001_alloc(pm8001_ha, ent))
576 return pm8001_ha;
577 failed_pci_alloc:
578 pm8001_free(pm8001_ha);
579 return NULL;
580 }
581
582 /**
583 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
584 * @pdev: pci device.
585 */
pci_go_44(struct pci_dev * pdev)586 static int pci_go_44(struct pci_dev *pdev)
587 {
588 int rc;
589
590 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
591 if (rc) {
592 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
593 if (rc)
594 dev_printk(KERN_ERR, &pdev->dev,
595 "32-bit DMA enable failed\n");
596 }
597 return rc;
598 }
599
600 /**
601 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
602 * @shost: scsi host which has been allocated outside.
603 * @chip_info: our ha struct.
604 */
pm8001_prep_sas_ha_init(struct Scsi_Host * shost,const struct pm8001_chip_info * chip_info)605 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
606 const struct pm8001_chip_info *chip_info)
607 {
608 int phy_nr, port_nr;
609 struct asd_sas_phy **arr_phy;
610 struct asd_sas_port **arr_port;
611 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
612
613 phy_nr = chip_info->n_phy;
614 port_nr = phy_nr;
615 memset(sha, 0x00, sizeof(*sha));
616 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
617 if (!arr_phy)
618 goto exit;
619 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
620 if (!arr_port)
621 goto exit_free2;
622
623 sha->sas_phy = arr_phy;
624 sha->sas_port = arr_port;
625 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
626 if (!sha->lldd_ha)
627 goto exit_free1;
628
629 shost->transportt = pm8001_stt;
630 shost->max_id = PM8001_MAX_DEVICES;
631 shost->unique_id = pm8001_id;
632 shost->max_cmd_len = 16;
633 return 0;
634 exit_free1:
635 kfree(arr_port);
636 exit_free2:
637 kfree(arr_phy);
638 exit:
639 return -1;
640 }
641
642 /**
643 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
644 * @shost: scsi host which has been allocated outside
645 * @chip_info: our ha struct.
646 */
pm8001_post_sas_ha_init(struct Scsi_Host * shost,const struct pm8001_chip_info * chip_info)647 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
648 const struct pm8001_chip_info *chip_info)
649 {
650 int i = 0;
651 struct pm8001_hba_info *pm8001_ha;
652 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
653
654 pm8001_ha = sha->lldd_ha;
655 for (i = 0; i < chip_info->n_phy; i++) {
656 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
657 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
658 sha->sas_phy[i]->sas_addr =
659 (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
660 }
661 sha->sas_ha_name = DRV_NAME;
662 sha->dev = pm8001_ha->dev;
663 sha->strict_wide_ports = 1;
664 sha->sas_addr = &pm8001_ha->sas_addr[0];
665 sha->num_phys = chip_info->n_phy;
666 sha->shost = shost;
667 }
668
669 /**
670 * pm8001_init_sas_add - initialize sas address
671 * @pm8001_ha: our ha struct.
672 *
673 * Currently we just set the fixed SAS address to our HBA, for manufacture,
674 * it should read from the EEPROM
675 */
pm8001_init_sas_add(struct pm8001_hba_info * pm8001_ha)676 static int pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
677 {
678 DECLARE_COMPLETION_ONSTACK(completion);
679 struct pm8001_ioctl_payload payload;
680 unsigned long time_remaining;
681 u8 sas_add[8];
682 u16 deviceid;
683 int rc;
684 u8 i, j;
685
686 if (!pm8001_read_wwn) {
687 __be64 dev_sas_addr = cpu_to_be64(0x50010c600047f9d0ULL);
688
689 for (i = 0; i < pm8001_ha->chip->n_phy; i++)
690 memcpy(&pm8001_ha->phy[i].dev_sas_addr, &dev_sas_addr,
691 SAS_ADDR_SIZE);
692 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
693 SAS_ADDR_SIZE);
694 return 0;
695 }
696
697 /*
698 * For new SPC controllers WWN is stored in flash vpd. For SPC/SPCve
699 * controllers WWN is stored in EEPROM. And for Older SPC WWN is stored
700 * in NVMD.
701 */
702 if (PM8001_CHIP_DISP->fatal_errors(pm8001_ha)) {
703 pm8001_dbg(pm8001_ha, FAIL, "controller is in fatal error state\n");
704 return -EIO;
705 }
706
707 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
708 pm8001_ha->nvmd_completion = &completion;
709
710 if (pm8001_ha->chip_id == chip_8001) {
711 if (deviceid == 0x8081 || deviceid == 0x0042) {
712 payload.minor_function = 4;
713 payload.rd_length = 4096;
714 } else {
715 payload.minor_function = 0;
716 payload.rd_length = 128;
717 }
718 } else if ((pm8001_ha->chip_id == chip_8070 ||
719 pm8001_ha->chip_id == chip_8072) &&
720 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
721 payload.minor_function = 4;
722 payload.rd_length = 4096;
723 } else {
724 payload.minor_function = 1;
725 payload.rd_length = 4096;
726 }
727 payload.offset = 0;
728 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
729 if (!payload.func_specific) {
730 pm8001_dbg(pm8001_ha, FAIL, "mem alloc fail\n");
731 return -ENOMEM;
732 }
733 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
734 if (rc) {
735 kfree(payload.func_specific);
736 pm8001_dbg(pm8001_ha, FAIL, "nvmd failed\n");
737 return -EIO;
738 }
739 time_remaining = wait_for_completion_timeout(&completion,
740 secs_to_jiffies(60)); // 1 min
741 if (!time_remaining) {
742 kfree(payload.func_specific);
743 pm8001_dbg(pm8001_ha, FAIL, "get_nvmd_req timeout\n");
744 return -EIO;
745 }
746
747
748 for (i = 0, j = 0; i <= 7; i++, j++) {
749 if (pm8001_ha->chip_id == chip_8001) {
750 if (deviceid == 0x8081)
751 pm8001_ha->sas_addr[j] =
752 payload.func_specific[0x704 + i];
753 else if (deviceid == 0x0042)
754 pm8001_ha->sas_addr[j] =
755 payload.func_specific[0x010 + i];
756 } else if ((pm8001_ha->chip_id == chip_8070 ||
757 pm8001_ha->chip_id == chip_8072) &&
758 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
759 pm8001_ha->sas_addr[j] =
760 payload.func_specific[0x010 + i];
761 } else
762 pm8001_ha->sas_addr[j] =
763 payload.func_specific[0x804 + i];
764 }
765 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
766 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
767 if (i && ((i % 4) == 0))
768 sas_add[7] = sas_add[7] + 4;
769 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
770 sas_add, SAS_ADDR_SIZE);
771 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
772 pm8001_ha->phy[i].dev_sas_addr);
773 }
774 kfree(payload.func_specific);
775
776 return 0;
777 }
778
779 /*
780 * pm8001_get_phy_settings_info : Read phy setting values.
781 * @pm8001_ha : our hba.
782 */
pm8001_get_phy_settings_info(struct pm8001_hba_info * pm8001_ha)783 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
784 {
785 DECLARE_COMPLETION_ONSTACK(completion);
786 struct pm8001_ioctl_payload payload;
787 int rc;
788
789 if (!pm8001_read_wwn)
790 return 0;
791
792 pm8001_ha->nvmd_completion = &completion;
793 /* SAS ADDRESS read from flash / EEPROM */
794 payload.minor_function = 6;
795 payload.offset = 0;
796 payload.rd_length = 4096;
797 payload.func_specific = kzalloc(4096, GFP_KERNEL);
798 if (!payload.func_specific)
799 return -ENOMEM;
800 /* Read phy setting values from flash */
801 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
802 if (rc) {
803 kfree(payload.func_specific);
804 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
805 return -ENOMEM;
806 }
807 wait_for_completion(&completion);
808 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
809 kfree(payload.func_specific);
810
811 return 0;
812 }
813
814 struct pm8001_mpi3_phy_pg_trx_config {
815 u32 LaneLosCfg;
816 u32 LanePgaCfg1;
817 u32 LanePisoCfg1;
818 u32 LanePisoCfg2;
819 u32 LanePisoCfg3;
820 u32 LanePisoCfg4;
821 u32 LanePisoCfg5;
822 u32 LanePisoCfg6;
823 u32 LaneBctCtrl;
824 };
825
826 /**
827 * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings
828 * @pm8001_ha : our adapter
829 * @phycfg : PHY config page to populate
830 */
831 static
pm8001_get_internal_phy_settings(struct pm8001_hba_info * pm8001_ha,struct pm8001_mpi3_phy_pg_trx_config * phycfg)832 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
833 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
834 {
835 phycfg->LaneLosCfg = 0x00000132;
836 phycfg->LanePgaCfg1 = 0x00203949;
837 phycfg->LanePisoCfg1 = 0x000000FF;
838 phycfg->LanePisoCfg2 = 0xFF000001;
839 phycfg->LanePisoCfg3 = 0xE7011300;
840 phycfg->LanePisoCfg4 = 0x631C40C0;
841 phycfg->LanePisoCfg5 = 0xF8102036;
842 phycfg->LanePisoCfg6 = 0xF74A1000;
843 phycfg->LaneBctCtrl = 0x00FB33F8;
844 }
845
846 /**
847 * pm8001_get_external_phy_settings - Retrieves the external PHY settings
848 * @pm8001_ha : our adapter
849 * @phycfg : PHY config page to populate
850 */
851 static
pm8001_get_external_phy_settings(struct pm8001_hba_info * pm8001_ha,struct pm8001_mpi3_phy_pg_trx_config * phycfg)852 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
853 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
854 {
855 phycfg->LaneLosCfg = 0x00000132;
856 phycfg->LanePgaCfg1 = 0x00203949;
857 phycfg->LanePisoCfg1 = 0x000000FF;
858 phycfg->LanePisoCfg2 = 0xFF000001;
859 phycfg->LanePisoCfg3 = 0xE7011300;
860 phycfg->LanePisoCfg4 = 0x63349140;
861 phycfg->LanePisoCfg5 = 0xF8102036;
862 phycfg->LanePisoCfg6 = 0xF80D9300;
863 phycfg->LaneBctCtrl = 0x00FB33F8;
864 }
865
866 /**
867 * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext
868 * @pm8001_ha : our adapter
869 * @phymask : The PHY mask
870 */
871 static
pm8001_get_phy_mask(struct pm8001_hba_info * pm8001_ha,int * phymask)872 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
873 {
874 switch (pm8001_ha->pdev->subsystem_device) {
875 case 0x0070: /* H1280 - 8 external 0 internal */
876 case 0x0072: /* H12F0 - 16 external 0 internal */
877 *phymask = 0x0000;
878 break;
879
880 case 0x0071: /* H1208 - 0 external 8 internal */
881 case 0x0073: /* H120F - 0 external 16 internal */
882 *phymask = 0xFFFF;
883 break;
884
885 case 0x0080: /* H1244 - 4 external 4 internal */
886 *phymask = 0x00F0;
887 break;
888
889 case 0x0081: /* H1248 - 4 external 8 internal */
890 *phymask = 0x0FF0;
891 break;
892
893 case 0x0082: /* H1288 - 8 external 8 internal */
894 *phymask = 0xFF00;
895 break;
896
897 default:
898 pm8001_dbg(pm8001_ha, INIT,
899 "Unknown subsystem device=0x%.04x\n",
900 pm8001_ha->pdev->subsystem_device);
901 }
902 }
903
904 /**
905 * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings
906 * @pm8001_ha : our adapter
907 */
908 static
pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info * pm8001_ha)909 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
910 {
911 struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
912 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
913 int phymask = 0;
914 int i = 0;
915
916 memset(&phycfg_int, 0, sizeof(phycfg_int));
917 memset(&phycfg_ext, 0, sizeof(phycfg_ext));
918
919 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
920 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
921 pm8001_get_phy_mask(pm8001_ha, &phymask);
922
923 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
924 if (phymask & (1 << i)) {/* Internal PHY */
925 pm8001_set_phy_profile_single(pm8001_ha, i,
926 sizeof(phycfg_int) / sizeof(u32),
927 (u32 *)&phycfg_int);
928
929 } else { /* External PHY */
930 pm8001_set_phy_profile_single(pm8001_ha, i,
931 sizeof(phycfg_ext) / sizeof(u32),
932 (u32 *)&phycfg_ext);
933 }
934 }
935
936 return 0;
937 }
938
939 /**
940 * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID.
941 * @pm8001_ha : our hba.
942 */
pm8001_configure_phy_settings(struct pm8001_hba_info * pm8001_ha)943 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
944 {
945 switch (pm8001_ha->pdev->subsystem_vendor) {
946 case PCI_VENDOR_ID_ATTO:
947 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
948 return 0;
949 else
950 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
951
952 case PCI_VENDOR_ID_ADAPTEC2:
953 case 0:
954 return 0;
955
956 default:
957 return pm8001_get_phy_settings_info(pm8001_ha);
958 }
959 }
960
961 /**
962 * pm8001_setup_msix - enable MSI-X interrupt
963 * @pm8001_ha: our ha struct.
964 */
pm8001_setup_msix(struct pm8001_hba_info * pm8001_ha)965 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
966 {
967 unsigned int allocated_irq_vectors;
968 int rc;
969
970 /* SPCv controllers supports 64 msi-x */
971 if (pm8001_ha->chip_id == chip_8001) {
972 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, 1, 1,
973 PCI_IRQ_MSIX);
974 } else {
975 /*
976 * Queue index #0 is used always for housekeeping, so don't
977 * include in the affinity spreading.
978 */
979 struct irq_affinity desc = {
980 .pre_vectors = 1,
981 };
982 rc = pci_alloc_irq_vectors_affinity(
983 pm8001_ha->pdev, 2, PM8001_MAX_MSIX_VEC,
984 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc);
985 }
986
987 allocated_irq_vectors = rc;
988 if (rc < 0)
989 return rc;
990
991 /* Assigns the number of interrupts */
992 pm8001_ha->number_of_intr = allocated_irq_vectors;
993
994 /* Maximum queue number updating in HBA structure */
995 pm8001_ha->max_q_num = allocated_irq_vectors;
996
997 pm8001_dbg(pm8001_ha, INIT,
998 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
999 rc, pm8001_ha->number_of_intr);
1000 return 0;
1001 }
1002
pm8001_request_msix(struct pm8001_hba_info * pm8001_ha)1003 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
1004 {
1005 u32 i = 0, j = 0;
1006 int flag = 0, rc = 0;
1007 int nr_irqs = pm8001_ha->number_of_intr;
1008
1009 if (pm8001_ha->chip_id != chip_8001)
1010 flag &= ~IRQF_SHARED;
1011
1012 pm8001_dbg(pm8001_ha, INIT,
1013 "pci_enable_msix request number of intr %d\n",
1014 pm8001_ha->number_of_intr);
1015
1016 if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname))
1017 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname);
1018
1019 for (i = 0; i < nr_irqs; i++) {
1020 snprintf(pm8001_ha->intr_drvname[i],
1021 sizeof(pm8001_ha->intr_drvname[0]),
1022 "%s-%d", pm8001_ha->name, i);
1023 pm8001_ha->irq_vector[i].irq_id = i;
1024 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
1025
1026 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
1027 pm8001_interrupt_handler_msix, flag,
1028 pm8001_ha->intr_drvname[i],
1029 &(pm8001_ha->irq_vector[i]));
1030 if (rc) {
1031 for (j = 0; j < i; j++) {
1032 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
1033 &(pm8001_ha->irq_vector[i]));
1034 }
1035 pci_free_irq_vectors(pm8001_ha->pdev);
1036 break;
1037 }
1038 }
1039
1040 return rc;
1041 }
1042
1043 /**
1044 * pm8001_request_irq - register interrupt
1045 * @pm8001_ha: our ha struct.
1046 */
pm8001_request_irq(struct pm8001_hba_info * pm8001_ha)1047 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1048 {
1049 struct pci_dev *pdev = pm8001_ha->pdev;
1050 int rc;
1051
1052 if (pm8001_use_msix && pci_find_capability(pdev, PCI_CAP_ID_MSIX)) {
1053 rc = pm8001_setup_msix(pm8001_ha);
1054 if (rc) {
1055 pm8001_dbg(pm8001_ha, FAIL,
1056 "pm8001_setup_irq failed [ret: %d]\n", rc);
1057 return rc;
1058 }
1059
1060 if (!pdev->msix_cap || !pci_msi_enabled())
1061 goto use_intx;
1062
1063 rc = pm8001_request_msix(pm8001_ha);
1064 if (rc)
1065 return rc;
1066
1067 pm8001_ha->use_msix = true;
1068
1069 return 0;
1070 }
1071
1072 use_intx:
1073 /* Initialize the INT-X interrupt */
1074 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1075 pm8001_ha->use_msix = false;
1076 pm8001_ha->irq_vector[0].irq_id = 0;
1077 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1078
1079 return request_irq(pdev->irq, pm8001_interrupt_handler_intx,
1080 IRQF_SHARED, pm8001_ha->name,
1081 SHOST_TO_SAS_HA(pm8001_ha->shost));
1082 }
1083
pm8001_free_irq(struct pm8001_hba_info * pm8001_ha)1084 static void pm8001_free_irq(struct pm8001_hba_info *pm8001_ha)
1085 {
1086 struct pci_dev *pdev = pm8001_ha->pdev;
1087 int i;
1088
1089 if (pm8001_ha->use_msix) {
1090 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1091 synchronize_irq(pci_irq_vector(pdev, i));
1092
1093 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1094 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1095
1096 pci_free_irq_vectors(pdev);
1097 return;
1098 }
1099
1100 /* INT-X */
1101 free_irq(pm8001_ha->irq, pm8001_ha->sas);
1102 }
1103
1104 /**
1105 * pm8001_pci_probe - probe supported device
1106 * @pdev: pci device which kernel has been prepared for.
1107 * @ent: pci device id
1108 *
1109 * This function is the main initialization function, when register a new
1110 * pci driver it is invoked, all struct and hardware initialization should be
1111 * done here, also, register interrupt.
1112 */
pm8001_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1113 static int pm8001_pci_probe(struct pci_dev *pdev,
1114 const struct pci_device_id *ent)
1115 {
1116 unsigned int rc;
1117 u32 pci_reg;
1118 u8 i = 0;
1119 struct pm8001_hba_info *pm8001_ha;
1120 struct Scsi_Host *shost = NULL;
1121 const struct pm8001_chip_info *chip;
1122 struct sas_ha_struct *sha;
1123
1124 dev_printk(KERN_INFO, &pdev->dev,
1125 "pm80xx: driver version %s\n", DRV_VERSION);
1126 rc = pci_enable_device(pdev);
1127 if (rc)
1128 goto err_out_enable;
1129 pci_set_master(pdev);
1130 /*
1131 * Enable pci slot busmaster by setting pci command register.
1132 * This is required by FW for Cyclone card.
1133 */
1134
1135 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1136 pci_reg |= 0x157;
1137 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1138 rc = pci_request_regions(pdev, DRV_NAME);
1139 if (rc)
1140 goto err_out_disable;
1141 rc = pci_go_44(pdev);
1142 if (rc)
1143 goto err_out_regions;
1144
1145 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1146 if (!shost) {
1147 rc = -ENOMEM;
1148 goto err_out_regions;
1149 }
1150 chip = &pm8001_chips[ent->driver_data];
1151 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1152 if (!sha) {
1153 rc = -ENOMEM;
1154 goto err_out_free_host;
1155 }
1156 SHOST_TO_SAS_HA(shost) = sha;
1157
1158 rc = pm8001_prep_sas_ha_init(shost, chip);
1159 if (rc) {
1160 rc = -ENOMEM;
1161 goto err_out_free;
1162 }
1163 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1164 /* ent->driver variable is used to differentiate between controllers */
1165 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1166 if (!pm8001_ha) {
1167 rc = -ENOMEM;
1168 goto err_out_free;
1169 }
1170
1171 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1172 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1173 if (rc) {
1174 pm8001_dbg(pm8001_ha, FAIL,
1175 "chip_init failed [ret: %d]\n", rc);
1176 goto err_out_ha_free;
1177 }
1178
1179 rc = pm8001_init_ccb_tag(pm8001_ha);
1180 if (rc)
1181 goto err_out_enable;
1182
1183
1184 PM8001_CHIP_DISP->chip_post_init(pm8001_ha);
1185
1186 if (pm8001_ha->number_of_intr > 1) {
1187 shost->nr_hw_queues = pm8001_ha->number_of_intr - 1;
1188 /*
1189 * For now, ensure we're not sent too many commands by setting
1190 * host_tagset. This is also required if we start using request
1191 * tag.
1192 */
1193 shost->host_tagset = 1;
1194 }
1195
1196 rc = scsi_add_host(shost, &pdev->dev);
1197 if (rc)
1198 goto err_out_ha_free;
1199
1200 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1201 if (pm8001_ha->chip_id != chip_8001) {
1202 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1203 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1204 /* setup thermal configuration. */
1205 pm80xx_set_thermal_config(pm8001_ha);
1206 }
1207
1208 rc = pm8001_init_sas_add(pm8001_ha);
1209 if (rc)
1210 goto err_out_shost;
1211 /* phy setting support for motherboard controller */
1212 rc = pm8001_configure_phy_settings(pm8001_ha);
1213 if (rc)
1214 goto err_out_shost;
1215
1216 pm8001_post_sas_ha_init(shost, chip);
1217 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1218 if (rc) {
1219 pm8001_dbg(pm8001_ha, FAIL,
1220 "sas_register_ha failed [ret: %d]\n", rc);
1221 goto err_out_shost;
1222 }
1223 list_add_tail(&pm8001_ha->list, &hba_list);
1224 pm8001_ha->flags = PM8001F_RUN_TIME;
1225 scsi_scan_host(pm8001_ha->shost);
1226 return 0;
1227
1228 err_out_shost:
1229 scsi_remove_host(pm8001_ha->shost);
1230 err_out_ha_free:
1231 pm8001_free(pm8001_ha);
1232 err_out_free:
1233 kfree(sha);
1234 err_out_free_host:
1235 scsi_host_put(shost);
1236 err_out_regions:
1237 pci_release_regions(pdev);
1238 err_out_disable:
1239 pci_disable_device(pdev);
1240 err_out_enable:
1241 return rc;
1242 }
1243
1244 /**
1245 * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1246 * @pm8001_ha: our hba card information.
1247 */
pm8001_init_ccb_tag(struct pm8001_hba_info * pm8001_ha)1248 static int pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha)
1249 {
1250 struct Scsi_Host *shost = pm8001_ha->shost;
1251 struct device *dev = pm8001_ha->dev;
1252 u32 max_out_io, ccb_count;
1253 int i;
1254
1255 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1256 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1257
1258 shost->can_queue = ccb_count - PM8001_RESERVE_SLOT;
1259
1260 pm8001_ha->rsvd_tags = bitmap_zalloc(PM8001_RESERVE_SLOT, GFP_KERNEL);
1261 if (!pm8001_ha->rsvd_tags)
1262 goto err_out;
1263
1264 /* Memory region for ccb_info*/
1265 pm8001_ha->ccb_count = ccb_count;
1266 pm8001_ha->ccb_info =
1267 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1268 if (!pm8001_ha->ccb_info) {
1269 pm8001_dbg(pm8001_ha, FAIL,
1270 "Unable to allocate memory for ccb\n");
1271 goto err_out_noccb;
1272 }
1273 for (i = 0; i < ccb_count; i++) {
1274 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(dev,
1275 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1276 &pm8001_ha->ccb_info[i].ccb_dma_handle,
1277 GFP_KERNEL);
1278 if (!pm8001_ha->ccb_info[i].buf_prd) {
1279 pm8001_dbg(pm8001_ha, FAIL,
1280 "ccb prd memory allocation error\n");
1281 goto err_out;
1282 }
1283 pm8001_ha->ccb_info[i].task = NULL;
1284 pm8001_ha->ccb_info[i].ccb_tag = PM8001_INVALID_TAG;
1285 pm8001_ha->ccb_info[i].device = NULL;
1286 }
1287
1288 return 0;
1289
1290 err_out_noccb:
1291 kfree(pm8001_ha->devices);
1292 err_out:
1293 return -ENOMEM;
1294 }
1295
pm8001_pci_remove(struct pci_dev * pdev)1296 static void pm8001_pci_remove(struct pci_dev *pdev)
1297 {
1298 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1299 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1300 int i;
1301
1302 sas_unregister_ha(sha);
1303 sas_remove_host(pm8001_ha->shost);
1304 list_del(&pm8001_ha->list);
1305 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1306 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1307
1308 pm8001_free_irq(pm8001_ha);
1309 pm8001_kill_tasklet(pm8001_ha);
1310 scsi_host_put(pm8001_ha->shost);
1311
1312 for (i = 0; i < pm8001_ha->ccb_count; i++) {
1313 dma_free_coherent(&pm8001_ha->pdev->dev,
1314 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1315 pm8001_ha->ccb_info[i].buf_prd,
1316 pm8001_ha->ccb_info[i].ccb_dma_handle);
1317 }
1318 kfree(pm8001_ha->ccb_info);
1319 kfree(pm8001_ha->devices);
1320
1321 pm8001_free(pm8001_ha);
1322 kfree(sha->sas_phy);
1323 kfree(sha->sas_port);
1324 kfree(sha);
1325 pci_release_regions(pdev);
1326 pci_disable_device(pdev);
1327 }
1328
1329 /**
1330 * pm8001_pci_suspend - power management suspend main entry point
1331 * @dev: Device struct
1332 *
1333 * Return: 0 on success, anything else on error.
1334 */
pm8001_pci_suspend(struct device * dev)1335 static int __maybe_unused pm8001_pci_suspend(struct device *dev)
1336 {
1337 struct pci_dev *pdev = to_pci_dev(dev);
1338 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1339 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1340
1341 sas_suspend_ha(sha);
1342 flush_workqueue(pm8001_wq);
1343 scsi_block_requests(pm8001_ha->shost);
1344 if (!pdev->pm_cap) {
1345 dev_err(dev, " PCI PM not supported\n");
1346 return -ENODEV;
1347 }
1348 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1349 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1350
1351 pm8001_free_irq(pm8001_ha);
1352 pm8001_kill_tasklet(pm8001_ha);
1353
1354 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "
1355 "suspended state\n", pdev,
1356 pm8001_ha->name);
1357 return 0;
1358 }
1359
1360 /**
1361 * pm8001_pci_resume - power management resume main entry point
1362 * @dev: Device struct
1363 *
1364 * Return: 0 on success, anything else on error.
1365 */
pm8001_pci_resume(struct device * dev)1366 static int __maybe_unused pm8001_pci_resume(struct device *dev)
1367 {
1368 struct pci_dev *pdev = to_pci_dev(dev);
1369 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1370 struct pm8001_hba_info *pm8001_ha;
1371 int rc;
1372 u8 i = 0;
1373 DECLARE_COMPLETION_ONSTACK(completion);
1374
1375 pm8001_ha = sha->lldd_ha;
1376
1377 pm8001_info(pm8001_ha,
1378 "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1379 pdev, pm8001_ha->name, pdev->current_state);
1380
1381 rc = pci_go_44(pdev);
1382 if (rc)
1383 goto err_out_disable;
1384 sas_prep_resume_ha(sha);
1385 /* chip soft rst only for spc */
1386 if (pm8001_ha->chip_id == chip_8001) {
1387 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1388 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1389 }
1390 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1391 if (rc)
1392 goto err_out_disable;
1393
1394 /* disable all the interrupt bits */
1395 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1396
1397 rc = pm8001_request_irq(pm8001_ha);
1398 if (rc)
1399 goto err_out_disable;
1400
1401 pm8001_init_tasklet(pm8001_ha);
1402
1403 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1404 if (pm8001_ha->chip_id != chip_8001) {
1405 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1406 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1407 }
1408
1409 /* Chip documentation for the 8070 and 8072 SPCv */
1410 /* states that a 500ms minimum delay is required */
1411 /* before issuing commands. Otherwise, the firmware */
1412 /* will enter an unrecoverable state. */
1413
1414 if (pm8001_ha->chip_id == chip_8070 ||
1415 pm8001_ha->chip_id == chip_8072) {
1416 mdelay(500);
1417 }
1418
1419 /* Spin up the PHYs */
1420
1421 pm8001_ha->flags = PM8001F_RUN_TIME;
1422 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1423 pm8001_ha->phy[i].enable_completion = &completion;
1424 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1425 wait_for_completion(&completion);
1426 }
1427 sas_resume_ha(sha);
1428 return 0;
1429
1430 err_out_disable:
1431 scsi_remove_host(pm8001_ha->shost);
1432
1433 return rc;
1434 }
1435
1436 /* update of pci device, vendor id and driver data with
1437 * unique value for each of the controller
1438 */
1439 static const struct pci_device_id pm8001_pci_table[] = {
1440 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1441 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1442 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1443 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1444 /* Support for SPC/SPCv/SPCve controllers */
1445 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1446 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1447 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1448 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1449 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1450 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1451 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1452 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1453 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1454 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1455 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1456 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1457 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1458 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1459 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1460 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1461 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1462 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1463 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1464 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1465 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1466 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1467 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1468 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1469 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1470 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1471 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1472 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1473 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1474 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1475 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1476 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1477 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1478 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1479 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1480 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1481 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1482 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1483 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1484 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1485 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1486 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1487 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1488 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1489 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1490 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1491 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1492 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1493 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1494 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1495 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1496 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1497 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1498 { PCI_VENDOR_ID_ATTO, 0x8070,
1499 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1500 { PCI_VENDOR_ID_ATTO, 0x8070,
1501 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1502 { PCI_VENDOR_ID_ATTO, 0x8072,
1503 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1504 { PCI_VENDOR_ID_ATTO, 0x8072,
1505 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1506 { PCI_VENDOR_ID_ATTO, 0x8070,
1507 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1508 { PCI_VENDOR_ID_ATTO, 0x8072,
1509 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1510 { PCI_VENDOR_ID_ATTO, 0x8072,
1511 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1512 {} /* terminate list */
1513 };
1514
1515 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,
1516 pm8001_pci_suspend,
1517 pm8001_pci_resume);
1518
1519 static struct pci_driver pm8001_pci_driver = {
1520 .name = DRV_NAME,
1521 .id_table = pm8001_pci_table,
1522 .probe = pm8001_pci_probe,
1523 .remove = pm8001_pci_remove,
1524 .driver.pm = &pm8001_pci_pm_ops,
1525 };
1526
1527 /**
1528 * pm8001_init - initialize scsi transport template
1529 */
pm8001_init(void)1530 static int __init pm8001_init(void)
1531 {
1532 int rc = -ENOMEM;
1533
1534 if (pm8001_use_tasklet && !pm8001_use_msix)
1535 pm8001_use_tasklet = false;
1536
1537 pm8001_wq = alloc_workqueue("pm80xx", WQ_PERCPU, 0);
1538 if (!pm8001_wq)
1539 goto err;
1540
1541 pm8001_id = 0;
1542 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1543 if (!pm8001_stt)
1544 goto err_wq;
1545 rc = pci_register_driver(&pm8001_pci_driver);
1546 if (rc)
1547 goto err_tp;
1548 return 0;
1549
1550 err_tp:
1551 sas_release_transport(pm8001_stt);
1552 err_wq:
1553 destroy_workqueue(pm8001_wq);
1554 err:
1555 return rc;
1556 }
1557
pm8001_exit(void)1558 static void __exit pm8001_exit(void)
1559 {
1560 pci_unregister_driver(&pm8001_pci_driver);
1561 sas_release_transport(pm8001_stt);
1562 destroy_workqueue(pm8001_wq);
1563 }
1564
1565 module_init(pm8001_init);
1566 module_exit(pm8001_exit);
1567
1568 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1569 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1570 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1571 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1572 MODULE_DESCRIPTION(
1573 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1574 "SAS/SATA controller driver");
1575 MODULE_VERSION(DRV_VERSION);
1576 MODULE_LICENSE("GPL");
1577 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1578
1579