1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2016 Broadcom
4 */
5
6 #include <linux/device.h>
7 #include <linux/io.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 #include <linux/pci-ecam.h>
12 #include <linux/slab.h>
13
14 /*
15 * On 64-bit systems, we do a single ioremap for the whole config space
16 * since we have enough virtual address range available. On 32-bit, we
17 * ioremap the config space for each bus individually.
18 */
19 static const bool per_bus_mapping = !IS_ENABLED(CONFIG_64BIT);
20
21 /*
22 * Create a PCI config space window
23 * - reserve mem region
24 * - alloc struct pci_config_window with space for all mappings
25 * - ioremap the config space
26 */
pci_ecam_create(struct device * dev,struct resource * cfgres,struct resource * busr,const struct pci_ecam_ops * ops)27 struct pci_config_window *pci_ecam_create(struct device *dev,
28 struct resource *cfgres, struct resource *busr,
29 const struct pci_ecam_ops *ops)
30 {
31 unsigned int bus_shift = ops->bus_shift;
32 struct pci_config_window *cfg;
33 unsigned int bus_range, bus_range_max, bsz;
34 struct resource *conflict;
35 int err;
36
37 if (busr->start > busr->end)
38 return ERR_PTR(-EINVAL);
39
40 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
41 if (!cfg)
42 return ERR_PTR(-ENOMEM);
43
44 /* ECAM-compliant platforms need not supply ops->bus_shift */
45 if (!bus_shift)
46 bus_shift = PCIE_ECAM_BUS_SHIFT;
47
48 cfg->parent = dev;
49 cfg->ops = ops;
50 cfg->busr.start = busr->start;
51 cfg->busr.end = busr->end;
52 cfg->busr.flags = IORESOURCE_BUS;
53 cfg->bus_shift = bus_shift;
54 bus_range = resource_size(&cfg->busr);
55 bus_range_max = resource_size(cfgres) >> bus_shift;
56 if (bus_range > bus_range_max) {
57 bus_range = bus_range_max;
58 resource_set_size(&cfg->busr, bus_range);
59 dev_warn(dev, "ECAM area %pR can only accommodate %pR (reduced from %pR desired)\n",
60 cfgres, &cfg->busr, busr);
61 }
62 bsz = 1 << bus_shift;
63
64 cfg->res.start = cfgres->start;
65 cfg->res.end = cfgres->end;
66 cfg->res.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
67 cfg->res.name = "PCI ECAM";
68
69 conflict = request_resource_conflict(&iomem_resource, &cfg->res);
70 if (conflict) {
71 err = -EBUSY;
72 dev_err(dev, "can't claim ECAM area %pR: address conflict with %s %pR\n",
73 &cfg->res, conflict->name, conflict);
74 goto err_exit;
75 }
76
77 if (per_bus_mapping) {
78 cfg->winp = kcalloc(bus_range, sizeof(*cfg->winp), GFP_KERNEL);
79 if (!cfg->winp)
80 goto err_exit_malloc;
81 } else {
82 cfg->win = pci_remap_cfgspace(cfgres->start, bus_range * bsz);
83 if (!cfg->win)
84 goto err_exit_iomap;
85 }
86
87 cfg->priv = dev_get_drvdata(dev);
88
89 if (ops->init) {
90 err = ops->init(cfg);
91 if (err)
92 goto err_exit;
93 }
94 dev_info(dev, "ECAM at %pR for %pR\n", &cfg->res, &cfg->busr);
95 return cfg;
96
97 err_exit_iomap:
98 dev_err(dev, "ECAM ioremap failed\n");
99 err_exit_malloc:
100 err = -ENOMEM;
101 err_exit:
102 pci_ecam_free(cfg);
103 return ERR_PTR(err);
104 }
105 EXPORT_SYMBOL_GPL(pci_ecam_create);
106
pci_ecam_free(struct pci_config_window * cfg)107 void pci_ecam_free(struct pci_config_window *cfg)
108 {
109 int i;
110
111 if (per_bus_mapping) {
112 if (cfg->winp) {
113 for (i = 0; i < resource_size(&cfg->busr); i++)
114 if (cfg->winp[i])
115 iounmap(cfg->winp[i]);
116 kfree(cfg->winp);
117 }
118 } else {
119 if (cfg->win)
120 iounmap(cfg->win);
121 }
122 if (cfg->res.parent)
123 release_resource(&cfg->res);
124 kfree(cfg);
125 }
126 EXPORT_SYMBOL_GPL(pci_ecam_free);
127
pci_ecam_add_bus(struct pci_bus * bus)128 static int pci_ecam_add_bus(struct pci_bus *bus)
129 {
130 struct pci_config_window *cfg = bus->sysdata;
131 unsigned int bsz = 1 << cfg->bus_shift;
132 unsigned int busn = bus->number;
133 phys_addr_t start;
134
135 if (!per_bus_mapping)
136 return 0;
137
138 if (busn < cfg->busr.start || busn > cfg->busr.end)
139 return -EINVAL;
140
141 busn -= cfg->busr.start;
142 start = cfg->res.start + busn * bsz;
143
144 cfg->winp[busn] = pci_remap_cfgspace(start, bsz);
145 if (!cfg->winp[busn])
146 return -ENOMEM;
147
148 return 0;
149 }
150
pci_ecam_remove_bus(struct pci_bus * bus)151 static void pci_ecam_remove_bus(struct pci_bus *bus)
152 {
153 struct pci_config_window *cfg = bus->sysdata;
154 unsigned int busn = bus->number;
155
156 if (!per_bus_mapping || busn < cfg->busr.start || busn > cfg->busr.end)
157 return;
158
159 busn -= cfg->busr.start;
160 if (cfg->winp[busn]) {
161 iounmap(cfg->winp[busn]);
162 cfg->winp[busn] = NULL;
163 }
164 }
165
166 /*
167 * Function to implement the pci_ops ->map_bus method
168 */
pci_ecam_map_bus(struct pci_bus * bus,unsigned int devfn,int where)169 void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn,
170 int where)
171 {
172 struct pci_config_window *cfg = bus->sysdata;
173 unsigned int bus_shift = cfg->ops->bus_shift;
174 unsigned int devfn_shift = cfg->ops->bus_shift - 8;
175 unsigned int busn = bus->number;
176 void __iomem *base;
177 u32 bus_offset, devfn_offset;
178
179 if (busn < cfg->busr.start || busn > cfg->busr.end)
180 return NULL;
181
182 busn -= cfg->busr.start;
183 if (per_bus_mapping) {
184 base = cfg->winp[busn];
185 busn = 0;
186 } else
187 base = cfg->win;
188
189 if (cfg->ops->bus_shift) {
190 bus_offset = (busn & PCIE_ECAM_BUS_MASK) << bus_shift;
191 devfn_offset = (devfn & PCIE_ECAM_DEVFN_MASK) << devfn_shift;
192 where &= PCIE_ECAM_REG_MASK;
193
194 return base + (bus_offset | devfn_offset | where);
195 }
196
197 return base + PCIE_ECAM_OFFSET(busn, devfn, where);
198 }
199 EXPORT_SYMBOL_GPL(pci_ecam_map_bus);
200
201 /* ECAM ops */
202 const struct pci_ecam_ops pci_generic_ecam_ops = {
203 .pci_ops = {
204 .add_bus = pci_ecam_add_bus,
205 .remove_bus = pci_ecam_remove_bus,
206 .map_bus = pci_ecam_map_bus,
207 .read = pci_generic_config_read,
208 .write = pci_generic_config_write,
209 }
210 };
211 EXPORT_SYMBOL_GPL(pci_generic_ecam_ops);
212
213 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
214 /* ECAM ops for 32-bit access only (non-compliant) */
215 const struct pci_ecam_ops pci_32b_ops = {
216 .pci_ops = {
217 .add_bus = pci_ecam_add_bus,
218 .remove_bus = pci_ecam_remove_bus,
219 .map_bus = pci_ecam_map_bus,
220 .read = pci_generic_config_read32,
221 .write = pci_generic_config_write32,
222 }
223 };
224
225 /* ECAM ops for 32-bit read only (non-compliant) */
226 const struct pci_ecam_ops pci_32b_read_ops = {
227 .pci_ops = {
228 .add_bus = pci_ecam_add_bus,
229 .remove_bus = pci_ecam_remove_bus,
230 .map_bus = pci_ecam_map_bus,
231 .read = pci_generic_config_read32,
232 .write = pci_generic_config_write,
233 }
234 };
235 #endif
236