1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/math.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/tty.h>
18 #include <linux/serial_reg.h>
19 #include <linux/serial_core.h>
20 #include <linux/8250_pci.h>
21 #include <linux/bitops.h>
22 #include <linux/bitfield.h>
23
24 #include <asm/byteorder.h>
25 #include <asm/io.h>
26
27 #include "8250.h"
28 #include "8250_pcilib.h"
29
30 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
31 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
32 #define PCI_DEVICE_ID_OCTPRO 0x0001
33 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
34 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
35 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
36 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
37 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
38 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
39 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
40 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
41 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
42 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
43 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
44 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
45 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
46 #define PCI_DEVICE_ID_TITAN_200I 0x8028
47 #define PCI_DEVICE_ID_TITAN_400I 0x8048
48 #define PCI_DEVICE_ID_TITAN_800I 0x8088
49 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
50 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
51 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
52 #define PCI_DEVICE_ID_TITAN_100E 0xA010
53 #define PCI_DEVICE_ID_TITAN_200E 0xA012
54 #define PCI_DEVICE_ID_TITAN_400E 0xA013
55 #define PCI_DEVICE_ID_TITAN_800E 0xA014
56 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
57 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
58 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
59 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
60 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
61 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
62 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
63 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
64 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
65 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
66 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
67
68 #define PCI_DEVICE_ID_WCHCN_CH352_2S 0x3253
69 #define PCI_DEVICE_ID_WCHCN_CH355_4S 0x7173
70
71 #define PCI_VENDOR_ID_AGESTAR 0x5372
72 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
73 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
74 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
75
76 #define PCI_DEVICE_ID_WCHIC_CH384_4S 0x3470
77 #define PCI_DEVICE_ID_WCHIC_CH384_8S 0x3853
78
79 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
80 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
81 #define PCI_DEVICE_ID_MOXA_CP102N 0x1027
82 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
83 #define PCI_DEVICE_ID_MOXA_CP104N 0x1046
84 #define PCI_DEVICE_ID_MOXA_CP112N 0x1121
85 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
86 #define PCI_DEVICE_ID_MOXA_CP114N 0x1145
87 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
88 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
89 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
90 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
91 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
92 #define PCI_DEVICE_ID_MOXA_CP132N 0x1323
93 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
94 #define PCI_DEVICE_ID_MOXA_CP134N 0x1343
95 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
96 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
97
98 #define PCI_DEVICE_ID_ADDIDATA_CPCI7500 0x7003
99 #define PCI_DEVICE_ID_ADDIDATA_CPCI7500_NG 0x7024
100 #define PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG 0x7025
101 #define PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG 0x7026
102
103 #define PCI_VENDOR_ID_SYSTEMBASE 0x14a1
104
105 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
106 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
107 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
108
109 /*
110 * init function returns:
111 * > 0 - number of ports
112 * = 0 - use board->num_ports
113 * < 0 - error
114 */
115 struct pci_serial_quirk {
116 u32 vendor;
117 u32 device;
118 u32 subvendor;
119 u32 subdevice;
120 int (*probe)(struct pci_dev *dev);
121 int (*init)(struct pci_dev *dev);
122 int (*setup)(struct serial_private *,
123 const struct pciserial_board *,
124 struct uart_8250_port *, int);
125 void (*exit)(struct pci_dev *dev);
126 };
127
128 struct f815xxa_data {
129 spinlock_t lock;
130 int idx;
131 };
132
133 struct serial_private {
134 struct pci_dev *dev;
135 unsigned int nr;
136 struct pci_serial_quirk *quirk;
137 const struct pciserial_board *board;
138 int line[];
139 };
140
141 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
142 #define PCIE_VENDOR_ID_ASIX 0x125B
143 #define PCIE_DEVICE_ID_AX99100 0x9100
144
145 static const struct pci_device_id pci_use_msi[] = {
146 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
147 0xA000, 0x1000) },
148 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
149 0xA000, 0x1000) },
150 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
151 0xA000, 0x1000) },
152 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
153 0xA000, 0x1000) },
154 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
155 PCI_ANY_ID, PCI_ANY_ID) },
156 { PCI_DEVICE_SUB(PCIE_VENDOR_ID_ASIX, PCIE_DEVICE_ID_AX99100,
157 0xA000, 0x1000) },
158 { }
159 };
160
161 static int pci_default_setup(struct serial_private*,
162 const struct pciserial_board*, struct uart_8250_port *, int);
163
moan_device(const char * str,struct pci_dev * dev)164 static void moan_device(const char *str, struct pci_dev *dev)
165 {
166 pci_err(dev, "%s\n"
167 "Please send the output of lspci -vv, this\n"
168 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
169 "manufacturer and name of serial board or\n"
170 "modem board to <linux-serial@vger.kernel.org>.\n",
171 str, dev->vendor, dev->device,
172 dev->subsystem_vendor, dev->subsystem_device);
173 }
174
175 static int
setup_port(struct serial_private * priv,struct uart_8250_port * port,u8 bar,unsigned int offset,int regshift)176 setup_port(struct serial_private *priv, struct uart_8250_port *port,
177 u8 bar, unsigned int offset, int regshift)
178 {
179 void __iomem *iomem = NULL;
180
181 if (pci_resource_flags(priv->dev, bar) & IORESOURCE_MEM) {
182 iomem = pcim_iomap(priv->dev, bar, 0);
183 if (!iomem)
184 return -ENOMEM;
185 }
186
187 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift, iomem);
188 }
189
190 /*
191 * ADDI-DATA GmbH communication cards <info@addi-data.com>
192 */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)193 static int addidata_apci7800_setup(struct serial_private *priv,
194 const struct pciserial_board *board,
195 struct uart_8250_port *port, int idx)
196 {
197 unsigned int bar = 0, offset = board->first_offset;
198 bar = FL_GET_BASE(board->flags);
199
200 if (idx < 2) {
201 offset += idx * board->uart_offset;
202 } else if ((idx >= 2) && (idx < 4)) {
203 bar += 1;
204 offset += ((idx - 2) * board->uart_offset);
205 } else if ((idx >= 4) && (idx < 6)) {
206 bar += 2;
207 offset += ((idx - 4) * board->uart_offset);
208 } else if (idx >= 6) {
209 bar += 3;
210 offset += ((idx - 6) * board->uart_offset);
211 }
212
213 return setup_port(priv, port, bar, offset, board->reg_shift);
214 }
215
216 /*
217 * AFAVLAB uses a different mixture of BARs and offsets
218 * Not that ugly ;) -- HW
219 */
220 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)221 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
222 struct uart_8250_port *port, int idx)
223 {
224 unsigned int bar, offset = board->first_offset;
225
226 bar = FL_GET_BASE(board->flags);
227 if (idx < 4)
228 bar += idx;
229 else {
230 bar = 4;
231 offset += (idx - 4) * board->uart_offset;
232 }
233
234 return setup_port(priv, port, bar, offset, board->reg_shift);
235 }
236
237 /*
238 * HP's Remote Management Console. The Diva chip came in several
239 * different versions. N-class, L2000 and A500 have two Diva chips, each
240 * with 3 UARTs (the third UART on the second chip is unused). Superdome
241 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
242 * one Diva chip, but it has been expanded to 5 UARTs.
243 */
pci_hp_diva_init(struct pci_dev * dev)244 static int pci_hp_diva_init(struct pci_dev *dev)
245 {
246 int rc = 0;
247
248 switch (dev->subsystem_device) {
249 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
250 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
251 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
252 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
253 rc = 3;
254 break;
255 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
256 rc = 2;
257 break;
258 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
259 rc = 4;
260 break;
261 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
262 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
263 rc = 1;
264 break;
265 }
266
267 return rc;
268 }
269
270 /*
271 * HP's Diva chip puts the 4th/5th serial port further out, and
272 * some serial ports are supposed to be hidden on certain models.
273 */
274 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)275 pci_hp_diva_setup(struct serial_private *priv,
276 const struct pciserial_board *board,
277 struct uart_8250_port *port, int idx)
278 {
279 unsigned int offset = board->first_offset;
280 unsigned int bar = FL_GET_BASE(board->flags);
281
282 switch (priv->dev->subsystem_device) {
283 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
284 if (idx == 3)
285 idx++;
286 break;
287 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
288 if (idx > 0)
289 idx++;
290 if (idx > 2)
291 idx++;
292 break;
293 }
294 if (idx > 2)
295 offset = 0x18;
296
297 offset += idx * board->uart_offset;
298
299 return setup_port(priv, port, bar, offset, board->reg_shift);
300 }
301
302 /*
303 * Added for EKF Intel i960 serial boards
304 */
pci_inteli960ni_init(struct pci_dev * dev)305 static int pci_inteli960ni_init(struct pci_dev *dev)
306 {
307 u32 oldval;
308
309 if (!(dev->subsystem_device & 0x1000))
310 return -ENODEV;
311
312 /* is firmware started? */
313 pci_read_config_dword(dev, 0x44, &oldval);
314 if (oldval == 0x00001000L) { /* RESET value */
315 pci_dbg(dev, "Local i960 firmware missing\n");
316 return -ENODEV;
317 }
318 return 0;
319 }
320
321 /*
322 * Some PCI serial cards using the PLX 9050 PCI interface chip require
323 * that the card interrupt be explicitly enabled or disabled. This
324 * seems to be mainly needed on card using the PLX which also use I/O
325 * mapped memory.
326 */
pci_plx9050_init(struct pci_dev * dev)327 static int pci_plx9050_init(struct pci_dev *dev)
328 {
329 u8 irq_config;
330 void __iomem *p;
331
332 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
333 moan_device("no memory in bar 0", dev);
334 return 0;
335 }
336
337 irq_config = 0x41;
338 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
339 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
340 irq_config = 0x43;
341
342 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
343 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
344 /*
345 * As the megawolf cards have the int pins active
346 * high, and have 2 UART chips, both ints must be
347 * enabled on the 9050. Also, the UARTS are set in
348 * 16450 mode by default, so we have to enable the
349 * 16C950 'enhanced' mode so that we can use the
350 * deep FIFOs
351 */
352 irq_config = 0x5b;
353 /*
354 * enable/disable interrupts
355 */
356 p = ioremap(pci_resource_start(dev, 0), 0x80);
357 if (p == NULL)
358 return -ENOMEM;
359 writel(irq_config, p + 0x4c);
360
361 /*
362 * Read the register back to ensure that it took effect.
363 */
364 readl(p + 0x4c);
365 iounmap(p);
366
367 return 0;
368 }
369
pci_plx9050_exit(struct pci_dev * dev)370 static void pci_plx9050_exit(struct pci_dev *dev)
371 {
372 u8 __iomem *p;
373
374 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
375 return;
376
377 /*
378 * disable interrupts
379 */
380 p = ioremap(pci_resource_start(dev, 0), 0x80);
381 if (p != NULL) {
382 writel(0, p + 0x4c);
383
384 /*
385 * Read the register back to ensure that it took effect.
386 */
387 readl(p + 0x4c);
388 iounmap(p);
389 }
390 }
391
392 #define NI8420_INT_ENABLE_REG 0x38
393 #define NI8420_INT_ENABLE_BIT 0x2000
394
pci_ni8420_exit(struct pci_dev * dev)395 static void pci_ni8420_exit(struct pci_dev *dev)
396 {
397 void __iomem *p;
398 unsigned int bar = 0;
399
400 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
401 moan_device("no memory in bar", dev);
402 return;
403 }
404
405 p = pci_ioremap_bar(dev, bar);
406 if (p == NULL)
407 return;
408
409 /* Disable the CPU Interrupt */
410 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
411 p + NI8420_INT_ENABLE_REG);
412 iounmap(p);
413 }
414
415
416 /* MITE registers */
417 #define MITE_IOWBSR1 0xc4
418 #define MITE_IOWCR1 0xf4
419 #define MITE_LCIMR1 0x08
420 #define MITE_LCIMR2 0x10
421
422 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
423
pci_ni8430_exit(struct pci_dev * dev)424 static void pci_ni8430_exit(struct pci_dev *dev)
425 {
426 void __iomem *p;
427 unsigned int bar = 0;
428
429 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
430 moan_device("no memory in bar", dev);
431 return;
432 }
433
434 p = pci_ioremap_bar(dev, bar);
435 if (p == NULL)
436 return;
437
438 /* Disable the CPU Interrupt */
439 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
440 iounmap(p);
441 }
442
443 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
444 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)445 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
446 struct uart_8250_port *port, int idx)
447 {
448 unsigned int bar, offset = board->first_offset;
449
450 bar = 0;
451
452 if (idx < 4) {
453 /* first four channels map to 0, 0x100, 0x200, 0x300 */
454 offset += idx * board->uart_offset;
455 } else if (idx < 8) {
456 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
457 offset += idx * board->uart_offset + 0xC00;
458 } else /* we have only 8 ports on PMC-OCTALPRO */
459 return 1;
460
461 return setup_port(priv, port, bar, offset, board->reg_shift);
462 }
463
464 /*
465 * This does initialization for PMC OCTALPRO cards:
466 * maps the device memory, resets the UARTs (needed, bc
467 * if the module is removed and inserted again, the card
468 * is in the sleep mode) and enables global interrupt.
469 */
470
471 /* global control register offset for SBS PMC-OctalPro */
472 #define OCT_REG_CR_OFF 0x500
473
sbs_init(struct pci_dev * dev)474 static int sbs_init(struct pci_dev *dev)
475 {
476 u8 __iomem *p;
477
478 p = pci_ioremap_bar(dev, 0);
479
480 if (p == NULL)
481 return -ENOMEM;
482 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
483 writeb(0x10, p + OCT_REG_CR_OFF);
484 udelay(50);
485 writeb(0x0, p + OCT_REG_CR_OFF);
486
487 /* Set bit-2 (INTENABLE) of Control Register */
488 writeb(0x4, p + OCT_REG_CR_OFF);
489 iounmap(p);
490
491 return 0;
492 }
493
494 /*
495 * Disables the global interrupt of PMC-OctalPro
496 */
497
sbs_exit(struct pci_dev * dev)498 static void sbs_exit(struct pci_dev *dev)
499 {
500 u8 __iomem *p;
501
502 p = pci_ioremap_bar(dev, 0);
503 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
504 if (p != NULL)
505 writeb(0, p + OCT_REG_CR_OFF);
506 iounmap(p);
507 }
508
509 /*
510 * SIIG serial cards have an PCI interface chip which also controls
511 * the UART clocking frequency. Each UART can be clocked independently
512 * (except cards equipped with 4 UARTs) and initial clocking settings
513 * are stored in the EEPROM chip. It can cause problems because this
514 * version of serial driver doesn't support differently clocked UART's
515 * on single PCI card. To prevent this, initialization functions set
516 * high frequency clocking for all UART's on given card. It is safe (I
517 * hope) because it doesn't touch EEPROM settings to prevent conflicts
518 * with other OSes (like M$ DOS).
519 *
520 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
521 *
522 * There is two family of SIIG serial cards with different PCI
523 * interface chip and different configuration methods:
524 * - 10x cards have control registers in IO and/or memory space;
525 * - 20x cards have control registers in standard PCI configuration space.
526 *
527 * Note: all 10x cards have PCI device ids 0x10..
528 * all 20x cards have PCI device ids 0x20..
529 *
530 * There are also Quartet Serial cards which use Oxford Semiconductor
531 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
532 *
533 * Note: some SIIG cards are probed by the parport_serial object.
534 */
535
536 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
537 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
538
pci_siig10x_init(struct pci_dev * dev)539 static int pci_siig10x_init(struct pci_dev *dev)
540 {
541 u16 data;
542 void __iomem *p;
543
544 switch (dev->device & 0xfff8) {
545 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
546 data = 0xffdf;
547 break;
548 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
549 data = 0xf7ff;
550 break;
551 default: /* 1S1P, 4S */
552 data = 0xfffb;
553 break;
554 }
555
556 p = ioremap(pci_resource_start(dev, 0), 0x80);
557 if (p == NULL)
558 return -ENOMEM;
559
560 writew(readw(p + 0x28) & data, p + 0x28);
561 readw(p + 0x28);
562 iounmap(p);
563 return 0;
564 }
565
566 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
567 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
568
pci_siig20x_init(struct pci_dev * dev)569 static int pci_siig20x_init(struct pci_dev *dev)
570 {
571 u8 data;
572
573 /* Change clock frequency for the first UART. */
574 pci_read_config_byte(dev, 0x6f, &data);
575 pci_write_config_byte(dev, 0x6f, data & 0xef);
576
577 /* If this card has 2 UART, we have to do the same with second UART. */
578 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
579 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
580 pci_read_config_byte(dev, 0x73, &data);
581 pci_write_config_byte(dev, 0x73, data & 0xef);
582 }
583 return 0;
584 }
585
pci_siig_init(struct pci_dev * dev)586 static int pci_siig_init(struct pci_dev *dev)
587 {
588 unsigned int type = dev->device & 0xff00;
589
590 if (type == 0x1000)
591 return pci_siig10x_init(dev);
592 if (type == 0x2000)
593 return pci_siig20x_init(dev);
594
595 moan_device("Unknown SIIG card", dev);
596 return -ENODEV;
597 }
598
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)599 static int pci_siig_setup(struct serial_private *priv,
600 const struct pciserial_board *board,
601 struct uart_8250_port *port, int idx)
602 {
603 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
604
605 if (idx > 3) {
606 bar = 4;
607 offset = (idx - 4) * 8;
608 }
609
610 return setup_port(priv, port, bar, offset, 0);
611 }
612
613 /*
614 * Timedia has an explosion of boards, and to avoid the PCI table from
615 * growing *huge*, we use this function to collapse some 70 entries
616 * in the PCI table into one, for sanity's and compactness's sake.
617 */
618 static const unsigned short timedia_single_port[] = {
619 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
620 };
621
622 static const unsigned short timedia_dual_port[] = {
623 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
624 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
625 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
626 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
627 0xD079, 0
628 };
629
630 static const unsigned short timedia_quad_port[] = {
631 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
632 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
633 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
634 0xB157, 0
635 };
636
637 static const unsigned short timedia_eight_port[] = {
638 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
639 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
640 };
641
642 static const struct timedia_struct {
643 int num;
644 const unsigned short *ids;
645 } timedia_data[] = {
646 { 1, timedia_single_port },
647 { 2, timedia_dual_port },
648 { 4, timedia_quad_port },
649 { 8, timedia_eight_port }
650 };
651
652 /*
653 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
654 * listing them individually, this driver merely grabs them all with
655 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
656 * and should be left free to be claimed by parport_serial instead.
657 */
pci_timedia_probe(struct pci_dev * dev)658 static int pci_timedia_probe(struct pci_dev *dev)
659 {
660 /*
661 * Check the third digit of the subdevice ID
662 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
663 */
664 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
665 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n",
666 dev->subsystem_device);
667 return -ENODEV;
668 }
669
670 return 0;
671 }
672
pci_timedia_init(struct pci_dev * dev)673 static int pci_timedia_init(struct pci_dev *dev)
674 {
675 const unsigned short *ids;
676 int i, j;
677
678 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
679 ids = timedia_data[i].ids;
680 for (j = 0; ids[j]; j++)
681 if (dev->subsystem_device == ids[j])
682 return timedia_data[i].num;
683 }
684 return 0;
685 }
686
687 /*
688 * Timedia/SUNIX uses a mixture of BARs and offsets
689 * Ugh, this is ugly as all hell --- TYT
690 */
691 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)692 pci_timedia_setup(struct serial_private *priv,
693 const struct pciserial_board *board,
694 struct uart_8250_port *port, int idx)
695 {
696 unsigned int bar = 0, offset = board->first_offset;
697
698 switch (idx) {
699 case 0:
700 bar = 0;
701 break;
702 case 1:
703 offset = board->uart_offset;
704 bar = 0;
705 break;
706 case 2:
707 bar = 1;
708 break;
709 case 3:
710 offset = board->uart_offset;
711 fallthrough;
712 case 4: /* BAR 2 */
713 case 5: /* BAR 3 */
714 case 6: /* BAR 4 */
715 case 7: /* BAR 5 */
716 bar = idx - 2;
717 }
718
719 return setup_port(priv, port, bar, offset, board->reg_shift);
720 }
721
722 /*
723 * Some Titan cards are also a little weird
724 */
725 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)726 titan_400l_800l_setup(struct serial_private *priv,
727 const struct pciserial_board *board,
728 struct uart_8250_port *port, int idx)
729 {
730 unsigned int bar, offset = board->first_offset;
731
732 switch (idx) {
733 case 0:
734 bar = 1;
735 break;
736 case 1:
737 bar = 2;
738 break;
739 default:
740 bar = 4;
741 offset = (idx - 2) * board->uart_offset;
742 }
743
744 return setup_port(priv, port, bar, offset, board->reg_shift);
745 }
746
pci_xircom_init(struct pci_dev * dev)747 static int pci_xircom_init(struct pci_dev *dev)
748 {
749 msleep(100);
750 return 0;
751 }
752
pci_ni8420_init(struct pci_dev * dev)753 static int pci_ni8420_init(struct pci_dev *dev)
754 {
755 void __iomem *p;
756 unsigned int bar = 0;
757
758 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
759 moan_device("no memory in bar", dev);
760 return 0;
761 }
762
763 p = pci_ioremap_bar(dev, bar);
764 if (p == NULL)
765 return -ENOMEM;
766
767 /* Enable CPU Interrupt */
768 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
769 p + NI8420_INT_ENABLE_REG);
770
771 iounmap(p);
772 return 0;
773 }
774
775 #define MITE_IOWBSR1_WSIZE 0xa
776 #define MITE_IOWBSR1_WIN_OFFSET 0x800
777 #define MITE_IOWBSR1_WENAB (1 << 7)
778 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
779 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
780 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
781
pci_ni8430_init(struct pci_dev * dev)782 static int pci_ni8430_init(struct pci_dev *dev)
783 {
784 void __iomem *p;
785 struct pci_bus_region region;
786 u32 device_window;
787 unsigned int bar = 0;
788
789 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
790 moan_device("no memory in bar", dev);
791 return 0;
792 }
793
794 p = pci_ioremap_bar(dev, bar);
795 if (p == NULL)
796 return -ENOMEM;
797
798 /*
799 * Set device window address and size in BAR0, while acknowledging that
800 * the resource structure may contain a translated address that differs
801 * from the address the device responds to.
802 */
803 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
804 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
805 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
806 writel(device_window, p + MITE_IOWBSR1);
807
808 /* Set window access to go to RAMSEL IO address space */
809 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
810 p + MITE_IOWCR1);
811
812 /* Enable IO Bus Interrupt 0 */
813 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
814
815 /* Enable CPU Interrupt */
816 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
817
818 iounmap(p);
819 return 0;
820 }
821
822 /* UART Port Control Register */
823 #define NI8430_PORTCON 0x0f
824 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
825
826 static int
pci_ni8430_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)827 pci_ni8430_setup(struct serial_private *priv,
828 const struct pciserial_board *board,
829 struct uart_8250_port *port, int idx)
830 {
831 struct pci_dev *dev = priv->dev;
832 void __iomem *p;
833 unsigned int bar, offset = board->first_offset;
834
835 if (idx >= board->num_ports)
836 return 1;
837
838 bar = FL_GET_BASE(board->flags);
839 offset += idx * board->uart_offset;
840
841 p = pci_ioremap_bar(dev, bar);
842 if (!p)
843 return -ENOMEM;
844
845 /* enable the transceiver */
846 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
847 p + offset + NI8430_PORTCON);
848
849 iounmap(p);
850
851 return setup_port(priv, port, bar, offset, board->reg_shift);
852 }
853
pci_netmos_9900_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)854 static int pci_netmos_9900_setup(struct serial_private *priv,
855 const struct pciserial_board *board,
856 struct uart_8250_port *port, int idx)
857 {
858 unsigned int bar;
859
860 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
861 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
862 /* netmos apparently orders BARs by datasheet layout, so serial
863 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
864 */
865 bar = 3 * idx;
866
867 return setup_port(priv, port, bar, 0, board->reg_shift);
868 }
869
870 return pci_default_setup(priv, board, port, idx);
871 }
872
873 /* the 99xx series comes with a range of device IDs and a variety
874 * of capabilities:
875 *
876 * 9900 has varying capabilities and can cascade to sub-controllers
877 * (cascading should be purely internal)
878 * 9904 is hardwired with 4 serial ports
879 * 9912 and 9922 are hardwired with 2 serial ports
880 */
pci_netmos_9900_numports(struct pci_dev * dev)881 static int pci_netmos_9900_numports(struct pci_dev *dev)
882 {
883 unsigned int c = dev->class;
884 unsigned int pi;
885 unsigned short sub_serports;
886
887 pi = c & 0xff;
888
889 if (pi == 2)
890 return 1;
891
892 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
893 /* two possibilities: 0x30ps encodes number of parallel and
894 * serial ports, or 0x1000 indicates *something*. This is not
895 * immediately obvious, since the 2s1p+4s configuration seems
896 * to offer all functionality on functions 0..2, while still
897 * advertising the same function 3 as the 4s+2s1p config.
898 */
899 sub_serports = dev->subsystem_device & 0xf;
900 if (sub_serports > 0)
901 return sub_serports;
902
903 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
904 return 0;
905 }
906
907 moan_device("unknown NetMos/Mostech program interface", dev);
908 return 0;
909 }
910
pci_netmos_init(struct pci_dev * dev)911 static int pci_netmos_init(struct pci_dev *dev)
912 {
913 /* subdevice 0x00PS means <P> parallel, <S> serial */
914 unsigned int num_serial = dev->subsystem_device & 0xf;
915
916 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
917 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
918 return 0;
919
920 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
921 dev->subsystem_device == 0x0299)
922 return 0;
923
924 switch (dev->device) { /* FALLTHROUGH on all */
925 case PCI_DEVICE_ID_NETMOS_9904:
926 case PCI_DEVICE_ID_NETMOS_9912:
927 case PCI_DEVICE_ID_NETMOS_9922:
928 case PCI_DEVICE_ID_NETMOS_9900:
929 case PCIE_DEVICE_ID_AX99100:
930 num_serial = pci_netmos_9900_numports(dev);
931 break;
932
933 default:
934 break;
935 }
936
937 if (num_serial == 0) {
938 moan_device("unknown NetMos/Mostech device", dev);
939 return -ENODEV;
940 }
941
942 return num_serial;
943 }
944
945 /*
946 * These chips are available with optionally one parallel port and up to
947 * two serial ports. Unfortunately they all have the same product id.
948 *
949 * Basic configuration is done over a region of 32 I/O ports. The base
950 * ioport is called INTA or INTC, depending on docs/other drivers.
951 *
952 * The region of the 32 I/O ports is configured in POSIO0R...
953 */
954
955 /* registers */
956 #define ITE_887x_MISCR 0x9c
957 #define ITE_887x_INTCBAR 0x78
958 #define ITE_887x_UARTBAR 0x7c
959 #define ITE_887x_PS0BAR 0x10
960 #define ITE_887x_POSIO0 0x60
961
962 /* I/O space size */
963 #define ITE_887x_IOSIZE 32
964 /* I/O space size (bits 26-24; 8 bytes = 011b) */
965 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
966 /* I/O space size (bits 26-24; 32 bytes = 101b) */
967 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
968 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
969 #define ITE_887x_POSIO_SPEED (3 << 29)
970 /* enable IO_Space bit */
971 #define ITE_887x_POSIO_ENABLE (1 << 31)
972
973 /* inta_addr are the configuration addresses of the ITE */
974 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
pci_ite887x_init(struct pci_dev * dev)975 static int pci_ite887x_init(struct pci_dev *dev)
976 {
977 int ret, i, type;
978 struct resource *iobase = NULL;
979 u32 miscr, uartbar, ioport;
980
981 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
982 return serial_8250_warn_need_ioport(dev);
983
984 /* search for the base-ioport */
985 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) {
986 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
987 "ite887x");
988 if (iobase != NULL) {
989 /* write POSIO0R - speed | size | ioport */
990 pci_write_config_dword(dev, ITE_887x_POSIO0,
991 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
992 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
993 /* write INTCBAR - ioport */
994 pci_write_config_dword(dev, ITE_887x_INTCBAR,
995 inta_addr[i]);
996 ret = inb(inta_addr[i]);
997 if (ret != 0xff) {
998 /* ioport connected */
999 break;
1000 }
1001 release_region(iobase->start, ITE_887x_IOSIZE);
1002 }
1003 }
1004
1005 if (i == ARRAY_SIZE(inta_addr)) {
1006 pci_err(dev, "could not find iobase\n");
1007 return -ENODEV;
1008 }
1009
1010 /* start of undocumented type checking (see parport_pc.c) */
1011 type = inb(iobase->start + 0x18) & 0x0f;
1012
1013 switch (type) {
1014 case 0x2: /* ITE8871 (1P) */
1015 case 0xa: /* ITE8875 (1P) */
1016 ret = 0;
1017 break;
1018 case 0xe: /* ITE8872 (2S1P) */
1019 ret = 2;
1020 break;
1021 case 0x6: /* ITE8873 (1S) */
1022 ret = 1;
1023 break;
1024 case 0x8: /* ITE8874 (2S) */
1025 ret = 2;
1026 break;
1027 default:
1028 moan_device("Unknown ITE887x", dev);
1029 ret = -ENODEV;
1030 }
1031
1032 /* configure all serial ports */
1033 for (i = 0; i < ret; i++) {
1034 /* read the I/O port from the device */
1035 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
1036 &ioport);
1037 ioport &= 0x0000FF00; /* the actual base address */
1038 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
1039 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
1040 ITE_887x_POSIO_IOSIZE_8 | ioport);
1041
1042 /* write the ioport to the UARTBAR */
1043 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
1044 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
1045 uartbar |= (ioport << (16 * i)); /* set the ioport */
1046 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
1047
1048 /* get current config */
1049 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
1050 /* disable interrupts (UARTx_Routing[3:0]) */
1051 miscr &= ~(0xf << (12 - 4 * i));
1052 /* activate the UART (UARTx_En) */
1053 miscr |= 1 << (23 - i);
1054 /* write new config with activated UART */
1055 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
1056 }
1057
1058 if (ret <= 0) {
1059 /* the device has no UARTs if we get here */
1060 release_region(iobase->start, ITE_887x_IOSIZE);
1061 }
1062
1063 return ret;
1064 }
1065
pci_ite887x_exit(struct pci_dev * dev)1066 static void pci_ite887x_exit(struct pci_dev *dev)
1067 {
1068 u32 ioport;
1069 /* the ioport is bit 0-15 in POSIO0R */
1070 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1071 ioport &= 0xffff;
1072 release_region(ioport, ITE_887x_IOSIZE);
1073 }
1074
1075 /*
1076 * Oxford Semiconductor Inc.
1077 * Check if an OxSemi device is part of the Tornado range of devices.
1078 */
1079 #define PCI_VENDOR_ID_ENDRUN 0x7401
1080 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1081
pci_oxsemi_tornado_p(struct pci_dev * dev)1082 static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
1083 {
1084 /* OxSemi Tornado devices are all 0xCxxx */
1085 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1086 (dev->device & 0xf000) != 0xc000)
1087 return false;
1088
1089 /* EndRun devices are all 0xExxx */
1090 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1091 (dev->device & 0xf000) != 0xe000)
1092 return false;
1093
1094 return true;
1095 }
1096
1097 /*
1098 * Determine the number of ports available on a Tornado device.
1099 */
pci_oxsemi_tornado_init(struct pci_dev * dev)1100 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1101 {
1102 u8 __iomem *p;
1103 unsigned long deviceID;
1104 unsigned int number_uarts = 0;
1105
1106 if (!pci_oxsemi_tornado_p(dev))
1107 return 0;
1108
1109 p = pci_iomap(dev, 0, 5);
1110 if (p == NULL)
1111 return -ENOMEM;
1112
1113 deviceID = ioread32(p);
1114 /* Tornado device */
1115 if (deviceID == 0x07000200) {
1116 number_uarts = ioread8(p + 4);
1117 pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
1118 number_uarts,
1119 dev->vendor == PCI_VENDOR_ID_ENDRUN ?
1120 "EndRun" : "Oxford");
1121 }
1122 pci_iounmap(dev, p);
1123 return number_uarts;
1124 }
1125
1126 /* Tornado-specific constants for the TCR and CPR registers; see below. */
1127 #define OXSEMI_TORNADO_TCR_MASK 0xf
1128 #define OXSEMI_TORNADO_CPR_MASK 0x1ff
1129 #define OXSEMI_TORNADO_CPR_MIN 0x008
1130 #define OXSEMI_TORNADO_CPR_DEF 0x10f
1131
1132 /*
1133 * Determine the oversampling rate, the clock prescaler, and the clock
1134 * divisor for the requested baud rate. The clock rate is 62.5 MHz,
1135 * which is four times the baud base, and the prescaler increments in
1136 * steps of 1/8. Therefore to make calculations on integers we need
1137 * to use a scaled clock rate, which is the baud base multiplied by 32
1138 * (or our assumed UART clock rate multiplied by 2).
1139 *
1140 * The allowed oversampling rates are from 4 up to 16 inclusive (values
1141 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows
1142 * values between 1.000 and 63.875 inclusive (operation for values from
1143 * 0.000 to 0.875 has not been specified). The clock divisor is the usual
1144 * unsigned 16-bit integer.
1145 *
1146 * For the most accurate baud rate we use a table of predetermined
1147 * oversampling rates and clock prescalers that records all possible
1148 * products of the two parameters in the range from 4 up to 255 inclusive,
1149 * and additionally 335 for the 1500000bps rate, with the prescaler scaled
1150 * by 8. The table is sorted by the decreasing value of the oversampling
1151 * rate and ties are resolved by sorting by the decreasing value of the
1152 * product. This way preference is given to higher oversampling rates.
1153 *
1154 * We iterate over the table and choose the product of an oversampling
1155 * rate and a clock prescaler that gives the lowest integer division
1156 * result deviation, or if an exact integer divider is found we stop
1157 * looking for it right away. We do some fixup if the resulting clock
1158 * divisor required would be out of its unsigned 16-bit integer range.
1159 *
1160 * Finally we abuse the supposed fractional part returned to encode the
1161 * 4-bit value of the oversampling rate and the 9-bit value of the clock
1162 * prescaler which will end up in the TCR and CPR/CPR2 registers.
1163 */
pci_oxsemi_tornado_get_divisor(struct uart_port * port,unsigned int baud,unsigned int * frac)1164 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port,
1165 unsigned int baud,
1166 unsigned int *frac)
1167 {
1168 static u8 p[][2] = {
1169 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, },
1170 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, },
1171 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, },
1172 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, },
1173 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, },
1174 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, },
1175 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, },
1176 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, },
1177 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, },
1178 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, },
1179 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, },
1180 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, },
1181 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, },
1182 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, },
1183 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, },
1184 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, },
1185 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, },
1186 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, },
1187 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, },
1188 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, },
1189 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, },
1190 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, },
1191 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, },
1192 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, },
1193 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, },
1194 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, },
1195 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, },
1196 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, },
1197 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, },
1198 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, },
1199 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, },
1200 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, },
1201 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, },
1202 { 4, 9, }, { 4, 8, },
1203 };
1204 /* Scale the quotient for comparison to get the fractional part. */
1205 const unsigned int quot_scale = 65536;
1206 unsigned int sclk = port->uartclk * 2;
1207 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud);
1208 unsigned int best_squot;
1209 unsigned int squot;
1210 unsigned int quot;
1211 u16 cpr;
1212 u8 tcr;
1213 int i;
1214
1215 best_squot = quot_scale;
1216 for (i = 0; i < ARRAY_SIZE(p); i++) {
1217 unsigned int spre;
1218 unsigned int srem;
1219 u8 cp;
1220 u8 tc;
1221
1222 tc = p[i][0];
1223 cp = p[i][1];
1224 spre = tc * cp;
1225
1226 srem = sdiv % spre;
1227 if (srem > spre / 2)
1228 srem = spre - srem;
1229 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre);
1230
1231 if (srem == 0) {
1232 tcr = tc;
1233 cpr = cp;
1234 quot = sdiv / spre;
1235 break;
1236 } else if (squot < best_squot) {
1237 best_squot = squot;
1238 tcr = tc;
1239 cpr = cp;
1240 quot = DIV_ROUND_CLOSEST(sdiv, spre);
1241 }
1242 }
1243 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 &&
1244 quot % 2 == 0) {
1245 quot >>= 1;
1246 tcr <<= 1;
1247 }
1248 while (quot > UART_DIV_MAX) {
1249 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) {
1250 quot >>= 1;
1251 tcr <<= 1;
1252 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) {
1253 quot >>= 1;
1254 cpr <<= 1;
1255 } else {
1256 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK;
1257 cpr = OXSEMI_TORNADO_CPR_MASK;
1258 }
1259 }
1260
1261 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK);
1262 return quot;
1263 }
1264
1265 /*
1266 * Set the oversampling rate in the transmitter clock cycle register (TCR),
1267 * the clock prescaler in the clock prescaler register (CPR and CPR2), and
1268 * the clock divisor in the divisor latch (DLL and DLM). Note that for
1269 * backwards compatibility any write to CPR clears CPR2 and therefore CPR
1270 * has to be written first, followed by CPR2, which occupies the location
1271 * of CKS used with earlier UART designs.
1272 */
pci_oxsemi_tornado_set_divisor(struct uart_port * port,unsigned int baud,unsigned int quot,unsigned int quot_frac)1273 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port,
1274 unsigned int baud,
1275 unsigned int quot,
1276 unsigned int quot_frac)
1277 {
1278 struct uart_8250_port *up = up_to_u8250p(port);
1279 u8 cpr2 = quot_frac >> 16;
1280 u8 cpr = quot_frac >> 8;
1281 u8 tcr = quot_frac;
1282
1283 serial_icr_write(up, UART_TCR, tcr);
1284 serial_icr_write(up, UART_CPR, cpr);
1285 serial_icr_write(up, UART_CKS, cpr2);
1286 serial8250_do_set_divisor(port, baud, quot);
1287 }
1288
1289 /*
1290 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate
1291 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used.
1292 */
pci_oxsemi_tornado_set_mctrl(struct uart_port * port,unsigned int mctrl)1293 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port,
1294 unsigned int mctrl)
1295 {
1296 struct uart_8250_port *up = up_to_u8250p(port);
1297
1298 up->mcr |= UART_MCR_CLKSEL;
1299 serial8250_do_set_mctrl(port, mctrl);
1300 }
1301
1302 /*
1303 * We require EFR features for clock programming, so set UPF_FULL_PROBE
1304 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting.
1305 */
pci_oxsemi_tornado_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * up,int idx)1306 static int pci_oxsemi_tornado_setup(struct serial_private *priv,
1307 const struct pciserial_board *board,
1308 struct uart_8250_port *up, int idx)
1309 {
1310 struct pci_dev *dev = priv->dev;
1311
1312 if (pci_oxsemi_tornado_p(dev)) {
1313 up->port.flags |= UPF_FULL_PROBE;
1314 up->port.get_divisor = pci_oxsemi_tornado_get_divisor;
1315 up->port.set_divisor = pci_oxsemi_tornado_set_divisor;
1316 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl;
1317 }
1318
1319 return pci_default_setup(priv, board, up, idx);
1320 }
1321
1322 #define QPCR_TEST_FOR1 0x3F
1323 #define QPCR_TEST_GET1 0x00
1324 #define QPCR_TEST_FOR2 0x40
1325 #define QPCR_TEST_GET2 0x40
1326 #define QPCR_TEST_FOR3 0x80
1327 #define QPCR_TEST_GET3 0x40
1328 #define QPCR_TEST_FOR4 0xC0
1329 #define QPCR_TEST_GET4 0x80
1330
1331 #define QOPR_CLOCK_X1 0x0000
1332 #define QOPR_CLOCK_X2 0x0001
1333 #define QOPR_CLOCK_X4 0x0002
1334 #define QOPR_CLOCK_X8 0x0003
1335 #define QOPR_CLOCK_RATE_MASK 0x0003
1336
1337 /* Quatech devices have their own extra interface features */
1338 static struct pci_device_id quatech_cards[] = {
1339 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) },
1340 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) },
1341 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) },
1342 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) },
1343 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) },
1344 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) },
1345 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) },
1346 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) },
1347 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) },
1348 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) },
1349 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) },
1350 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) },
1351 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) },
1352 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) },
1353 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) },
1354 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) },
1355 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) },
1356 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) },
1357 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) },
1358 { 0, }
1359 };
1360
pci_quatech_rqopr(struct uart_8250_port * port)1361 static int pci_quatech_rqopr(struct uart_8250_port *port)
1362 {
1363 unsigned long base = port->port.iobase;
1364 u8 LCR, val;
1365
1366 LCR = inb(base + UART_LCR);
1367 outb(0xBF, base + UART_LCR);
1368 val = inb(base + UART_SCR);
1369 outb(LCR, base + UART_LCR);
1370 return val;
1371 }
1372
pci_quatech_wqopr(struct uart_8250_port * port,u8 qopr)1373 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1374 {
1375 unsigned long base = port->port.iobase;
1376 u8 LCR;
1377
1378 LCR = inb(base + UART_LCR);
1379 outb(0xBF, base + UART_LCR);
1380 inb(base + UART_SCR);
1381 outb(qopr, base + UART_SCR);
1382 outb(LCR, base + UART_LCR);
1383 }
1384
pci_quatech_rqmcr(struct uart_8250_port * port)1385 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1386 {
1387 unsigned long base = port->port.iobase;
1388 u8 LCR, val, qmcr;
1389
1390 LCR = inb(base + UART_LCR);
1391 outb(0xBF, base + UART_LCR);
1392 val = inb(base + UART_SCR);
1393 outb(val | 0x10, base + UART_SCR);
1394 qmcr = inb(base + UART_MCR);
1395 outb(val, base + UART_SCR);
1396 outb(LCR, base + UART_LCR);
1397
1398 return qmcr;
1399 }
1400
pci_quatech_wqmcr(struct uart_8250_port * port,u8 qmcr)1401 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1402 {
1403 unsigned long base = port->port.iobase;
1404 u8 LCR, val;
1405
1406 LCR = inb(base + UART_LCR);
1407 outb(0xBF, base + UART_LCR);
1408 val = inb(base + UART_SCR);
1409 outb(val | 0x10, base + UART_SCR);
1410 outb(qmcr, base + UART_MCR);
1411 outb(val, base + UART_SCR);
1412 outb(LCR, base + UART_LCR);
1413 }
1414
pci_quatech_has_qmcr(struct uart_8250_port * port)1415 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1416 {
1417 unsigned long base = port->port.iobase;
1418 u8 LCR, val;
1419
1420 LCR = inb(base + UART_LCR);
1421 outb(0xBF, base + UART_LCR);
1422 val = inb(base + UART_SCR);
1423 if (val & 0x20) {
1424 outb(0x80, UART_LCR);
1425 if (!(inb(UART_SCR) & 0x20)) {
1426 outb(LCR, base + UART_LCR);
1427 return 1;
1428 }
1429 }
1430 return 0;
1431 }
1432
pci_quatech_test(struct uart_8250_port * port)1433 static int pci_quatech_test(struct uart_8250_port *port)
1434 {
1435 u8 reg, qopr;
1436
1437 qopr = pci_quatech_rqopr(port);
1438 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1439 reg = pci_quatech_rqopr(port) & 0xC0;
1440 if (reg != QPCR_TEST_GET1)
1441 return -EINVAL;
1442 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1443 reg = pci_quatech_rqopr(port) & 0xC0;
1444 if (reg != QPCR_TEST_GET2)
1445 return -EINVAL;
1446 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1447 reg = pci_quatech_rqopr(port) & 0xC0;
1448 if (reg != QPCR_TEST_GET3)
1449 return -EINVAL;
1450 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1451 reg = pci_quatech_rqopr(port) & 0xC0;
1452 if (reg != QPCR_TEST_GET4)
1453 return -EINVAL;
1454
1455 pci_quatech_wqopr(port, qopr);
1456 return 0;
1457 }
1458
pci_quatech_clock(struct uart_8250_port * port)1459 static int pci_quatech_clock(struct uart_8250_port *port)
1460 {
1461 u8 qopr, reg, set;
1462 unsigned long clock;
1463
1464 if (pci_quatech_test(port) < 0)
1465 return 1843200;
1466
1467 qopr = pci_quatech_rqopr(port);
1468
1469 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1470 reg = pci_quatech_rqopr(port);
1471 if (reg & QOPR_CLOCK_X8) {
1472 clock = 1843200;
1473 goto out;
1474 }
1475 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1476 reg = pci_quatech_rqopr(port);
1477 if (!(reg & QOPR_CLOCK_X8)) {
1478 clock = 1843200;
1479 goto out;
1480 }
1481 reg &= QOPR_CLOCK_X8;
1482 if (reg == QOPR_CLOCK_X2) {
1483 clock = 3685400;
1484 set = QOPR_CLOCK_X2;
1485 } else if (reg == QOPR_CLOCK_X4) {
1486 clock = 7372800;
1487 set = QOPR_CLOCK_X4;
1488 } else if (reg == QOPR_CLOCK_X8) {
1489 clock = 14745600;
1490 set = QOPR_CLOCK_X8;
1491 } else {
1492 clock = 1843200;
1493 set = QOPR_CLOCK_X1;
1494 }
1495 qopr &= ~QOPR_CLOCK_RATE_MASK;
1496 qopr |= set;
1497
1498 out:
1499 pci_quatech_wqopr(port, qopr);
1500 return clock;
1501 }
1502
pci_quatech_rs422(struct uart_8250_port * port)1503 static int pci_quatech_rs422(struct uart_8250_port *port)
1504 {
1505 u8 qmcr;
1506 int rs422 = 0;
1507
1508 if (!pci_quatech_has_qmcr(port))
1509 return 0;
1510 qmcr = pci_quatech_rqmcr(port);
1511 pci_quatech_wqmcr(port, 0xFF);
1512 if (pci_quatech_rqmcr(port))
1513 rs422 = 1;
1514 pci_quatech_wqmcr(port, qmcr);
1515 return rs422;
1516 }
1517
pci_quatech_init(struct pci_dev * dev)1518 static int pci_quatech_init(struct pci_dev *dev)
1519 {
1520 const struct pci_device_id *match;
1521 bool amcc = false;
1522
1523 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1524 return serial_8250_warn_need_ioport(dev);
1525
1526 match = pci_match_id(quatech_cards, dev);
1527 if (match)
1528 amcc = match->driver_data;
1529 else
1530 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
1531
1532 if (amcc) {
1533 unsigned long base = pci_resource_start(dev, 0);
1534 if (base) {
1535 u32 tmp;
1536
1537 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1538 tmp = inl(base + 0x3c);
1539 outl(tmp | 0x01000000, base + 0x3c);
1540 outl(tmp & ~0x01000000, base + 0x3c);
1541 }
1542 }
1543 return 0;
1544 }
1545
pci_quatech_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1546 static int pci_quatech_setup(struct serial_private *priv,
1547 const struct pciserial_board *board,
1548 struct uart_8250_port *port, int idx)
1549 {
1550 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1551 return serial_8250_warn_need_ioport(priv->dev);
1552
1553 /* Needed by pci_quatech calls below */
1554 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1555 /* Set up the clocking */
1556 port->port.uartclk = pci_quatech_clock(port);
1557 /* For now just warn about RS422 */
1558 if (pci_quatech_rs422(port))
1559 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n");
1560 return pci_default_setup(priv, board, port, idx);
1561 }
1562
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1563 static int pci_default_setup(struct serial_private *priv,
1564 const struct pciserial_board *board,
1565 struct uart_8250_port *port, int idx)
1566 {
1567 unsigned int bar, offset = board->first_offset, maxnr;
1568
1569 bar = FL_GET_BASE(board->flags);
1570 if (board->flags & FL_BASE_BARS)
1571 bar += idx;
1572 else
1573 offset += idx * board->uart_offset;
1574
1575 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1576 (board->reg_shift + 3);
1577
1578 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1579 return 1;
1580
1581 return setup_port(priv, port, bar, offset, board->reg_shift);
1582 }
1583
1584 static int
ce4100_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1585 ce4100_serial_setup(struct serial_private *priv,
1586 const struct pciserial_board *board,
1587 struct uart_8250_port *port, int idx)
1588 {
1589 int ret;
1590
1591 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1592 port->port.iotype = UPIO_MEM32;
1593 port->port.type = PORT_XSCALE;
1594 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1595 port->port.regshift = 2;
1596
1597 return ret;
1598 }
1599
1600 static int
pci_omegapci_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1601 pci_omegapci_setup(struct serial_private *priv,
1602 const struct pciserial_board *board,
1603 struct uart_8250_port *port, int idx)
1604 {
1605 return setup_port(priv, port, 2, idx * 8, 0);
1606 }
1607
1608 static int
pci_brcm_trumanage_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1609 pci_brcm_trumanage_setup(struct serial_private *priv,
1610 const struct pciserial_board *board,
1611 struct uart_8250_port *port, int idx)
1612 {
1613 int ret = pci_default_setup(priv, board, port, idx);
1614
1615 port->port.type = PORT_BRCM_TRUMANAGE;
1616 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1617 return ret;
1618 }
1619
1620 /* RTS will control by MCR if this bit is 0 */
1621 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1622 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1623 #define FINTEK_RTS_INVERT BIT(5)
1624
1625 /* We should do proper H/W transceiver setting before change to RS485 mode */
pci_fintek_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1626 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios,
1627 struct serial_rs485 *rs485)
1628 {
1629 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1630 u8 setting;
1631 u8 *index = (u8 *) port->private_data;
1632
1633 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1634
1635 if (rs485->flags & SER_RS485_ENABLED) {
1636 /* Enable RTS H/W control mode */
1637 setting |= FINTEK_RTS_CONTROL_BY_HW;
1638
1639 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1640 /* RTS driving high on TX */
1641 setting &= ~FINTEK_RTS_INVERT;
1642 } else {
1643 /* RTS driving low on TX */
1644 setting |= FINTEK_RTS_INVERT;
1645 }
1646 } else {
1647 /* Disable RTS H/W control mode */
1648 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1649 }
1650
1651 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1652
1653 return 0;
1654 }
1655
1656 static const struct serial_rs485 pci_fintek_rs485_supported = {
1657 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
1658 /* F81504/508/512 does not support RTS delay before or after send */
1659 };
1660
pci_fintek_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1661 static int pci_fintek_setup(struct serial_private *priv,
1662 const struct pciserial_board *board,
1663 struct uart_8250_port *port, int idx)
1664 {
1665 struct pci_dev *pdev = priv->dev;
1666 u8 *data;
1667 u8 config_base;
1668 u16 iobase;
1669
1670 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1671 return serial_8250_warn_need_ioport(pdev);
1672
1673 config_base = 0x40 + 0x08 * idx;
1674
1675 /* Get the io address from configuration space */
1676 pci_read_config_word(pdev, config_base + 4, &iobase);
1677
1678 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase);
1679
1680 port->port.iotype = UPIO_PORT;
1681 port->port.iobase = iobase;
1682 port->port.rs485_config = pci_fintek_rs485_config;
1683 port->port.rs485_supported = pci_fintek_rs485_supported;
1684
1685 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1686 if (!data)
1687 return -ENOMEM;
1688
1689 /* preserve index in PCI configuration space */
1690 *data = idx;
1691 port->port.private_data = data;
1692
1693 return 0;
1694 }
1695
pci_fintek_init(struct pci_dev * dev)1696 static int pci_fintek_init(struct pci_dev *dev)
1697 {
1698 unsigned long iobase;
1699 u32 max_port, i;
1700 resource_size_t bar_data[3];
1701 u8 config_base;
1702 struct serial_private *priv = pci_get_drvdata(dev);
1703
1704 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1705 return serial_8250_warn_need_ioport(dev);
1706
1707 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1708 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1709 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1710 return -ENODEV;
1711
1712 switch (dev->device) {
1713 case 0x1104: /* 4 ports */
1714 case 0x1108: /* 8 ports */
1715 max_port = dev->device & 0xff;
1716 break;
1717 case 0x1112: /* 12 ports */
1718 max_port = 12;
1719 break;
1720 default:
1721 return -EINVAL;
1722 }
1723
1724 /* Get the io address dispatch from the BIOS */
1725 bar_data[0] = pci_resource_start(dev, 5);
1726 bar_data[1] = pci_resource_start(dev, 4);
1727 bar_data[2] = pci_resource_start(dev, 3);
1728
1729 for (i = 0; i < max_port; ++i) {
1730 /* UART0 configuration offset start from 0x40 */
1731 config_base = 0x40 + 0x08 * i;
1732
1733 /* Calculate Real IO Port */
1734 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1735
1736 /* Enable UART I/O port */
1737 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1738
1739 /* Select 128-byte FIFO and 8x FIFO threshold */
1740 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1741
1742 /* LSB UART */
1743 pci_write_config_byte(dev, config_base + 0x04,
1744 (u8)(iobase & 0xff));
1745
1746 /* MSB UART */
1747 pci_write_config_byte(dev, config_base + 0x05,
1748 (u8)((iobase & 0xff00) >> 8));
1749
1750 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1751
1752 if (!priv) {
1753 /* First init without port data
1754 * force init to RS232 Mode
1755 */
1756 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1757 }
1758 }
1759
1760 return max_port;
1761 }
1762
f815xxa_mem_serial_out(struct uart_port * p,unsigned int offset,u32 value)1763 static void f815xxa_mem_serial_out(struct uart_port *p, unsigned int offset, u32 value)
1764 {
1765 struct f815xxa_data *data = p->private_data;
1766 unsigned long flags;
1767
1768 spin_lock_irqsave(&data->lock, flags);
1769 writeb(value, p->membase + offset);
1770 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1771 spin_unlock_irqrestore(&data->lock, flags);
1772 }
1773
pci_fintek_f815xxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1774 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1775 const struct pciserial_board *board,
1776 struct uart_8250_port *port, int idx)
1777 {
1778 struct pci_dev *pdev = priv->dev;
1779 struct f815xxa_data *data;
1780
1781 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1782 if (!data)
1783 return -ENOMEM;
1784
1785 data->idx = idx;
1786 spin_lock_init(&data->lock);
1787
1788 port->port.private_data = data;
1789 port->port.iotype = UPIO_MEM;
1790 port->port.flags |= UPF_IOREMAP;
1791 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1792 port->port.serial_out = f815xxa_mem_serial_out;
1793
1794 return 0;
1795 }
1796
pci_fintek_f815xxa_init(struct pci_dev * dev)1797 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1798 {
1799 u32 max_port, i;
1800 int config_base;
1801
1802 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1803 return -ENODEV;
1804
1805 switch (dev->device) {
1806 case 0x1204: /* 4 ports */
1807 case 0x1208: /* 8 ports */
1808 max_port = dev->device & 0xff;
1809 break;
1810 case 0x1212: /* 12 ports */
1811 max_port = 12;
1812 break;
1813 default:
1814 return -EINVAL;
1815 }
1816
1817 /* Set to mmio decode */
1818 pci_write_config_byte(dev, 0x209, 0x40);
1819
1820 for (i = 0; i < max_port; ++i) {
1821 /* UART0 configuration offset start from 0x2A0 */
1822 config_base = 0x2A0 + 0x08 * i;
1823
1824 /* Select 128-byte FIFO and 8x FIFO threshold */
1825 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1826
1827 /* Enable UART I/O port */
1828 pci_write_config_byte(dev, config_base + 0, 0x01);
1829 }
1830
1831 return max_port;
1832 }
1833
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1834 static int skip_tx_en_setup(struct serial_private *priv,
1835 const struct pciserial_board *board,
1836 struct uart_8250_port *port, int idx)
1837 {
1838 port->port.quirks |= UPQ_NO_TXEN_TEST;
1839 pci_dbg(priv->dev,
1840 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1841 priv->dev->vendor, priv->dev->device,
1842 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1843
1844 return pci_default_setup(priv, board, port, idx);
1845 }
1846
kt_handle_break(struct uart_port * p)1847 static void kt_handle_break(struct uart_port *p)
1848 {
1849 struct uart_8250_port *up = up_to_u8250p(p);
1850 /*
1851 * On receipt of a BI, serial device in Intel ME (Intel
1852 * management engine) needs to have its fifos cleared for sane
1853 * SOL (Serial Over Lan) output.
1854 */
1855 serial8250_clear_and_reinit_fifos(up);
1856 }
1857
kt_serial_in(struct uart_port * p,unsigned int offset)1858 static u32 kt_serial_in(struct uart_port *p, unsigned int offset)
1859 {
1860 struct uart_8250_port *up = up_to_u8250p(p);
1861 u32 val;
1862
1863 /*
1864 * When the Intel ME (management engine) gets reset its serial
1865 * port registers could return 0 momentarily. Functions like
1866 * serial8250_console_write, read and save the IER, perform
1867 * some operation and then restore it. In order to avoid
1868 * setting IER register inadvertently to 0, if the value read
1869 * is 0, double check with ier value in uart_8250_port and use
1870 * that instead. up->ier should be the same value as what is
1871 * currently configured.
1872 */
1873 val = inb(p->iobase + offset);
1874 if (offset == UART_IER) {
1875 if (val == 0)
1876 val = up->ier;
1877 }
1878 return val;
1879 }
1880
kt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1881 static int kt_serial_setup(struct serial_private *priv,
1882 const struct pciserial_board *board,
1883 struct uart_8250_port *port, int idx)
1884 {
1885 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1886 return serial_8250_warn_need_ioport(priv->dev);
1887
1888 port->port.flags |= UPF_BUG_THRE;
1889 port->port.serial_in = kt_serial_in;
1890 port->port.handle_break = kt_handle_break;
1891 return skip_tx_en_setup(priv, board, port, idx);
1892 }
1893
pci_eg20t_init(struct pci_dev * dev)1894 static int pci_eg20t_init(struct pci_dev *dev)
1895 {
1896 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1897 return -ENODEV;
1898 #else
1899 return 0;
1900 #endif
1901 }
1902
1903 static int
pci_wch_ch353_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1904 pci_wch_ch353_setup(struct serial_private *priv,
1905 const struct pciserial_board *board,
1906 struct uart_8250_port *port, int idx)
1907 {
1908 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1909 return serial_8250_warn_need_ioport(priv->dev);
1910
1911 port->port.flags |= UPF_FIXED_TYPE;
1912 port->port.type = PORT_16550A;
1913 return pci_default_setup(priv, board, port, idx);
1914 }
1915
1916 static int
pci_wch_ch355_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1917 pci_wch_ch355_setup(struct serial_private *priv,
1918 const struct pciserial_board *board,
1919 struct uart_8250_port *port, int idx)
1920 {
1921 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1922 return serial_8250_warn_need_ioport(priv->dev);
1923
1924 port->port.flags |= UPF_FIXED_TYPE;
1925 port->port.type = PORT_16550A;
1926 return pci_default_setup(priv, board, port, idx);
1927 }
1928
1929 static int
pci_wch_ch38x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1930 pci_wch_ch38x_setup(struct serial_private *priv,
1931 const struct pciserial_board *board,
1932 struct uart_8250_port *port, int idx)
1933 {
1934 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1935 return serial_8250_warn_need_ioport(priv->dev);
1936
1937 port->port.flags |= UPF_FIXED_TYPE;
1938 port->port.type = PORT_16850;
1939 return pci_default_setup(priv, board, port, idx);
1940 }
1941
1942
1943 #define CH384_XINT_ENABLE_REG 0xEB
1944 #define CH384_XINT_ENABLE_BIT 0x02
1945
pci_wch_ch38x_init(struct pci_dev * dev)1946 static int pci_wch_ch38x_init(struct pci_dev *dev)
1947 {
1948 int max_port;
1949 unsigned long iobase;
1950
1951 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1952 return serial_8250_warn_need_ioport(dev);
1953
1954 switch (dev->device) {
1955 case 0x3853: /* 8 ports */
1956 max_port = 8;
1957 break;
1958 default:
1959 return -EINVAL;
1960 }
1961
1962 iobase = pci_resource_start(dev, 0);
1963 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
1964
1965 return max_port;
1966 }
1967
pci_wch_ch38x_exit(struct pci_dev * dev)1968 static void pci_wch_ch38x_exit(struct pci_dev *dev)
1969 {
1970 unsigned long iobase;
1971
1972 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) {
1973 serial_8250_warn_need_ioport(dev);
1974 return;
1975 }
1976
1977 iobase = pci_resource_start(dev, 0);
1978 outb(0x0, iobase + CH384_XINT_ENABLE_REG);
1979 }
1980
1981
1982 static int
pci_sunix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1983 pci_sunix_setup(struct serial_private *priv,
1984 const struct pciserial_board *board,
1985 struct uart_8250_port *port, int idx)
1986 {
1987 int bar;
1988 int offset;
1989
1990 port->port.flags |= UPF_FIXED_TYPE;
1991 port->port.type = PORT_SUNIX;
1992
1993 if (idx < 4) {
1994 bar = 0;
1995 offset = idx * board->uart_offset;
1996 } else {
1997 bar = 1;
1998 idx -= 4;
1999 idx = div_s64_rem(idx, 4, &offset);
2000 offset = idx * 64 + offset * board->uart_offset;
2001 }
2002
2003 return setup_port(priv, port, bar, offset, 0);
2004 }
2005
2006 #define MOXA_PUART_GPIO_EN 0x09
2007 #define MOXA_PUART_GPIO_OUT 0x0A
2008
2009 #define MOXA_GPIO_PIN2 BIT(2)
2010
2011 #define MOXA_RS232 0x00
2012 #define MOXA_RS422 0x01
2013 #define MOXA_RS485_4W 0x0B
2014 #define MOXA_RS485_2W 0x0F
2015 #define MOXA_UIR_OFFSET 0x04
2016 #define MOXA_EVEN_RS_MASK GENMASK(3, 0)
2017 #define MOXA_ODD_RS_MASK GENMASK(7, 4)
2018
2019 enum {
2020 MOXA_SUPP_RS232 = BIT(0),
2021 MOXA_SUPP_RS422 = BIT(1),
2022 MOXA_SUPP_RS485 = BIT(2),
2023 };
2024
moxa_get_nports(unsigned short device)2025 static unsigned short moxa_get_nports(unsigned short device)
2026 {
2027 switch (device) {
2028 case PCI_DEVICE_ID_MOXA_CP116E_A_A:
2029 case PCI_DEVICE_ID_MOXA_CP116E_A_B:
2030 return 8;
2031 }
2032
2033 return FIELD_GET(0x00F0, device);
2034 }
2035
pci_moxa_is_mini_pcie(unsigned short device)2036 static bool pci_moxa_is_mini_pcie(unsigned short device)
2037 {
2038 if (device == PCI_DEVICE_ID_MOXA_CP102N ||
2039 device == PCI_DEVICE_ID_MOXA_CP104N ||
2040 device == PCI_DEVICE_ID_MOXA_CP112N ||
2041 device == PCI_DEVICE_ID_MOXA_CP114N ||
2042 device == PCI_DEVICE_ID_MOXA_CP132N ||
2043 device == PCI_DEVICE_ID_MOXA_CP134N)
2044 return true;
2045
2046 return false;
2047 }
2048
pci_moxa_supported_rs(struct pci_dev * dev)2049 static unsigned int pci_moxa_supported_rs(struct pci_dev *dev)
2050 {
2051 switch (dev->device & 0x0F00) {
2052 case 0x0000:
2053 case 0x0600:
2054 return MOXA_SUPP_RS232;
2055 case 0x0100:
2056 return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2057 case 0x0300:
2058 return MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2059 }
2060 return 0;
2061 }
2062
pci_moxa_set_interface(const struct pci_dev * dev,unsigned int port_idx,u8 mode)2063 static int pci_moxa_set_interface(const struct pci_dev *dev,
2064 unsigned int port_idx,
2065 u8 mode)
2066 {
2067 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2068 resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2;
2069 u8 val;
2070
2071 val = inb(UIR_addr);
2072
2073 if (port_idx % 2) {
2074 val &= ~MOXA_ODD_RS_MASK;
2075 val |= FIELD_PREP(MOXA_ODD_RS_MASK, mode);
2076 } else {
2077 val &= ~MOXA_EVEN_RS_MASK;
2078 val |= FIELD_PREP(MOXA_EVEN_RS_MASK, mode);
2079 }
2080 outb(val, UIR_addr);
2081
2082 return 0;
2083 }
2084
pci_moxa_init(struct pci_dev * dev)2085 static int pci_moxa_init(struct pci_dev *dev)
2086 {
2087 unsigned short device = dev->device;
2088 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2089 unsigned int i, num_ports = moxa_get_nports(device);
2090 u8 val, init_mode = MOXA_RS232;
2091
2092 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
2093 return serial_8250_warn_need_ioport(dev);
2094
2095 if (!(pci_moxa_supported_rs(dev) & MOXA_SUPP_RS232)) {
2096 init_mode = MOXA_RS422;
2097 }
2098 for (i = 0; i < num_ports; ++i)
2099 pci_moxa_set_interface(dev, i, init_mode);
2100
2101 /*
2102 * Enable hardware buffer to prevent break signal output when system boots up.
2103 * This hardware buffer is only supported on Mini PCIe series.
2104 */
2105 if (pci_moxa_is_mini_pcie(device)) {
2106 /* Set GPIO direction */
2107 val = inb(iobar_addr + MOXA_PUART_GPIO_EN);
2108 val |= MOXA_GPIO_PIN2;
2109 outb(val, iobar_addr + MOXA_PUART_GPIO_EN);
2110 /* Enable low GPIO */
2111 val = inb(iobar_addr + MOXA_PUART_GPIO_OUT);
2112 val &= ~MOXA_GPIO_PIN2;
2113 outb(val, iobar_addr + MOXA_PUART_GPIO_OUT);
2114 }
2115
2116 return num_ports;
2117 }
2118
2119 static int
pci_moxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)2120 pci_moxa_setup(struct serial_private *priv,
2121 const struct pciserial_board *board,
2122 struct uart_8250_port *port, int idx)
2123 {
2124 unsigned int bar = FL_GET_BASE(board->flags);
2125 int offset;
2126
2127 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
2128 return serial_8250_warn_need_ioport(priv->dev);
2129
2130 if (board->num_ports == 4 && idx == 3)
2131 offset = 7 * board->uart_offset;
2132 else
2133 offset = idx * board->uart_offset;
2134
2135 return setup_port(priv, port, bar, offset, 0);
2136 }
2137
2138 #define SB_OPTR_IMR0 0x0c /* Interrupt mask register, p0 to p7 */
pci_systembase_init(struct pci_dev * dev)2139 static int pci_systembase_init(struct pci_dev *dev)
2140 {
2141 resource_size_t iobase;
2142
2143 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
2144 return serial_8250_warn_need_ioport(dev);
2145
2146 iobase = pci_resource_start(dev, 1);
2147
2148 /* This will support up to 8 ports */
2149 outb(0xff, iobase + SB_OPTR_IMR0);
2150
2151 return 0;
2152 }
2153
pci_systembase_exit(struct pci_dev * dev)2154 static void pci_systembase_exit(struct pci_dev *dev)
2155 {
2156 resource_size_t iobase;
2157
2158 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) {
2159 serial_8250_warn_need_ioport(dev);
2160 return;
2161 }
2162
2163 iobase = pci_resource_start(dev, 0);
2164 outb(0x00, iobase + SB_OPTR_IMR0);
2165 }
2166
2167 /*
2168 * Master list of serial port init/setup/exit quirks.
2169 * This does not describe the general nature of the port.
2170 * (ie, baud base, number and location of ports, etc)
2171 *
2172 * This list is ordered alphabetically by vendor then device.
2173 * Specific entries must come before more generic entries.
2174 */
2175 static struct pci_serial_quirk pci_serial_quirks[] = {
2176 /*
2177 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2178 */
2179 {
2180 .vendor = PCI_VENDOR_ID_AMCC,
2181 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2182 .subvendor = PCI_ANY_ID,
2183 .subdevice = PCI_ANY_ID,
2184 .setup = addidata_apci7800_setup,
2185 },
2186 /*
2187 * AFAVLAB cards - these may be called via parport_serial
2188 * It is not clear whether this applies to all products.
2189 */
2190 {
2191 .vendor = PCI_VENDOR_ID_AFAVLAB,
2192 .device = PCI_ANY_ID,
2193 .subvendor = PCI_ANY_ID,
2194 .subdevice = PCI_ANY_ID,
2195 .setup = afavlab_setup,
2196 },
2197 /*
2198 * HP Diva
2199 */
2200 {
2201 .vendor = PCI_VENDOR_ID_HP,
2202 .device = PCI_DEVICE_ID_HP_DIVA,
2203 .subvendor = PCI_ANY_ID,
2204 .subdevice = PCI_ANY_ID,
2205 .init = pci_hp_diva_init,
2206 .setup = pci_hp_diva_setup,
2207 },
2208 /*
2209 * HPE PCI serial device
2210 */
2211 {
2212 .vendor = PCI_VENDOR_ID_HP_3PAR,
2213 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
2214 .subvendor = PCI_ANY_ID,
2215 .subdevice = PCI_ANY_ID,
2216 .setup = pci_hp_diva_setup,
2217 },
2218 /*
2219 * Intel
2220 */
2221 {
2222 .vendor = PCI_VENDOR_ID_INTEL,
2223 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2224 .subvendor = 0xe4bf,
2225 .subdevice = PCI_ANY_ID,
2226 .init = pci_inteli960ni_init,
2227 .setup = pci_default_setup,
2228 },
2229 {
2230 .vendor = PCI_VENDOR_ID_INTEL,
2231 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2232 .subvendor = PCI_ANY_ID,
2233 .subdevice = PCI_ANY_ID,
2234 .setup = skip_tx_en_setup,
2235 },
2236 {
2237 .vendor = PCI_VENDOR_ID_INTEL,
2238 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2239 .subvendor = PCI_ANY_ID,
2240 .subdevice = PCI_ANY_ID,
2241 .setup = skip_tx_en_setup,
2242 },
2243 {
2244 .vendor = PCI_VENDOR_ID_INTEL,
2245 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2246 .subvendor = PCI_ANY_ID,
2247 .subdevice = PCI_ANY_ID,
2248 .setup = skip_tx_en_setup,
2249 },
2250 {
2251 .vendor = PCI_VENDOR_ID_INTEL,
2252 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2253 .subvendor = PCI_ANY_ID,
2254 .subdevice = PCI_ANY_ID,
2255 .setup = ce4100_serial_setup,
2256 },
2257 {
2258 .vendor = PCI_VENDOR_ID_INTEL,
2259 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2260 .subvendor = PCI_ANY_ID,
2261 .subdevice = PCI_ANY_ID,
2262 .setup = kt_serial_setup,
2263 },
2264 /*
2265 * ITE
2266 */
2267 {
2268 .vendor = PCI_VENDOR_ID_ITE,
2269 .device = PCI_DEVICE_ID_ITE_8872,
2270 .subvendor = PCI_ANY_ID,
2271 .subdevice = PCI_ANY_ID,
2272 .init = pci_ite887x_init,
2273 .setup = pci_default_setup,
2274 .exit = pci_ite887x_exit,
2275 },
2276 /*
2277 * National Instruments
2278 */
2279 {
2280 .vendor = PCI_VENDOR_ID_NI,
2281 .device = PCI_DEVICE_ID_NI_PCI23216,
2282 .subvendor = PCI_ANY_ID,
2283 .subdevice = PCI_ANY_ID,
2284 .init = pci_ni8420_init,
2285 .setup = pci_default_setup,
2286 .exit = pci_ni8420_exit,
2287 },
2288 {
2289 .vendor = PCI_VENDOR_ID_NI,
2290 .device = PCI_DEVICE_ID_NI_PCI2328,
2291 .subvendor = PCI_ANY_ID,
2292 .subdevice = PCI_ANY_ID,
2293 .init = pci_ni8420_init,
2294 .setup = pci_default_setup,
2295 .exit = pci_ni8420_exit,
2296 },
2297 {
2298 .vendor = PCI_VENDOR_ID_NI,
2299 .device = PCI_DEVICE_ID_NI_PCI2324,
2300 .subvendor = PCI_ANY_ID,
2301 .subdevice = PCI_ANY_ID,
2302 .init = pci_ni8420_init,
2303 .setup = pci_default_setup,
2304 .exit = pci_ni8420_exit,
2305 },
2306 {
2307 .vendor = PCI_VENDOR_ID_NI,
2308 .device = PCI_DEVICE_ID_NI_PCI2322,
2309 .subvendor = PCI_ANY_ID,
2310 .subdevice = PCI_ANY_ID,
2311 .init = pci_ni8420_init,
2312 .setup = pci_default_setup,
2313 .exit = pci_ni8420_exit,
2314 },
2315 {
2316 .vendor = PCI_VENDOR_ID_NI,
2317 .device = PCI_DEVICE_ID_NI_PCI2324I,
2318 .subvendor = PCI_ANY_ID,
2319 .subdevice = PCI_ANY_ID,
2320 .init = pci_ni8420_init,
2321 .setup = pci_default_setup,
2322 .exit = pci_ni8420_exit,
2323 },
2324 {
2325 .vendor = PCI_VENDOR_ID_NI,
2326 .device = PCI_DEVICE_ID_NI_PCI2322I,
2327 .subvendor = PCI_ANY_ID,
2328 .subdevice = PCI_ANY_ID,
2329 .init = pci_ni8420_init,
2330 .setup = pci_default_setup,
2331 .exit = pci_ni8420_exit,
2332 },
2333 {
2334 .vendor = PCI_VENDOR_ID_NI,
2335 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2336 .subvendor = PCI_ANY_ID,
2337 .subdevice = PCI_ANY_ID,
2338 .init = pci_ni8420_init,
2339 .setup = pci_default_setup,
2340 .exit = pci_ni8420_exit,
2341 },
2342 {
2343 .vendor = PCI_VENDOR_ID_NI,
2344 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2345 .subvendor = PCI_ANY_ID,
2346 .subdevice = PCI_ANY_ID,
2347 .init = pci_ni8420_init,
2348 .setup = pci_default_setup,
2349 .exit = pci_ni8420_exit,
2350 },
2351 {
2352 .vendor = PCI_VENDOR_ID_NI,
2353 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2354 .subvendor = PCI_ANY_ID,
2355 .subdevice = PCI_ANY_ID,
2356 .init = pci_ni8420_init,
2357 .setup = pci_default_setup,
2358 .exit = pci_ni8420_exit,
2359 },
2360 {
2361 .vendor = PCI_VENDOR_ID_NI,
2362 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2363 .subvendor = PCI_ANY_ID,
2364 .subdevice = PCI_ANY_ID,
2365 .init = pci_ni8420_init,
2366 .setup = pci_default_setup,
2367 .exit = pci_ni8420_exit,
2368 },
2369 {
2370 .vendor = PCI_VENDOR_ID_NI,
2371 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2372 .subvendor = PCI_ANY_ID,
2373 .subdevice = PCI_ANY_ID,
2374 .init = pci_ni8420_init,
2375 .setup = pci_default_setup,
2376 .exit = pci_ni8420_exit,
2377 },
2378 {
2379 .vendor = PCI_VENDOR_ID_NI,
2380 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2381 .subvendor = PCI_ANY_ID,
2382 .subdevice = PCI_ANY_ID,
2383 .init = pci_ni8420_init,
2384 .setup = pci_default_setup,
2385 .exit = pci_ni8420_exit,
2386 },
2387 {
2388 .vendor = PCI_VENDOR_ID_NI,
2389 .device = PCI_ANY_ID,
2390 .subvendor = PCI_ANY_ID,
2391 .subdevice = PCI_ANY_ID,
2392 .init = pci_ni8430_init,
2393 .setup = pci_ni8430_setup,
2394 .exit = pci_ni8430_exit,
2395 },
2396 /* Quatech */
2397 {
2398 .vendor = PCI_VENDOR_ID_QUATECH,
2399 .device = PCI_ANY_ID,
2400 .subvendor = PCI_ANY_ID,
2401 .subdevice = PCI_ANY_ID,
2402 .init = pci_quatech_init,
2403 .setup = pci_quatech_setup,
2404 },
2405 /*
2406 * Panacom
2407 */
2408 {
2409 .vendor = PCI_VENDOR_ID_PANACOM,
2410 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2411 .subvendor = PCI_ANY_ID,
2412 .subdevice = PCI_ANY_ID,
2413 .init = pci_plx9050_init,
2414 .setup = pci_default_setup,
2415 .exit = pci_plx9050_exit,
2416 },
2417 {
2418 .vendor = PCI_VENDOR_ID_PANACOM,
2419 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2420 .subvendor = PCI_ANY_ID,
2421 .subdevice = PCI_ANY_ID,
2422 .init = pci_plx9050_init,
2423 .setup = pci_default_setup,
2424 .exit = pci_plx9050_exit,
2425 },
2426 /*
2427 * PLX
2428 */
2429 {
2430 .vendor = PCI_VENDOR_ID_PLX,
2431 .device = PCI_DEVICE_ID_PLX_9050,
2432 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2433 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2434 .init = pci_plx9050_init,
2435 .setup = pci_default_setup,
2436 .exit = pci_plx9050_exit,
2437 },
2438 {
2439 .vendor = PCI_VENDOR_ID_PLX,
2440 .device = PCI_DEVICE_ID_PLX_9050,
2441 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2442 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2443 .init = pci_plx9050_init,
2444 .setup = pci_default_setup,
2445 .exit = pci_plx9050_exit,
2446 },
2447 {
2448 .vendor = PCI_VENDOR_ID_PLX,
2449 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2450 .subvendor = PCI_VENDOR_ID_PLX,
2451 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2452 .init = pci_plx9050_init,
2453 .setup = pci_default_setup,
2454 .exit = pci_plx9050_exit,
2455 },
2456 /*
2457 * SBS Technologies, Inc., PMC-OCTALPRO 232
2458 */
2459 {
2460 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2461 .device = PCI_DEVICE_ID_OCTPRO,
2462 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2463 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2464 .init = sbs_init,
2465 .setup = sbs_setup,
2466 .exit = sbs_exit,
2467 },
2468 /*
2469 * SBS Technologies, Inc., PMC-OCTALPRO 422
2470 */
2471 {
2472 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2473 .device = PCI_DEVICE_ID_OCTPRO,
2474 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2475 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2476 .init = sbs_init,
2477 .setup = sbs_setup,
2478 .exit = sbs_exit,
2479 },
2480 /*
2481 * SBS Technologies, Inc., P-Octal 232
2482 */
2483 {
2484 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2485 .device = PCI_DEVICE_ID_OCTPRO,
2486 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2487 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2488 .init = sbs_init,
2489 .setup = sbs_setup,
2490 .exit = sbs_exit,
2491 },
2492 /*
2493 * SBS Technologies, Inc., P-Octal 422
2494 */
2495 {
2496 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2497 .device = PCI_DEVICE_ID_OCTPRO,
2498 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2499 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2500 .init = sbs_init,
2501 .setup = sbs_setup,
2502 .exit = sbs_exit,
2503 },
2504 /*
2505 * SIIG cards - these may be called via parport_serial
2506 */
2507 {
2508 .vendor = PCI_VENDOR_ID_SIIG,
2509 .device = PCI_ANY_ID,
2510 .subvendor = PCI_ANY_ID,
2511 .subdevice = PCI_ANY_ID,
2512 .init = pci_siig_init,
2513 .setup = pci_siig_setup,
2514 },
2515 /* Systembase */
2516 {
2517 .vendor = PCI_VENDOR_ID_SYSTEMBASE,
2518 .device = 0x0008,
2519 .subvendor = PCI_ANY_ID,
2520 .subdevice = PCI_ANY_ID,
2521 .init = pci_systembase_init,
2522 .setup = pci_default_setup,
2523 .exit = pci_systembase_exit,
2524 },
2525 /*
2526 * Titan cards
2527 */
2528 {
2529 .vendor = PCI_VENDOR_ID_TITAN,
2530 .device = PCI_DEVICE_ID_TITAN_400L,
2531 .subvendor = PCI_ANY_ID,
2532 .subdevice = PCI_ANY_ID,
2533 .setup = titan_400l_800l_setup,
2534 },
2535 {
2536 .vendor = PCI_VENDOR_ID_TITAN,
2537 .device = PCI_DEVICE_ID_TITAN_800L,
2538 .subvendor = PCI_ANY_ID,
2539 .subdevice = PCI_ANY_ID,
2540 .setup = titan_400l_800l_setup,
2541 },
2542 /*
2543 * Timedia cards
2544 */
2545 {
2546 .vendor = PCI_VENDOR_ID_TIMEDIA,
2547 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2548 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2549 .subdevice = PCI_ANY_ID,
2550 .probe = pci_timedia_probe,
2551 .init = pci_timedia_init,
2552 .setup = pci_timedia_setup,
2553 },
2554 {
2555 .vendor = PCI_VENDOR_ID_TIMEDIA,
2556 .device = PCI_ANY_ID,
2557 .subvendor = PCI_ANY_ID,
2558 .subdevice = PCI_ANY_ID,
2559 .setup = pci_timedia_setup,
2560 },
2561 /*
2562 * Sunix PCI serial boards
2563 */
2564 {
2565 .vendor = PCI_VENDOR_ID_SUNIX,
2566 .device = PCI_DEVICE_ID_SUNIX_1999,
2567 .subvendor = PCI_VENDOR_ID_SUNIX,
2568 .subdevice = PCI_ANY_ID,
2569 .setup = pci_sunix_setup,
2570 },
2571 /*
2572 * Xircom cards
2573 */
2574 {
2575 .vendor = PCI_VENDOR_ID_XIRCOM,
2576 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2577 .subvendor = PCI_ANY_ID,
2578 .subdevice = PCI_ANY_ID,
2579 .init = pci_xircom_init,
2580 .setup = pci_default_setup,
2581 },
2582 /*
2583 * Netmos cards - these may be called via parport_serial
2584 */
2585 {
2586 .vendor = PCI_VENDOR_ID_NETMOS,
2587 .device = PCI_ANY_ID,
2588 .subvendor = PCI_ANY_ID,
2589 .subdevice = PCI_ANY_ID,
2590 .init = pci_netmos_init,
2591 .setup = pci_netmos_9900_setup,
2592 },
2593 {
2594 .vendor = PCIE_VENDOR_ID_ASIX,
2595 .device = PCI_ANY_ID,
2596 .subvendor = PCI_ANY_ID,
2597 .subdevice = PCI_ANY_ID,
2598 .init = pci_netmos_init,
2599 .setup = pci_netmos_9900_setup,
2600 },
2601 /*
2602 * EndRun Technologies
2603 */
2604 {
2605 .vendor = PCI_VENDOR_ID_ENDRUN,
2606 .device = PCI_ANY_ID,
2607 .subvendor = PCI_ANY_ID,
2608 .subdevice = PCI_ANY_ID,
2609 .init = pci_oxsemi_tornado_init,
2610 .setup = pci_default_setup,
2611 },
2612 /*
2613 * For Oxford Semiconductor Tornado based devices
2614 */
2615 {
2616 .vendor = PCI_VENDOR_ID_OXSEMI,
2617 .device = PCI_ANY_ID,
2618 .subvendor = PCI_ANY_ID,
2619 .subdevice = PCI_ANY_ID,
2620 .init = pci_oxsemi_tornado_init,
2621 .setup = pci_oxsemi_tornado_setup,
2622 },
2623 {
2624 .vendor = PCI_VENDOR_ID_MAINPINE,
2625 .device = PCI_ANY_ID,
2626 .subvendor = PCI_ANY_ID,
2627 .subdevice = PCI_ANY_ID,
2628 .init = pci_oxsemi_tornado_init,
2629 .setup = pci_oxsemi_tornado_setup,
2630 },
2631 {
2632 .vendor = PCI_VENDOR_ID_DIGI,
2633 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2634 .subvendor = PCI_SUBVENDOR_ID_IBM,
2635 .subdevice = PCI_ANY_ID,
2636 .init = pci_oxsemi_tornado_init,
2637 .setup = pci_oxsemi_tornado_setup,
2638 },
2639 /*
2640 * Brainboxes devices - all Oxsemi based
2641 */
2642 {
2643 .vendor = PCI_VENDOR_ID_INTASHIELD,
2644 .device = 0x4027,
2645 .subvendor = PCI_ANY_ID,
2646 .subdevice = PCI_ANY_ID,
2647 .init = pci_oxsemi_tornado_init,
2648 .setup = pci_oxsemi_tornado_setup,
2649 },
2650 {
2651 .vendor = PCI_VENDOR_ID_INTASHIELD,
2652 .device = 0x4028,
2653 .subvendor = PCI_ANY_ID,
2654 .subdevice = PCI_ANY_ID,
2655 .init = pci_oxsemi_tornado_init,
2656 .setup = pci_oxsemi_tornado_setup,
2657 },
2658 {
2659 .vendor = PCI_VENDOR_ID_INTASHIELD,
2660 .device = 0x4029,
2661 .subvendor = PCI_ANY_ID,
2662 .subdevice = PCI_ANY_ID,
2663 .init = pci_oxsemi_tornado_init,
2664 .setup = pci_oxsemi_tornado_setup,
2665 },
2666 {
2667 .vendor = PCI_VENDOR_ID_INTASHIELD,
2668 .device = 0x4019,
2669 .subvendor = PCI_ANY_ID,
2670 .subdevice = PCI_ANY_ID,
2671 .init = pci_oxsemi_tornado_init,
2672 .setup = pci_oxsemi_tornado_setup,
2673 },
2674 {
2675 .vendor = PCI_VENDOR_ID_INTASHIELD,
2676 .device = 0x4016,
2677 .subvendor = PCI_ANY_ID,
2678 .subdevice = PCI_ANY_ID,
2679 .init = pci_oxsemi_tornado_init,
2680 .setup = pci_oxsemi_tornado_setup,
2681 },
2682 {
2683 .vendor = PCI_VENDOR_ID_INTASHIELD,
2684 .device = 0x4015,
2685 .subvendor = PCI_ANY_ID,
2686 .subdevice = PCI_ANY_ID,
2687 .init = pci_oxsemi_tornado_init,
2688 .setup = pci_oxsemi_tornado_setup,
2689 },
2690 {
2691 .vendor = PCI_VENDOR_ID_INTASHIELD,
2692 .device = 0x400A,
2693 .subvendor = PCI_ANY_ID,
2694 .subdevice = PCI_ANY_ID,
2695 .init = pci_oxsemi_tornado_init,
2696 .setup = pci_oxsemi_tornado_setup,
2697 },
2698 {
2699 .vendor = PCI_VENDOR_ID_INTASHIELD,
2700 .device = 0x400E,
2701 .subvendor = PCI_ANY_ID,
2702 .subdevice = PCI_ANY_ID,
2703 .init = pci_oxsemi_tornado_init,
2704 .setup = pci_oxsemi_tornado_setup,
2705 },
2706 {
2707 .vendor = PCI_VENDOR_ID_INTASHIELD,
2708 .device = 0x400C,
2709 .subvendor = PCI_ANY_ID,
2710 .subdevice = PCI_ANY_ID,
2711 .init = pci_oxsemi_tornado_init,
2712 .setup = pci_oxsemi_tornado_setup,
2713 },
2714 {
2715 .vendor = PCI_VENDOR_ID_INTASHIELD,
2716 .device = 0x400B,
2717 .subvendor = PCI_ANY_ID,
2718 .subdevice = PCI_ANY_ID,
2719 .init = pci_oxsemi_tornado_init,
2720 .setup = pci_oxsemi_tornado_setup,
2721 },
2722 {
2723 .vendor = PCI_VENDOR_ID_INTASHIELD,
2724 .device = 0x400F,
2725 .subvendor = PCI_ANY_ID,
2726 .subdevice = PCI_ANY_ID,
2727 .init = pci_oxsemi_tornado_init,
2728 .setup = pci_oxsemi_tornado_setup,
2729 },
2730 {
2731 .vendor = PCI_VENDOR_ID_INTASHIELD,
2732 .device = 0x4010,
2733 .subvendor = PCI_ANY_ID,
2734 .subdevice = PCI_ANY_ID,
2735 .init = pci_oxsemi_tornado_init,
2736 .setup = pci_oxsemi_tornado_setup,
2737 },
2738 {
2739 .vendor = PCI_VENDOR_ID_INTASHIELD,
2740 .device = 0x4011,
2741 .subvendor = PCI_ANY_ID,
2742 .subdevice = PCI_ANY_ID,
2743 .init = pci_oxsemi_tornado_init,
2744 .setup = pci_oxsemi_tornado_setup,
2745 },
2746 {
2747 .vendor = PCI_VENDOR_ID_INTASHIELD,
2748 .device = 0x401D,
2749 .subvendor = PCI_ANY_ID,
2750 .subdevice = PCI_ANY_ID,
2751 .init = pci_oxsemi_tornado_init,
2752 .setup = pci_oxsemi_tornado_setup,
2753 },
2754 {
2755 .vendor = PCI_VENDOR_ID_INTASHIELD,
2756 .device = 0x401E,
2757 .subvendor = PCI_ANY_ID,
2758 .subdevice = PCI_ANY_ID,
2759 .init = pci_oxsemi_tornado_init,
2760 .setup = pci_oxsemi_tornado_setup,
2761 },
2762 {
2763 .vendor = PCI_VENDOR_ID_INTASHIELD,
2764 .device = 0x4013,
2765 .subvendor = PCI_ANY_ID,
2766 .subdevice = PCI_ANY_ID,
2767 .init = pci_oxsemi_tornado_init,
2768 .setup = pci_oxsemi_tornado_setup,
2769 },
2770 {
2771 .vendor = PCI_VENDOR_ID_INTASHIELD,
2772 .device = 0x4017,
2773 .subvendor = PCI_ANY_ID,
2774 .subdevice = PCI_ANY_ID,
2775 .init = pci_oxsemi_tornado_init,
2776 .setup = pci_oxsemi_tornado_setup,
2777 },
2778 {
2779 .vendor = PCI_VENDOR_ID_INTASHIELD,
2780 .device = 0x4018,
2781 .subvendor = PCI_ANY_ID,
2782 .subdevice = PCI_ANY_ID,
2783 .init = pci_oxsemi_tornado_init,
2784 .setup = pci_oxsemi_tornado_setup,
2785 },
2786 {
2787 .vendor = PCI_VENDOR_ID_INTASHIELD,
2788 .device = 0x4026,
2789 .subvendor = PCI_ANY_ID,
2790 .subdevice = PCI_ANY_ID,
2791 .init = pci_oxsemi_tornado_init,
2792 .setup = pci_oxsemi_tornado_setup,
2793 },
2794 {
2795 .vendor = PCI_VENDOR_ID_INTASHIELD,
2796 .device = 0x4021,
2797 .subvendor = PCI_ANY_ID,
2798 .subdevice = PCI_ANY_ID,
2799 .init = pci_oxsemi_tornado_init,
2800 .setup = pci_oxsemi_tornado_setup,
2801 },
2802 {
2803 .vendor = PCI_VENDOR_ID_INTEL,
2804 .device = 0x8811,
2805 .subvendor = PCI_ANY_ID,
2806 .subdevice = PCI_ANY_ID,
2807 .init = pci_eg20t_init,
2808 .setup = pci_default_setup,
2809 },
2810 {
2811 .vendor = PCI_VENDOR_ID_INTEL,
2812 .device = 0x8812,
2813 .subvendor = PCI_ANY_ID,
2814 .subdevice = PCI_ANY_ID,
2815 .init = pci_eg20t_init,
2816 .setup = pci_default_setup,
2817 },
2818 {
2819 .vendor = PCI_VENDOR_ID_INTEL,
2820 .device = 0x8813,
2821 .subvendor = PCI_ANY_ID,
2822 .subdevice = PCI_ANY_ID,
2823 .init = pci_eg20t_init,
2824 .setup = pci_default_setup,
2825 },
2826 {
2827 .vendor = PCI_VENDOR_ID_INTEL,
2828 .device = 0x8814,
2829 .subvendor = PCI_ANY_ID,
2830 .subdevice = PCI_ANY_ID,
2831 .init = pci_eg20t_init,
2832 .setup = pci_default_setup,
2833 },
2834 {
2835 .vendor = 0x10DB,
2836 .device = 0x8027,
2837 .subvendor = PCI_ANY_ID,
2838 .subdevice = PCI_ANY_ID,
2839 .init = pci_eg20t_init,
2840 .setup = pci_default_setup,
2841 },
2842 {
2843 .vendor = 0x10DB,
2844 .device = 0x8028,
2845 .subvendor = PCI_ANY_ID,
2846 .subdevice = PCI_ANY_ID,
2847 .init = pci_eg20t_init,
2848 .setup = pci_default_setup,
2849 },
2850 {
2851 .vendor = 0x10DB,
2852 .device = 0x8029,
2853 .subvendor = PCI_ANY_ID,
2854 .subdevice = PCI_ANY_ID,
2855 .init = pci_eg20t_init,
2856 .setup = pci_default_setup,
2857 },
2858 {
2859 .vendor = 0x10DB,
2860 .device = 0x800C,
2861 .subvendor = PCI_ANY_ID,
2862 .subdevice = PCI_ANY_ID,
2863 .init = pci_eg20t_init,
2864 .setup = pci_default_setup,
2865 },
2866 {
2867 .vendor = 0x10DB,
2868 .device = 0x800D,
2869 .subvendor = PCI_ANY_ID,
2870 .subdevice = PCI_ANY_ID,
2871 .init = pci_eg20t_init,
2872 .setup = pci_default_setup,
2873 },
2874 /*
2875 * Cronyx Omega PCI (PLX-chip based)
2876 */
2877 {
2878 .vendor = PCI_VENDOR_ID_PLX,
2879 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2880 .subvendor = PCI_ANY_ID,
2881 .subdevice = PCI_ANY_ID,
2882 .setup = pci_omegapci_setup,
2883 },
2884 /* WCH CH353 1S1P card (16550 clone) */
2885 {
2886 .vendor = PCI_VENDOR_ID_WCHCN,
2887 .device = PCI_DEVICE_ID_WCHCN_CH353_1S1P,
2888 .subvendor = PCI_ANY_ID,
2889 .subdevice = PCI_ANY_ID,
2890 .setup = pci_wch_ch353_setup,
2891 },
2892 /* WCH CH353 2S1P card (16550 clone) */
2893 {
2894 .vendor = PCI_VENDOR_ID_WCHCN,
2895 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1P,
2896 .subvendor = PCI_ANY_ID,
2897 .subdevice = PCI_ANY_ID,
2898 .setup = pci_wch_ch353_setup,
2899 },
2900 /* WCH CH353 4S card (16550 clone) */
2901 {
2902 .vendor = PCI_VENDOR_ID_WCHCN,
2903 .device = PCI_DEVICE_ID_WCHCN_CH353_4S,
2904 .subvendor = PCI_ANY_ID,
2905 .subdevice = PCI_ANY_ID,
2906 .setup = pci_wch_ch353_setup,
2907 },
2908 /* WCH CH353 2S1PF card (16550 clone) */
2909 {
2910 .vendor = PCI_VENDOR_ID_WCHCN,
2911 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1PF,
2912 .subvendor = PCI_ANY_ID,
2913 .subdevice = PCI_ANY_ID,
2914 .setup = pci_wch_ch353_setup,
2915 },
2916 /* WCH CH352 2S card (16550 clone) */
2917 {
2918 .vendor = PCI_VENDOR_ID_WCHCN,
2919 .device = PCI_DEVICE_ID_WCHCN_CH352_2S,
2920 .subvendor = PCI_ANY_ID,
2921 .subdevice = PCI_ANY_ID,
2922 .setup = pci_wch_ch353_setup,
2923 },
2924 /* WCH CH355 4S card (16550 clone) */
2925 {
2926 .vendor = PCI_VENDOR_ID_WCHCN,
2927 .device = PCI_DEVICE_ID_WCHCN_CH355_4S,
2928 .subvendor = PCI_ANY_ID,
2929 .subdevice = PCI_ANY_ID,
2930 .setup = pci_wch_ch355_setup,
2931 },
2932 /* WCH CH382 2S card (16850 clone) */
2933 {
2934 .vendor = PCI_VENDOR_ID_WCHIC,
2935 .device = PCI_DEVICE_ID_WCHIC_CH382_2S,
2936 .subvendor = PCI_ANY_ID,
2937 .subdevice = PCI_ANY_ID,
2938 .setup = pci_wch_ch38x_setup,
2939 },
2940 /* WCH CH382 2S1P card (16850 clone) */
2941 {
2942 .vendor = PCI_VENDOR_ID_WCHIC,
2943 .device = PCI_DEVICE_ID_WCHIC_CH382_2S1P,
2944 .subvendor = PCI_ANY_ID,
2945 .subdevice = PCI_ANY_ID,
2946 .setup = pci_wch_ch38x_setup,
2947 },
2948 /* WCH CH384 4S card (16850 clone) */
2949 {
2950 .vendor = PCI_VENDOR_ID_WCHIC,
2951 .device = PCI_DEVICE_ID_WCHIC_CH384_4S,
2952 .subvendor = PCI_ANY_ID,
2953 .subdevice = PCI_ANY_ID,
2954 .setup = pci_wch_ch38x_setup,
2955 },
2956 /* WCH CH384 8S card (16850 clone) */
2957 {
2958 .vendor = PCI_VENDOR_ID_WCHIC,
2959 .device = PCI_DEVICE_ID_WCHIC_CH384_8S,
2960 .subvendor = PCI_ANY_ID,
2961 .subdevice = PCI_ANY_ID,
2962 .init = pci_wch_ch38x_init,
2963 .exit = pci_wch_ch38x_exit,
2964 .setup = pci_wch_ch38x_setup,
2965 },
2966 /*
2967 * Broadcom TruManage (NetXtreme)
2968 */
2969 {
2970 .vendor = PCI_VENDOR_ID_BROADCOM,
2971 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2972 .subvendor = PCI_ANY_ID,
2973 .subdevice = PCI_ANY_ID,
2974 .setup = pci_brcm_trumanage_setup,
2975 },
2976 {
2977 .vendor = 0x1c29,
2978 .device = 0x1104,
2979 .subvendor = PCI_ANY_ID,
2980 .subdevice = PCI_ANY_ID,
2981 .setup = pci_fintek_setup,
2982 .init = pci_fintek_init,
2983 },
2984 {
2985 .vendor = 0x1c29,
2986 .device = 0x1108,
2987 .subvendor = PCI_ANY_ID,
2988 .subdevice = PCI_ANY_ID,
2989 .setup = pci_fintek_setup,
2990 .init = pci_fintek_init,
2991 },
2992 {
2993 .vendor = 0x1c29,
2994 .device = 0x1112,
2995 .subvendor = PCI_ANY_ID,
2996 .subdevice = PCI_ANY_ID,
2997 .setup = pci_fintek_setup,
2998 .init = pci_fintek_init,
2999 },
3000 /*
3001 * MOXA
3002 */
3003 {
3004 .vendor = PCI_VENDOR_ID_MOXA,
3005 .device = PCI_ANY_ID,
3006 .subvendor = PCI_ANY_ID,
3007 .subdevice = PCI_ANY_ID,
3008 .init = pci_moxa_init,
3009 .setup = pci_moxa_setup,
3010 },
3011 {
3012 .vendor = 0x1c29,
3013 .device = 0x1204,
3014 .subvendor = PCI_ANY_ID,
3015 .subdevice = PCI_ANY_ID,
3016 .setup = pci_fintek_f815xxa_setup,
3017 .init = pci_fintek_f815xxa_init,
3018 },
3019 {
3020 .vendor = 0x1c29,
3021 .device = 0x1208,
3022 .subvendor = PCI_ANY_ID,
3023 .subdevice = PCI_ANY_ID,
3024 .setup = pci_fintek_f815xxa_setup,
3025 .init = pci_fintek_f815xxa_init,
3026 },
3027 {
3028 .vendor = 0x1c29,
3029 .device = 0x1212,
3030 .subvendor = PCI_ANY_ID,
3031 .subdevice = PCI_ANY_ID,
3032 .setup = pci_fintek_f815xxa_setup,
3033 .init = pci_fintek_f815xxa_init,
3034 },
3035
3036 /*
3037 * Default "match everything" terminator entry
3038 */
3039 {
3040 .vendor = PCI_ANY_ID,
3041 .device = PCI_ANY_ID,
3042 .subvendor = PCI_ANY_ID,
3043 .subdevice = PCI_ANY_ID,
3044 .setup = pci_default_setup,
3045 }
3046 };
3047
quirk_id_matches(u32 quirk_id,u32 dev_id)3048 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
3049 {
3050 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
3051 }
3052
find_quirk(struct pci_dev * dev)3053 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
3054 {
3055 struct pci_serial_quirk *quirk;
3056
3057 for (quirk = pci_serial_quirks; ; quirk++)
3058 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
3059 quirk_id_matches(quirk->device, dev->device) &&
3060 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
3061 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
3062 break;
3063 return quirk;
3064 }
3065
3066 /*
3067 * This is the configuration table for all of the PCI serial boards
3068 * which we support. It is directly indexed by the pci_board_num_t enum
3069 * value, which is encoded in the pci_device_id PCI probe table's
3070 * driver_data member.
3071 *
3072 * The makeup of these names are:
3073 * pbn_bn{_bt}_n_baud{_offsetinhex}
3074 *
3075 * bn = PCI BAR number
3076 * bt = Index using PCI BARs
3077 * n = number of serial ports
3078 * baud = baud rate
3079 * offsetinhex = offset for each sequential port (in hex)
3080 *
3081 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
3082 *
3083 * Please note: in theory if n = 1, _bt infix should make no difference.
3084 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
3085 */
3086 enum pci_board_num_t {
3087 pbn_default = 0,
3088
3089 pbn_b0_1_115200,
3090 pbn_b0_2_115200,
3091 pbn_b0_4_115200,
3092 pbn_b0_5_115200,
3093 pbn_b0_8_115200,
3094
3095 pbn_b0_1_921600,
3096 pbn_b0_2_921600,
3097 pbn_b0_4_921600,
3098 pbn_b0_8_921600,
3099
3100 pbn_b0_2_1130000,
3101
3102 pbn_b0_4_1152000,
3103
3104 pbn_b0_4_1250000,
3105
3106 pbn_b0_2_1843200,
3107 pbn_b0_4_1843200,
3108
3109 pbn_b0_1_15625000,
3110
3111 pbn_b0_bt_1_115200,
3112 pbn_b0_bt_2_115200,
3113 pbn_b0_bt_4_115200,
3114 pbn_b0_bt_8_115200,
3115
3116 pbn_b0_bt_1_460800,
3117 pbn_b0_bt_2_460800,
3118 pbn_b0_bt_4_460800,
3119
3120 pbn_b0_bt_1_921600,
3121 pbn_b0_bt_2_921600,
3122 pbn_b0_bt_4_921600,
3123 pbn_b0_bt_8_921600,
3124
3125 pbn_b1_1_115200,
3126 pbn_b1_2_115200,
3127 pbn_b1_4_115200,
3128 pbn_b1_8_115200,
3129 pbn_b1_16_115200,
3130
3131 pbn_b1_1_921600,
3132 pbn_b1_2_921600,
3133 pbn_b1_4_921600,
3134 pbn_b1_8_921600,
3135
3136 pbn_b1_2_1250000,
3137
3138 pbn_b1_bt_1_115200,
3139 pbn_b1_bt_2_115200,
3140 pbn_b1_bt_4_115200,
3141
3142 pbn_b1_bt_2_921600,
3143
3144 pbn_b1_1_1382400,
3145 pbn_b1_2_1382400,
3146 pbn_b1_4_1382400,
3147 pbn_b1_8_1382400,
3148
3149 pbn_b2_1_115200,
3150 pbn_b2_2_115200,
3151 pbn_b2_4_115200,
3152 pbn_b2_8_115200,
3153
3154 pbn_b2_1_460800,
3155 pbn_b2_4_460800,
3156 pbn_b2_8_460800,
3157 pbn_b2_16_460800,
3158
3159 pbn_b2_1_921600,
3160 pbn_b2_4_921600,
3161 pbn_b2_8_921600,
3162
3163 pbn_b2_8_1152000,
3164
3165 pbn_b2_bt_1_115200,
3166 pbn_b2_bt_2_115200,
3167 pbn_b2_bt_4_115200,
3168
3169 pbn_b2_bt_2_921600,
3170 pbn_b2_bt_4_921600,
3171
3172 pbn_b3_2_115200,
3173 pbn_b3_4_115200,
3174 pbn_b3_8_115200,
3175
3176 pbn_b4_bt_2_921600,
3177 pbn_b4_bt_4_921600,
3178 pbn_b4_bt_8_921600,
3179
3180 /*
3181 * Board-specific versions.
3182 */
3183 pbn_panacom,
3184 pbn_panacom2,
3185 pbn_panacom4,
3186 pbn_plx_romulus,
3187 pbn_oxsemi,
3188 pbn_oxsemi_1_15625000,
3189 pbn_oxsemi_2_15625000,
3190 pbn_oxsemi_4_15625000,
3191 pbn_oxsemi_8_15625000,
3192 pbn_intel_i960,
3193 pbn_sgi_ioc3,
3194 pbn_computone_4,
3195 pbn_computone_6,
3196 pbn_computone_8,
3197 pbn_sbsxrsio,
3198 pbn_pasemi_1682M,
3199 pbn_ni8430_2,
3200 pbn_ni8430_4,
3201 pbn_ni8430_8,
3202 pbn_ni8430_16,
3203 pbn_ADDIDATA_PCIe_1_3906250,
3204 pbn_ADDIDATA_PCIe_2_3906250,
3205 pbn_ADDIDATA_PCIe_4_3906250,
3206 pbn_ADDIDATA_PCIe_8_3906250,
3207 pbn_ce4100_1_115200,
3208 pbn_omegapci,
3209 pbn_NETMOS9900_2s_115200,
3210 pbn_brcm_trumanage,
3211 pbn_fintek_4,
3212 pbn_fintek_8,
3213 pbn_fintek_12,
3214 pbn_fintek_F81504A,
3215 pbn_fintek_F81508A,
3216 pbn_fintek_F81512A,
3217 pbn_wch382_2,
3218 pbn_wch384_4,
3219 pbn_wch384_8,
3220 pbn_sunix_pci_1s,
3221 pbn_sunix_pci_2s,
3222 pbn_sunix_pci_4s,
3223 pbn_sunix_pci_8s,
3224 pbn_sunix_pci_16s,
3225 pbn_titan_1_4000000,
3226 pbn_titan_2_4000000,
3227 pbn_titan_4_4000000,
3228 pbn_titan_8_4000000,
3229 pbn_moxa_2,
3230 pbn_moxa_4,
3231 pbn_moxa_8,
3232 };
3233
3234 /*
3235 * uart_offset - the space between channels
3236 * reg_shift - describes how the UART registers are mapped
3237 * to PCI memory by the card.
3238 * For example IER register on SBS, Inc. PMC-OctPro is located at
3239 * offset 0x10 from the UART base, while UART_IER is defined as 1
3240 * in include/linux/serial_reg.h,
3241 * see first lines of serial_in() and serial_out() in 8250.c
3242 */
3243
3244 static struct pciserial_board pci_boards[] = {
3245 [pbn_default] = {
3246 .flags = FL_BASE0,
3247 .num_ports = 1,
3248 .base_baud = 115200,
3249 .uart_offset = 8,
3250 },
3251 [pbn_b0_1_115200] = {
3252 .flags = FL_BASE0,
3253 .num_ports = 1,
3254 .base_baud = 115200,
3255 .uart_offset = 8,
3256 },
3257 [pbn_b0_2_115200] = {
3258 .flags = FL_BASE0,
3259 .num_ports = 2,
3260 .base_baud = 115200,
3261 .uart_offset = 8,
3262 },
3263 [pbn_b0_4_115200] = {
3264 .flags = FL_BASE0,
3265 .num_ports = 4,
3266 .base_baud = 115200,
3267 .uart_offset = 8,
3268 },
3269 [pbn_b0_5_115200] = {
3270 .flags = FL_BASE0,
3271 .num_ports = 5,
3272 .base_baud = 115200,
3273 .uart_offset = 8,
3274 },
3275 [pbn_b0_8_115200] = {
3276 .flags = FL_BASE0,
3277 .num_ports = 8,
3278 .base_baud = 115200,
3279 .uart_offset = 8,
3280 },
3281 [pbn_b0_1_921600] = {
3282 .flags = FL_BASE0,
3283 .num_ports = 1,
3284 .base_baud = 921600,
3285 .uart_offset = 8,
3286 },
3287 [pbn_b0_2_921600] = {
3288 .flags = FL_BASE0,
3289 .num_ports = 2,
3290 .base_baud = 921600,
3291 .uart_offset = 8,
3292 },
3293 [pbn_b0_4_921600] = {
3294 .flags = FL_BASE0,
3295 .num_ports = 4,
3296 .base_baud = 921600,
3297 .uart_offset = 8,
3298 },
3299 [pbn_b0_8_921600] = {
3300 .flags = FL_BASE0,
3301 .num_ports = 8,
3302 .base_baud = 921600,
3303 .uart_offset = 8,
3304 },
3305
3306 [pbn_b0_2_1130000] = {
3307 .flags = FL_BASE0,
3308 .num_ports = 2,
3309 .base_baud = 1130000,
3310 .uart_offset = 8,
3311 },
3312
3313 [pbn_b0_4_1152000] = {
3314 .flags = FL_BASE0,
3315 .num_ports = 4,
3316 .base_baud = 1152000,
3317 .uart_offset = 8,
3318 },
3319
3320 [pbn_b0_4_1250000] = {
3321 .flags = FL_BASE0,
3322 .num_ports = 4,
3323 .base_baud = 1250000,
3324 .uart_offset = 8,
3325 },
3326
3327 [pbn_b0_2_1843200] = {
3328 .flags = FL_BASE0,
3329 .num_ports = 2,
3330 .base_baud = 1843200,
3331 .uart_offset = 8,
3332 },
3333 [pbn_b0_4_1843200] = {
3334 .flags = FL_BASE0,
3335 .num_ports = 4,
3336 .base_baud = 1843200,
3337 .uart_offset = 8,
3338 },
3339
3340 [pbn_b0_1_15625000] = {
3341 .flags = FL_BASE0,
3342 .num_ports = 1,
3343 .base_baud = 15625000,
3344 .uart_offset = 8,
3345 },
3346
3347 [pbn_b0_bt_1_115200] = {
3348 .flags = FL_BASE0|FL_BASE_BARS,
3349 .num_ports = 1,
3350 .base_baud = 115200,
3351 .uart_offset = 8,
3352 },
3353 [pbn_b0_bt_2_115200] = {
3354 .flags = FL_BASE0|FL_BASE_BARS,
3355 .num_ports = 2,
3356 .base_baud = 115200,
3357 .uart_offset = 8,
3358 },
3359 [pbn_b0_bt_4_115200] = {
3360 .flags = FL_BASE0|FL_BASE_BARS,
3361 .num_ports = 4,
3362 .base_baud = 115200,
3363 .uart_offset = 8,
3364 },
3365 [pbn_b0_bt_8_115200] = {
3366 .flags = FL_BASE0|FL_BASE_BARS,
3367 .num_ports = 8,
3368 .base_baud = 115200,
3369 .uart_offset = 8,
3370 },
3371
3372 [pbn_b0_bt_1_460800] = {
3373 .flags = FL_BASE0|FL_BASE_BARS,
3374 .num_ports = 1,
3375 .base_baud = 460800,
3376 .uart_offset = 8,
3377 },
3378 [pbn_b0_bt_2_460800] = {
3379 .flags = FL_BASE0|FL_BASE_BARS,
3380 .num_ports = 2,
3381 .base_baud = 460800,
3382 .uart_offset = 8,
3383 },
3384 [pbn_b0_bt_4_460800] = {
3385 .flags = FL_BASE0|FL_BASE_BARS,
3386 .num_ports = 4,
3387 .base_baud = 460800,
3388 .uart_offset = 8,
3389 },
3390
3391 [pbn_b0_bt_1_921600] = {
3392 .flags = FL_BASE0|FL_BASE_BARS,
3393 .num_ports = 1,
3394 .base_baud = 921600,
3395 .uart_offset = 8,
3396 },
3397 [pbn_b0_bt_2_921600] = {
3398 .flags = FL_BASE0|FL_BASE_BARS,
3399 .num_ports = 2,
3400 .base_baud = 921600,
3401 .uart_offset = 8,
3402 },
3403 [pbn_b0_bt_4_921600] = {
3404 .flags = FL_BASE0|FL_BASE_BARS,
3405 .num_ports = 4,
3406 .base_baud = 921600,
3407 .uart_offset = 8,
3408 },
3409 [pbn_b0_bt_8_921600] = {
3410 .flags = FL_BASE0|FL_BASE_BARS,
3411 .num_ports = 8,
3412 .base_baud = 921600,
3413 .uart_offset = 8,
3414 },
3415
3416 [pbn_b1_1_115200] = {
3417 .flags = FL_BASE1,
3418 .num_ports = 1,
3419 .base_baud = 115200,
3420 .uart_offset = 8,
3421 },
3422 [pbn_b1_2_115200] = {
3423 .flags = FL_BASE1,
3424 .num_ports = 2,
3425 .base_baud = 115200,
3426 .uart_offset = 8,
3427 },
3428 [pbn_b1_4_115200] = {
3429 .flags = FL_BASE1,
3430 .num_ports = 4,
3431 .base_baud = 115200,
3432 .uart_offset = 8,
3433 },
3434 [pbn_b1_8_115200] = {
3435 .flags = FL_BASE1,
3436 .num_ports = 8,
3437 .base_baud = 115200,
3438 .uart_offset = 8,
3439 },
3440 [pbn_b1_16_115200] = {
3441 .flags = FL_BASE1,
3442 .num_ports = 16,
3443 .base_baud = 115200,
3444 .uart_offset = 8,
3445 },
3446
3447 [pbn_b1_1_921600] = {
3448 .flags = FL_BASE1,
3449 .num_ports = 1,
3450 .base_baud = 921600,
3451 .uart_offset = 8,
3452 },
3453 [pbn_b1_2_921600] = {
3454 .flags = FL_BASE1,
3455 .num_ports = 2,
3456 .base_baud = 921600,
3457 .uart_offset = 8,
3458 },
3459 [pbn_b1_4_921600] = {
3460 .flags = FL_BASE1,
3461 .num_ports = 4,
3462 .base_baud = 921600,
3463 .uart_offset = 8,
3464 },
3465 [pbn_b1_8_921600] = {
3466 .flags = FL_BASE1,
3467 .num_ports = 8,
3468 .base_baud = 921600,
3469 .uart_offset = 8,
3470 },
3471 [pbn_b1_2_1250000] = {
3472 .flags = FL_BASE1,
3473 .num_ports = 2,
3474 .base_baud = 1250000,
3475 .uart_offset = 8,
3476 },
3477
3478 [pbn_b1_bt_1_115200] = {
3479 .flags = FL_BASE1|FL_BASE_BARS,
3480 .num_ports = 1,
3481 .base_baud = 115200,
3482 .uart_offset = 8,
3483 },
3484 [pbn_b1_bt_2_115200] = {
3485 .flags = FL_BASE1|FL_BASE_BARS,
3486 .num_ports = 2,
3487 .base_baud = 115200,
3488 .uart_offset = 8,
3489 },
3490 [pbn_b1_bt_4_115200] = {
3491 .flags = FL_BASE1|FL_BASE_BARS,
3492 .num_ports = 4,
3493 .base_baud = 115200,
3494 .uart_offset = 8,
3495 },
3496
3497 [pbn_b1_bt_2_921600] = {
3498 .flags = FL_BASE1|FL_BASE_BARS,
3499 .num_ports = 2,
3500 .base_baud = 921600,
3501 .uart_offset = 8,
3502 },
3503
3504 [pbn_b1_1_1382400] = {
3505 .flags = FL_BASE1,
3506 .num_ports = 1,
3507 .base_baud = 1382400,
3508 .uart_offset = 8,
3509 },
3510 [pbn_b1_2_1382400] = {
3511 .flags = FL_BASE1,
3512 .num_ports = 2,
3513 .base_baud = 1382400,
3514 .uart_offset = 8,
3515 },
3516 [pbn_b1_4_1382400] = {
3517 .flags = FL_BASE1,
3518 .num_ports = 4,
3519 .base_baud = 1382400,
3520 .uart_offset = 8,
3521 },
3522 [pbn_b1_8_1382400] = {
3523 .flags = FL_BASE1,
3524 .num_ports = 8,
3525 .base_baud = 1382400,
3526 .uart_offset = 8,
3527 },
3528
3529 [pbn_b2_1_115200] = {
3530 .flags = FL_BASE2,
3531 .num_ports = 1,
3532 .base_baud = 115200,
3533 .uart_offset = 8,
3534 },
3535 [pbn_b2_2_115200] = {
3536 .flags = FL_BASE2,
3537 .num_ports = 2,
3538 .base_baud = 115200,
3539 .uart_offset = 8,
3540 },
3541 [pbn_b2_4_115200] = {
3542 .flags = FL_BASE2,
3543 .num_ports = 4,
3544 .base_baud = 115200,
3545 .uart_offset = 8,
3546 },
3547 [pbn_b2_8_115200] = {
3548 .flags = FL_BASE2,
3549 .num_ports = 8,
3550 .base_baud = 115200,
3551 .uart_offset = 8,
3552 },
3553
3554 [pbn_b2_1_460800] = {
3555 .flags = FL_BASE2,
3556 .num_ports = 1,
3557 .base_baud = 460800,
3558 .uart_offset = 8,
3559 },
3560 [pbn_b2_4_460800] = {
3561 .flags = FL_BASE2,
3562 .num_ports = 4,
3563 .base_baud = 460800,
3564 .uart_offset = 8,
3565 },
3566 [pbn_b2_8_460800] = {
3567 .flags = FL_BASE2,
3568 .num_ports = 8,
3569 .base_baud = 460800,
3570 .uart_offset = 8,
3571 },
3572 [pbn_b2_16_460800] = {
3573 .flags = FL_BASE2,
3574 .num_ports = 16,
3575 .base_baud = 460800,
3576 .uart_offset = 8,
3577 },
3578
3579 [pbn_b2_1_921600] = {
3580 .flags = FL_BASE2,
3581 .num_ports = 1,
3582 .base_baud = 921600,
3583 .uart_offset = 8,
3584 },
3585 [pbn_b2_4_921600] = {
3586 .flags = FL_BASE2,
3587 .num_ports = 4,
3588 .base_baud = 921600,
3589 .uart_offset = 8,
3590 },
3591 [pbn_b2_8_921600] = {
3592 .flags = FL_BASE2,
3593 .num_ports = 8,
3594 .base_baud = 921600,
3595 .uart_offset = 8,
3596 },
3597
3598 [pbn_b2_8_1152000] = {
3599 .flags = FL_BASE2,
3600 .num_ports = 8,
3601 .base_baud = 1152000,
3602 .uart_offset = 8,
3603 },
3604
3605 [pbn_b2_bt_1_115200] = {
3606 .flags = FL_BASE2|FL_BASE_BARS,
3607 .num_ports = 1,
3608 .base_baud = 115200,
3609 .uart_offset = 8,
3610 },
3611 [pbn_b2_bt_2_115200] = {
3612 .flags = FL_BASE2|FL_BASE_BARS,
3613 .num_ports = 2,
3614 .base_baud = 115200,
3615 .uart_offset = 8,
3616 },
3617 [pbn_b2_bt_4_115200] = {
3618 .flags = FL_BASE2|FL_BASE_BARS,
3619 .num_ports = 4,
3620 .base_baud = 115200,
3621 .uart_offset = 8,
3622 },
3623
3624 [pbn_b2_bt_2_921600] = {
3625 .flags = FL_BASE2|FL_BASE_BARS,
3626 .num_ports = 2,
3627 .base_baud = 921600,
3628 .uart_offset = 8,
3629 },
3630 [pbn_b2_bt_4_921600] = {
3631 .flags = FL_BASE2|FL_BASE_BARS,
3632 .num_ports = 4,
3633 .base_baud = 921600,
3634 .uart_offset = 8,
3635 },
3636
3637 [pbn_b3_2_115200] = {
3638 .flags = FL_BASE3,
3639 .num_ports = 2,
3640 .base_baud = 115200,
3641 .uart_offset = 8,
3642 },
3643 [pbn_b3_4_115200] = {
3644 .flags = FL_BASE3,
3645 .num_ports = 4,
3646 .base_baud = 115200,
3647 .uart_offset = 8,
3648 },
3649 [pbn_b3_8_115200] = {
3650 .flags = FL_BASE3,
3651 .num_ports = 8,
3652 .base_baud = 115200,
3653 .uart_offset = 8,
3654 },
3655
3656 [pbn_b4_bt_2_921600] = {
3657 .flags = FL_BASE4,
3658 .num_ports = 2,
3659 .base_baud = 921600,
3660 .uart_offset = 8,
3661 },
3662 [pbn_b4_bt_4_921600] = {
3663 .flags = FL_BASE4,
3664 .num_ports = 4,
3665 .base_baud = 921600,
3666 .uart_offset = 8,
3667 },
3668 [pbn_b4_bt_8_921600] = {
3669 .flags = FL_BASE4,
3670 .num_ports = 8,
3671 .base_baud = 921600,
3672 .uart_offset = 8,
3673 },
3674
3675 /*
3676 * Entries following this are board-specific.
3677 */
3678
3679 /*
3680 * Panacom - IOMEM
3681 */
3682 [pbn_panacom] = {
3683 .flags = FL_BASE2,
3684 .num_ports = 2,
3685 .base_baud = 921600,
3686 .uart_offset = 0x400,
3687 .reg_shift = 7,
3688 },
3689 [pbn_panacom2] = {
3690 .flags = FL_BASE2|FL_BASE_BARS,
3691 .num_ports = 2,
3692 .base_baud = 921600,
3693 .uart_offset = 0x400,
3694 .reg_shift = 7,
3695 },
3696 [pbn_panacom4] = {
3697 .flags = FL_BASE2|FL_BASE_BARS,
3698 .num_ports = 4,
3699 .base_baud = 921600,
3700 .uart_offset = 0x400,
3701 .reg_shift = 7,
3702 },
3703
3704 /* I think this entry is broken - the first_offset looks wrong --rmk */
3705 [pbn_plx_romulus] = {
3706 .flags = FL_BASE2,
3707 .num_ports = 4,
3708 .base_baud = 921600,
3709 .uart_offset = 8 << 2,
3710 .reg_shift = 2,
3711 .first_offset = 0x03,
3712 },
3713
3714 /*
3715 * This board uses the size of PCI Base region 0 to
3716 * signal now many ports are available
3717 */
3718 [pbn_oxsemi] = {
3719 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3720 .num_ports = 32,
3721 .base_baud = 115200,
3722 .uart_offset = 8,
3723 },
3724 [pbn_oxsemi_1_15625000] = {
3725 .flags = FL_BASE0,
3726 .num_ports = 1,
3727 .base_baud = 15625000,
3728 .uart_offset = 0x200,
3729 .first_offset = 0x1000,
3730 },
3731 [pbn_oxsemi_2_15625000] = {
3732 .flags = FL_BASE0,
3733 .num_ports = 2,
3734 .base_baud = 15625000,
3735 .uart_offset = 0x200,
3736 .first_offset = 0x1000,
3737 },
3738 [pbn_oxsemi_4_15625000] = {
3739 .flags = FL_BASE0,
3740 .num_ports = 4,
3741 .base_baud = 15625000,
3742 .uart_offset = 0x200,
3743 .first_offset = 0x1000,
3744 },
3745 [pbn_oxsemi_8_15625000] = {
3746 .flags = FL_BASE0,
3747 .num_ports = 8,
3748 .base_baud = 15625000,
3749 .uart_offset = 0x200,
3750 .first_offset = 0x1000,
3751 },
3752
3753
3754 /*
3755 * EKF addition for i960 Boards form EKF with serial port.
3756 * Max 256 ports.
3757 */
3758 [pbn_intel_i960] = {
3759 .flags = FL_BASE0,
3760 .num_ports = 32,
3761 .base_baud = 921600,
3762 .uart_offset = 8 << 2,
3763 .reg_shift = 2,
3764 .first_offset = 0x10000,
3765 },
3766 [pbn_sgi_ioc3] = {
3767 .flags = FL_BASE0|FL_NOIRQ,
3768 .num_ports = 1,
3769 .base_baud = 458333,
3770 .uart_offset = 8,
3771 .reg_shift = 0,
3772 .first_offset = 0x20178,
3773 },
3774
3775 /*
3776 * Computone - uses IOMEM.
3777 */
3778 [pbn_computone_4] = {
3779 .flags = FL_BASE0,
3780 .num_ports = 4,
3781 .base_baud = 921600,
3782 .uart_offset = 0x40,
3783 .reg_shift = 2,
3784 .first_offset = 0x200,
3785 },
3786 [pbn_computone_6] = {
3787 .flags = FL_BASE0,
3788 .num_ports = 6,
3789 .base_baud = 921600,
3790 .uart_offset = 0x40,
3791 .reg_shift = 2,
3792 .first_offset = 0x200,
3793 },
3794 [pbn_computone_8] = {
3795 .flags = FL_BASE0,
3796 .num_ports = 8,
3797 .base_baud = 921600,
3798 .uart_offset = 0x40,
3799 .reg_shift = 2,
3800 .first_offset = 0x200,
3801 },
3802 [pbn_sbsxrsio] = {
3803 .flags = FL_BASE0,
3804 .num_ports = 8,
3805 .base_baud = 460800,
3806 .uart_offset = 256,
3807 .reg_shift = 4,
3808 },
3809 /*
3810 * PA Semi PWRficient PA6T-1682M on-chip UART
3811 */
3812 [pbn_pasemi_1682M] = {
3813 .flags = FL_BASE0,
3814 .num_ports = 1,
3815 .base_baud = 8333333,
3816 },
3817 /*
3818 * National Instruments 843x
3819 */
3820 [pbn_ni8430_16] = {
3821 .flags = FL_BASE0,
3822 .num_ports = 16,
3823 .base_baud = 3686400,
3824 .uart_offset = 0x10,
3825 .first_offset = 0x800,
3826 },
3827 [pbn_ni8430_8] = {
3828 .flags = FL_BASE0,
3829 .num_ports = 8,
3830 .base_baud = 3686400,
3831 .uart_offset = 0x10,
3832 .first_offset = 0x800,
3833 },
3834 [pbn_ni8430_4] = {
3835 .flags = FL_BASE0,
3836 .num_ports = 4,
3837 .base_baud = 3686400,
3838 .uart_offset = 0x10,
3839 .first_offset = 0x800,
3840 },
3841 [pbn_ni8430_2] = {
3842 .flags = FL_BASE0,
3843 .num_ports = 2,
3844 .base_baud = 3686400,
3845 .uart_offset = 0x10,
3846 .first_offset = 0x800,
3847 },
3848 /*
3849 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3850 */
3851 [pbn_ADDIDATA_PCIe_1_3906250] = {
3852 .flags = FL_BASE0,
3853 .num_ports = 1,
3854 .base_baud = 3906250,
3855 .uart_offset = 0x200,
3856 .first_offset = 0x1000,
3857 },
3858 [pbn_ADDIDATA_PCIe_2_3906250] = {
3859 .flags = FL_BASE0,
3860 .num_ports = 2,
3861 .base_baud = 3906250,
3862 .uart_offset = 0x200,
3863 .first_offset = 0x1000,
3864 },
3865 [pbn_ADDIDATA_PCIe_4_3906250] = {
3866 .flags = FL_BASE0,
3867 .num_ports = 4,
3868 .base_baud = 3906250,
3869 .uart_offset = 0x200,
3870 .first_offset = 0x1000,
3871 },
3872 [pbn_ADDIDATA_PCIe_8_3906250] = {
3873 .flags = FL_BASE0,
3874 .num_ports = 8,
3875 .base_baud = 3906250,
3876 .uart_offset = 0x200,
3877 .first_offset = 0x1000,
3878 },
3879 [pbn_ce4100_1_115200] = {
3880 .flags = FL_BASE_BARS,
3881 .num_ports = 2,
3882 .base_baud = 921600,
3883 .reg_shift = 2,
3884 },
3885 [pbn_omegapci] = {
3886 .flags = FL_BASE0,
3887 .num_ports = 8,
3888 .base_baud = 115200,
3889 .uart_offset = 0x200,
3890 },
3891 [pbn_NETMOS9900_2s_115200] = {
3892 .flags = FL_BASE0,
3893 .num_ports = 2,
3894 .base_baud = 115200,
3895 },
3896 [pbn_brcm_trumanage] = {
3897 .flags = FL_BASE0,
3898 .num_ports = 1,
3899 .reg_shift = 2,
3900 .base_baud = 115200,
3901 },
3902 [pbn_fintek_4] = {
3903 .num_ports = 4,
3904 .uart_offset = 8,
3905 .base_baud = 115200,
3906 .first_offset = 0x40,
3907 },
3908 [pbn_fintek_8] = {
3909 .num_ports = 8,
3910 .uart_offset = 8,
3911 .base_baud = 115200,
3912 .first_offset = 0x40,
3913 },
3914 [pbn_fintek_12] = {
3915 .num_ports = 12,
3916 .uart_offset = 8,
3917 .base_baud = 115200,
3918 .first_offset = 0x40,
3919 },
3920 [pbn_fintek_F81504A] = {
3921 .num_ports = 4,
3922 .uart_offset = 8,
3923 .base_baud = 115200,
3924 },
3925 [pbn_fintek_F81508A] = {
3926 .num_ports = 8,
3927 .uart_offset = 8,
3928 .base_baud = 115200,
3929 },
3930 [pbn_fintek_F81512A] = {
3931 .num_ports = 12,
3932 .uart_offset = 8,
3933 .base_baud = 115200,
3934 },
3935 [pbn_wch382_2] = {
3936 .flags = FL_BASE0,
3937 .num_ports = 2,
3938 .base_baud = 115200,
3939 .uart_offset = 8,
3940 .first_offset = 0xC0,
3941 },
3942 [pbn_wch384_4] = {
3943 .flags = FL_BASE0,
3944 .num_ports = 4,
3945 .base_baud = 115200,
3946 .uart_offset = 8,
3947 .first_offset = 0xC0,
3948 },
3949 [pbn_wch384_8] = {
3950 .flags = FL_BASE0,
3951 .num_ports = 8,
3952 .base_baud = 115200,
3953 .uart_offset = 8,
3954 .first_offset = 0x00,
3955 },
3956 [pbn_sunix_pci_1s] = {
3957 .num_ports = 1,
3958 .base_baud = 921600,
3959 .uart_offset = 0x8,
3960 },
3961 [pbn_sunix_pci_2s] = {
3962 .num_ports = 2,
3963 .base_baud = 921600,
3964 .uart_offset = 0x8,
3965 },
3966 [pbn_sunix_pci_4s] = {
3967 .num_ports = 4,
3968 .base_baud = 921600,
3969 .uart_offset = 0x8,
3970 },
3971 [pbn_sunix_pci_8s] = {
3972 .num_ports = 8,
3973 .base_baud = 921600,
3974 .uart_offset = 0x8,
3975 },
3976 [pbn_sunix_pci_16s] = {
3977 .num_ports = 16,
3978 .base_baud = 921600,
3979 .uart_offset = 0x8,
3980 },
3981 [pbn_titan_1_4000000] = {
3982 .flags = FL_BASE0,
3983 .num_ports = 1,
3984 .base_baud = 4000000,
3985 .uart_offset = 0x200,
3986 .first_offset = 0x1000,
3987 },
3988 [pbn_titan_2_4000000] = {
3989 .flags = FL_BASE0,
3990 .num_ports = 2,
3991 .base_baud = 4000000,
3992 .uart_offset = 0x200,
3993 .first_offset = 0x1000,
3994 },
3995 [pbn_titan_4_4000000] = {
3996 .flags = FL_BASE0,
3997 .num_ports = 4,
3998 .base_baud = 4000000,
3999 .uart_offset = 0x200,
4000 .first_offset = 0x1000,
4001 },
4002 [pbn_titan_8_4000000] = {
4003 .flags = FL_BASE0,
4004 .num_ports = 8,
4005 .base_baud = 4000000,
4006 .uart_offset = 0x200,
4007 .first_offset = 0x1000,
4008 },
4009 [pbn_moxa_2] = {
4010 .flags = FL_BASE1,
4011 .num_ports = 2,
4012 .base_baud = 921600,
4013 .uart_offset = 0x200,
4014 },
4015 [pbn_moxa_4] = {
4016 .flags = FL_BASE1,
4017 .num_ports = 4,
4018 .base_baud = 921600,
4019 .uart_offset = 0x200,
4020 },
4021 [pbn_moxa_8] = {
4022 .flags = FL_BASE1,
4023 .num_ports = 8,
4024 .base_baud = 921600,
4025 .uart_offset = 0x200,
4026 },
4027 };
4028
4029 #define REPORT_CONFIG(option) \
4030 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option)
4031 #define REPORT_8250_CONFIG(option) \
4032 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \
4033 0 : (kernel_ulong_t)&"SERIAL_8250_"#option)
4034
4035 static const struct pci_device_id blacklist[] = {
4036 /* softmodems */
4037 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
4038 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
4039 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
4040
4041 /* multi-io cards handled by parport_serial */
4042 /* WCH CH353 2S1P */
4043 { PCI_VDEVICE(WCHCN, 0x7053), REPORT_CONFIG(PARPORT_SERIAL), },
4044 /* WCH CH353 1S1P */
4045 { PCI_VDEVICE(WCHCN, 0x5053), REPORT_CONFIG(PARPORT_SERIAL), },
4046 /* WCH CH382 2S1P */
4047 { PCI_VDEVICE(WCHIC, 0x3250), REPORT_CONFIG(PARPORT_SERIAL), },
4048
4049 /* Intel platforms with MID UART */
4050 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
4051 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
4052 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
4053 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
4054 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
4055 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
4056
4057 /* Intel platforms with DesignWare UART */
4058 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
4059 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
4060 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
4061 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
4062 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
4063 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
4064 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
4065 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
4066 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
4067 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
4068 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
4069 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
4070 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
4071
4072 /* Exar devices */
4073 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
4074 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
4075
4076 /* Pericom devices */
4077 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
4078 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
4079
4080 /* End of the black list */
4081 { }
4082 };
4083
serial_pci_is_class_communication(struct pci_dev * dev)4084 static int serial_pci_is_class_communication(struct pci_dev *dev)
4085 {
4086 /*
4087 * If it is not a communications device or the programming
4088 * interface is greater than 6, give up.
4089 */
4090 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
4091 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
4092 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
4093 (dev->class & 0xff) > 6)
4094 return -ENODEV;
4095
4096 return 0;
4097 }
4098
4099 /*
4100 * Given a complete unknown PCI device, try to use some heuristics to
4101 * guess what the configuration might be, based on the pitiful PCI
4102 * serial specs. Returns 0 on success, -ENODEV on failure.
4103 */
4104 static int
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)4105 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
4106 {
4107 int num_iomem, num_port, first_port = -1, i;
4108 int rc;
4109
4110 rc = serial_pci_is_class_communication(dev);
4111 if (rc)
4112 return rc;
4113
4114 /*
4115 * Should we try to make guesses for multiport serial devices later?
4116 */
4117 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
4118 return -ENODEV;
4119
4120 num_iomem = num_port = 0;
4121 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4122 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
4123 num_port++;
4124 if (first_port == -1)
4125 first_port = i;
4126 }
4127 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
4128 num_iomem++;
4129 }
4130
4131 /*
4132 * If there is 1 or 0 iomem regions, and exactly one port,
4133 * use it. We guess the number of ports based on the IO
4134 * region size.
4135 */
4136 if (num_iomem <= 1 && num_port == 1) {
4137 board->flags = first_port;
4138 board->num_ports = pci_resource_len(dev, first_port) / 8;
4139 return 0;
4140 }
4141
4142 /*
4143 * Now guess if we've got a board which indexes by BARs.
4144 * Each IO BAR should be 8 bytes, and they should follow
4145 * consecutively.
4146 */
4147 first_port = -1;
4148 num_port = 0;
4149 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4150 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
4151 pci_resource_len(dev, i) == 8 &&
4152 (first_port == -1 || (first_port + num_port) == i)) {
4153 num_port++;
4154 if (first_port == -1)
4155 first_port = i;
4156 }
4157 }
4158
4159 if (num_port > 1) {
4160 board->flags = first_port | FL_BASE_BARS;
4161 board->num_ports = num_port;
4162 return 0;
4163 }
4164
4165 return -ENODEV;
4166 }
4167
4168 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)4169 serial_pci_matches(const struct pciserial_board *board,
4170 const struct pciserial_board *guessed)
4171 {
4172 return
4173 board->num_ports == guessed->num_ports &&
4174 board->base_baud == guessed->base_baud &&
4175 board->uart_offset == guessed->uart_offset &&
4176 board->reg_shift == guessed->reg_shift &&
4177 board->first_offset == guessed->first_offset;
4178 }
4179
4180 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)4181 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
4182 {
4183 struct uart_8250_port uart;
4184 struct serial_private *priv;
4185 struct pci_serial_quirk *quirk;
4186 int rc, nr_ports, i;
4187
4188 nr_ports = board->num_ports;
4189
4190 /*
4191 * Find an init and setup quirks.
4192 */
4193 quirk = find_quirk(dev);
4194
4195 /*
4196 * Run the new-style initialization function.
4197 * The initialization function returns:
4198 * <0 - error
4199 * 0 - use board->num_ports
4200 * >0 - number of ports
4201 */
4202 if (quirk->init) {
4203 rc = quirk->init(dev);
4204 if (rc < 0) {
4205 priv = ERR_PTR(rc);
4206 goto err_out;
4207 }
4208 if (rc)
4209 nr_ports = rc;
4210 }
4211
4212 priv = kzalloc_flex(*priv, line, nr_ports);
4213 if (!priv) {
4214 priv = ERR_PTR(-ENOMEM);
4215 goto err_deinit;
4216 }
4217
4218 priv->dev = dev;
4219 priv->quirk = quirk;
4220
4221 memset(&uart, 0, sizeof(uart));
4222 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4223 uart.port.uartclk = board->base_baud * 16;
4224
4225 if (board->flags & FL_NOIRQ) {
4226 uart.port.irq = 0;
4227 } else {
4228 if (pci_match_id(pci_use_msi, dev)) {
4229 pci_dbg(dev, "Using MSI(-X) interrupts\n");
4230 pci_set_master(dev);
4231 uart.port.flags &= ~UPF_SHARE_IRQ;
4232 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
4233 } else {
4234 pci_dbg(dev, "Using legacy interrupts\n");
4235 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_INTX);
4236 }
4237 if (rc < 0) {
4238 kfree(priv);
4239 priv = ERR_PTR(rc);
4240 goto err_deinit;
4241 }
4242
4243 uart.port.irq = pci_irq_vector(dev, 0);
4244 }
4245
4246 uart.port.dev = &dev->dev;
4247
4248 for (i = 0; i < nr_ports; i++) {
4249 if (quirk->setup(priv, board, &uart, i))
4250 break;
4251
4252 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4253 uart.port.iobase, uart.port.irq, uart.port.iotype);
4254
4255 priv->line[i] = serial8250_register_8250_port(&uart);
4256 if (priv->line[i] < 0) {
4257 pci_err(dev,
4258 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4259 uart.port.iobase, uart.port.irq,
4260 uart.port.iotype, priv->line[i]);
4261 break;
4262 }
4263 }
4264 priv->nr = i;
4265 priv->board = board;
4266 return priv;
4267
4268 err_deinit:
4269 if (quirk->exit)
4270 quirk->exit(dev);
4271 err_out:
4272 return priv;
4273 }
4274 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4275
pciserial_detach_ports(struct serial_private * priv)4276 static void pciserial_detach_ports(struct serial_private *priv)
4277 {
4278 struct pci_serial_quirk *quirk;
4279 int i;
4280
4281 for (i = 0; i < priv->nr; i++)
4282 serial8250_unregister_port(priv->line[i]);
4283
4284 /*
4285 * Find the exit quirks.
4286 */
4287 quirk = find_quirk(priv->dev);
4288 if (quirk->exit)
4289 quirk->exit(priv->dev);
4290 }
4291
pciserial_remove_ports(struct serial_private * priv)4292 void pciserial_remove_ports(struct serial_private *priv)
4293 {
4294 pciserial_detach_ports(priv);
4295 kfree(priv);
4296 }
4297 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4298
pciserial_suspend_ports(struct serial_private * priv)4299 void pciserial_suspend_ports(struct serial_private *priv)
4300 {
4301 int i;
4302
4303 for (i = 0; i < priv->nr; i++)
4304 if (priv->line[i] >= 0)
4305 serial8250_suspend_port(priv->line[i]);
4306
4307 /*
4308 * Ensure that every init quirk is properly torn down
4309 */
4310 if (priv->quirk->exit)
4311 priv->quirk->exit(priv->dev);
4312 }
4313 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4314
pciserial_resume_ports(struct serial_private * priv)4315 void pciserial_resume_ports(struct serial_private *priv)
4316 {
4317 int i;
4318
4319 /*
4320 * Ensure that the board is correctly configured.
4321 */
4322 if (priv->quirk->init)
4323 priv->quirk->init(priv->dev);
4324
4325 for (i = 0; i < priv->nr; i++)
4326 if (priv->line[i] >= 0)
4327 serial8250_resume_port(priv->line[i]);
4328 }
4329 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4330
4331 /*
4332 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4333 * to the arrangement of serial ports on a PCI card.
4334 */
4335 static int
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)4336 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4337 {
4338 struct pci_serial_quirk *quirk;
4339 struct serial_private *priv;
4340 const struct pciserial_board *board;
4341 const struct pci_device_id *exclude;
4342 struct pciserial_board tmp;
4343 int rc;
4344
4345 quirk = find_quirk(dev);
4346 if (quirk->probe) {
4347 rc = quirk->probe(dev);
4348 if (rc)
4349 return rc;
4350 }
4351
4352 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4353 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data);
4354 return -EINVAL;
4355 }
4356
4357 board = &pci_boards[ent->driver_data];
4358
4359 exclude = pci_match_id(blacklist, dev);
4360 if (exclude) {
4361 if (exclude->driver_data)
4362 pci_warn(dev, "ignoring port, enable %s to handle\n",
4363 (const char *)exclude->driver_data);
4364 return -ENODEV;
4365 }
4366
4367 rc = pcim_enable_device(dev);
4368 pci_save_state(dev);
4369 if (rc)
4370 return rc;
4371
4372 if (ent->driver_data == pbn_default) {
4373 /*
4374 * Use a copy of the pci_board entry for this;
4375 * avoid changing entries in the table.
4376 */
4377 memcpy(&tmp, board, sizeof(struct pciserial_board));
4378 board = &tmp;
4379
4380 /*
4381 * We matched one of our class entries. Try to
4382 * determine the parameters of this board.
4383 */
4384 rc = serial_pci_guess_board(dev, &tmp);
4385 if (rc)
4386 return rc;
4387 } else {
4388 /*
4389 * We matched an explicit entry. If we are able to
4390 * detect this boards settings with our heuristic,
4391 * then we no longer need this entry.
4392 */
4393 memcpy(&tmp, &pci_boards[pbn_default],
4394 sizeof(struct pciserial_board));
4395 rc = serial_pci_guess_board(dev, &tmp);
4396 if (rc == 0 && serial_pci_matches(board, &tmp))
4397 moan_device("Redundant entry in serial pci_table.",
4398 dev);
4399 }
4400
4401 priv = pciserial_init_ports(dev, board);
4402 if (IS_ERR(priv))
4403 return PTR_ERR(priv);
4404
4405 pci_set_drvdata(dev, priv);
4406 return 0;
4407 }
4408
pciserial_remove_one(struct pci_dev * dev)4409 static void pciserial_remove_one(struct pci_dev *dev)
4410 {
4411 struct serial_private *priv = pci_get_drvdata(dev);
4412
4413 pciserial_remove_ports(priv);
4414 }
4415
4416 #ifdef CONFIG_PM_SLEEP
pciserial_suspend_one(struct device * dev)4417 static int pciserial_suspend_one(struct device *dev)
4418 {
4419 struct serial_private *priv = dev_get_drvdata(dev);
4420
4421 if (priv)
4422 pciserial_suspend_ports(priv);
4423
4424 return 0;
4425 }
4426
pciserial_resume_one(struct device * dev)4427 static int pciserial_resume_one(struct device *dev)
4428 {
4429 struct pci_dev *pdev = to_pci_dev(dev);
4430 struct serial_private *priv = pci_get_drvdata(pdev);
4431 int err;
4432
4433 if (priv) {
4434 /*
4435 * The device may have been disabled. Re-enable it.
4436 */
4437 err = pci_enable_device(pdev);
4438 /* FIXME: We cannot simply error out here */
4439 if (err)
4440 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n");
4441 pciserial_resume_ports(priv);
4442 }
4443 return 0;
4444 }
4445 #endif
4446
4447 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4448 pciserial_resume_one);
4449
4450 static const struct pci_device_id serial_pci_tbl[] = {
4451 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
4452 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
4453 pbn_b0_4_921600 },
4454 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4455 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4456 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4457 pbn_b2_8_921600 },
4458 /* Advantech also use 0x3618 and 0xf618 */
4459 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4460 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4461 pbn_b0_4_921600 },
4462 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4463 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4464 pbn_b0_4_921600 },
4465 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4466 PCI_SUBVENDOR_ID_CONNECT_TECH,
4467 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4468 pbn_b1_8_1382400 },
4469 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4470 PCI_SUBVENDOR_ID_CONNECT_TECH,
4471 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4472 pbn_b1_4_1382400 },
4473 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4474 PCI_SUBVENDOR_ID_CONNECT_TECH,
4475 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4476 pbn_b1_2_1382400 },
4477 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4478 PCI_SUBVENDOR_ID_CONNECT_TECH,
4479 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4480 pbn_b1_8_1382400 },
4481 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4482 PCI_SUBVENDOR_ID_CONNECT_TECH,
4483 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4484 pbn_b1_4_1382400 },
4485 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4486 PCI_SUBVENDOR_ID_CONNECT_TECH,
4487 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4488 pbn_b1_2_1382400 },
4489 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4490 PCI_SUBVENDOR_ID_CONNECT_TECH,
4491 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4492 pbn_b1_8_921600 },
4493 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4494 PCI_SUBVENDOR_ID_CONNECT_TECH,
4495 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4496 pbn_b1_8_921600 },
4497 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4498 PCI_SUBVENDOR_ID_CONNECT_TECH,
4499 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4500 pbn_b1_4_921600 },
4501 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4502 PCI_SUBVENDOR_ID_CONNECT_TECH,
4503 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4504 pbn_b1_4_921600 },
4505 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4506 PCI_SUBVENDOR_ID_CONNECT_TECH,
4507 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4508 pbn_b1_2_921600 },
4509 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4510 PCI_SUBVENDOR_ID_CONNECT_TECH,
4511 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4512 pbn_b1_8_921600 },
4513 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4514 PCI_SUBVENDOR_ID_CONNECT_TECH,
4515 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4516 pbn_b1_8_921600 },
4517 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4518 PCI_SUBVENDOR_ID_CONNECT_TECH,
4519 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4520 pbn_b1_4_921600 },
4521 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4522 PCI_SUBVENDOR_ID_CONNECT_TECH,
4523 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4524 pbn_b1_2_1250000 },
4525 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4526 PCI_SUBVENDOR_ID_CONNECT_TECH,
4527 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4528 pbn_b0_2_1843200 },
4529 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4530 PCI_SUBVENDOR_ID_CONNECT_TECH,
4531 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4532 pbn_b0_4_1843200 },
4533 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4534 PCI_VENDOR_ID_AFAVLAB,
4535 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4536 pbn_b0_4_1152000 },
4537 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4539 pbn_b2_bt_1_115200 },
4540 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4542 pbn_b2_bt_2_115200 },
4543 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545 pbn_b2_bt_4_115200 },
4546 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548 pbn_b2_bt_2_115200 },
4549 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551 pbn_b2_bt_4_115200 },
4552 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554 pbn_b2_8_115200 },
4555 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4556 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4557 pbn_b2_8_460800 },
4558 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4559 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4560 pbn_b2_8_115200 },
4561
4562 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4563 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4564 pbn_b2_bt_2_115200 },
4565 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4566 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4567 pbn_b2_bt_2_921600 },
4568 /*
4569 * VScom SPCOM800, from sl@s.pl
4570 */
4571 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4572 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4573 pbn_b2_8_921600 },
4574 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4575 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4576 pbn_b2_4_921600 },
4577 /* Unknown card - subdevice 0x1584 */
4578 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4579 PCI_VENDOR_ID_PLX,
4580 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4581 pbn_b2_4_115200 },
4582 /* Unknown card - subdevice 0x1588 */
4583 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4584 PCI_VENDOR_ID_PLX,
4585 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4586 pbn_b2_8_115200 },
4587 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4588 PCI_SUBVENDOR_ID_KEYSPAN,
4589 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4590 pbn_panacom },
4591 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_panacom4 },
4594 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_panacom2 },
4597 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4598 PCI_VENDOR_ID_ESDGMBH,
4599 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4600 pbn_b2_4_115200 },
4601 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4602 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4603 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4604 pbn_b2_4_460800 },
4605 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4606 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4607 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4608 pbn_b2_8_460800 },
4609 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4610 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4611 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4612 pbn_b2_16_460800 },
4613 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4614 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4615 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4616 pbn_b2_16_460800 },
4617 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4618 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4619 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4620 pbn_b2_4_460800 },
4621 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4622 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4623 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4624 pbn_b2_8_460800 },
4625 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4626 PCI_SUBVENDOR_ID_EXSYS,
4627 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4628 pbn_b2_4_115200 },
4629 /*
4630 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4631 * (Exoray@isys.ca)
4632 */
4633 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4634 0x10b5, 0x106a, 0, 0,
4635 pbn_plx_romulus },
4636 /*
4637 * Quatech cards. These actually have configurable clocks but for
4638 * now we just use the default.
4639 *
4640 * 100 series are RS232, 200 series RS422,
4641 */
4642 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 pbn_b1_4_115200 },
4645 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 pbn_b1_2_115200 },
4648 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650 pbn_b2_2_115200 },
4651 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653 pbn_b1_2_115200 },
4654 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656 pbn_b2_2_115200 },
4657 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4658 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4659 pbn_b1_4_115200 },
4660 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662 pbn_b1_8_115200 },
4663 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4664 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4665 pbn_b1_8_115200 },
4666 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4667 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4668 pbn_b1_4_115200 },
4669 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4670 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4671 pbn_b1_2_115200 },
4672 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4674 pbn_b1_4_115200 },
4675 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4677 pbn_b1_2_115200 },
4678 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4680 pbn_b2_4_115200 },
4681 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4682 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4683 pbn_b2_2_115200 },
4684 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4685 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4686 pbn_b2_1_115200 },
4687 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4688 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4689 pbn_b2_4_115200 },
4690 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4691 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4692 pbn_b2_2_115200 },
4693 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695 pbn_b2_1_115200 },
4696 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4698 pbn_b0_8_115200 },
4699
4700 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4701 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4702 0, 0,
4703 pbn_b0_4_921600 },
4704 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4705 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4706 0, 0,
4707 pbn_b0_4_1152000 },
4708 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 pbn_b0_bt_2_921600 },
4711
4712 /*
4713 * The below card is a little controversial since it is the
4714 * subject of a PCI vendor/device ID clash. (See
4715 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4716 * For now just used the hex ID 0x950a.
4717 */
4718 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4719 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4720 0, 0, pbn_b0_2_115200 },
4721 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4722 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4723 0, 0, pbn_b0_2_115200 },
4724 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726 pbn_b0_2_1130000 },
4727 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4728 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4729 pbn_b0_1_921600 },
4730 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4732 pbn_b0_4_115200 },
4733 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735 pbn_b0_bt_2_921600 },
4736 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4738 pbn_b2_8_1152000 },
4739
4740 /*
4741 * Oxford Semiconductor Inc. Tornado PCI express device range.
4742 */
4743 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4745 pbn_b0_1_15625000 },
4746 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4748 pbn_b0_1_15625000 },
4749 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4751 pbn_oxsemi_1_15625000 },
4752 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4754 pbn_oxsemi_1_15625000 },
4755 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4757 pbn_b0_1_15625000 },
4758 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4760 pbn_b0_1_15625000 },
4761 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4763 pbn_oxsemi_1_15625000 },
4764 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4766 pbn_oxsemi_1_15625000 },
4767 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4769 pbn_b0_1_15625000 },
4770 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4772 pbn_b0_1_15625000 },
4773 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4775 pbn_b0_1_15625000 },
4776 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4778 pbn_b0_1_15625000 },
4779 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4781 pbn_oxsemi_2_15625000 },
4782 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784 pbn_oxsemi_2_15625000 },
4785 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787 pbn_oxsemi_4_15625000 },
4788 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790 pbn_oxsemi_4_15625000 },
4791 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793 pbn_oxsemi_8_15625000 },
4794 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796 pbn_oxsemi_8_15625000 },
4797 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799 pbn_oxsemi_1_15625000 },
4800 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4802 pbn_oxsemi_1_15625000 },
4803 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805 pbn_oxsemi_1_15625000 },
4806 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4808 pbn_oxsemi_1_15625000 },
4809 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811 pbn_oxsemi_1_15625000 },
4812 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814 pbn_oxsemi_1_15625000 },
4815 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4816 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4817 pbn_oxsemi_1_15625000 },
4818 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4819 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4820 pbn_oxsemi_1_15625000 },
4821 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4822 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4823 pbn_oxsemi_1_15625000 },
4824 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4825 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4826 pbn_oxsemi_1_15625000 },
4827 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4828 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4829 pbn_oxsemi_1_15625000 },
4830 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4832 pbn_oxsemi_1_15625000 },
4833 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4834 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4835 pbn_oxsemi_1_15625000 },
4836 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4837 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4838 pbn_oxsemi_1_15625000 },
4839 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4840 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4841 pbn_oxsemi_1_15625000 },
4842 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4843 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4844 pbn_oxsemi_1_15625000 },
4845 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4847 pbn_oxsemi_1_15625000 },
4848 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4849 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4850 pbn_oxsemi_1_15625000 },
4851 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4853 pbn_oxsemi_1_15625000 },
4854 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4855 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4856 pbn_oxsemi_1_15625000 },
4857 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4858 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4859 pbn_oxsemi_1_15625000 },
4860 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4862 pbn_oxsemi_1_15625000 },
4863 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4864 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4865 pbn_oxsemi_1_15625000 },
4866 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4868 pbn_oxsemi_1_15625000 },
4869 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4870 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4871 pbn_oxsemi_1_15625000 },
4872 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4873 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4874 pbn_oxsemi_1_15625000 },
4875 /*
4876 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4877 */
4878 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4879 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4880 pbn_oxsemi_1_15625000 },
4881 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4882 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4883 pbn_oxsemi_2_15625000 },
4884 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4885 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4886 pbn_oxsemi_4_15625000 },
4887 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4888 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4889 pbn_oxsemi_8_15625000 },
4890
4891 /*
4892 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4893 */
4894 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4895 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4896 pbn_oxsemi_2_15625000 },
4897 /*
4898 * EndRun Technologies. PCI express device range.
4899 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
4900 */
4901 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4902 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4903 pbn_oxsemi_2_15625000 },
4904
4905 /*
4906 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4907 * from skokodyn@yahoo.com
4908 */
4909 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4910 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4911 pbn_sbsxrsio },
4912 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4913 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4914 pbn_sbsxrsio },
4915 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4916 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4917 pbn_sbsxrsio },
4918 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4919 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4920 pbn_sbsxrsio },
4921
4922 /*
4923 * Digitan DS560-558, from jimd@esoft.com
4924 */
4925 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4926 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4927 pbn_b1_1_115200 },
4928
4929 /*
4930 * Titan Electronic cards
4931 * The 400L and 800L have a custom setup quirk.
4932 */
4933 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4935 pbn_b0_1_921600 },
4936 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4938 pbn_b0_2_921600 },
4939 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4941 pbn_b0_4_921600 },
4942 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944 pbn_b0_4_921600 },
4945 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4947 pbn_b1_1_921600 },
4948 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4950 pbn_b1_bt_2_921600 },
4951 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4953 pbn_b0_bt_4_921600 },
4954 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4956 pbn_b0_bt_8_921600 },
4957 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4959 pbn_b4_bt_2_921600 },
4960 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4962 pbn_b4_bt_4_921600 },
4963 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4965 pbn_b4_bt_8_921600 },
4966 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4968 pbn_b0_4_921600 },
4969 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4971 pbn_b0_4_921600 },
4972 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4974 pbn_b0_4_921600 },
4975 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4977 pbn_titan_1_4000000 },
4978 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4980 pbn_titan_2_4000000 },
4981 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4983 pbn_titan_4_4000000 },
4984 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4986 pbn_titan_8_4000000 },
4987 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4989 pbn_titan_2_4000000 },
4990 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4992 pbn_titan_2_4000000 },
4993 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4995 pbn_b0_bt_2_921600 },
4996 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4998 pbn_b0_4_921600 },
4999 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
5000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5001 pbn_b0_4_921600 },
5002 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
5003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5004 pbn_b0_4_921600 },
5005 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
5006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5007 pbn_b0_4_921600 },
5008
5009 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
5010 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5011 pbn_b2_1_460800 },
5012 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
5013 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5014 pbn_b2_1_460800 },
5015 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
5016 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5017 pbn_b2_1_460800 },
5018 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
5019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5020 pbn_b2_bt_2_921600 },
5021 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
5022 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5023 pbn_b2_bt_2_921600 },
5024 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
5025 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5026 pbn_b2_bt_2_921600 },
5027 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
5028 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5029 pbn_b2_bt_4_921600 },
5030 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
5031 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5032 pbn_b2_bt_4_921600 },
5033 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
5034 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5035 pbn_b2_bt_4_921600 },
5036 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
5037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5038 pbn_b0_1_921600 },
5039 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
5040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5041 pbn_b0_1_921600 },
5042 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
5043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5044 pbn_b0_1_921600 },
5045 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
5046 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5047 pbn_b0_bt_2_921600 },
5048 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
5049 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5050 pbn_b0_bt_2_921600 },
5051 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
5052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5053 pbn_b0_bt_2_921600 },
5054 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
5055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5056 pbn_b0_bt_4_921600 },
5057 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
5058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5059 pbn_b0_bt_4_921600 },
5060 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
5061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5062 pbn_b0_bt_4_921600 },
5063 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
5064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5065 pbn_b0_bt_8_921600 },
5066 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
5067 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5068 pbn_b0_bt_8_921600 },
5069 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
5070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5071 pbn_b0_bt_8_921600 },
5072
5073 /*
5074 * Computone devices submitted by Doug McNash dmcnash@computone.com
5075 */
5076 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5077 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
5078 0, 0, pbn_computone_4 },
5079 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5080 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
5081 0, 0, pbn_computone_8 },
5082 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5083 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
5084 0, 0, pbn_computone_6 },
5085
5086 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
5087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5088 pbn_oxsemi },
5089 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
5090 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
5091 pbn_b0_bt_1_921600 },
5092
5093 /*
5094 * Sunix PCI serial boards
5095 */
5096 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5097 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
5098 pbn_sunix_pci_1s },
5099 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5100 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
5101 pbn_sunix_pci_2s },
5102 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5103 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
5104 pbn_sunix_pci_4s },
5105 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5106 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
5107 pbn_sunix_pci_4s },
5108 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5109 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
5110 pbn_sunix_pci_8s },
5111 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5112 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
5113 pbn_sunix_pci_8s },
5114 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5115 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
5116 pbn_sunix_pci_16s },
5117
5118 /*
5119 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
5120 */
5121 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
5122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5123 pbn_b0_bt_8_115200 },
5124 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
5125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5126 pbn_b0_bt_8_115200 },
5127
5128 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
5129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5130 pbn_b0_bt_2_115200 },
5131 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
5132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5133 pbn_b0_bt_2_115200 },
5134 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
5135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5136 pbn_b0_bt_2_115200 },
5137 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
5138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5139 pbn_b0_bt_4_460800 },
5140 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
5141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5142 pbn_b0_bt_4_460800 },
5143 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
5144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5145 pbn_b0_bt_2_460800 },
5146 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
5147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5148 pbn_b0_bt_2_460800 },
5149 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
5150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5151 pbn_b0_bt_2_460800 },
5152 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
5153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5154 pbn_b0_bt_1_115200 },
5155 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
5156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5157 pbn_b0_bt_1_460800 },
5158
5159 /*
5160 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
5161 * Cards are identified by their subsystem vendor IDs, which
5162 * (in hex) match the model number.
5163 *
5164 * Note that JC140x are RS422/485 cards which require ox950
5165 * ACR = 0x10, and as such are not currently fully supported.
5166 */
5167 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5168 0x1204, 0x0004, 0, 0,
5169 pbn_b0_4_921600 },
5170 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5171 0x1208, 0x0004, 0, 0,
5172 pbn_b0_4_921600 },
5173 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5174 0x1402, 0x0002, 0, 0,
5175 pbn_b0_2_921600 }, */
5176 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5177 0x1404, 0x0004, 0, 0,
5178 pbn_b0_4_921600 }, */
5179 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5180 0x1208, 0x0004, 0, 0,
5181 pbn_b0_4_921600 },
5182
5183 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5184 0x1204, 0x0004, 0, 0,
5185 pbn_b0_4_921600 },
5186 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5187 0x1208, 0x0004, 0, 0,
5188 pbn_b0_4_921600 },
5189 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5190 0x1208, 0x0004, 0, 0,
5191 pbn_b0_4_921600 },
5192 /*
5193 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5194 */
5195 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5196 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5197 pbn_b1_1_1382400 },
5198
5199 /*
5200 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5201 */
5202 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5204 pbn_b1_1_1382400 },
5205
5206 /*
5207 * RAStel 2 port modem, gerg@moreton.com.au
5208 */
5209 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5211 pbn_b2_bt_2_115200 },
5212
5213 /*
5214 * EKF addition for i960 Boards form EKF with serial port
5215 */
5216 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5217 0xE4BF, PCI_ANY_ID, 0, 0,
5218 pbn_intel_i960 },
5219
5220 /*
5221 * Xircom Cardbus/Ethernet combos
5222 */
5223 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5225 pbn_b0_1_115200 },
5226 /*
5227 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5228 */
5229 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5231 pbn_b0_1_115200 },
5232
5233 /*
5234 * Untested PCI modems, sent in from various folks...
5235 */
5236
5237 /*
5238 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5239 */
5240 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5241 0x1048, 0x1500, 0, 0,
5242 pbn_b1_1_115200 },
5243
5244 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5245 0xFF00, 0, 0, 0,
5246 pbn_sgi_ioc3 },
5247
5248 /*
5249 * HP Diva card
5250 */
5251 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5252 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5253 pbn_b1_1_115200 },
5254 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5255 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5256 pbn_b0_5_115200 },
5257 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5258 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5259 pbn_b2_1_115200 },
5260 /* HPE PCI serial device */
5261 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
5262 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5263 pbn_b1_1_115200 },
5264
5265 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5267 pbn_b3_2_115200 },
5268 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5270 pbn_b3_4_115200 },
5271 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5273 pbn_b3_8_115200 },
5274 /*
5275 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5276 */
5277 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5279 pbn_b0_1_115200 },
5280 /*
5281 * ITE
5282 */
5283 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5284 PCI_ANY_ID, PCI_ANY_ID,
5285 0, 0,
5286 pbn_b1_bt_1_115200 },
5287
5288 /*
5289 * IntaShield IS-100
5290 */
5291 { PCI_VENDOR_ID_INTASHIELD, 0x0D60,
5292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5293 pbn_b2_1_115200 },
5294 /*
5295 * IntaShield IS-200
5296 */
5297 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */
5299 pbn_b2_2_115200 },
5300 /*
5301 * IntaShield IS-400
5302 */
5303 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5305 pbn_b2_4_115200 },
5306 /*
5307 * IntaShield IX-100
5308 */
5309 { PCI_VENDOR_ID_INTASHIELD, 0x4027,
5310 PCI_ANY_ID, PCI_ANY_ID,
5311 0, 0,
5312 pbn_oxsemi_1_15625000 },
5313 /*
5314 * IntaShield IX-200
5315 */
5316 { PCI_VENDOR_ID_INTASHIELD, 0x4028,
5317 PCI_ANY_ID, PCI_ANY_ID,
5318 0, 0,
5319 pbn_oxsemi_2_15625000 },
5320 /*
5321 * IntaShield IX-400
5322 */
5323 { PCI_VENDOR_ID_INTASHIELD, 0x4029,
5324 PCI_ANY_ID, PCI_ANY_ID,
5325 0, 0,
5326 pbn_oxsemi_4_15625000 },
5327 /* Brainboxes Devices */
5328 /*
5329 * Brainboxes UC-101
5330 */
5331 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5332 PCI_ANY_ID, PCI_ANY_ID,
5333 0, 0,
5334 pbn_b2_2_115200 },
5335 { PCI_VENDOR_ID_INTASHIELD, 0x0BA2,
5336 PCI_ANY_ID, PCI_ANY_ID,
5337 0, 0,
5338 pbn_b2_2_115200 },
5339 { PCI_VENDOR_ID_INTASHIELD, 0x0BA3,
5340 PCI_ANY_ID, PCI_ANY_ID,
5341 0, 0,
5342 pbn_b2_2_115200 },
5343 /*
5344 * Brainboxes UC-235/246
5345 */
5346 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5347 PCI_ANY_ID, PCI_ANY_ID,
5348 0, 0,
5349 pbn_b2_1_115200 },
5350 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2,
5351 PCI_ANY_ID, PCI_ANY_ID,
5352 0, 0,
5353 pbn_b2_1_115200 },
5354 /*
5355 * Brainboxes UC-253/UC-734
5356 */
5357 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1,
5358 PCI_ANY_ID, PCI_ANY_ID,
5359 0, 0,
5360 pbn_b2_2_115200 },
5361 /*
5362 * Brainboxes UC-260/271/701/756
5363 */
5364 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5365 PCI_ANY_ID, PCI_ANY_ID,
5366 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5367 pbn_b2_4_115200 },
5368 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5369 PCI_ANY_ID, PCI_ANY_ID,
5370 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5371 pbn_b2_4_115200 },
5372 /*
5373 * Brainboxes UC-268
5374 */
5375 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
5376 PCI_ANY_ID, PCI_ANY_ID,
5377 0, 0,
5378 pbn_b2_4_115200 },
5379 /*
5380 * Brainboxes UC-275/279
5381 */
5382 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
5383 PCI_ANY_ID, PCI_ANY_ID,
5384 0, 0,
5385 pbn_b2_8_115200 },
5386 /*
5387 * Brainboxes UC-302
5388 */
5389 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5390 PCI_ANY_ID, PCI_ANY_ID,
5391 0, 0,
5392 pbn_b2_2_115200 },
5393 { PCI_VENDOR_ID_INTASHIELD, 0x08E2,
5394 PCI_ANY_ID, PCI_ANY_ID,
5395 0, 0,
5396 pbn_b2_2_115200 },
5397 { PCI_VENDOR_ID_INTASHIELD, 0x08E3,
5398 PCI_ANY_ID, PCI_ANY_ID,
5399 0, 0,
5400 pbn_b2_2_115200 },
5401 /*
5402 * Brainboxes UC-310
5403 */
5404 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5405 PCI_ANY_ID, PCI_ANY_ID,
5406 0, 0,
5407 pbn_b2_2_115200 },
5408 /*
5409 * Brainboxes UC-313
5410 */
5411 { PCI_VENDOR_ID_INTASHIELD, 0x08A1,
5412 PCI_ANY_ID, PCI_ANY_ID,
5413 0, 0,
5414 pbn_b2_2_115200 },
5415 { PCI_VENDOR_ID_INTASHIELD, 0x08A2,
5416 PCI_ANY_ID, PCI_ANY_ID,
5417 0, 0,
5418 pbn_b2_2_115200 },
5419 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5420 PCI_ANY_ID, PCI_ANY_ID,
5421 0, 0,
5422 pbn_b2_2_115200 },
5423 /*
5424 * Brainboxes UC-320/324
5425 */
5426 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5427 PCI_ANY_ID, PCI_ANY_ID,
5428 0, 0,
5429 pbn_b2_1_115200 },
5430 /*
5431 * Brainboxes UC-346
5432 */
5433 { PCI_VENDOR_ID_INTASHIELD, 0x0B01,
5434 PCI_ANY_ID, PCI_ANY_ID,
5435 0, 0,
5436 pbn_b2_4_115200 },
5437 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5438 PCI_ANY_ID, PCI_ANY_ID,
5439 0, 0,
5440 pbn_b2_4_115200 },
5441 /*
5442 * Brainboxes UC-357
5443 */
5444 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5445 PCI_ANY_ID, PCI_ANY_ID,
5446 0, 0,
5447 pbn_b2_2_115200 },
5448 { PCI_VENDOR_ID_INTASHIELD, 0x0A82,
5449 PCI_ANY_ID, PCI_ANY_ID,
5450 0, 0,
5451 pbn_b2_2_115200 },
5452 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5453 PCI_ANY_ID, PCI_ANY_ID,
5454 0, 0,
5455 pbn_b2_2_115200 },
5456 /*
5457 * Brainboxes UC-368
5458 */
5459 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5460 PCI_ANY_ID, PCI_ANY_ID,
5461 0, 0,
5462 pbn_b2_4_115200 },
5463 { PCI_VENDOR_ID_INTASHIELD, 0x0C42,
5464 PCI_ANY_ID, PCI_ANY_ID,
5465 0, 0,
5466 pbn_b2_4_115200 },
5467 { PCI_VENDOR_ID_INTASHIELD, 0x0C43,
5468 PCI_ANY_ID, PCI_ANY_ID,
5469 0, 0,
5470 pbn_b2_4_115200 },
5471 /*
5472 * Brainboxes UC-420
5473 */
5474 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5475 PCI_ANY_ID, PCI_ANY_ID,
5476 0, 0,
5477 pbn_b2_4_115200 },
5478 /*
5479 * Brainboxes UC-607
5480 */
5481 { PCI_VENDOR_ID_INTASHIELD, 0x09A1,
5482 PCI_ANY_ID, PCI_ANY_ID,
5483 0, 0,
5484 pbn_b2_2_115200 },
5485 { PCI_VENDOR_ID_INTASHIELD, 0x09A2,
5486 PCI_ANY_ID, PCI_ANY_ID,
5487 0, 0,
5488 pbn_b2_2_115200 },
5489 { PCI_VENDOR_ID_INTASHIELD, 0x09A3,
5490 PCI_ANY_ID, PCI_ANY_ID,
5491 0, 0,
5492 pbn_b2_2_115200 },
5493 /*
5494 * Brainboxes UC-836
5495 */
5496 { PCI_VENDOR_ID_INTASHIELD, 0x0D41,
5497 PCI_ANY_ID, PCI_ANY_ID,
5498 0, 0,
5499 pbn_b2_4_115200 },
5500 /*
5501 * Brainboxes UP-189
5502 */
5503 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1,
5504 PCI_ANY_ID, PCI_ANY_ID,
5505 0, 0,
5506 pbn_b2_2_115200 },
5507 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2,
5508 PCI_ANY_ID, PCI_ANY_ID,
5509 0, 0,
5510 pbn_b2_2_115200 },
5511 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3,
5512 PCI_ANY_ID, PCI_ANY_ID,
5513 0, 0,
5514 pbn_b2_2_115200 },
5515 /*
5516 * Brainboxes UP-200
5517 */
5518 { PCI_VENDOR_ID_INTASHIELD, 0x0B21,
5519 PCI_ANY_ID, PCI_ANY_ID,
5520 0, 0,
5521 pbn_b2_2_115200 },
5522 { PCI_VENDOR_ID_INTASHIELD, 0x0B22,
5523 PCI_ANY_ID, PCI_ANY_ID,
5524 0, 0,
5525 pbn_b2_2_115200 },
5526 { PCI_VENDOR_ID_INTASHIELD, 0x0B23,
5527 PCI_ANY_ID, PCI_ANY_ID,
5528 0, 0,
5529 pbn_b2_2_115200 },
5530 /*
5531 * Brainboxes UP-869
5532 */
5533 { PCI_VENDOR_ID_INTASHIELD, 0x0C01,
5534 PCI_ANY_ID, PCI_ANY_ID,
5535 0, 0,
5536 pbn_b2_2_115200 },
5537 { PCI_VENDOR_ID_INTASHIELD, 0x0C02,
5538 PCI_ANY_ID, PCI_ANY_ID,
5539 0, 0,
5540 pbn_b2_2_115200 },
5541 { PCI_VENDOR_ID_INTASHIELD, 0x0C03,
5542 PCI_ANY_ID, PCI_ANY_ID,
5543 0, 0,
5544 pbn_b2_2_115200 },
5545 /*
5546 * Brainboxes UP-880
5547 */
5548 { PCI_VENDOR_ID_INTASHIELD, 0x0C21,
5549 PCI_ANY_ID, PCI_ANY_ID,
5550 0, 0,
5551 pbn_b2_2_115200 },
5552 { PCI_VENDOR_ID_INTASHIELD, 0x0C22,
5553 PCI_ANY_ID, PCI_ANY_ID,
5554 0, 0,
5555 pbn_b2_2_115200 },
5556 { PCI_VENDOR_ID_INTASHIELD, 0x0C23,
5557 PCI_ANY_ID, PCI_ANY_ID,
5558 0, 0,
5559 pbn_b2_2_115200 },
5560 /*
5561 * Brainboxes PX-101
5562 */
5563 { PCI_VENDOR_ID_INTASHIELD, 0x4005,
5564 PCI_ANY_ID, PCI_ANY_ID,
5565 0, 0,
5566 pbn_b0_2_115200 },
5567 { PCI_VENDOR_ID_INTASHIELD, 0x4019,
5568 PCI_ANY_ID, PCI_ANY_ID,
5569 0, 0,
5570 pbn_oxsemi_2_15625000 },
5571 /*
5572 * Brainboxes PX-235/246
5573 */
5574 { PCI_VENDOR_ID_INTASHIELD, 0x4004,
5575 PCI_ANY_ID, PCI_ANY_ID,
5576 0, 0,
5577 pbn_b0_1_115200 },
5578 { PCI_VENDOR_ID_INTASHIELD, 0x4016,
5579 PCI_ANY_ID, PCI_ANY_ID,
5580 0, 0,
5581 pbn_oxsemi_1_15625000 },
5582 /*
5583 * Brainboxes PX-203/PX-257
5584 */
5585 { PCI_VENDOR_ID_INTASHIELD, 0x4006,
5586 PCI_ANY_ID, PCI_ANY_ID,
5587 0, 0,
5588 pbn_b0_2_115200 },
5589 { PCI_VENDOR_ID_INTASHIELD, 0x4015,
5590 PCI_ANY_ID, PCI_ANY_ID,
5591 0, 0,
5592 pbn_oxsemi_2_15625000 },
5593 /*
5594 * Brainboxes PX-260/PX-701
5595 */
5596 { PCI_VENDOR_ID_INTASHIELD, 0x400A,
5597 PCI_ANY_ID, PCI_ANY_ID,
5598 0, 0,
5599 pbn_oxsemi_4_15625000 },
5600 /*
5601 * Brainboxes PX-275/279
5602 */
5603 { PCI_VENDOR_ID_INTASHIELD, 0x0E41,
5604 PCI_ANY_ID, PCI_ANY_ID,
5605 0, 0,
5606 pbn_b2_8_115200 },
5607 /*
5608 * Brainboxes PX-310
5609 */
5610 { PCI_VENDOR_ID_INTASHIELD, 0x400E,
5611 PCI_ANY_ID, PCI_ANY_ID,
5612 0, 0,
5613 pbn_oxsemi_2_15625000 },
5614 /*
5615 * Brainboxes PX-313
5616 */
5617 { PCI_VENDOR_ID_INTASHIELD, 0x400C,
5618 PCI_ANY_ID, PCI_ANY_ID,
5619 0, 0,
5620 pbn_oxsemi_2_15625000 },
5621 /*
5622 * Brainboxes PX-320/324/PX-376/PX-387
5623 */
5624 { PCI_VENDOR_ID_INTASHIELD, 0x400B,
5625 PCI_ANY_ID, PCI_ANY_ID,
5626 0, 0,
5627 pbn_oxsemi_1_15625000 },
5628 /*
5629 * Brainboxes PX-335/346
5630 */
5631 { PCI_VENDOR_ID_INTASHIELD, 0x400F,
5632 PCI_ANY_ID, PCI_ANY_ID,
5633 0, 0,
5634 pbn_oxsemi_4_15625000 },
5635 /*
5636 * Brainboxes PX-368
5637 */
5638 { PCI_VENDOR_ID_INTASHIELD, 0x4010,
5639 PCI_ANY_ID, PCI_ANY_ID,
5640 0, 0,
5641 pbn_oxsemi_4_15625000 },
5642 /*
5643 * Brainboxes PX-420
5644 */
5645 { PCI_VENDOR_ID_INTASHIELD, 0x4000,
5646 PCI_ANY_ID, PCI_ANY_ID,
5647 0, 0,
5648 pbn_b0_4_115200 },
5649 { PCI_VENDOR_ID_INTASHIELD, 0x4011,
5650 PCI_ANY_ID, PCI_ANY_ID,
5651 0, 0,
5652 pbn_oxsemi_4_15625000 },
5653 /*
5654 * Brainboxes PX-475
5655 */
5656 { PCI_VENDOR_ID_INTASHIELD, 0x401D,
5657 PCI_ANY_ID, PCI_ANY_ID,
5658 0, 0,
5659 pbn_oxsemi_1_15625000 },
5660 /*
5661 * Brainboxes PX-803/PX-857
5662 */
5663 { PCI_VENDOR_ID_INTASHIELD, 0x4009,
5664 PCI_ANY_ID, PCI_ANY_ID,
5665 0, 0,
5666 pbn_b0_2_115200 },
5667 { PCI_VENDOR_ID_INTASHIELD, 0x4018,
5668 PCI_ANY_ID, PCI_ANY_ID,
5669 0, 0,
5670 pbn_oxsemi_2_15625000 },
5671 { PCI_VENDOR_ID_INTASHIELD, 0x401E,
5672 PCI_ANY_ID, PCI_ANY_ID,
5673 0, 0,
5674 pbn_oxsemi_2_15625000 },
5675 /*
5676 * Brainboxes PX-820
5677 */
5678 { PCI_VENDOR_ID_INTASHIELD, 0x4002,
5679 PCI_ANY_ID, PCI_ANY_ID,
5680 0, 0,
5681 pbn_b0_4_115200 },
5682 { PCI_VENDOR_ID_INTASHIELD, 0x4013,
5683 PCI_ANY_ID, PCI_ANY_ID,
5684 0, 0,
5685 pbn_oxsemi_4_15625000 },
5686 /*
5687 * Brainboxes PX-835/PX-846
5688 */
5689 { PCI_VENDOR_ID_INTASHIELD, 0x4008,
5690 PCI_ANY_ID, PCI_ANY_ID,
5691 0, 0,
5692 pbn_b0_1_115200 },
5693 { PCI_VENDOR_ID_INTASHIELD, 0x4017,
5694 PCI_ANY_ID, PCI_ANY_ID,
5695 0, 0,
5696 pbn_oxsemi_1_15625000 },
5697 /*
5698 * Brainboxes XC-235
5699 */
5700 { PCI_VENDOR_ID_INTASHIELD, 0x4026,
5701 PCI_ANY_ID, PCI_ANY_ID,
5702 0, 0,
5703 pbn_oxsemi_1_15625000 },
5704 /*
5705 * Brainboxes XC-475
5706 */
5707 { PCI_VENDOR_ID_INTASHIELD, 0x4021,
5708 PCI_ANY_ID, PCI_ANY_ID,
5709 0, 0,
5710 pbn_oxsemi_1_15625000 },
5711
5712 /*
5713 * Perle PCI-RAS cards
5714 */
5715 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5716 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5717 0, 0, pbn_b2_4_921600 },
5718 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5719 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5720 0, 0, pbn_b2_8_921600 },
5721
5722 /*
5723 * Mainpine series cards: Fairly standard layout but fools
5724 * parts of the autodetect in some cases and uses otherwise
5725 * unmatched communications subclasses in the PCI Express case
5726 */
5727
5728 { /* RockForceDUO */
5729 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5730 PCI_VENDOR_ID_MAINPINE, 0x0200,
5731 0, 0, pbn_b0_2_115200 },
5732 { /* RockForceQUATRO */
5733 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5734 PCI_VENDOR_ID_MAINPINE, 0x0300,
5735 0, 0, pbn_b0_4_115200 },
5736 { /* RockForceDUO+ */
5737 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5738 PCI_VENDOR_ID_MAINPINE, 0x0400,
5739 0, 0, pbn_b0_2_115200 },
5740 { /* RockForceQUATRO+ */
5741 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5742 PCI_VENDOR_ID_MAINPINE, 0x0500,
5743 0, 0, pbn_b0_4_115200 },
5744 { /* RockForce+ */
5745 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5746 PCI_VENDOR_ID_MAINPINE, 0x0600,
5747 0, 0, pbn_b0_2_115200 },
5748 { /* RockForce+ */
5749 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5750 PCI_VENDOR_ID_MAINPINE, 0x0700,
5751 0, 0, pbn_b0_4_115200 },
5752 { /* RockForceOCTO+ */
5753 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5754 PCI_VENDOR_ID_MAINPINE, 0x0800,
5755 0, 0, pbn_b0_8_115200 },
5756 { /* RockForceDUO+ */
5757 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5758 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5759 0, 0, pbn_b0_2_115200 },
5760 { /* RockForceQUARTRO+ */
5761 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5762 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5763 0, 0, pbn_b0_4_115200 },
5764 { /* RockForceOCTO+ */
5765 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5766 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5767 0, 0, pbn_b0_8_115200 },
5768 { /* RockForceD1 */
5769 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5770 PCI_VENDOR_ID_MAINPINE, 0x2000,
5771 0, 0, pbn_b0_1_115200 },
5772 { /* RockForceF1 */
5773 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5774 PCI_VENDOR_ID_MAINPINE, 0x2100,
5775 0, 0, pbn_b0_1_115200 },
5776 { /* RockForceD2 */
5777 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5778 PCI_VENDOR_ID_MAINPINE, 0x2200,
5779 0, 0, pbn_b0_2_115200 },
5780 { /* RockForceF2 */
5781 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5782 PCI_VENDOR_ID_MAINPINE, 0x2300,
5783 0, 0, pbn_b0_2_115200 },
5784 { /* RockForceD4 */
5785 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5786 PCI_VENDOR_ID_MAINPINE, 0x2400,
5787 0, 0, pbn_b0_4_115200 },
5788 { /* RockForceF4 */
5789 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5790 PCI_VENDOR_ID_MAINPINE, 0x2500,
5791 0, 0, pbn_b0_4_115200 },
5792 { /* RockForceD8 */
5793 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5794 PCI_VENDOR_ID_MAINPINE, 0x2600,
5795 0, 0, pbn_b0_8_115200 },
5796 { /* RockForceF8 */
5797 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5798 PCI_VENDOR_ID_MAINPINE, 0x2700,
5799 0, 0, pbn_b0_8_115200 },
5800 { /* IQ Express D1 */
5801 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5802 PCI_VENDOR_ID_MAINPINE, 0x3000,
5803 0, 0, pbn_b0_1_115200 },
5804 { /* IQ Express F1 */
5805 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5806 PCI_VENDOR_ID_MAINPINE, 0x3100,
5807 0, 0, pbn_b0_1_115200 },
5808 { /* IQ Express D2 */
5809 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5810 PCI_VENDOR_ID_MAINPINE, 0x3200,
5811 0, 0, pbn_b0_2_115200 },
5812 { /* IQ Express F2 */
5813 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5814 PCI_VENDOR_ID_MAINPINE, 0x3300,
5815 0, 0, pbn_b0_2_115200 },
5816 { /* IQ Express D4 */
5817 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5818 PCI_VENDOR_ID_MAINPINE, 0x3400,
5819 0, 0, pbn_b0_4_115200 },
5820 { /* IQ Express F4 */
5821 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5822 PCI_VENDOR_ID_MAINPINE, 0x3500,
5823 0, 0, pbn_b0_4_115200 },
5824 { /* IQ Express D8 */
5825 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5826 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5827 0, 0, pbn_b0_8_115200 },
5828 { /* IQ Express F8 */
5829 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5830 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5831 0, 0, pbn_b0_8_115200 },
5832
5833
5834 /*
5835 * PA Semi PA6T-1682M on-chip UART
5836 */
5837 { PCI_VENDOR_ID_PASEMI, 0xa004,
5838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5839 pbn_pasemi_1682M },
5840
5841 /*
5842 * National Instruments
5843 */
5844 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5846 pbn_b1_16_115200 },
5847 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5849 pbn_b1_8_115200 },
5850 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5852 pbn_b1_bt_4_115200 },
5853 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5855 pbn_b1_bt_2_115200 },
5856 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5857 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5858 pbn_b1_bt_4_115200 },
5859 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5860 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5861 pbn_b1_bt_2_115200 },
5862 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5864 pbn_b1_16_115200 },
5865 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5867 pbn_b1_8_115200 },
5868 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5869 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5870 pbn_b1_bt_4_115200 },
5871 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5872 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5873 pbn_b1_bt_2_115200 },
5874 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5875 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5876 pbn_b1_bt_4_115200 },
5877 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5879 pbn_b1_bt_2_115200 },
5880 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5882 pbn_ni8430_2 },
5883 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5885 pbn_ni8430_2 },
5886 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5888 pbn_ni8430_4 },
5889 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5891 pbn_ni8430_4 },
5892 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5894 pbn_ni8430_8 },
5895 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5897 pbn_ni8430_8 },
5898 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5900 pbn_ni8430_16 },
5901 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5902 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5903 pbn_ni8430_16 },
5904 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5905 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5906 pbn_ni8430_2 },
5907 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5908 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5909 pbn_ni8430_2 },
5910 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5911 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5912 pbn_ni8430_4 },
5913 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5914 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5915 pbn_ni8430_4 },
5916
5917 /*
5918 * MOXA
5919 */
5920 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 },
5921 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), pbn_moxa_2 },
5922 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), pbn_moxa_2 },
5923 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), pbn_moxa_4 },
5924 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), pbn_moxa_4 },
5925 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), pbn_moxa_2 },
5926 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), pbn_moxa_4 },
5927 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), pbn_moxa_4 },
5928 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), pbn_moxa_8 },
5929 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), pbn_moxa_8 },
5930 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), pbn_moxa_8 },
5931 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), pbn_moxa_8 },
5932 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), pbn_moxa_2 },
5933 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), pbn_moxa_2 },
5934 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), pbn_moxa_4 },
5935 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), pbn_moxa_4 },
5936 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), pbn_moxa_8 },
5937 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), pbn_moxa_8 },
5938
5939 /*
5940 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5941 */
5942 { PCI_VENDOR_ID_ADDIDATA,
5943 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5944 PCI_ANY_ID,
5945 PCI_ANY_ID,
5946 0,
5947 0,
5948 pbn_b0_4_115200 },
5949
5950 { PCI_VENDOR_ID_ADDIDATA,
5951 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5952 PCI_ANY_ID,
5953 PCI_ANY_ID,
5954 0,
5955 0,
5956 pbn_b0_2_115200 },
5957
5958 { PCI_VENDOR_ID_ADDIDATA,
5959 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5960 PCI_ANY_ID,
5961 PCI_ANY_ID,
5962 0,
5963 0,
5964 pbn_b0_1_115200 },
5965
5966 { PCI_VENDOR_ID_AMCC,
5967 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5968 PCI_ANY_ID,
5969 PCI_ANY_ID,
5970 0,
5971 0,
5972 pbn_b1_8_115200 },
5973
5974 { PCI_VENDOR_ID_ADDIDATA,
5975 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5976 PCI_ANY_ID,
5977 PCI_ANY_ID,
5978 0,
5979 0,
5980 pbn_b0_4_115200 },
5981
5982 { PCI_VENDOR_ID_ADDIDATA,
5983 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5984 PCI_ANY_ID,
5985 PCI_ANY_ID,
5986 0,
5987 0,
5988 pbn_b0_2_115200 },
5989
5990 { PCI_VENDOR_ID_ADDIDATA,
5991 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5992 PCI_ANY_ID,
5993 PCI_ANY_ID,
5994 0,
5995 0,
5996 pbn_b0_1_115200 },
5997
5998 { PCI_VENDOR_ID_ADDIDATA,
5999 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
6000 PCI_ANY_ID,
6001 PCI_ANY_ID,
6002 0,
6003 0,
6004 pbn_b0_4_115200 },
6005
6006 { PCI_VENDOR_ID_ADDIDATA,
6007 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
6008 PCI_ANY_ID,
6009 PCI_ANY_ID,
6010 0,
6011 0,
6012 pbn_b0_2_115200 },
6013
6014 { PCI_VENDOR_ID_ADDIDATA,
6015 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
6016 PCI_ANY_ID,
6017 PCI_ANY_ID,
6018 0,
6019 0,
6020 pbn_b0_1_115200 },
6021
6022 { PCI_VENDOR_ID_ADDIDATA,
6023 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
6024 PCI_ANY_ID,
6025 PCI_ANY_ID,
6026 0,
6027 0,
6028 pbn_b0_8_115200 },
6029
6030 { PCI_VENDOR_ID_ADDIDATA,
6031 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
6032 PCI_ANY_ID,
6033 PCI_ANY_ID,
6034 0,
6035 0,
6036 pbn_ADDIDATA_PCIe_4_3906250 },
6037
6038 { PCI_VENDOR_ID_ADDIDATA,
6039 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
6040 PCI_ANY_ID,
6041 PCI_ANY_ID,
6042 0,
6043 0,
6044 pbn_ADDIDATA_PCIe_2_3906250 },
6045
6046 { PCI_VENDOR_ID_ADDIDATA,
6047 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
6048 PCI_ANY_ID,
6049 PCI_ANY_ID,
6050 0,
6051 0,
6052 pbn_ADDIDATA_PCIe_1_3906250 },
6053
6054 { PCI_VENDOR_ID_ADDIDATA,
6055 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
6056 PCI_ANY_ID,
6057 PCI_ANY_ID,
6058 0,
6059 0,
6060 pbn_ADDIDATA_PCIe_8_3906250 },
6061
6062 { PCI_VENDOR_ID_ADDIDATA,
6063 PCI_DEVICE_ID_ADDIDATA_CPCI7500,
6064 PCI_ANY_ID,
6065 PCI_ANY_ID,
6066 0,
6067 0,
6068 pbn_b0_4_115200 },
6069
6070 { PCI_VENDOR_ID_ADDIDATA,
6071 PCI_DEVICE_ID_ADDIDATA_CPCI7500_NG,
6072 PCI_ANY_ID,
6073 PCI_ANY_ID,
6074 0,
6075 0,
6076 pbn_b0_4_115200 },
6077
6078 { PCI_VENDOR_ID_ADDIDATA,
6079 PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG,
6080 PCI_ANY_ID,
6081 PCI_ANY_ID,
6082 0,
6083 0,
6084 pbn_b0_2_115200 },
6085
6086 { PCI_VENDOR_ID_ADDIDATA,
6087 PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG,
6088 PCI_ANY_ID,
6089 PCI_ANY_ID,
6090 0,
6091 0,
6092 pbn_b0_1_115200 },
6093
6094 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
6095 PCI_VENDOR_ID_IBM, 0x0299,
6096 0, 0, pbn_b0_bt_2_115200 },
6097
6098 /*
6099 * other NetMos 9835 devices are most likely handled by the
6100 * parport_serial driver, check drivers/parport/parport_serial.c
6101 * before adding them here.
6102 */
6103
6104 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
6105 0xA000, 0x1000,
6106 0, 0, pbn_b0_1_115200 },
6107
6108 /* the 9901 is a rebranded 9912 */
6109 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
6110 0xA000, 0x1000,
6111 0, 0, pbn_b0_1_115200 },
6112
6113 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
6114 0xA000, 0x1000,
6115 0, 0, pbn_b0_1_115200 },
6116
6117 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
6118 0xA000, 0x1000,
6119 0, 0, pbn_b0_1_115200 },
6120
6121 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
6122 0xA000, 0x1000,
6123 0, 0, pbn_b0_1_115200 },
6124
6125 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
6126 0xA000, 0x3002,
6127 0, 0, pbn_NETMOS9900_2s_115200 },
6128
6129 { PCIE_VENDOR_ID_ASIX, PCIE_DEVICE_ID_AX99100,
6130 0xA000, 0x1000,
6131 0, 0, pbn_b0_1_115200 },
6132
6133 /*
6134 * Best Connectivity and Rosewill PCI Multi I/O cards
6135 */
6136
6137 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6138 0xA000, 0x1000,
6139 0, 0, pbn_b0_1_115200 },
6140
6141 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6142 0xA000, 0x3002,
6143 0, 0, pbn_b0_bt_2_115200 },
6144
6145 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6146 0xA000, 0x3004,
6147 0, 0, pbn_b0_bt_4_115200 },
6148
6149 /*
6150 * ASIX AX99100 PCIe to Multi I/O Controller
6151 */
6152 { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
6153 0xA000, 0x1000,
6154 0, 0, pbn_b0_1_115200 },
6155
6156 /* Intel CE4100 */
6157 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
6158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6159 pbn_ce4100_1_115200 },
6160
6161 /*
6162 * Cronyx Omega PCI
6163 */
6164 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
6165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6166 pbn_omegapci },
6167
6168 /*
6169 * Broadcom TruManage
6170 */
6171 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
6172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6173 pbn_brcm_trumanage },
6174
6175 /*
6176 * AgeStar as-prs2-009
6177 */
6178 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
6179 PCI_ANY_ID, PCI_ANY_ID,
6180 0, 0, pbn_b0_bt_2_115200 },
6181
6182 /*
6183 * WCH CH353 series devices: The 2S1P is handled by parport_serial
6184 * so not listed here.
6185 */
6186 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_4S,
6187 PCI_ANY_ID, PCI_ANY_ID,
6188 0, 0, pbn_b0_bt_4_115200 },
6189
6190 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_2S1PF,
6191 PCI_ANY_ID, PCI_ANY_ID,
6192 0, 0, pbn_b0_bt_2_115200 },
6193
6194 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH355_4S,
6195 PCI_ANY_ID, PCI_ANY_ID,
6196 0, 0, pbn_b0_bt_4_115200 },
6197
6198 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH382_2S,
6199 PCI_ANY_ID, PCI_ANY_ID,
6200 0, 0, pbn_wch382_2 },
6201
6202 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_4S,
6203 PCI_ANY_ID, PCI_ANY_ID,
6204 0, 0, pbn_wch384_4 },
6205
6206 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_8S,
6207 PCI_ANY_ID, PCI_ANY_ID,
6208 0, 0, pbn_wch384_8 },
6209 /*
6210 * Realtek RealManage
6211 */
6212 { PCI_VENDOR_ID_REALTEK, 0x816a,
6213 PCI_ANY_ID, PCI_ANY_ID,
6214 0, 0, pbn_b0_1_115200 },
6215
6216 { PCI_VENDOR_ID_REALTEK, 0x816b,
6217 PCI_ANY_ID, PCI_ANY_ID,
6218 0, 0, pbn_b0_1_115200 },
6219
6220 /* Systembase Multi I/O cards */
6221 { PCI_VDEVICE(SYSTEMBASE, 0x0008), pbn_b0_8_921600 },
6222
6223 /* Fintek PCI serial cards */
6224 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
6225 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
6226 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
6227 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
6228 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
6229 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
6230
6231 /* MKS Tenta SCOM-080x serial cards */
6232 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
6233 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
6234
6235 /* Amazon PCI serial device */
6236 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
6237
6238 /*
6239 * These entries match devices with class COMMUNICATION_SERIAL,
6240 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
6241 */
6242 { PCI_ANY_ID, PCI_ANY_ID,
6243 PCI_ANY_ID, PCI_ANY_ID,
6244 PCI_CLASS_COMMUNICATION_SERIAL << 8,
6245 0xffff00, pbn_default },
6246 { PCI_ANY_ID, PCI_ANY_ID,
6247 PCI_ANY_ID, PCI_ANY_ID,
6248 PCI_CLASS_COMMUNICATION_MODEM << 8,
6249 0xffff00, pbn_default },
6250 { PCI_ANY_ID, PCI_ANY_ID,
6251 PCI_ANY_ID, PCI_ANY_ID,
6252 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
6253 0xffff00, pbn_default },
6254 { 0, }
6255 };
6256
serial8250_io_error_detected(struct pci_dev * dev,pci_channel_state_t state)6257 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
6258 pci_channel_state_t state)
6259 {
6260 struct serial_private *priv = pci_get_drvdata(dev);
6261
6262 if (state == pci_channel_io_perm_failure)
6263 return PCI_ERS_RESULT_DISCONNECT;
6264
6265 if (priv)
6266 pciserial_detach_ports(priv);
6267
6268 pci_disable_device(dev);
6269
6270 return PCI_ERS_RESULT_NEED_RESET;
6271 }
6272
serial8250_io_slot_reset(struct pci_dev * dev)6273 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
6274 {
6275 int rc;
6276
6277 rc = pci_enable_device(dev);
6278
6279 if (rc)
6280 return PCI_ERS_RESULT_DISCONNECT;
6281
6282 pci_restore_state(dev);
6283
6284 return PCI_ERS_RESULT_RECOVERED;
6285 }
6286
serial8250_io_resume(struct pci_dev * dev)6287 static void serial8250_io_resume(struct pci_dev *dev)
6288 {
6289 struct serial_private *priv = pci_get_drvdata(dev);
6290 struct serial_private *new;
6291
6292 if (!priv)
6293 return;
6294
6295 new = pciserial_init_ports(dev, priv->board);
6296 if (!IS_ERR(new)) {
6297 pci_set_drvdata(dev, new);
6298 kfree(priv);
6299 }
6300 }
6301
6302 static const struct pci_error_handlers serial8250_err_handler = {
6303 .error_detected = serial8250_io_error_detected,
6304 .slot_reset = serial8250_io_slot_reset,
6305 .resume = serial8250_io_resume,
6306 };
6307
6308 static struct pci_driver serial_pci_driver = {
6309 .name = "serial",
6310 .probe = pciserial_init_one,
6311 .remove = pciserial_remove_one,
6312 .driver = {
6313 .pm = &pciserial_pm_ops,
6314 },
6315 .id_table = serial_pci_tbl,
6316 .err_handler = &serial8250_err_handler,
6317 };
6318
6319 module_pci_driver(serial_pci_driver);
6320
6321 MODULE_LICENSE("GPL");
6322 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
6323 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
6324 MODULE_IMPORT_NS("SERIAL_8250_PCI");
6325