1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15 #include <linux/aer.h> 16 #include <linux/align.h> 17 #include <linux/bitfield.h> 18 #include <linux/types.h> 19 #include <linux/kernel.h> 20 #include <linux/export.h> 21 #include <linux/pci.h> 22 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */ 23 #include <linux/init.h> 24 #include <linux/iommu.h> 25 #include <linux/iopoll.h> 26 #include <linux/delay.h> 27 #include <linux/acpi.h> 28 #include <linux/dmi.h> 29 #include <linux/ioport.h> 30 #include <linux/sched.h> 31 #include <linux/ktime.h> 32 #include <linux/mm.h> 33 #include <linux/nvme.h> 34 #include <linux/platform_data/x86/apple.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/sizes.h> 37 #include <linux/suspend.h> 38 #include <linux/switchtec.h> 39 #include "pci.h" 40 41 static bool pcie_lbms_seen(struct pci_dev *dev, u16 lnksta) 42 { 43 if (test_bit(PCI_LINK_LBMS_SEEN, &dev->priv_flags)) 44 return true; 45 46 return lnksta & PCI_EXP_LNKSTA_LBMS; 47 } 48 49 /* 50 * Retrain the link of a downstream PCIe port by hand if necessary. 51 * 52 * This is needed at least where a downstream port of the ASMedia ASM2824 53 * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304 54 * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 > 55 * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched 56 * board. 57 * 58 * In such a configuration the switches are supposed to negotiate the link 59 * speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link 60 * continues switching between the two speeds indefinitely and the data 61 * link layer never reaches the active state, with link training reported 62 * repeatedly active ~84% of the time. Forcing the target link speed to 63 * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to 64 * each other correctly however. And more interestingly retraining with a 65 * higher target link speed afterwards lets the two successfully negotiate 66 * 5.0GT/s. 67 * 68 * With the ASM2824 we can rely on the otherwise optional Data Link Layer 69 * Link Active status bit and in the failed link training scenario it will 70 * be off along with the Link Bandwidth Management Status indicating that 71 * hardware has changed the link speed or width in an attempt to correct 72 * unreliable link operation. For a port that has been left unconnected 73 * both bits will be clear. So use this information to detect the problem 74 * rather than polling the Link Training bit and watching out for flips or 75 * at least the active status. 76 * 77 * Since the exact nature of the problem isn't known and in principle this 78 * could trigger where an ASM2824 device is downstream rather upstream, 79 * apply this erratum workaround to any downstream ports as long as they 80 * support Link Active reporting and have the Link Control 2 register. 81 * Restrict the speed to 2.5GT/s then with the Target Link Speed field, 82 * request a retrain and check the result. 83 * 84 * If this turns out successful, or where a 2.5GT/s speed restriction has 85 * been previously arranged by the firmware and the port reports its link 86 * already being up, lift the restriction, in a hope it is safe to do so, 87 * letting the devices negotiate a higher speed. 88 * 89 * Otherwise revert the speed to the original setting and request a retrain 90 * again to remove any residual state, ignoring the result as it's supposed 91 * to fail anyway. 92 * 93 * Return 0 if the link has been successfully retrained. Return an error 94 * if retraining was not needed or we attempted a retrain and it failed. 95 */ 96 int pcie_failed_link_retrain(struct pci_dev *dev) 97 { 98 u16 lnksta, lnkctl2, oldlnkctl2; 99 enum pci_bus_speed speed_cap; 100 int ret = -ENOTTY; 101 102 if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) || 103 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) 104 return ret; 105 106 speed_cap = pcie_get_speed_cap(dev); 107 if (speed_cap <= PCIE_SPEED_2_5GT) 108 return ret; 109 110 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 111 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &oldlnkctl2); 112 if (lnksta & PCI_EXP_LNKSTA_DLLLA) { 113 ; 114 } else if (PCIE_LNKCTL2_TLS2SPEED(oldlnkctl2) == PCIE_SPEED_2_5GT) { 115 return ret; 116 } else if (pcie_lbms_seen(dev, lnksta)) { 117 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); 118 ret = pcie_set_target_speed(dev, PCIE_SPEED_2_5GT, false); 119 if (ret) 120 goto err; 121 } 122 123 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); 124 if ((lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT) { 125 pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n"); 126 ret = pcie_set_target_speed(dev, speed_cap, false); 127 if (ret) 128 goto err; 129 } 130 131 return ret; 132 err: 133 pci_info(dev, "retraining failed\n"); 134 pcie_set_target_speed(dev, PCIE_LNKCTL2_TLS2SPEED(oldlnkctl2), true); 135 return ret; 136 } 137 138 static ktime_t fixup_debug_start(struct pci_dev *dev, 139 void (*fn)(struct pci_dev *dev)) 140 { 141 if (initcall_debug) 142 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); 143 144 return ktime_get(); 145 } 146 147 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 148 void (*fn)(struct pci_dev *dev)) 149 { 150 ktime_t delta, rettime; 151 unsigned long long duration; 152 153 rettime = ktime_get(); 154 delta = ktime_sub(rettime, calltime); 155 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 156 if (initcall_debug || duration > 10000) 157 pci_info(dev, "%pS took %lld usecs\n", fn, duration); 158 } 159 160 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 161 struct pci_fixup *end) 162 { 163 ktime_t calltime; 164 165 for (; f < end; f++) 166 if ((f->class == (u32) (dev->class >> f->class_shift) || 167 f->class == (u32) PCI_ANY_ID) && 168 (f->vendor == dev->vendor || 169 f->vendor == (u16) PCI_ANY_ID) && 170 (f->device == dev->device || 171 f->device == (u16) PCI_ANY_ID)) { 172 void (*hook)(struct pci_dev *dev); 173 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 174 hook = offset_to_ptr(&f->hook_offset); 175 #else 176 hook = f->hook; 177 #endif 178 calltime = fixup_debug_start(dev, hook); 179 hook(dev); 180 fixup_debug_report(dev, calltime, hook); 181 } 182 } 183 184 extern struct pci_fixup __start_pci_fixups_early[]; 185 extern struct pci_fixup __end_pci_fixups_early[]; 186 extern struct pci_fixup __start_pci_fixups_header[]; 187 extern struct pci_fixup __end_pci_fixups_header[]; 188 extern struct pci_fixup __start_pci_fixups_final[]; 189 extern struct pci_fixup __end_pci_fixups_final[]; 190 extern struct pci_fixup __start_pci_fixups_enable[]; 191 extern struct pci_fixup __end_pci_fixups_enable[]; 192 extern struct pci_fixup __start_pci_fixups_resume[]; 193 extern struct pci_fixup __end_pci_fixups_resume[]; 194 extern struct pci_fixup __start_pci_fixups_resume_early[]; 195 extern struct pci_fixup __end_pci_fixups_resume_early[]; 196 extern struct pci_fixup __start_pci_fixups_suspend[]; 197 extern struct pci_fixup __end_pci_fixups_suspend[]; 198 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 199 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 200 201 static bool pci_apply_fixup_final_quirks; 202 203 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 204 { 205 struct pci_fixup *start, *end; 206 207 switch (pass) { 208 case pci_fixup_early: 209 start = __start_pci_fixups_early; 210 end = __end_pci_fixups_early; 211 break; 212 213 case pci_fixup_header: 214 start = __start_pci_fixups_header; 215 end = __end_pci_fixups_header; 216 break; 217 218 case pci_fixup_final: 219 if (!pci_apply_fixup_final_quirks) 220 return; 221 start = __start_pci_fixups_final; 222 end = __end_pci_fixups_final; 223 break; 224 225 case pci_fixup_enable: 226 start = __start_pci_fixups_enable; 227 end = __end_pci_fixups_enable; 228 break; 229 230 case pci_fixup_resume: 231 start = __start_pci_fixups_resume; 232 end = __end_pci_fixups_resume; 233 break; 234 235 case pci_fixup_resume_early: 236 start = __start_pci_fixups_resume_early; 237 end = __end_pci_fixups_resume_early; 238 break; 239 240 case pci_fixup_suspend: 241 start = __start_pci_fixups_suspend; 242 end = __end_pci_fixups_suspend; 243 break; 244 245 case pci_fixup_suspend_late: 246 start = __start_pci_fixups_suspend_late; 247 end = __end_pci_fixups_suspend_late; 248 break; 249 250 default: 251 /* stupid compiler warning, you would think with an enum... */ 252 return; 253 } 254 pci_do_fixups(dev, start, end); 255 } 256 EXPORT_SYMBOL(pci_fixup_device); 257 258 static int __init pci_apply_final_quirks(void) 259 { 260 struct pci_dev *dev = NULL; 261 u8 cls = 0; 262 u8 tmp; 263 264 if (pci_cache_line_size) 265 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); 266 267 pci_apply_fixup_final_quirks = true; 268 for_each_pci_dev(dev) { 269 pci_fixup_device(pci_fixup_final, dev); 270 /* 271 * If arch hasn't set it explicitly yet, use the CLS 272 * value shared by all PCI devices. If there's a 273 * mismatch, fall back to the default value. 274 */ 275 if (!pci_cache_line_size) { 276 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 277 if (!cls) 278 cls = tmp; 279 if (!tmp || cls == tmp) 280 continue; 281 282 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", 283 cls << 2, tmp << 2, 284 pci_dfl_cache_line_size << 2); 285 pci_cache_line_size = pci_dfl_cache_line_size; 286 } 287 } 288 289 if (!pci_cache_line_size) { 290 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, 291 pci_dfl_cache_line_size << 2); 292 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 293 } 294 295 return 0; 296 } 297 fs_initcall_sync(pci_apply_final_quirks); 298 299 /* 300 * Decoding should be disabled for a PCI device during BAR sizing to avoid 301 * conflict. But doing so may cause problems on host bridge and perhaps other 302 * key system devices. For devices that need to have mmio decoding always-on, 303 * we need to set the dev->mmio_always_on bit. 304 */ 305 static void quirk_mmio_always_on(struct pci_dev *dev) 306 { 307 dev->mmio_always_on = 1; 308 } 309 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 310 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 311 312 /* 313 * The Mellanox Tavor device gives false positive parity errors. Disable 314 * parity error reporting. 315 */ 316 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity); 317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity); 318 319 /* 320 * Deal with broken BIOSes that neglect to enable passive release, 321 * which can cause problems in combination with the 82441FX/PPro MTRRs 322 */ 323 static void quirk_passive_release(struct pci_dev *dev) 324 { 325 struct pci_dev *d = NULL; 326 unsigned char dlc; 327 328 /* 329 * We have to make sure a particular bit is set in the PIIX3 330 * ISA bridge, so we have to go out and find it. 331 */ 332 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 333 pci_read_config_byte(d, 0x82, &dlc); 334 if (!(dlc & 1<<1)) { 335 pci_info(d, "PIIX3: Enabling Passive Release\n"); 336 dlc |= 1<<1; 337 pci_write_config_byte(d, 0x82, dlc); 338 } 339 } 340 } 341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 342 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 343 344 #ifdef CONFIG_X86_32 345 /* 346 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 347 * workaround but VIA don't answer queries. If you happen to have good 348 * contacts at VIA ask them for me please -- Alan 349 * 350 * This appears to be BIOS not version dependent. So presumably there is a 351 * chipset level fix. 352 */ 353 static void quirk_isa_dma_hangs(struct pci_dev *dev) 354 { 355 if (!isa_dma_bridge_buggy) { 356 isa_dma_bridge_buggy = 1; 357 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 358 } 359 } 360 /* 361 * It's not totally clear which chipsets are the problematic ones. We know 362 * 82C586 and 82C596 variants are affected. 363 */ 364 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 365 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 366 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 367 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 368 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 369 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 370 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 371 #endif 372 373 #ifdef CONFIG_HAS_IOPORT 374 /* 375 * Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear 376 * for some HT machines to use C4 w/o hanging. 377 */ 378 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 379 { 380 u32 pmbase; 381 u16 pm1a; 382 383 pci_read_config_dword(dev, 0x40, &pmbase); 384 pmbase = pmbase & 0xff80; 385 pm1a = inw(pmbase); 386 387 if (pm1a & 0x10) { 388 pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n"); 389 outw(0x10, pmbase); 390 } 391 } 392 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 393 #endif 394 395 /* Chipsets where PCI->PCI transfers vanish or hang */ 396 static void quirk_nopcipci(struct pci_dev *dev) 397 { 398 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 399 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 400 pci_pci_problems |= PCIPCI_FAIL; 401 } 402 } 403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 405 406 static void quirk_nopciamd(struct pci_dev *dev) 407 { 408 u8 rev; 409 pci_read_config_byte(dev, 0x08, &rev); 410 if (rev == 0x13) { 411 /* Erratum 24 */ 412 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 413 pci_pci_problems |= PCIAGP_FAIL; 414 } 415 } 416 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 417 418 /* Triton requires workarounds to be used by the drivers */ 419 static void quirk_triton(struct pci_dev *dev) 420 { 421 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 422 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 423 pci_pci_problems |= PCIPCI_TRITON; 424 } 425 } 426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 427 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 428 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 429 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 430 431 /* 432 * VIA Apollo KT133 needs PCI latency patch 433 * Made according to a Windows driver-based patch by George E. Breese; 434 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 435 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 436 * which Mr Breese based his work. 437 * 438 * Updated based on further information from the site and also on 439 * information provided by VIA 440 */ 441 static void quirk_vialatency(struct pci_dev *dev) 442 { 443 struct pci_dev *p; 444 u8 busarb; 445 446 /* 447 * Ok, we have a potential problem chipset here. Now see if we have 448 * a buggy southbridge. 449 */ 450 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 451 if (p != NULL) { 452 453 /* 454 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 455 * thanks Dan Hollis. 456 * Check for buggy part revisions 457 */ 458 if (p->revision < 0x40 || p->revision > 0x42) 459 goto exit; 460 } else { 461 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 462 if (p == NULL) /* No problem parts */ 463 goto exit; 464 465 /* Check for buggy part revisions */ 466 if (p->revision < 0x10 || p->revision > 0x12) 467 goto exit; 468 } 469 470 /* 471 * Ok we have the problem. Now set the PCI master grant to occur 472 * every master grant. The apparent bug is that under high PCI load 473 * (quite common in Linux of course) you can get data loss when the 474 * CPU is held off the bus for 3 bus master requests. This happens 475 * to include the IDE controllers.... 476 * 477 * VIA only apply this fix when an SB Live! is present but under 478 * both Linux and Windows this isn't enough, and we have seen 479 * corruption without SB Live! but with things like 3 UDMA IDE 480 * controllers. So we ignore that bit of the VIA recommendation.. 481 */ 482 pci_read_config_byte(dev, 0x76, &busarb); 483 484 /* 485 * Set bit 4 and bit 5 of byte 76 to 0x01 486 * "Master priority rotation on every PCI master grant" 487 */ 488 busarb &= ~(1<<5); 489 busarb |= (1<<4); 490 pci_write_config_byte(dev, 0x76, busarb); 491 pci_info(dev, "Applying VIA southbridge workaround\n"); 492 exit: 493 pci_dev_put(p); 494 } 495 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 496 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 497 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 498 /* Must restore this on a resume from RAM */ 499 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 500 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 501 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 502 503 /* VIA Apollo VP3 needs ETBF on BT848/878 */ 504 static void quirk_viaetbf(struct pci_dev *dev) 505 { 506 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 507 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 508 pci_pci_problems |= PCIPCI_VIAETBF; 509 } 510 } 511 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 512 513 static void quirk_vsfx(struct pci_dev *dev) 514 { 515 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 516 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 517 pci_pci_problems |= PCIPCI_VSFX; 518 } 519 } 520 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 521 522 /* 523 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 524 * space. Latency must be set to 0xA and Triton workaround applied too. 525 * [Info kindly provided by ALi] 526 */ 527 static void quirk_alimagik(struct pci_dev *dev) 528 { 529 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 530 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 531 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 532 } 533 } 534 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 535 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 536 537 /* Natoma has some interesting boundary conditions with Zoran stuff at least */ 538 static void quirk_natoma(struct pci_dev *dev) 539 { 540 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 541 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 542 pci_pci_problems |= PCIPCI_NATOMA; 543 } 544 } 545 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 546 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 547 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 548 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 549 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 550 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 551 552 /* 553 * This chip can cause PCI parity errors if config register 0xA0 is read 554 * while DMAs are occurring. 555 */ 556 static void quirk_citrine(struct pci_dev *dev) 557 { 558 dev->cfg_size = 0xA0; 559 } 560 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 561 562 /* 563 * This chip can cause bus lockups if config addresses above 0x600 564 * are read or written. 565 */ 566 static void quirk_nfp6000(struct pci_dev *dev) 567 { 568 dev->cfg_size = 0x600; 569 } 570 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 571 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 572 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); 573 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 574 575 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 576 static void quirk_extend_bar_to_page(struct pci_dev *dev) 577 { 578 int i; 579 580 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 581 struct resource *r = &dev->resource[i]; 582 const char *r_name = pci_resource_name(dev, i); 583 584 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 585 resource_set_range(r, 0, PAGE_SIZE); 586 r->flags |= IORESOURCE_UNSET; 587 pci_info(dev, "%s %pR: expanded to page size\n", 588 r_name, r); 589 } 590 } 591 } 592 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 593 594 /* 595 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 596 * If it's needed, re-allocate the region. 597 */ 598 static void quirk_s3_64M(struct pci_dev *dev) 599 { 600 struct resource *r = &dev->resource[0]; 601 602 if (!IS_ALIGNED(r->start, SZ_64M) || resource_size(r) != SZ_64M) { 603 r->flags |= IORESOURCE_UNSET; 604 resource_set_range(r, 0, SZ_64M); 605 } 606 } 607 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 608 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 609 610 static void quirk_io(struct pci_dev *dev, int pos, unsigned int size, 611 const char *name) 612 { 613 u32 region; 614 struct pci_bus_region bus_region; 615 struct resource *res = pci_resource_n(dev, pos); 616 const char *res_name = pci_resource_name(dev, pos); 617 618 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 619 620 if (!region) 621 return; 622 623 res->name = pci_name(dev); 624 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 625 res->flags |= 626 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 627 region &= ~(size - 1); 628 629 /* Convert from PCI bus to resource space */ 630 bus_region.start = region; 631 bus_region.end = region + size - 1; 632 pcibios_bus_to_resource(dev->bus, res, &bus_region); 633 634 pci_info(dev, FW_BUG "%s %pR: %s quirk\n", res_name, res, name); 635 } 636 637 /* 638 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 639 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 640 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 641 * (which conflicts w/ BAR1's memory range). 642 * 643 * CS553x's ISA PCI BARs may also be read-only (ref: 644 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 645 */ 646 static void quirk_cs5536_vsa(struct pci_dev *dev) 647 { 648 static char *name = "CS5536 ISA bridge"; 649 650 if (pci_resource_len(dev, 0) != 8) { 651 quirk_io(dev, 0, 8, name); /* SMB */ 652 quirk_io(dev, 1, 256, name); /* GPIO */ 653 quirk_io(dev, 2, 64, name); /* MFGPT */ 654 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 655 name); 656 } 657 } 658 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 659 660 static void quirk_io_region(struct pci_dev *dev, int port, 661 unsigned int size, int nr, const char *name) 662 { 663 u16 region; 664 struct pci_bus_region bus_region; 665 struct resource *res = pci_resource_n(dev, nr); 666 667 pci_read_config_word(dev, port, ®ion); 668 region &= ~(size - 1); 669 670 if (!region) 671 return; 672 673 res->name = pci_name(dev); 674 res->flags = IORESOURCE_IO; 675 676 /* Convert from PCI bus to resource space */ 677 bus_region.start = region; 678 bus_region.end = region + size - 1; 679 pcibios_bus_to_resource(dev->bus, res, &bus_region); 680 681 /* 682 * "res" is typically a bridge window resource that's not being 683 * used for a bridge window, so it's just a place to stash this 684 * non-standard resource. Printing "nr" or pci_resource_name() of 685 * it doesn't really make sense. 686 */ 687 if (!pci_claim_resource(dev, nr)) 688 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 689 } 690 691 /* 692 * ATI Northbridge setups MCE the processor if you even read somewhere 693 * between 0x3b0->0x3bb or read 0x3d3 694 */ 695 static void quirk_ati_exploding_mce(struct pci_dev *dev) 696 { 697 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 698 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 699 request_region(0x3b0, 0x0C, "RadeonIGP"); 700 request_region(0x3d3, 0x01, "RadeonIGP"); 701 } 702 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 703 704 /* 705 * In the AMD NL platform, this device ([1022:7912]) has a class code of 706 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 707 * claim it. The same applies on the VanGogh platform device ([1022:163a]). 708 * 709 * But the dwc3 driver is a more specific driver for this device, and we'd 710 * prefer to use it instead of xhci. To prevent xhci from claiming the 711 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 712 * defines as "USB device (not host controller)". The dwc3 driver can then 713 * claim it based on its Vendor and Device ID. 714 */ 715 static void quirk_amd_dwc_class(struct pci_dev *pdev) 716 { 717 u32 class = pdev->class; 718 719 if (class != PCI_CLASS_SERIAL_USB_DEVICE) { 720 /* Use "USB Device (not host controller)" class */ 721 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 722 pci_info(pdev, 723 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 724 class, pdev->class); 725 } 726 } 727 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 728 quirk_amd_dwc_class); 729 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB, 730 quirk_amd_dwc_class); 731 732 /* 733 * Synopsys USB 3.x host HAPS platform has a class code of 734 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these 735 * devices should use dwc3-haps driver. Change these devices' class code to 736 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming 737 * them. 738 */ 739 static void quirk_synopsys_haps(struct pci_dev *pdev) 740 { 741 u32 class = pdev->class; 742 743 switch (pdev->device) { 744 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: 745 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: 746 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: 747 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 748 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 749 class, pdev->class); 750 break; 751 } 752 } 753 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, 754 PCI_CLASS_SERIAL_USB_XHCI, 0, 755 quirk_synopsys_haps); 756 757 /* 758 * Let's make the southbridge information explicit instead of having to 759 * worry about people probing the ACPI areas, for example.. (Yes, it 760 * happens, and if you read the wrong ACPI register it will put the machine 761 * to sleep with no way of waking it up again. Bummer). 762 * 763 * ALI M7101: Two IO regions pointed to by words at 764 * 0xE0 (64 bytes of ACPI registers) 765 * 0xE2 (32 bytes of SMB registers) 766 */ 767 static void quirk_ali7101_acpi(struct pci_dev *dev) 768 { 769 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 770 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 771 } 772 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 773 774 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 775 { 776 u32 devres; 777 u32 mask, size, base; 778 779 pci_read_config_dword(dev, port, &devres); 780 if ((devres & enable) != enable) 781 return; 782 mask = (devres >> 16) & 15; 783 base = devres & 0xffff; 784 size = 16; 785 for (;;) { 786 unsigned int bit = size >> 1; 787 if ((bit & mask) == bit) 788 break; 789 size = bit; 790 } 791 /* 792 * For now we only print it out. Eventually we'll want to 793 * reserve it (at least if it's in the 0x1000+ range), but 794 * let's get enough confirmation reports first. 795 */ 796 base &= -size; 797 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 798 } 799 800 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 801 { 802 u32 devres; 803 u32 mask, size, base; 804 805 pci_read_config_dword(dev, port, &devres); 806 if ((devres & enable) != enable) 807 return; 808 base = devres & 0xffff0000; 809 mask = (devres & 0x3f) << 16; 810 size = 128 << 16; 811 for (;;) { 812 unsigned int bit = size >> 1; 813 if ((bit & mask) == bit) 814 break; 815 size = bit; 816 } 817 818 /* 819 * For now we only print it out. Eventually we'll want to 820 * reserve it, but let's get enough confirmation reports first. 821 */ 822 base &= -size; 823 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 824 } 825 826 /* 827 * PIIX4 ACPI: Two IO regions pointed to by longwords at 828 * 0x40 (64 bytes of ACPI registers) 829 * 0x90 (16 bytes of SMB registers) 830 * and a few strange programmable PIIX4 device resources. 831 */ 832 static void quirk_piix4_acpi(struct pci_dev *dev) 833 { 834 u32 res_a; 835 836 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 837 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 838 839 /* Device resource A has enables for some of the other ones */ 840 pci_read_config_dword(dev, 0x5c, &res_a); 841 842 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 843 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 844 845 /* Device resource D is just bitfields for static resources */ 846 847 /* Device 12 enabled? */ 848 if (res_a & (1 << 29)) { 849 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 850 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 851 } 852 /* Device 13 enabled? */ 853 if (res_a & (1 << 30)) { 854 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 855 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 856 } 857 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 858 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 859 } 860 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 861 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 862 863 #define ICH_PMBASE 0x40 864 #define ICH_ACPI_CNTL 0x44 865 #define ICH4_ACPI_EN 0x10 866 #define ICH6_ACPI_EN 0x80 867 #define ICH4_GPIOBASE 0x58 868 #define ICH4_GPIO_CNTL 0x5c 869 #define ICH4_GPIO_EN 0x10 870 #define ICH6_GPIOBASE 0x48 871 #define ICH6_GPIO_CNTL 0x4c 872 #define ICH6_GPIO_EN 0x10 873 874 /* 875 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 876 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 877 * 0x58 (64 bytes of GPIO I/O space) 878 */ 879 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 880 { 881 u8 enable; 882 883 /* 884 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 885 * with low legacy (and fixed) ports. We don't know the decoding 886 * priority and can't tell whether the legacy device or the one created 887 * here is really at that address. This happens on boards with broken 888 * BIOSes. 889 */ 890 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 891 if (enable & ICH4_ACPI_EN) 892 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 893 "ICH4 ACPI/GPIO/TCO"); 894 895 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 896 if (enable & ICH4_GPIO_EN) 897 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 898 "ICH4 GPIO"); 899 } 900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 906 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 910 911 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 912 { 913 u8 enable; 914 915 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 916 if (enable & ICH6_ACPI_EN) 917 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 918 "ICH6 ACPI/GPIO/TCO"); 919 920 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 921 if (enable & ICH6_GPIO_EN) 922 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 923 "ICH6 GPIO"); 924 } 925 926 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 927 const char *name, int dynsize) 928 { 929 u32 val; 930 u32 size, base; 931 932 pci_read_config_dword(dev, reg, &val); 933 934 /* Enabled? */ 935 if (!(val & 1)) 936 return; 937 base = val & 0xfffc; 938 if (dynsize) { 939 /* 940 * This is not correct. It is 16, 32 or 64 bytes depending on 941 * register D31:F0:ADh bits 5:4. 942 * 943 * But this gets us at least _part_ of it. 944 */ 945 size = 16; 946 } else { 947 size = 128; 948 } 949 base &= ~(size-1); 950 951 /* 952 * Just print it out for now. We should reserve it after more 953 * debugging. 954 */ 955 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 956 } 957 958 static void quirk_ich6_lpc(struct pci_dev *dev) 959 { 960 /* Shared ACPI/GPIO decode with all ICH6+ */ 961 ich6_lpc_acpi_gpio(dev); 962 963 /* ICH6-specific generic IO decode */ 964 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 965 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 966 } 967 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 968 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 969 970 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 971 const char *name) 972 { 973 u32 val; 974 u32 mask, base; 975 976 pci_read_config_dword(dev, reg, &val); 977 978 /* Enabled? */ 979 if (!(val & 1)) 980 return; 981 982 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 983 base = val & 0xfffc; 984 mask = (val >> 16) & 0xfc; 985 mask |= 3; 986 987 /* 988 * Just print it out for now. We should reserve it after more 989 * debugging. 990 */ 991 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 992 } 993 994 /* ICH7-10 has the same common LPC generic IO decode registers */ 995 static void quirk_ich7_lpc(struct pci_dev *dev) 996 { 997 /* We share the common ACPI/GPIO decode with ICH6 */ 998 ich6_lpc_acpi_gpio(dev); 999 1000 /* And have 4 ICH7+ generic decodes */ 1001 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 1002 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 1003 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 1004 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 1005 } 1006 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 1007 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 1008 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 1009 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 1010 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 1011 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 1012 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 1013 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 1014 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 1015 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 1016 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 1017 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 1018 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 1019 1020 /* 1021 * VIA ACPI: One IO region pointed to by longword at 1022 * 0x48 or 0x20 (256 bytes of ACPI registers) 1023 */ 1024 static void quirk_vt82c586_acpi(struct pci_dev *dev) 1025 { 1026 if (dev->revision & 0x10) 1027 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 1028 "vt82c586 ACPI"); 1029 } 1030 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 1031 1032 /* 1033 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 1034 * 0x48 (256 bytes of ACPI registers) 1035 * 0x70 (128 bytes of hardware monitoring register) 1036 * 0x90 (16 bytes of SMB registers) 1037 */ 1038 static void quirk_vt82c686_acpi(struct pci_dev *dev) 1039 { 1040 quirk_vt82c586_acpi(dev); 1041 1042 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 1043 "vt82c686 HW-mon"); 1044 1045 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 1046 } 1047 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 1048 1049 /* 1050 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 1051 * 0x88 (128 bytes of power management registers) 1052 * 0xd0 (16 bytes of SMB registers) 1053 */ 1054 static void quirk_vt8235_acpi(struct pci_dev *dev) 1055 { 1056 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 1057 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 1058 } 1059 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 1060 1061 /* 1062 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 1063 * back-to-back: Disable fast back-to-back on the secondary bus segment 1064 */ 1065 static void quirk_xio2000a(struct pci_dev *dev) 1066 { 1067 struct pci_dev *pdev; 1068 u16 command; 1069 1070 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 1071 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 1072 pci_read_config_word(pdev, PCI_COMMAND, &command); 1073 if (command & PCI_COMMAND_FAST_BACK) 1074 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 1075 } 1076 } 1077 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 1078 quirk_xio2000a); 1079 1080 #ifdef CONFIG_X86_IO_APIC 1081 1082 #include <asm/io_apic.h> 1083 1084 /* 1085 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 1086 * devices to the external APIC. 1087 * 1088 * TODO: When we have device-specific interrupt routers, this code will go 1089 * away from quirks. 1090 */ 1091 static void quirk_via_ioapic(struct pci_dev *dev) 1092 { 1093 u8 tmp; 1094 1095 if (nr_ioapics < 1) 1096 tmp = 0; /* nothing routed to external APIC */ 1097 else 1098 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 1099 1100 pci_info(dev, "%s VIA external APIC routing\n", 1101 tmp ? "Enabling" : "Disabling"); 1102 1103 /* Offset 0x58: External APIC IRQ output control */ 1104 pci_write_config_byte(dev, 0x58, tmp); 1105 } 1106 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1107 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1108 1109 /* 1110 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 1111 * This leads to doubled level interrupt rates. 1112 * Set this bit to get rid of cycle wastage. 1113 * Otherwise uncritical. 1114 */ 1115 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 1116 { 1117 u8 misc_control2; 1118 #define BYPASS_APIC_DEASSERT 8 1119 1120 pci_read_config_byte(dev, 0x5B, &misc_control2); 1121 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 1122 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 1123 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 1124 } 1125 } 1126 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1127 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1128 1129 /* 1130 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 1131 * We check all revs >= B0 (yet not in the pre production!) as the bug 1132 * is currently marked NoFix 1133 * 1134 * We have multiple reports of hangs with this chipset that went away with 1135 * noapic specified. For the moment we assume it's the erratum. We may be wrong 1136 * of course. However the advice is demonstrably good even if so. 1137 */ 1138 static void quirk_amd_ioapic(struct pci_dev *dev) 1139 { 1140 if (dev->revision >= 0x02) { 1141 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 1142 pci_warn(dev, " : booting with the \"noapic\" option\n"); 1143 } 1144 } 1145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1146 #endif /* CONFIG_X86_IO_APIC */ 1147 1148 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1149 1150 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1151 { 1152 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1153 if (dev->subsystem_device == 0xa118) 1154 dev->sriov->link = dev->devfn; 1155 } 1156 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1157 #endif 1158 1159 /* 1160 * Some settings of MMRBC can lead to data corruption so block changes. 1161 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1162 */ 1163 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1164 { 1165 if (dev->subordinate && dev->revision <= 0x12) { 1166 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1167 dev->revision); 1168 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1169 } 1170 } 1171 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1172 1173 /* 1174 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1175 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1176 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1177 * of the ACPI SCI interrupt is only done for convenience. 1178 * -jgarzik 1179 */ 1180 static void quirk_via_acpi(struct pci_dev *d) 1181 { 1182 u8 irq; 1183 1184 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1185 pci_read_config_byte(d, 0x42, &irq); 1186 irq &= 0xf; 1187 if (irq && (irq != 2)) 1188 d->irq = irq; 1189 } 1190 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1191 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1192 1193 /* VIA bridges which have VLink */ 1194 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1195 1196 static void quirk_via_bridge(struct pci_dev *dev) 1197 { 1198 /* See what bridge we have and find the device ranges */ 1199 switch (dev->device) { 1200 case PCI_DEVICE_ID_VIA_82C686: 1201 /* 1202 * The VT82C686 is special; it attaches to PCI and can have 1203 * any device number. All its subdevices are functions of 1204 * that single device. 1205 */ 1206 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1207 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1208 break; 1209 case PCI_DEVICE_ID_VIA_8237: 1210 case PCI_DEVICE_ID_VIA_8237A: 1211 via_vlink_dev_lo = 15; 1212 break; 1213 case PCI_DEVICE_ID_VIA_8235: 1214 via_vlink_dev_lo = 16; 1215 break; 1216 case PCI_DEVICE_ID_VIA_8231: 1217 case PCI_DEVICE_ID_VIA_8233_0: 1218 case PCI_DEVICE_ID_VIA_8233A: 1219 case PCI_DEVICE_ID_VIA_8233C_0: 1220 via_vlink_dev_lo = 17; 1221 break; 1222 } 1223 } 1224 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1225 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1227 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1228 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1229 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1230 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1231 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1232 1233 /* 1234 * quirk_via_vlink - VIA VLink IRQ number update 1235 * @dev: PCI device 1236 * 1237 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1238 * the IRQ line register which usually is not relevant for PCI cards, is 1239 * actually written so that interrupts get sent to the right place. 1240 * 1241 * We only do this on systems where a VIA south bridge was detected, and 1242 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1243 */ 1244 static void quirk_via_vlink(struct pci_dev *dev) 1245 { 1246 u8 irq, new_irq; 1247 1248 /* Check if we have VLink at all */ 1249 if (via_vlink_dev_lo == -1) 1250 return; 1251 1252 new_irq = dev->irq; 1253 1254 /* Don't quirk interrupts outside the legacy IRQ range */ 1255 if (!new_irq || new_irq > 15) 1256 return; 1257 1258 /* Internal device ? */ 1259 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1260 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1261 return; 1262 1263 /* 1264 * This is an internal VLink device on a PIC interrupt. The BIOS 1265 * ought to have set this but may not have, so we redo it. 1266 */ 1267 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1268 if (new_irq != irq) { 1269 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1270 irq, new_irq); 1271 udelay(15); /* unknown if delay really needed */ 1272 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1273 } 1274 } 1275 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1276 1277 /* 1278 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1279 * of VT82C597 for backward compatibility. We need to switch it off to be 1280 * able to recognize the real type of the chip. 1281 */ 1282 static void quirk_vt82c598_id(struct pci_dev *dev) 1283 { 1284 pci_write_config_byte(dev, 0xfc, 0); 1285 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1286 } 1287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1288 1289 /* 1290 * CardBus controllers have a legacy base address that enables them to 1291 * respond as i82365 PCMCIA controllers. We don't want them to do this. 1292 */ 1293 static void quirk_cardbus_legacy(struct pci_dev *dev) 1294 { 1295 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1296 } 1297 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1298 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1299 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1300 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1301 1302 /* 1303 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1304 * what the designers were smoking but let's not inhale... 1305 * 1306 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1307 * turn it off! 1308 */ 1309 static void quirk_amd_ordering(struct pci_dev *dev) 1310 { 1311 u32 pcic; 1312 pci_read_config_dword(dev, 0x4C, &pcic); 1313 if ((pcic & 6) != 6) { 1314 pcic |= 6; 1315 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1316 pci_write_config_dword(dev, 0x4C, pcic); 1317 pci_read_config_dword(dev, 0x84, &pcic); 1318 pcic |= (1 << 23); /* Required in this mode */ 1319 pci_write_config_dword(dev, 0x84, pcic); 1320 } 1321 } 1322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1323 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1324 1325 /* 1326 * DreamWorks-provided workaround for Dunord I-3000 problem 1327 * 1328 * This card decodes and responds to addresses not apparently assigned to 1329 * it. We force a larger allocation to ensure that nothing gets put too 1330 * close to it. 1331 */ 1332 static void quirk_dunord(struct pci_dev *dev) 1333 { 1334 struct resource *r = &dev->resource[1]; 1335 1336 r->flags |= IORESOURCE_UNSET; 1337 resource_set_range(r, 0, SZ_16M); 1338 } 1339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1340 1341 /* 1342 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1343 * decoding (transparent), and does indicate this in the ProgIf. 1344 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1345 */ 1346 static void quirk_transparent_bridge(struct pci_dev *dev) 1347 { 1348 dev->transparent = 1; 1349 } 1350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1352 1353 /* 1354 * Enabling Link Bandwidth Management Interrupts (BW notifications) can cause 1355 * boot hangs on P45. 1356 */ 1357 static void quirk_p45_bw_notifications(struct pci_dev *dev) 1358 { 1359 dev->no_bw_notif = 1; 1360 } 1361 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e21, quirk_p45_bw_notifications); 1362 1363 /* 1364 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1365 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1366 * found at http://www.national.com/analog for info on what these bits do. 1367 * <christer@weinigel.se> 1368 */ 1369 static void quirk_mediagx_master(struct pci_dev *dev) 1370 { 1371 u8 reg; 1372 1373 pci_read_config_byte(dev, 0x41, ®); 1374 if (reg & 2) { 1375 reg &= ~2; 1376 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1377 reg); 1378 pci_write_config_byte(dev, 0x41, reg); 1379 } 1380 } 1381 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1382 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1383 1384 /* 1385 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1386 * in the odd case it is not the results are corruption hence the presence 1387 * of a Linux check. 1388 */ 1389 static void quirk_disable_pxb(struct pci_dev *pdev) 1390 { 1391 u16 config; 1392 1393 if (pdev->revision != 0x04) /* Only C0 requires this */ 1394 return; 1395 pci_read_config_word(pdev, 0x40, &config); 1396 if (config & (1<<6)) { 1397 config &= ~(1<<6); 1398 pci_write_config_word(pdev, 0x40, config); 1399 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1400 } 1401 } 1402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1403 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1404 1405 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1406 { 1407 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1408 u8 tmp; 1409 1410 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1411 if (tmp == 0x01) { 1412 pci_read_config_byte(pdev, 0x40, &tmp); 1413 pci_write_config_byte(pdev, 0x40, tmp|1); 1414 pci_write_config_byte(pdev, 0x9, 1); 1415 pci_write_config_byte(pdev, 0xa, 6); 1416 pci_write_config_byte(pdev, 0x40, tmp); 1417 1418 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1419 pci_info(pdev, "set SATA to AHCI mode\n"); 1420 } 1421 } 1422 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1423 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1425 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1426 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1427 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1428 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1429 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1430 1431 /* Serverworks CSB5 IDE does not fully support native mode */ 1432 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1433 { 1434 u8 prog; 1435 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1436 if (prog & 5) { 1437 prog &= ~5; 1438 pdev->class &= ~5; 1439 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1440 /* PCI layer will sort out resources */ 1441 } 1442 } 1443 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1444 1445 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1446 static void quirk_ide_samemode(struct pci_dev *pdev) 1447 { 1448 u8 prog; 1449 1450 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1451 1452 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1453 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1454 prog &= ~5; 1455 pdev->class &= ~5; 1456 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1457 } 1458 } 1459 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1460 1461 /* Some ATA devices break if put into D3 */ 1462 static void quirk_no_ata_d3(struct pci_dev *pdev) 1463 { 1464 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1465 } 1466 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1467 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1468 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1469 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1470 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1471 /* ALi loses some register settings that we cannot then restore */ 1472 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1473 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1474 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1475 occur when mode detecting */ 1476 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1477 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1478 1479 /* 1480 * This was originally an Alpha-specific thing, but it really fits here. 1481 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1482 */ 1483 static void quirk_eisa_bridge(struct pci_dev *dev) 1484 { 1485 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1486 } 1487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1488 1489 /* 1490 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1491 * is not activated. The myth is that Asus said that they do not want the 1492 * users to be irritated by just another PCI Device in the Win98 device 1493 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1494 * package 2.7.0 for details) 1495 * 1496 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1497 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1498 * becomes necessary to do this tweak in two steps -- the chosen trigger 1499 * is either the Host bridge (preferred) or on-board VGA controller. 1500 * 1501 * Note that we used to unhide the SMBus that way on Toshiba laptops 1502 * (Satellite A40 and Tecra M2) but then found that the thermal management 1503 * was done by SMM code, which could cause unsynchronized concurrent 1504 * accesses to the SMBus registers, with potentially bad effects. Thus you 1505 * should be very careful when adding new entries: if SMM is accessing the 1506 * Intel SMBus, this is a very good reason to leave it hidden. 1507 * 1508 * Likewise, many recent laptops use ACPI for thermal management. If the 1509 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1510 * natively, and keeping the SMBus hidden is the right thing to do. If you 1511 * are about to add an entry in the table below, please first disassemble 1512 * the DSDT and double-check that there is no code accessing the SMBus. 1513 */ 1514 static int asus_hides_smbus; 1515 1516 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1517 { 1518 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1519 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1520 switch (dev->subsystem_device) { 1521 case 0x8025: /* P4B-LX */ 1522 case 0x8070: /* P4B */ 1523 case 0x8088: /* P4B533 */ 1524 case 0x1626: /* L3C notebook */ 1525 asus_hides_smbus = 1; 1526 } 1527 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1528 switch (dev->subsystem_device) { 1529 case 0x80b1: /* P4GE-V */ 1530 case 0x80b2: /* P4PE */ 1531 case 0x8093: /* P4B533-V */ 1532 asus_hides_smbus = 1; 1533 } 1534 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1535 switch (dev->subsystem_device) { 1536 case 0x8030: /* P4T533 */ 1537 asus_hides_smbus = 1; 1538 } 1539 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1540 switch (dev->subsystem_device) { 1541 case 0x8070: /* P4G8X Deluxe */ 1542 asus_hides_smbus = 1; 1543 } 1544 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1545 switch (dev->subsystem_device) { 1546 case 0x80c9: /* PU-DLS */ 1547 asus_hides_smbus = 1; 1548 } 1549 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1550 switch (dev->subsystem_device) { 1551 case 0x1751: /* M2N notebook */ 1552 case 0x1821: /* M5N notebook */ 1553 case 0x1897: /* A6L notebook */ 1554 asus_hides_smbus = 1; 1555 } 1556 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1557 switch (dev->subsystem_device) { 1558 case 0x184b: /* W1N notebook */ 1559 case 0x186a: /* M6Ne notebook */ 1560 asus_hides_smbus = 1; 1561 } 1562 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1563 switch (dev->subsystem_device) { 1564 case 0x80f2: /* P4P800-X */ 1565 asus_hides_smbus = 1; 1566 } 1567 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1568 switch (dev->subsystem_device) { 1569 case 0x1882: /* M6V notebook */ 1570 case 0x1977: /* A6VA notebook */ 1571 asus_hides_smbus = 1; 1572 } 1573 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1574 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1575 switch (dev->subsystem_device) { 1576 case 0x088C: /* HP Compaq nc8000 */ 1577 case 0x0890: /* HP Compaq nc6000 */ 1578 asus_hides_smbus = 1; 1579 } 1580 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1581 switch (dev->subsystem_device) { 1582 case 0x12bc: /* HP D330L */ 1583 case 0x12bd: /* HP D530 */ 1584 case 0x006a: /* HP Compaq nx9500 */ 1585 asus_hides_smbus = 1; 1586 } 1587 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1588 switch (dev->subsystem_device) { 1589 case 0x12bf: /* HP xw4100 */ 1590 asus_hides_smbus = 1; 1591 } 1592 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1593 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1594 switch (dev->subsystem_device) { 1595 case 0xC00C: /* Samsung P35 notebook */ 1596 asus_hides_smbus = 1; 1597 } 1598 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1599 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1600 switch (dev->subsystem_device) { 1601 case 0x0058: /* Compaq Evo N620c */ 1602 asus_hides_smbus = 1; 1603 } 1604 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1605 switch (dev->subsystem_device) { 1606 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1607 /* Motherboard doesn't have Host bridge 1608 * subvendor/subdevice IDs, therefore checking 1609 * its on-board VGA controller */ 1610 asus_hides_smbus = 1; 1611 } 1612 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1613 switch (dev->subsystem_device) { 1614 case 0x00b8: /* Compaq Evo D510 CMT */ 1615 case 0x00b9: /* Compaq Evo D510 SFF */ 1616 case 0x00ba: /* Compaq Evo D510 USDT */ 1617 /* Motherboard doesn't have Host bridge 1618 * subvendor/subdevice IDs and on-board VGA 1619 * controller is disabled if an AGP card is 1620 * inserted, therefore checking USB UHCI 1621 * Controller #1 */ 1622 asus_hides_smbus = 1; 1623 } 1624 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1625 switch (dev->subsystem_device) { 1626 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1627 /* Motherboard doesn't have host bridge 1628 * subvendor/subdevice IDs, therefore checking 1629 * its on-board VGA controller */ 1630 asus_hides_smbus = 1; 1631 } 1632 } 1633 } 1634 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1635 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1636 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1638 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1639 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1640 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1641 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1643 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1644 1645 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1646 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1647 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1648 1649 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1650 { 1651 u16 val; 1652 1653 if (likely(!asus_hides_smbus)) 1654 return; 1655 1656 pci_read_config_word(dev, 0xF2, &val); 1657 if (val & 0x8) { 1658 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1659 pci_read_config_word(dev, 0xF2, &val); 1660 if (val & 0x8) 1661 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1662 val); 1663 else 1664 pci_info(dev, "Enabled i801 SMBus device\n"); 1665 } 1666 } 1667 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1668 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1669 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1670 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1671 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1672 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1673 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1674 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1675 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1676 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1677 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1678 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1679 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1680 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1681 1682 /* It appears we just have one such device. If not, we have a warning */ 1683 static void __iomem *asus_rcba_base; 1684 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1685 { 1686 u32 rcba; 1687 1688 if (likely(!asus_hides_smbus)) 1689 return; 1690 WARN_ON(asus_rcba_base); 1691 1692 pci_read_config_dword(dev, 0xF0, &rcba); 1693 /* use bits 31:14, 16 kB aligned */ 1694 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); 1695 if (asus_rcba_base == NULL) 1696 return; 1697 } 1698 1699 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1700 { 1701 u32 val; 1702 1703 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1704 return; 1705 1706 /* read the Function Disable register, dword mode only */ 1707 val = readl(asus_rcba_base + 0x3418); 1708 1709 /* enable the SMBus device */ 1710 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1711 } 1712 1713 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1714 { 1715 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1716 return; 1717 1718 iounmap(asus_rcba_base); 1719 asus_rcba_base = NULL; 1720 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1721 } 1722 1723 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1724 { 1725 asus_hides_smbus_lpc_ich6_suspend(dev); 1726 asus_hides_smbus_lpc_ich6_resume_early(dev); 1727 asus_hides_smbus_lpc_ich6_resume(dev); 1728 } 1729 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1730 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1731 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1732 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1733 1734 /* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1735 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1736 { 1737 u8 val = 0; 1738 pci_read_config_byte(dev, 0x77, &val); 1739 if (val & 0x10) { 1740 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1741 pci_write_config_byte(dev, 0x77, val & ~0x10); 1742 } 1743 } 1744 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1745 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1746 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1748 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1749 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1750 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1751 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1752 1753 /* 1754 * ... This is further complicated by the fact that some SiS96x south 1755 * bridges pretend to be 85C503/5513 instead. In that case see if we 1756 * spotted a compatible north bridge to make sure. 1757 * (pci_find_device() doesn't work yet) 1758 * 1759 * We can also enable the sis96x bit in the discovery register.. 1760 */ 1761 #define SIS_DETECT_REGISTER 0x40 1762 1763 static void quirk_sis_503(struct pci_dev *dev) 1764 { 1765 u8 reg; 1766 u16 devid; 1767 1768 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1769 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1770 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1771 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1772 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1773 return; 1774 } 1775 1776 /* 1777 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1778 * it has already been processed. (Depends on link order, which is 1779 * apparently not guaranteed) 1780 */ 1781 dev->device = devid; 1782 quirk_sis_96x_smbus(dev); 1783 } 1784 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1785 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1786 1787 /* 1788 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1789 * and MC97 modem controller are disabled when a second PCI soundcard is 1790 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1791 * -- bjd 1792 */ 1793 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1794 { 1795 u8 val; 1796 int asus_hides_ac97 = 0; 1797 1798 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1799 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1800 asus_hides_ac97 = 1; 1801 } 1802 1803 if (!asus_hides_ac97) 1804 return; 1805 1806 pci_read_config_byte(dev, 0x50, &val); 1807 if (val & 0xc0) { 1808 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1809 pci_read_config_byte(dev, 0x50, &val); 1810 if (val & 0xc0) 1811 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1812 val); 1813 else 1814 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1815 } 1816 } 1817 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1818 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1819 1820 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1821 1822 /* 1823 * If we are using libata we can drive this chip properly but must do this 1824 * early on to make the additional device appear during the PCI scanning. 1825 */ 1826 static void quirk_jmicron_ata(struct pci_dev *pdev) 1827 { 1828 u32 conf1, conf5, class; 1829 u8 hdr; 1830 1831 /* Only poke fn 0 */ 1832 if (PCI_FUNC(pdev->devfn)) 1833 return; 1834 1835 pci_read_config_dword(pdev, 0x40, &conf1); 1836 pci_read_config_dword(pdev, 0x80, &conf5); 1837 1838 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1839 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1840 1841 switch (pdev->device) { 1842 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1843 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1844 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1845 /* The controller should be in single function ahci mode */ 1846 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1847 break; 1848 1849 case PCI_DEVICE_ID_JMICRON_JMB365: 1850 case PCI_DEVICE_ID_JMICRON_JMB366: 1851 /* Redirect IDE second PATA port to the right spot */ 1852 conf5 |= (1 << 24); 1853 fallthrough; 1854 case PCI_DEVICE_ID_JMICRON_JMB361: 1855 case PCI_DEVICE_ID_JMICRON_JMB363: 1856 case PCI_DEVICE_ID_JMICRON_JMB369: 1857 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1858 /* Set the class codes correctly and then direct IDE 0 */ 1859 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1860 break; 1861 1862 case PCI_DEVICE_ID_JMICRON_JMB368: 1863 /* The controller should be in single function IDE mode */ 1864 conf1 |= 0x00C00000; /* Set 22, 23 */ 1865 break; 1866 } 1867 1868 pci_write_config_dword(pdev, 0x40, conf1); 1869 pci_write_config_dword(pdev, 0x80, conf5); 1870 1871 /* Update pdev accordingly */ 1872 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1873 pdev->hdr_type = hdr & PCI_HEADER_TYPE_MASK; 1874 pdev->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr); 1875 1876 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1877 pdev->class = class >> 8; 1878 } 1879 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1880 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1881 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1882 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1883 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1884 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1885 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1886 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1887 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1888 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1889 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1890 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1891 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1892 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1893 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1894 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1895 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1896 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1897 1898 #endif 1899 1900 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1901 { 1902 if (dev->multifunction) { 1903 device_disable_async_suspend(&dev->dev); 1904 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1905 } 1906 } 1907 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1908 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1909 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1910 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1911 1912 #ifdef CONFIG_X86_IO_APIC 1913 static void quirk_alder_ioapic(struct pci_dev *pdev) 1914 { 1915 int i; 1916 1917 if ((pdev->class >> 8) != 0xff00) 1918 return; 1919 1920 /* 1921 * The first BAR is the location of the IO-APIC... we must 1922 * not touch this (and it's already covered by the fixmap), so 1923 * forcibly insert it into the resource tree. 1924 */ 1925 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1926 insert_resource(&iomem_resource, &pdev->resource[0]); 1927 1928 /* 1929 * The next five BARs all seem to be rubbish, so just clean 1930 * them out. 1931 */ 1932 for (i = 1; i < PCI_STD_NUM_BARS; i++) 1933 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1934 } 1935 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1936 #endif 1937 1938 static void quirk_no_msi(struct pci_dev *dev) 1939 { 1940 pci_info(dev, "avoiding MSI to work around a hardware defect\n"); 1941 dev->no_msi = 1; 1942 } 1943 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi); 1944 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi); 1945 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi); 1946 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi); 1947 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi); 1948 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi); 1949 /* ULi M1575 EHCI (10b9:5239): MSI stalls the async schedule */ 1950 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5239, quirk_no_msi); 1951 1952 static void quirk_pcie_mch(struct pci_dev *pdev) 1953 { 1954 pdev->no_msi = 1; 1955 } 1956 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1957 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1958 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1959 1960 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1961 1962 /* 1963 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are 1964 * actually on the AMBA bus. These fake PCI devices can support SVA via 1965 * SMMU stall feature, by setting dma-can-stall for ACPI platforms. 1966 * 1967 * Normally stalling must not be enabled for PCI devices, since it would 1968 * break the PCI requirement for free-flowing writes and may lead to 1969 * deadlock. We expect PCI devices to support ATS and PRI if they want to 1970 * be fault-tolerant, so there's no ACPI binding to describe anything else, 1971 * even when a "PCI" device turns out to be a regular old SoC device 1972 * dressed up as a RCiEP and normal rules don't apply. 1973 */ 1974 static void quirk_huawei_pcie_sva(struct pci_dev *pdev) 1975 { 1976 struct property_entry properties[] = { 1977 PROPERTY_ENTRY_BOOL("dma-can-stall"), 1978 {}, 1979 }; 1980 1981 if (pdev->revision != 0x21 && pdev->revision != 0x30) 1982 return; 1983 1984 pdev->pasid_no_tlp = 1; 1985 1986 /* 1987 * Set the dma-can-stall property on ACPI platforms. Device tree 1988 * can set it directly. 1989 */ 1990 if (!pdev->dev.of_node && 1991 device_create_managed_software_node(&pdev->dev, properties, NULL)) 1992 pci_warn(pdev, "could not add stall property"); 1993 } 1994 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva); 1995 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva); 1996 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva); 1997 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva); 1998 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva); 1999 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva); 2000 2001 /* 2002 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 2003 * together on certain PXH-based systems. 2004 */ 2005 static void quirk_pcie_pxh(struct pci_dev *dev) 2006 { 2007 dev->no_msi = 1; 2008 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 2009 } 2010 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 2011 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 2012 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 2013 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 2014 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 2015 2016 /* 2017 * Some Intel PCI Express chipsets have trouble with downstream device 2018 * power management. 2019 */ 2020 static void quirk_intel_pcie_pm(struct pci_dev *dev) 2021 { 2022 pci_pm_d3hot_delay = 120; 2023 dev->no_d1d2 = 1; 2024 } 2025 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 2026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 2027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 2028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 2029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 2030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 2031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 2032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 2033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 2034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 2036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 2037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 2038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 2039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 2040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 2041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 2042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 2043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 2044 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 2045 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 2046 2047 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) 2048 { 2049 if (dev->d3hot_delay >= delay) 2050 return; 2051 2052 dev->d3hot_delay = delay; 2053 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", 2054 dev->d3hot_delay); 2055 } 2056 2057 static void quirk_radeon_pm(struct pci_dev *dev) 2058 { 2059 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 2060 dev->subsystem_device == 0x00e2) 2061 quirk_d3hot_delay(dev, 20); 2062 } 2063 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 2064 2065 /* 2066 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus 2067 * reset is performed too soon after transition to D0, extend d3hot_delay 2068 * to previous effective default for all NVIDIA HDA controllers. 2069 */ 2070 static void quirk_nvidia_hda_pm(struct pci_dev *dev) 2071 { 2072 quirk_d3hot_delay(dev, 20); 2073 } 2074 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 2075 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, 2076 quirk_nvidia_hda_pm); 2077 2078 /* 2079 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. 2080 * https://bugzilla.kernel.org/show_bug.cgi?id=205587 2081 * 2082 * The kernel attempts to transition these devices to D3cold, but that seems 2083 * to be ineffective on the platforms in question; the PCI device appears to 2084 * remain on in D3hot state. The D3hot-to-D0 transition then requires an 2085 * extended delay in order to succeed. 2086 */ 2087 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) 2088 { 2089 quirk_d3hot_delay(dev, 20); 2090 } 2091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); 2092 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); 2093 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); 2094 2095 #ifdef CONFIG_X86_IO_APIC 2096 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 2097 { 2098 noioapicreroute = 1; 2099 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 2100 2101 return 0; 2102 } 2103 2104 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 2105 /* 2106 * Systems to exclude from boot interrupt reroute quirks 2107 */ 2108 { 2109 .callback = dmi_disable_ioapicreroute, 2110 .ident = "ASUSTek Computer INC. M2N-LR", 2111 .matches = { 2112 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 2113 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 2114 }, 2115 }, 2116 {} 2117 }; 2118 2119 /* 2120 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 2121 * remap the original interrupt in the Linux kernel to the boot interrupt, so 2122 * that a PCI device's interrupt handler is installed on the boot interrupt 2123 * line instead. 2124 */ 2125 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 2126 { 2127 dmi_check_system(boot_interrupt_dmi_table); 2128 if (noioapicquirk || noioapicreroute) 2129 return; 2130 2131 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 2132 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 2133 dev->vendor, dev->device); 2134 } 2135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2136 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2137 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2138 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2139 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2141 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2142 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2143 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2144 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2145 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2146 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2147 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2148 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2149 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2150 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2151 2152 /* 2153 * On some chipsets we can disable the generation of legacy INTx boot 2154 * interrupts. 2155 */ 2156 2157 /* 2158 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 2159 * 300641-004US, section 5.7.3. 2160 * 2161 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003. 2162 * Core IO on Xeon E5 v2, see Intel order no 329188-003. 2163 * Core IO on Xeon E7 v2, see Intel order no 329595-002. 2164 * Core IO on Xeon E5 v3, see Intel order no 330784-003. 2165 * Core IO on Xeon E7 v3, see Intel order no 332315-001US. 2166 * Core IO on Xeon E5 v4, see Intel order no 333810-002US. 2167 * Core IO on Xeon E7 v4, see Intel order no 332315-001US. 2168 * Core IO on Xeon D-1500, see Intel order no 332051-001. 2169 * Core IO on Xeon Scalable, see Intel order no 610950. 2170 */ 2171 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */ 2172 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 2173 2174 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */ 2175 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25) 2176 2177 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 2178 { 2179 u16 pci_config_word; 2180 u32 pci_config_dword; 2181 2182 if (noioapicquirk) 2183 return; 2184 2185 switch (dev->device) { 2186 case PCI_DEVICE_ID_INTEL_ESB_10: 2187 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2188 &pci_config_word); 2189 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 2190 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2191 pci_config_word); 2192 break; 2193 case 0x3c28: /* Xeon E5 1600/2600/4600 */ 2194 case 0x0e28: /* Xeon E5/E7 V2 */ 2195 case 0x2f28: /* Xeon E5/E7 V3,V4 */ 2196 case 0x6f28: /* Xeon D-1500 */ 2197 case 0x2034: /* Xeon Scalable Family */ 2198 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2199 &pci_config_dword); 2200 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH; 2201 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2202 pci_config_dword); 2203 break; 2204 default: 2205 return; 2206 } 2207 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2208 dev->vendor, dev->device); 2209 } 2210 /* 2211 * Device 29 Func 5 Device IDs of IO-APIC 2212 * containing ABAR—APIC1 Alternate Base Address Register 2213 */ 2214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2215 quirk_disable_intel_boot_interrupt); 2216 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2217 quirk_disable_intel_boot_interrupt); 2218 2219 /* 2220 * Device 5 Func 0 Device IDs of Core IO modules/hubs 2221 * containing Coherent Interface Protocol Interrupt Control 2222 * 2223 * Device IDs obtained from volume 2 datasheets of commented 2224 * families above. 2225 */ 2226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28, 2227 quirk_disable_intel_boot_interrupt); 2228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28, 2229 quirk_disable_intel_boot_interrupt); 2230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28, 2231 quirk_disable_intel_boot_interrupt); 2232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28, 2233 quirk_disable_intel_boot_interrupt); 2234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034, 2235 quirk_disable_intel_boot_interrupt); 2236 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28, 2237 quirk_disable_intel_boot_interrupt); 2238 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28, 2239 quirk_disable_intel_boot_interrupt); 2240 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28, 2241 quirk_disable_intel_boot_interrupt); 2242 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28, 2243 quirk_disable_intel_boot_interrupt); 2244 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034, 2245 quirk_disable_intel_boot_interrupt); 2246 2247 /* Disable boot interrupts on HT-1000 */ 2248 #define BC_HT1000_FEATURE_REG 0x64 2249 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 2250 #define BC_HT1000_MAP_IDX 0xC00 2251 #define BC_HT1000_MAP_DATA 0xC01 2252 2253 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 2254 { 2255 u32 pci_config_dword; 2256 u8 irq; 2257 2258 if (noioapicquirk) 2259 return; 2260 2261 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 2262 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 2263 BC_HT1000_PIC_REGS_ENABLE); 2264 2265 for (irq = 0x10; irq < 0x10 + 32; irq++) { 2266 outb(irq, BC_HT1000_MAP_IDX); 2267 outb(0x00, BC_HT1000_MAP_DATA); 2268 } 2269 2270 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 2271 2272 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2273 dev->vendor, dev->device); 2274 } 2275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2276 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2277 2278 /* Disable boot interrupts on AMD and ATI chipsets */ 2279 2280 /* 2281 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 2282 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 2283 * (due to an erratum). 2284 */ 2285 #define AMD_813X_MISC 0x40 2286 #define AMD_813X_NOIOAMODE (1<<0) 2287 #define AMD_813X_REV_B1 0x12 2288 #define AMD_813X_REV_B2 0x13 2289 2290 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 2291 { 2292 u32 pci_config_dword; 2293 2294 if (noioapicquirk) 2295 return; 2296 if ((dev->revision == AMD_813X_REV_B1) || 2297 (dev->revision == AMD_813X_REV_B2)) 2298 return; 2299 2300 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 2301 pci_config_dword &= ~AMD_813X_NOIOAMODE; 2302 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 2303 2304 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2305 dev->vendor, dev->device); 2306 } 2307 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2308 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2310 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2311 2312 #define AMD_8111_PCI_IRQ_ROUTING 0x56 2313 2314 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2315 { 2316 u16 pci_config_word; 2317 2318 if (noioapicquirk) 2319 return; 2320 2321 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2322 if (!pci_config_word) { 2323 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2324 dev->vendor, dev->device); 2325 return; 2326 } 2327 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2328 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2329 dev->vendor, dev->device); 2330 } 2331 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2332 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2333 #endif /* CONFIG_X86_IO_APIC */ 2334 2335 /* 2336 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2337 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2338 * Re-allocate the region if needed... 2339 */ 2340 static void quirk_tc86c001_ide(struct pci_dev *dev) 2341 { 2342 struct resource *r = &dev->resource[0]; 2343 2344 if (r->start & 0x8) { 2345 r->flags |= IORESOURCE_UNSET; 2346 resource_set_range(r, 0, SZ_16); 2347 } 2348 } 2349 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2350 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2351 quirk_tc86c001_ide); 2352 2353 /* 2354 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2355 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2356 * being read correctly if bit 7 of the base address is set. 2357 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2358 * Re-allocate the regions to a 256-byte boundary if necessary. 2359 */ 2360 static void quirk_plx_pci9050(struct pci_dev *dev) 2361 { 2362 unsigned int bar; 2363 2364 /* Fixed in revision 2 (PCI 9052). */ 2365 if (dev->revision >= 2) 2366 return; 2367 for (bar = 0; bar <= 1; bar++) 2368 if (pci_resource_len(dev, bar) == 0x80 && 2369 (pci_resource_start(dev, bar) & 0x80)) { 2370 struct resource *r = &dev->resource[bar]; 2371 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2372 bar); 2373 r->flags |= IORESOURCE_UNSET; 2374 resource_set_range(r, 0, SZ_256); 2375 } 2376 } 2377 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2378 quirk_plx_pci9050); 2379 /* 2380 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2381 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2382 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2383 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2384 * 2385 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2386 * driver. 2387 */ 2388 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2389 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2390 2391 /* 2392 * An idle downstream port of a PLX/Broadcom PEX 8532/8533/8548 switch 2393 * autosuspends into D3hot, and that takes the whole switch down with 2394 * it -- any device behind another port of the same switch then sees a 2395 * fatal, non-recoverable bus fault on its next access. Keep these 2396 * ports out of D3 entirely. 2397 */ 2398 static void quirk_plx_pex_no_d3(struct pci_dev *dev) 2399 { 2400 if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) { 2401 dev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 2402 pci_info(dev, "avoiding D3 on this downstream port\n"); 2403 } 2404 } 2405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PLX, 0x8532, quirk_plx_pex_no_d3); 2406 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PLX, 0x8533, quirk_plx_pex_no_d3); 2407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PLX, 0x8548, quirk_plx_pex_no_d3); 2408 2409 static void quirk_netmos(struct pci_dev *dev) 2410 { 2411 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2412 unsigned int num_serial = dev->subsystem_device & 0xf; 2413 2414 /* 2415 * These Netmos parts are multiport serial devices with optional 2416 * parallel ports. Even when parallel ports are present, they 2417 * are identified as class SERIAL, which means the serial driver 2418 * will claim them. To prevent this, mark them as class OTHER. 2419 * These combo devices should be claimed by parport_serial. 2420 * 2421 * The subdevice ID is of the form 0x00PS, where <P> is the number 2422 * of parallel ports and <S> is the number of serial ports. 2423 */ 2424 switch (dev->device) { 2425 case PCI_DEVICE_ID_NETMOS_9835: 2426 /* Well, this rule doesn't hold for the following 9835 device */ 2427 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2428 dev->subsystem_device == 0x0299) 2429 return; 2430 fallthrough; 2431 case PCI_DEVICE_ID_NETMOS_9735: 2432 case PCI_DEVICE_ID_NETMOS_9745: 2433 case PCI_DEVICE_ID_NETMOS_9845: 2434 case PCI_DEVICE_ID_NETMOS_9855: 2435 if (num_parallel) { 2436 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2437 dev->device, num_parallel, num_serial); 2438 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2439 (dev->class & 0xff); 2440 } 2441 } 2442 } 2443 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2444 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2445 2446 static void quirk_e100_interrupt(struct pci_dev *dev) 2447 { 2448 u16 command, pmcsr; 2449 u8 __iomem *csr; 2450 u8 cmd_hi; 2451 2452 switch (dev->device) { 2453 /* PCI IDs taken from drivers/net/e100.c */ 2454 case 0x1029: 2455 case 0x1030 ... 0x1034: 2456 case 0x1038 ... 0x103E: 2457 case 0x1050 ... 0x1057: 2458 case 0x1059: 2459 case 0x1064 ... 0x106B: 2460 case 0x1091 ... 0x1095: 2461 case 0x1209: 2462 case 0x1229: 2463 case 0x2449: 2464 case 0x2459: 2465 case 0x245D: 2466 case 0x27DC: 2467 break; 2468 default: 2469 return; 2470 } 2471 2472 /* 2473 * Some firmware hands off the e100 with interrupts enabled, 2474 * which can cause a flood of interrupts if packets are 2475 * received before the driver attaches to the device. So 2476 * disable all e100 interrupts here. The driver will 2477 * re-enable them when it's ready. 2478 */ 2479 pci_read_config_word(dev, PCI_COMMAND, &command); 2480 2481 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2482 return; 2483 2484 /* 2485 * Check that the device is in the D0 power state. If it's not, 2486 * there is no point to look any further. 2487 */ 2488 if (dev->pm_cap) { 2489 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2490 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2491 return; 2492 } 2493 2494 /* Convert from PCI bus to resource space. */ 2495 csr = ioremap(pci_resource_start(dev, 0), 8); 2496 if (!csr) { 2497 pci_warn(dev, "Can't map e100 registers\n"); 2498 return; 2499 } 2500 2501 cmd_hi = readb(csr + 3); 2502 if (cmd_hi == 0) { 2503 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2504 writeb(1, csr + 3); 2505 } 2506 2507 iounmap(csr); 2508 } 2509 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2510 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2511 2512 /* 2513 * The 82575 and 82598 may experience data corruption issues when transitioning 2514 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2515 */ 2516 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2517 { 2518 pcie_aspm_remove_cap(dev, PCI_EXP_LNKCAP_ASPM_L0S); 2519 } 2520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2530 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2531 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2534 2535 /* Realtek RTS525A generates a Replay Timer Timeout storm when L0s is enabled. */ 2536 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x525a, quirk_disable_aspm_l0s); 2537 2538 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) 2539 { 2540 pcie_aspm_remove_cap(dev, 2541 PCI_EXP_LNKCAP_ASPM_L0S | PCI_EXP_LNKCAP_ASPM_L1); 2542 } 2543 2544 /* 2545 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the 2546 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected; 2547 * disable both L0s and L1 for now to be safe. 2548 */ 2549 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); 2550 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1); 2551 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PASEMI, 0xa002, quirk_disable_aspm_l0s_l1); 2552 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1); 2553 2554 /* 2555 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain 2556 * Link bit cleared after starting the link retrain process to allow this 2557 * process to finish. 2558 * 2559 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the 2560 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. 2561 */ 2562 static void quirk_enable_clear_retrain_link(struct pci_dev *dev) 2563 { 2564 dev->clear_retrain_link = 1; 2565 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); 2566 } 2567 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link); 2568 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link); 2569 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link); 2570 2571 static void fixup_rev1_53c810(struct pci_dev *dev) 2572 { 2573 u32 class = dev->class; 2574 2575 /* 2576 * rev 1 ncr53c810 chips don't set the class at all which means 2577 * they don't get their resources remapped. Fix that here. 2578 */ 2579 if (class) 2580 return; 2581 2582 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2583 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2584 class, dev->class); 2585 } 2586 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2587 2588 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2589 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2590 { 2591 u16 en1k; 2592 2593 pci_read_config_word(dev, 0x40, &en1k); 2594 2595 if (en1k & 0x200) { 2596 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2597 dev->io_window_1k = 1; 2598 } 2599 } 2600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2601 2602 /* 2603 * Unmasking Advisory Non-Fatal Errors on the Apple T2 Secure Enclave 2604 * causes a MacBookPro16,1 to lose power. Set this before pci_aer_init() 2605 * so that it leaves the ANFE mask bit unchanged. 2606 */ 2607 static void quirk_no_aer_anfe(struct pci_dev *dev) 2608 { 2609 dev->no_aer_anfe = 1; 2610 } 2611 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_APPLE, 0x1802, quirk_no_aer_anfe); 2612 2613 /* 2614 * Under some circumstances, AER is not linked with extended capabilities. 2615 * Force it to be linked by setting the corresponding control bit in the 2616 * config space. 2617 */ 2618 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2619 { 2620 uint8_t b; 2621 2622 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2623 if (!(b & 0x20)) { 2624 pci_write_config_byte(dev, 0xf41, b | 0x20); 2625 pci_info(dev, "Linking AER extended capability\n"); 2626 } 2627 } 2628 } 2629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2630 quirk_nvidia_ck804_pcie_aer_ext_cap); 2631 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2632 quirk_nvidia_ck804_pcie_aer_ext_cap); 2633 2634 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2635 { 2636 /* 2637 * Disable PCI Bus Parking and PCI Master read caching on CX700 2638 * which causes unspecified timing errors with a VT6212L on the PCI 2639 * bus leading to USB2.0 packet loss. 2640 * 2641 * This quirk is only enabled if a second (on the external PCI bus) 2642 * VT6212L is found -- the CX700 core itself also contains a USB 2643 * host controller with the same PCI ID as the VT6212L. 2644 */ 2645 2646 /* Count VT6212L instances */ 2647 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2648 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2649 uint8_t b; 2650 2651 /* 2652 * p should contain the first (internal) VT6212L -- see if we have 2653 * an external one by searching again. 2654 */ 2655 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2656 if (!p) 2657 return; 2658 pci_dev_put(p); 2659 2660 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2661 if (b & 0x40) { 2662 /* Turn off PCI Bus Parking */ 2663 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2664 2665 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2666 } 2667 } 2668 2669 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2670 if (b != 0) { 2671 /* Turn off PCI Master read caching */ 2672 pci_write_config_byte(dev, 0x72, 0x0); 2673 2674 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2675 pci_write_config_byte(dev, 0x75, 0x1); 2676 2677 /* Disable "Read FIFO Timer" */ 2678 pci_write_config_byte(dev, 0x77, 0x0); 2679 2680 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2681 } 2682 } 2683 } 2684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2685 2686 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2687 { 2688 u32 rev; 2689 2690 pci_read_config_dword(dev, 0xf4, &rev); 2691 2692 /* Only CAP the MRRS if the device is a 5719 A0 */ 2693 if (rev == 0x05719000) { 2694 int readrq = pcie_get_readrq(dev); 2695 if (readrq > 2048) 2696 pcie_set_readrq(dev, 2048); 2697 } 2698 } 2699 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2700 PCI_DEVICE_ID_TIGON3_5719, 2701 quirk_brcm_5719_limit_mrrs); 2702 2703 /* 2704 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2705 * hide device 6 which configures the overflow device access containing the 2706 * DRBs - this is where we expose device 6. 2707 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2708 */ 2709 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2710 { 2711 u8 reg; 2712 2713 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2714 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2715 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2716 } 2717 } 2718 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2719 quirk_unhide_mch_dev6); 2720 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2721 quirk_unhide_mch_dev6); 2722 2723 #ifdef CONFIG_PCI_MSI 2724 /* 2725 * Some chipsets do not support MSI. We cannot easily rely on setting 2726 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2727 * other buses controlled by the chipset even if Linux is not aware of it. 2728 * Instead of setting the flag on all buses in the machine, simply disable 2729 * MSI globally. 2730 */ 2731 static void quirk_disable_all_msi(struct pci_dev *dev) 2732 { 2733 pci_no_msi(); 2734 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2735 } 2736 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2737 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2738 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2739 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2740 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2742 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2743 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2744 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); 2745 2746 /* Disable MSI on chipsets that are known to not support it */ 2747 static void quirk_disable_msi(struct pci_dev *dev) 2748 { 2749 if (dev->subordinate) { 2750 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2751 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2752 } 2753 } 2754 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2755 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2756 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2757 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RDC, 0x1031, quirk_disable_msi); 2758 2759 /* 2760 * The APC bridge device in AMD 780 family northbridges has some random 2761 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2762 * we use the possible vendor/device IDs of the host bridge for the 2763 * declared quirk, and search for the APC bridge by slot number. 2764 */ 2765 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2766 { 2767 struct pci_dev *apc_bridge; 2768 2769 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2770 if (apc_bridge) { 2771 if (apc_bridge->device == 0x9602) 2772 quirk_disable_msi(apc_bridge); 2773 pci_dev_put(apc_bridge); 2774 } 2775 } 2776 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2777 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2778 2779 /* 2780 * Go through the list of HyperTransport capabilities and return 1 if a HT 2781 * MSI capability is found and enabled. 2782 */ 2783 static int msi_ht_cap_enabled(struct pci_dev *dev) 2784 { 2785 int pos, ttl = PCI_FIND_CAP_TTL; 2786 2787 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2788 while (pos && ttl--) { 2789 u8 flags; 2790 2791 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2792 &flags) == 0) { 2793 pci_info(dev, "Found %s HT MSI Mapping\n", 2794 flags & HT_MSI_FLAGS_ENABLE ? 2795 "enabled" : "disabled"); 2796 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2797 } 2798 2799 pos = pci_find_next_ht_capability(dev, pos, 2800 HT_CAPTYPE_MSI_MAPPING); 2801 } 2802 return 0; 2803 } 2804 2805 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2806 static void quirk_msi_ht_cap(struct pci_dev *dev) 2807 { 2808 if (!msi_ht_cap_enabled(dev)) 2809 quirk_disable_msi(dev); 2810 } 2811 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2812 quirk_msi_ht_cap); 2813 2814 /* 2815 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2816 * if the MSI capability is set in any of these mappings. 2817 */ 2818 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2819 { 2820 struct pci_dev *pdev; 2821 2822 /* 2823 * Check HT MSI cap on this chipset and the root one. A single one 2824 * having MSI is enough to be sure that MSI is supported. 2825 */ 2826 pdev = pci_get_slot(dev->bus, 0); 2827 if (!pdev) 2828 return; 2829 if (!msi_ht_cap_enabled(pdev)) 2830 quirk_msi_ht_cap(dev); 2831 pci_dev_put(pdev); 2832 } 2833 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2834 quirk_nvidia_ck804_msi_ht_cap); 2835 2836 /* Force enable MSI mapping capability on HT bridges */ 2837 static void ht_enable_msi_mapping(struct pci_dev *dev) 2838 { 2839 int pos, ttl = PCI_FIND_CAP_TTL; 2840 2841 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2842 while (pos && ttl--) { 2843 u8 flags; 2844 2845 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2846 &flags) == 0) { 2847 pci_info(dev, "Enabling HT MSI Mapping\n"); 2848 2849 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2850 flags | HT_MSI_FLAGS_ENABLE); 2851 } 2852 pos = pci_find_next_ht_capability(dev, pos, 2853 HT_CAPTYPE_MSI_MAPPING); 2854 } 2855 } 2856 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2857 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2858 ht_enable_msi_mapping); 2859 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2860 ht_enable_msi_mapping); 2861 2862 /* 2863 * The P5N32-SLI motherboards from Asus have a problem with MSI 2864 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2865 * also affects other devices. As for now, turn off MSI for this device. 2866 */ 2867 static void nvenet_msi_disable(struct pci_dev *dev) 2868 { 2869 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2870 2871 if (board_name && 2872 (strstr(board_name, "P5N32-SLI PREMIUM") || 2873 strstr(board_name, "P5N32-E SLI"))) { 2874 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2875 dev->no_msi = 1; 2876 } 2877 } 2878 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2879 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2880 nvenet_msi_disable); 2881 2882 /* 2883 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device 2884 * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI 2885 * interrupts for PME and AER events; instead only INTx interrupts are 2886 * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts 2887 * for other events, since PCIe specification doesn't support using a mix of 2888 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port 2889 * service drivers registering their respective ISRs for MSIs. 2890 */ 2891 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) 2892 { 2893 dev->no_msi = 1; 2894 } 2895 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, 2896 PCI_CLASS_BRIDGE_PCI, 8, 2897 pci_quirk_nvidia_tegra_disable_rp_msi); 2898 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, 2899 PCI_CLASS_BRIDGE_PCI, 8, 2900 pci_quirk_nvidia_tegra_disable_rp_msi); 2901 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, 2902 PCI_CLASS_BRIDGE_PCI, 8, 2903 pci_quirk_nvidia_tegra_disable_rp_msi); 2904 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, 2905 PCI_CLASS_BRIDGE_PCI, 8, 2906 pci_quirk_nvidia_tegra_disable_rp_msi); 2907 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, 2908 PCI_CLASS_BRIDGE_PCI, 8, 2909 pci_quirk_nvidia_tegra_disable_rp_msi); 2910 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, 2911 PCI_CLASS_BRIDGE_PCI, 8, 2912 pci_quirk_nvidia_tegra_disable_rp_msi); 2913 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, 2914 PCI_CLASS_BRIDGE_PCI, 8, 2915 pci_quirk_nvidia_tegra_disable_rp_msi); 2916 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, 2917 PCI_CLASS_BRIDGE_PCI, 8, 2918 pci_quirk_nvidia_tegra_disable_rp_msi); 2919 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, 2920 PCI_CLASS_BRIDGE_PCI, 8, 2921 pci_quirk_nvidia_tegra_disable_rp_msi); 2922 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, 2923 PCI_CLASS_BRIDGE_PCI, 8, 2924 pci_quirk_nvidia_tegra_disable_rp_msi); 2925 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, 2926 PCI_CLASS_BRIDGE_PCI, 8, 2927 pci_quirk_nvidia_tegra_disable_rp_msi); 2928 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, 2929 PCI_CLASS_BRIDGE_PCI, 8, 2930 pci_quirk_nvidia_tegra_disable_rp_msi); 2931 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, 2932 PCI_CLASS_BRIDGE_PCI, 8, 2933 pci_quirk_nvidia_tegra_disable_rp_msi); 2934 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a, 2935 PCI_CLASS_BRIDGE_PCI, 8, 2936 pci_quirk_nvidia_tegra_disable_rp_msi); 2937 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c, 2938 PCI_CLASS_BRIDGE_PCI, 8, 2939 pci_quirk_nvidia_tegra_disable_rp_msi); 2940 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e, 2941 PCI_CLASS_BRIDGE_PCI, 8, 2942 pci_quirk_nvidia_tegra_disable_rp_msi); 2943 2944 /* 2945 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2946 * config register. This register controls the routing of legacy 2947 * interrupts from devices that route through the MCP55. If this register 2948 * is misprogrammed, interrupts are only sent to the BSP, unlike 2949 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2950 * having this register set properly prevents kdump from booting up 2951 * properly, so let's make sure that we have it set correctly. 2952 * Note that this is an undocumented register. 2953 */ 2954 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2955 { 2956 u32 cfg; 2957 2958 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2959 return; 2960 2961 pci_read_config_dword(dev, 0x74, &cfg); 2962 2963 if (cfg & ((1 << 2) | (1 << 15))) { 2964 pr_info("Rewriting IRQ routing register on MCP55\n"); 2965 cfg &= ~((1 << 2) | (1 << 15)); 2966 pci_write_config_dword(dev, 0x74, cfg); 2967 } 2968 } 2969 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2970 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2971 nvbridge_check_legacy_irq_routing); 2972 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2973 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2974 nvbridge_check_legacy_irq_routing); 2975 2976 static int ht_check_msi_mapping(struct pci_dev *dev) 2977 { 2978 int pos, ttl = PCI_FIND_CAP_TTL; 2979 int found = 0; 2980 2981 /* Check if there is HT MSI cap or enabled on this device */ 2982 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2983 while (pos && ttl--) { 2984 u8 flags; 2985 2986 if (found < 1) 2987 found = 1; 2988 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2989 &flags) == 0) { 2990 if (flags & HT_MSI_FLAGS_ENABLE) { 2991 if (found < 2) { 2992 found = 2; 2993 break; 2994 } 2995 } 2996 } 2997 pos = pci_find_next_ht_capability(dev, pos, 2998 HT_CAPTYPE_MSI_MAPPING); 2999 } 3000 3001 return found; 3002 } 3003 3004 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 3005 { 3006 struct pci_dev *dev; 3007 int pos; 3008 int i, dev_no; 3009 int found = 0; 3010 3011 dev_no = host_bridge->devfn >> 3; 3012 for (i = dev_no + 1; i < 0x20; i++) { 3013 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 3014 if (!dev) 3015 continue; 3016 3017 /* found next host bridge? */ 3018 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 3019 if (pos != 0) { 3020 pci_dev_put(dev); 3021 break; 3022 } 3023 3024 if (ht_check_msi_mapping(dev)) { 3025 found = 1; 3026 pci_dev_put(dev); 3027 break; 3028 } 3029 pci_dev_put(dev); 3030 } 3031 3032 return found; 3033 } 3034 3035 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 3036 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 3037 3038 static int is_end_of_ht_chain(struct pci_dev *dev) 3039 { 3040 int pos, ctrl_off; 3041 int end = 0; 3042 u16 flags, ctrl; 3043 3044 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 3045 3046 if (!pos) 3047 goto out; 3048 3049 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 3050 3051 ctrl_off = ((flags >> 10) & 1) ? 3052 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 3053 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 3054 3055 if (ctrl & (1 << 6)) 3056 end = 1; 3057 3058 out: 3059 return end; 3060 } 3061 3062 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 3063 { 3064 struct pci_dev *host_bridge; 3065 int pos; 3066 int i, dev_no; 3067 int found = 0; 3068 3069 dev_no = dev->devfn >> 3; 3070 for (i = dev_no; i >= 0; i--) { 3071 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 3072 if (!host_bridge) 3073 continue; 3074 3075 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3076 if (pos != 0) { 3077 found = 1; 3078 break; 3079 } 3080 pci_dev_put(host_bridge); 3081 } 3082 3083 if (!found) 3084 return; 3085 3086 /* don't enable end_device/host_bridge with leaf directly here */ 3087 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 3088 host_bridge_with_leaf(host_bridge)) 3089 goto out; 3090 3091 /* root did that ! */ 3092 if (msi_ht_cap_enabled(host_bridge)) 3093 goto out; 3094 3095 ht_enable_msi_mapping(dev); 3096 3097 out: 3098 pci_dev_put(host_bridge); 3099 } 3100 3101 static void ht_disable_msi_mapping(struct pci_dev *dev) 3102 { 3103 int pos, ttl = PCI_FIND_CAP_TTL; 3104 3105 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 3106 while (pos && ttl--) { 3107 u8 flags; 3108 3109 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 3110 &flags) == 0) { 3111 pci_info(dev, "Disabling HT MSI Mapping\n"); 3112 3113 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 3114 flags & ~HT_MSI_FLAGS_ENABLE); 3115 } 3116 pos = pci_find_next_ht_capability(dev, pos, 3117 HT_CAPTYPE_MSI_MAPPING); 3118 } 3119 } 3120 3121 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 3122 { 3123 struct pci_dev *host_bridge; 3124 int pos; 3125 int found; 3126 3127 if (!pci_msi_enabled()) 3128 return; 3129 3130 /* check if there is HT MSI cap or enabled on this device */ 3131 found = ht_check_msi_mapping(dev); 3132 3133 /* no HT MSI CAP */ 3134 if (found == 0) 3135 return; 3136 3137 /* 3138 * HT MSI mapping should be disabled on devices that are below 3139 * a non-HyperTransport host bridge. Locate the host bridge. 3140 */ 3141 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 3142 PCI_DEVFN(0, 0)); 3143 if (host_bridge == NULL) { 3144 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 3145 return; 3146 } 3147 3148 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3149 if (pos != 0) { 3150 /* Host bridge is to HT */ 3151 if (found == 1) { 3152 /* it is not enabled, try to enable it */ 3153 if (all) 3154 ht_enable_msi_mapping(dev); 3155 else 3156 nv_ht_enable_msi_mapping(dev); 3157 } 3158 goto out; 3159 } 3160 3161 /* HT MSI is not enabled */ 3162 if (found == 1) 3163 goto out; 3164 3165 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 3166 ht_disable_msi_mapping(dev); 3167 3168 out: 3169 pci_dev_put(host_bridge); 3170 } 3171 3172 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 3173 { 3174 return __nv_msi_ht_cap_quirk(dev, 1); 3175 } 3176 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3177 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3178 3179 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 3180 { 3181 return __nv_msi_ht_cap_quirk(dev, 0); 3182 } 3183 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3184 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3185 3186 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 3187 { 3188 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3189 } 3190 3191 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 3192 { 3193 struct pci_dev *p; 3194 3195 /* 3196 * SB700 MSI issue will be fixed at HW level from revision A21; 3197 * we need check PCI REVISION ID of SMBus controller to get SB700 3198 * revision. 3199 */ 3200 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 3201 NULL); 3202 if (!p) 3203 return; 3204 3205 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 3206 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3207 pci_dev_put(p); 3208 } 3209 3210 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 3211 { 3212 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 3213 if (dev->revision < 0x18) { 3214 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 3215 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3216 } 3217 } 3218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3219 PCI_DEVICE_ID_TIGON3_5780, 3220 quirk_msi_intx_disable_bug); 3221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3222 PCI_DEVICE_ID_TIGON3_5780S, 3223 quirk_msi_intx_disable_bug); 3224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3225 PCI_DEVICE_ID_TIGON3_5714, 3226 quirk_msi_intx_disable_bug); 3227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3228 PCI_DEVICE_ID_TIGON3_5714S, 3229 quirk_msi_intx_disable_bug); 3230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3231 PCI_DEVICE_ID_TIGON3_5715, 3232 quirk_msi_intx_disable_bug); 3233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3234 PCI_DEVICE_ID_TIGON3_5715S, 3235 quirk_msi_intx_disable_bug); 3236 3237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 3238 quirk_msi_intx_disable_ati_bug); 3239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 3240 quirk_msi_intx_disable_ati_bug); 3241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 3242 quirk_msi_intx_disable_ati_bug); 3243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 3244 quirk_msi_intx_disable_ati_bug); 3245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 3246 quirk_msi_intx_disable_ati_bug); 3247 3248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 3249 quirk_msi_intx_disable_bug); 3250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 3251 quirk_msi_intx_disable_bug); 3252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 3253 quirk_msi_intx_disable_bug); 3254 3255 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 3256 quirk_msi_intx_disable_bug); 3257 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 3258 quirk_msi_intx_disable_bug); 3259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 3260 quirk_msi_intx_disable_bug); 3261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 3262 quirk_msi_intx_disable_bug); 3263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 3264 quirk_msi_intx_disable_bug); 3265 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 3266 quirk_msi_intx_disable_bug); 3267 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 3268 quirk_msi_intx_disable_qca_bug); 3269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 3270 quirk_msi_intx_disable_qca_bug); 3271 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 3272 quirk_msi_intx_disable_qca_bug); 3273 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 3274 quirk_msi_intx_disable_qca_bug); 3275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 3276 quirk_msi_intx_disable_qca_bug); 3277 3278 /* 3279 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it 3280 * should be disabled on platforms where the device (mistakenly) advertises it. 3281 * 3282 * Notice that this quirk also disables MSI (which may work, but hasn't been 3283 * tested), since currently there is no standard way to disable only MSI-X. 3284 * 3285 * The 0031 device id is reused for other non Root Port device types, 3286 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class. 3287 */ 3288 static void quirk_al_msi_disable(struct pci_dev *dev) 3289 { 3290 dev->no_msi = 1; 3291 pci_warn(dev, "Disabling MSI/MSI-X\n"); 3292 } 3293 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, 3294 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable); 3295 #endif /* CONFIG_PCI_MSI */ 3296 3297 /* 3298 * Allow manual resource allocation for PCI hotplug bridges via 3299 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 3300 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 3301 * allocate resources when hotplug device is inserted and PCI bus is 3302 * rescanned. 3303 */ 3304 static void quirk_hotplug_bridge(struct pci_dev *dev) 3305 { 3306 dev->is_hotplug_bridge = 1; 3307 } 3308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 3309 3310 /* 3311 * This is a quirk for the Ricoh MMC controller found as a part of some 3312 * multifunction chips. 3313 * 3314 * This is very similar and based on the ricoh_mmc driver written by 3315 * Philip Langdale. Thank you for these magic sequences. 3316 * 3317 * These chips implement the four main memory card controllers (SD, MMC, 3318 * MS, xD) and one or both of CardBus or FireWire. 3319 * 3320 * It happens that they implement SD and MMC support as separate 3321 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 3322 * cards but the chip detects MMC cards in hardware and directs them to the 3323 * MMC controller - so the SDHCI driver never sees them. 3324 * 3325 * To get around this, we must disable the useless MMC controller. At that 3326 * point, the SDHCI controller will start seeing them. It seems to be the 3327 * case that the relevant PCI registers to deactivate the MMC controller 3328 * live on PCI function 0, which might be the CardBus controller or the 3329 * FireWire controller, depending on the particular chip in question 3330 * 3331 * This has to be done early, because as soon as we disable the MMC controller 3332 * other PCI functions shift up one level, e.g. function #2 becomes function 3333 * #1, and this will confuse the PCI core. 3334 */ 3335 #ifdef CONFIG_MMC_RICOH_MMC 3336 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 3337 { 3338 u8 write_enable; 3339 u8 write_target; 3340 u8 disable; 3341 3342 /* 3343 * Disable via CardBus interface 3344 * 3345 * This must be done via function #0 3346 */ 3347 if (PCI_FUNC(dev->devfn)) 3348 return; 3349 3350 pci_read_config_byte(dev, 0xB7, &disable); 3351 if (disable & 0x02) 3352 return; 3353 3354 pci_read_config_byte(dev, 0x8E, &write_enable); 3355 pci_write_config_byte(dev, 0x8E, 0xAA); 3356 pci_read_config_byte(dev, 0x8D, &write_target); 3357 pci_write_config_byte(dev, 0x8D, 0xB7); 3358 pci_write_config_byte(dev, 0xB7, disable | 0x02); 3359 pci_write_config_byte(dev, 0x8E, write_enable); 3360 pci_write_config_byte(dev, 0x8D, write_target); 3361 3362 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 3363 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3364 } 3365 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3366 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3367 3368 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 3369 { 3370 u8 write_enable; 3371 u8 disable; 3372 3373 /* 3374 * Disable via FireWire interface 3375 * 3376 * This must be done via function #0 3377 */ 3378 if (PCI_FUNC(dev->devfn)) 3379 return; 3380 /* 3381 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 3382 * certain types of SD/MMC cards. Lowering the SD base clock 3383 * frequency from 200Mhz to 50Mhz fixes this issue. 3384 * 3385 * 0x150 - SD2.0 mode enable for changing base clock 3386 * frequency to 50Mhz 3387 * 0xe1 - Base clock frequency 3388 * 0x32 - 50Mhz new clock frequency 3389 * 0xf9 - Key register for 0x150 3390 * 0xfc - key register for 0xe1 3391 */ 3392 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 3393 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 3394 pci_write_config_byte(dev, 0xf9, 0xfc); 3395 pci_write_config_byte(dev, 0x150, 0x10); 3396 pci_write_config_byte(dev, 0xf9, 0x00); 3397 pci_write_config_byte(dev, 0xfc, 0x01); 3398 pci_write_config_byte(dev, 0xe1, 0x32); 3399 pci_write_config_byte(dev, 0xfc, 0x00); 3400 3401 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 3402 } 3403 3404 pci_read_config_byte(dev, 0xCB, &disable); 3405 3406 if (disable & 0x02) 3407 return; 3408 3409 pci_read_config_byte(dev, 0xCA, &write_enable); 3410 pci_write_config_byte(dev, 0xCA, 0x57); 3411 pci_write_config_byte(dev, 0xCB, disable | 0x02); 3412 pci_write_config_byte(dev, 0xCA, write_enable); 3413 3414 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 3415 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3416 3417 } 3418 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3419 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3420 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3421 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3422 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3423 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3424 #endif /*CONFIG_MMC_RICOH_MMC*/ 3425 3426 #ifdef CONFIG_DMAR_TABLE 3427 #define VTUNCERRMSK_REG 0x1ac 3428 #define VTD_MSK_SPEC_ERRORS (1 << 31) 3429 /* 3430 * This is a quirk for masking VT-d spec-defined errors to platform error 3431 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3432 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3433 * on the RAS config settings of the platform) when a VT-d fault happens. 3434 * The resulting SMI caused the system to hang. 3435 * 3436 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3437 * need to report the same error through other channels. 3438 */ 3439 static void vtd_mask_spec_errors(struct pci_dev *dev) 3440 { 3441 u32 word; 3442 3443 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3444 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3445 } 3446 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3447 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3448 #endif 3449 3450 static void fixup_ti816x_class(struct pci_dev *dev) 3451 { 3452 u32 class = dev->class; 3453 3454 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3455 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3456 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3457 class, dev->class); 3458 } 3459 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3460 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3461 3462 /* 3463 * Some PCIe devices do not work reliably with the claimed maximum 3464 * payload size supported. 3465 */ 3466 static void fixup_mpss_256(struct pci_dev *dev) 3467 { 3468 dev->pcie_mpss = 1; /* 256 bytes */ 3469 } 3470 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3471 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3472 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3473 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3474 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3475 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3476 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); 3477 3478 /* 3479 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3480 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3481 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3482 * until all of the devices are discovered and buses walked, read completion 3483 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3484 * it is possible to hotplug a device with MPS of 256B. 3485 */ 3486 static void quirk_intel_mc_errata(struct pci_dev *dev) 3487 { 3488 int err; 3489 u16 rcc; 3490 3491 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3492 pcie_bus_config == PCIE_BUS_DEFAULT) 3493 return; 3494 3495 /* 3496 * Intel erratum specifies bits to change but does not say what 3497 * they are. Keeping them magical until such time as the registers 3498 * and values can be explained. 3499 */ 3500 err = pci_read_config_word(dev, 0x48, &rcc); 3501 if (err) { 3502 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3503 return; 3504 } 3505 3506 if (!(rcc & (1 << 10))) 3507 return; 3508 3509 rcc &= ~(1 << 10); 3510 3511 err = pci_write_config_word(dev, 0x48, rcc); 3512 if (err) { 3513 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3514 return; 3515 } 3516 3517 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3518 } 3519 /* Intel 5000 series memory controllers and ports 2-7 */ 3520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3530 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3531 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3534 /* Intel 5100 series memory controllers and ports 2-7 */ 3535 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3536 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3537 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3538 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3539 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3540 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3541 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3542 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3543 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3544 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3545 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3546 3547 /* 3548 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3549 * To work around this, query the size it should be configured to by the 3550 * device and modify the resource end to correspond to this new size. 3551 */ 3552 static void quirk_intel_ntb(struct pci_dev *dev) 3553 { 3554 int rc; 3555 u8 val; 3556 3557 rc = pci_read_config_byte(dev, 0x00D0, &val); 3558 if (rc) 3559 return; 3560 3561 resource_set_size(&dev->resource[2], (resource_size_t)1 << val); 3562 3563 rc = pci_read_config_byte(dev, 0x00D1, &val); 3564 if (rc) 3565 return; 3566 3567 resource_set_size(&dev->resource[4], (resource_size_t)1 << val); 3568 } 3569 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3570 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3571 3572 /* 3573 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3574 * though no one is handling them (e.g., if the i915 driver is never 3575 * loaded). Additionally the interrupt destination is not set up properly 3576 * and the interrupt ends up -somewhere-. 3577 * 3578 * These spurious interrupts are "sticky" and the kernel disables the 3579 * (shared) interrupt line after 100,000+ generated interrupts. 3580 * 3581 * Fix it by disabling the still enabled interrupts. This resolves crashes 3582 * often seen on monitor unplug. 3583 */ 3584 #define I915_DEIER_REG 0x4400c 3585 static void disable_igfx_irq(struct pci_dev *dev) 3586 { 3587 void __iomem *regs = pci_iomap(dev, 0, 0); 3588 if (regs == NULL) { 3589 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3590 return; 3591 } 3592 3593 /* Check if any interrupt line is still enabled */ 3594 if (readl(regs + I915_DEIER_REG) != 0) { 3595 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3596 3597 writel(0, regs + I915_DEIER_REG); 3598 } 3599 3600 pci_iounmap(dev, regs); 3601 } 3602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); 3603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); 3604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); 3605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); 3607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3609 3610 /* 3611 * PCI devices which are on Intel chips can skip the 10ms delay 3612 * before entering D3 mode. 3613 */ 3614 static void quirk_remove_d3hot_delay(struct pci_dev *dev) 3615 { 3616 dev->d3hot_delay = 0; 3617 } 3618 /* C600 Series devices do not need 10ms d3hot_delay */ 3619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay); 3620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay); 3621 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay); 3622 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */ 3623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay); 3624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay); 3625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay); 3626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay); 3627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay); 3628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay); 3629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay); 3630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay); 3631 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay); 3632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay); 3633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay); 3634 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */ 3635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay); 3636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay); 3637 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay); 3638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay); 3639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay); 3640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay); 3641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay); 3642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay); 3643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay); 3644 3645 /* 3646 * Some devices may pass our check in pci_intx_mask_supported() if 3647 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3648 * support this feature. 3649 */ 3650 static void quirk_broken_intx_masking(struct pci_dev *dev) 3651 { 3652 dev->broken_intx_masking = 1; 3653 } 3654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3655 quirk_broken_intx_masking); 3656 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3657 quirk_broken_intx_masking); 3658 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3659 quirk_broken_intx_masking); 3660 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_20K2, 3661 quirk_broken_intx_masking); 3662 3663 /* 3664 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3665 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3666 * 3667 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3668 */ 3669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3670 quirk_broken_intx_masking); 3671 3672 /* 3673 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3674 * DisINTx can be set but the interrupt status bit is non-functional. 3675 */ 3676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3687 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3688 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3689 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3690 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3691 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3692 3693 static u16 mellanox_broken_intx_devs[] = { 3694 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3695 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3696 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3697 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3698 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3699 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3700 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3701 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3702 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3703 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3704 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3705 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3706 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3707 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3708 }; 3709 3710 #define CONNECTX_4_CURR_MAX_MINOR 99 3711 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3712 3713 /* 3714 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3715 * If so, don't mark it as broken. 3716 * FW minor > 99 means older FW version format and no INTx masking support. 3717 * FW minor < 14 means new FW version format and no INTx masking support. 3718 */ 3719 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3720 { 3721 __be32 __iomem *fw_ver; 3722 u16 fw_major; 3723 u16 fw_minor; 3724 u16 fw_subminor; 3725 u32 fw_maj_min; 3726 u32 fw_sub_min; 3727 int i; 3728 3729 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3730 if (pdev->device == mellanox_broken_intx_devs[i]) { 3731 pdev->broken_intx_masking = 1; 3732 return; 3733 } 3734 } 3735 3736 /* 3737 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3738 * support so shouldn't be checked further 3739 */ 3740 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3741 return; 3742 3743 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3744 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3745 return; 3746 3747 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3748 if (pci_enable_device_mem(pdev)) { 3749 pci_warn(pdev, "Can't enable device memory\n"); 3750 return; 3751 } 3752 3753 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3754 if (!fw_ver) { 3755 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3756 goto out; 3757 } 3758 3759 /* Reading from resource space should be 32b aligned */ 3760 fw_maj_min = ioread32be(fw_ver); 3761 fw_sub_min = ioread32be(fw_ver + 1); 3762 fw_major = fw_maj_min & 0xffff; 3763 fw_minor = fw_maj_min >> 16; 3764 fw_subminor = fw_sub_min & 0xffff; 3765 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3766 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3767 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3768 fw_major, fw_minor, fw_subminor, pdev->device == 3769 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3770 pdev->broken_intx_masking = 1; 3771 } 3772 3773 iounmap(fw_ver); 3774 3775 out: 3776 pci_disable_device(pdev); 3777 } 3778 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3779 mellanox_check_broken_intx_masking); 3780 3781 static void quirk_no_bus_reset(struct pci_dev *dev) 3782 { 3783 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3784 } 3785 3786 /* 3787 * After asserting Secondary Bus Reset to downstream devices via a GB10 3788 * Root Port, the link may not retrain correctly. 3789 * https://lore.kernel.org/r/20251113084441.2124737-1-Johnny-CC.Chang@mediatek.com 3790 */ 3791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x22CE, quirk_no_bus_reset); 3792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x22D0, quirk_no_bus_reset); 3793 3794 /* 3795 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be 3796 * prevented for those affected devices. 3797 */ 3798 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) 3799 { 3800 if ((dev->device & 0xffc0) == 0x2340) 3801 quirk_no_bus_reset(dev); 3802 } 3803 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 3804 quirk_nvidia_no_bus_reset); 3805 3806 /* 3807 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3808 * The device will throw a Link Down error on AER-capable systems and 3809 * regardless of AER, config space of the device is never accessible again 3810 * and typically causes the system to hang or reset when access is attempted. 3811 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ 3812 */ 3813 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3814 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3815 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3816 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3817 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); 3818 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); 3819 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x1103, quirk_no_bus_reset); /* WCN6855 */ 3820 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x1107, quirk_no_bus_reset); /* WCN7850 */ 3821 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x0308, quirk_no_bus_reset); /* SDX62/SDX65 */ 3822 3823 /* 3824 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3825 * reset when used with certain child devices. After the reset, config 3826 * accesses to the child may fail. 3827 */ 3828 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3829 3830 /* 3831 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS 3832 * automatically disables LTSSM when Secondary Bus Reset is received and 3833 * the device stops working. Prevent bus reset for these devices. With 3834 * this change, the device can be assigned to VMs with VFIO, but it will 3835 * leak state between VMs. Reference 3836 * https://e2e.ti.com/support/processors/f/791/t/954382 3837 */ 3838 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); 3839 3840 /* 3841 * Reports from users making use of PCI device assignment with ASM1164 3842 * controllers indicate an issue with bus reset where the device fails to 3843 * retrain. The issue appears more common in configurations with multiple 3844 * controllers. The device does indicate PM reset support (NoSoftRst-), 3845 * therefore this still leaves a viable reset method. 3846 * https://forum.proxmox.com/threads/problems-with-pcie-passthrough-with-two-identical-devices.149003/ 3847 */ 3848 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1164, quirk_no_bus_reset); 3849 3850 /* Intel DG1 0x4905 may not recover from bus reset */ 3851 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4905, quirk_no_bus_reset); 3852 3853 static void quirk_no_pm_reset(struct pci_dev *dev) 3854 { 3855 /* 3856 * We can't do a bus reset on root bus devices, but an ineffective 3857 * PM reset may be better than nothing. 3858 */ 3859 if (!pci_is_root_bus(dev->bus)) 3860 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3861 } 3862 3863 /* 3864 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3865 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3866 * to have no effect on the device: it retains the framebuffer contents and 3867 * monitor sync. Advertising this support makes other layers, like VFIO, 3868 * assume pci_reset_function() is viable for this device. Mark it as 3869 * unavailable to skip it when testing reset methods. 3870 */ 3871 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3872 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3873 3874 /* 3875 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset 3876 * (i.e., they advertise NoSoftRst-). However, this transition does not have 3877 * any effect on the device: It continues to be operational and network ports 3878 * remain up. Advertising this support makes it seem as if a PM reset is viable 3879 * for these devices. Mark it as unavailable to skip it when testing reset 3880 * methods. 3881 */ 3882 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset); 3883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset); 3884 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset); 3885 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset); 3886 3887 /* 3888 * Thunderbolt controllers with broken MSI hotplug signaling: 3889 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3890 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3891 */ 3892 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3893 { 3894 if (pdev->is_pciehp && 3895 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3896 pdev->revision <= 1)) 3897 pdev->no_msi = 1; 3898 } 3899 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3900 quirk_thunderbolt_hotplug_msi); 3901 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3902 quirk_thunderbolt_hotplug_msi); 3903 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3904 quirk_thunderbolt_hotplug_msi); 3905 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3906 quirk_thunderbolt_hotplug_msi); 3907 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3908 quirk_thunderbolt_hotplug_msi); 3909 3910 #ifdef CONFIG_ACPI 3911 /* 3912 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3913 * 3914 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3915 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3916 * be present after resume if a device was plugged in before suspend. 3917 * 3918 * The Thunderbolt controller consists of a PCIe switch with downstream 3919 * bridges leading to the NHI and to the tunnel PCI bridges. 3920 * 3921 * This quirk cuts power to the whole chip. Therefore we have to apply it 3922 * during suspend_noirq of the upstream bridge. 3923 * 3924 * Power is automagically restored before resume. No action is needed. 3925 */ 3926 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3927 { 3928 acpi_handle bridge, SXIO, SXFP, SXLV; 3929 3930 if (!x86_apple_machine) 3931 return; 3932 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3933 return; 3934 3935 /* 3936 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller. 3937 * We don't know how to turn it back on again, but firmware does, 3938 * so we can only use SXIO/SXFP/SXLF if we're suspending via 3939 * firmware. 3940 */ 3941 if (!pm_suspend_via_firmware()) 3942 return; 3943 3944 bridge = ACPI_HANDLE(&dev->dev); 3945 if (!bridge) 3946 return; 3947 3948 /* 3949 * SXIO and SXLV are present only on machines requiring this quirk. 3950 * Thunderbolt bridges in external devices might have the same 3951 * device ID as those on the host, but they will not have the 3952 * associated ACPI methods. This implicitly checks that we are at 3953 * the right bridge. 3954 */ 3955 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3956 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3957 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3958 return; 3959 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3960 3961 /* magic sequence */ 3962 acpi_execute_simple_method(SXIO, NULL, 1); 3963 acpi_execute_simple_method(SXFP, NULL, 0); 3964 msleep(300); 3965 acpi_execute_simple_method(SXLV, NULL, 0); 3966 acpi_execute_simple_method(SXIO, NULL, 0); 3967 acpi_execute_simple_method(SXLV, NULL, 0); 3968 } 3969 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3970 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3971 quirk_apple_poweroff_thunderbolt); 3972 #endif 3973 3974 /* 3975 * Following are device-specific reset methods which can be used to 3976 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3977 * not available. 3978 */ 3979 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe) 3980 { 3981 /* 3982 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3983 * 3984 * The 82599 supports FLR on VFs, but FLR support is reported only 3985 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3986 * Thus we must call pcie_flr() directly without first checking if it is 3987 * supported. 3988 */ 3989 if (!probe) 3990 pcie_flr(dev); 3991 return 0; 3992 } 3993 3994 #define SOUTH_CHICKEN2 0xc2004 3995 #define PCH_PP_STATUS 0xc7200 3996 #define PCH_PP_CONTROL 0xc7204 3997 #define MSG_CTL 0x45010 3998 #define NSDE_PWR_STATE 0xd0100 3999 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 4000 4001 static int reset_ivb_igd(struct pci_dev *dev, bool probe) 4002 { 4003 void __iomem *mmio_base; 4004 unsigned long timeout; 4005 u32 val; 4006 4007 if (probe) 4008 return 0; 4009 4010 mmio_base = pci_iomap(dev, 0, 0); 4011 if (!mmio_base) 4012 return -ENOMEM; 4013 4014 iowrite32(0x00000002, mmio_base + MSG_CTL); 4015 4016 /* 4017 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 4018 * driver loaded sets the right bits. However, this's a reset and 4019 * the bits have been set by i915 previously, so we clobber 4020 * SOUTH_CHICKEN2 register directly here. 4021 */ 4022 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 4023 4024 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 4025 iowrite32(val, mmio_base + PCH_PP_CONTROL); 4026 4027 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 4028 do { 4029 val = ioread32(mmio_base + PCH_PP_STATUS); 4030 if ((val & 0xb0000000) == 0) 4031 goto reset_complete; 4032 msleep(10); 4033 } while (time_before(jiffies, timeout)); 4034 pci_warn(dev, "timeout during reset\n"); 4035 4036 reset_complete: 4037 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 4038 4039 pci_iounmap(dev, mmio_base); 4040 return 0; 4041 } 4042 4043 /* Device-specific reset method for Chelsio T4-based adapters */ 4044 static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe) 4045 { 4046 u16 old_command; 4047 u16 msix_flags; 4048 4049 /* 4050 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 4051 * that we have no device-specific reset method. 4052 */ 4053 if ((dev->device & 0xf000) != 0x4000) 4054 return -ENOTTY; 4055 4056 /* 4057 * If this is the "probe" phase, return 0 indicating that we can 4058 * reset this device. 4059 */ 4060 if (probe) 4061 return 0; 4062 4063 /* 4064 * T4 can wedge if there are DMAs in flight within the chip and Bus 4065 * Master has been disabled. We need to have it on till the Function 4066 * Level Reset completes. (BUS_MASTER is disabled in 4067 * pci_reset_function()). 4068 */ 4069 pci_read_config_word(dev, PCI_COMMAND, &old_command); 4070 pci_write_config_word(dev, PCI_COMMAND, 4071 old_command | PCI_COMMAND_MASTER); 4072 4073 /* 4074 * Perform the actual device function reset, saving and restoring 4075 * configuration information around the reset. 4076 */ 4077 pci_save_state(dev); 4078 4079 /* 4080 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 4081 * are disabled when an MSI-X interrupt message needs to be delivered. 4082 * So we briefly re-enable MSI-X interrupts for the duration of the 4083 * FLR. The pci_restore_state() below will restore the original 4084 * MSI-X state. 4085 */ 4086 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 4087 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 4088 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 4089 msix_flags | 4090 PCI_MSIX_FLAGS_ENABLE | 4091 PCI_MSIX_FLAGS_MASKALL); 4092 4093 pcie_flr(dev); 4094 4095 /* 4096 * Restore the configuration information (BAR values, etc.) including 4097 * the original PCI Configuration Space Command word, and return 4098 * success. 4099 */ 4100 pci_restore_state(dev); 4101 pci_write_config_word(dev, PCI_COMMAND, old_command); 4102 return 0; 4103 } 4104 4105 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 4106 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 4107 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 4108 4109 /* 4110 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after 4111 * FLR where config space reads from the device return -1. We seem to be 4112 * able to avoid this condition if we disable the NVMe controller prior to 4113 * FLR. This quirk is generic for any NVMe class device requiring similar 4114 * assistance to quiesce the device prior to FLR. 4115 * 4116 * NVMe specification: https://nvmexpress.org/resources/specifications/ 4117 * Revision 1.0e: 4118 * Chapter 2: Required and optional PCI config registers 4119 * Chapter 3: NVMe control registers 4120 * Chapter 7.3: Reset behavior 4121 */ 4122 static int nvme_disable_and_flr(struct pci_dev *dev, bool probe) 4123 { 4124 void __iomem *bar; 4125 u16 cmd; 4126 u32 cfg; 4127 4128 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || 4129 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) 4130 return -ENOTTY; 4131 4132 if (probe) 4133 return 0; 4134 4135 bar = pci_iomap(dev, 0, NVME_REG_CSTS + sizeof(u32)); 4136 if (!bar) 4137 return -ENOTTY; 4138 4139 pci_read_config_word(dev, PCI_COMMAND, &cmd); 4140 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 4141 4142 cfg = readl(bar + NVME_REG_CC); 4143 4144 /* Disable controller if enabled */ 4145 if (cfg & NVME_CC_ENABLE) { 4146 u32 cap = readl(bar + NVME_REG_CAP); 4147 unsigned long timeout; 4148 4149 /* 4150 * Per nvme_disable_ctrl() skip shutdown notification as it 4151 * could complete commands to the admin queue. We only intend 4152 * to quiesce the device before reset. 4153 */ 4154 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); 4155 4156 writel(cfg, bar + NVME_REG_CC); 4157 4158 /* 4159 * Some controllers require an additional delay here, see 4160 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet 4161 * supported by this quirk. 4162 */ 4163 4164 /* Cap register provides max timeout in 500ms increments */ 4165 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; 4166 4167 for (;;) { 4168 u32 status = readl(bar + NVME_REG_CSTS); 4169 4170 /* Ready status becomes zero on disable complete */ 4171 if (!(status & NVME_CSTS_RDY)) 4172 break; 4173 4174 msleep(100); 4175 4176 if (time_after(jiffies, timeout)) { 4177 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); 4178 break; 4179 } 4180 } 4181 } 4182 4183 pci_iounmap(dev, bar); 4184 4185 pcie_flr(dev); 4186 4187 return 0; 4188 } 4189 4190 /* 4191 * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will 4192 * timeout waiting for ready status to change after NVMe enable if the driver 4193 * starts interacting with the device too soon after FLR. A 250ms delay after 4194 * FLR has heuristically proven to produce reliably working results for device 4195 * assignment cases. 4196 */ 4197 static int delay_250ms_after_flr(struct pci_dev *dev, bool probe) 4198 { 4199 if (probe) 4200 return pcie_reset_flr(dev, PCI_RESET_PROBE); 4201 4202 pcie_reset_flr(dev, PCI_RESET_DO_RESET); 4203 4204 msleep(250); 4205 4206 return 0; 4207 } 4208 4209 #define PCI_DEVICE_ID_HINIC_VF 0x375E 4210 #define HINIC_VF_FLR_TYPE 0x1000 4211 #define HINIC_VF_FLR_CAP_BIT (1UL << 30) 4212 #define HINIC_VF_OP 0xE80 4213 #define HINIC_VF_FLR_PROC_BIT (1UL << 18) 4214 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ 4215 4216 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ 4217 static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe) 4218 { 4219 unsigned long timeout; 4220 void __iomem *bar; 4221 u32 val; 4222 4223 if (probe) 4224 return 0; 4225 4226 bar = pci_iomap(pdev, 0, 0); 4227 if (!bar) 4228 return -ENOTTY; 4229 4230 /* Get and check firmware capabilities */ 4231 val = ioread32be(bar + HINIC_VF_FLR_TYPE); 4232 if (!(val & HINIC_VF_FLR_CAP_BIT)) { 4233 pci_iounmap(pdev, bar); 4234 return -ENOTTY; 4235 } 4236 4237 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */ 4238 val = ioread32be(bar + HINIC_VF_OP); 4239 val = val | HINIC_VF_FLR_PROC_BIT; 4240 iowrite32be(val, bar + HINIC_VF_OP); 4241 4242 pcie_flr(pdev); 4243 4244 /* 4245 * The device must recapture its Bus and Device Numbers after FLR 4246 * in order generate Completions. Issue a config write to let the 4247 * device capture this information. 4248 */ 4249 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); 4250 4251 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */ 4252 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT); 4253 do { 4254 val = ioread32be(bar + HINIC_VF_OP); 4255 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4256 goto reset_complete; 4257 msleep(20); 4258 } while (time_before(jiffies, timeout)); 4259 4260 val = ioread32be(bar + HINIC_VF_OP); 4261 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4262 goto reset_complete; 4263 4264 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val); 4265 4266 reset_complete: 4267 pci_iounmap(pdev, bar); 4268 4269 return 0; 4270 } 4271 4272 #define QUALCOMM_WLAN_PCIE_SOC_GLOBAL_RESET 0x3008 4273 #define QUALCOMM_WLAN_PCIE_SOC_GLOBAL_RESET_V BIT(0) 4274 #define QUALCOMM_WLAN_MHICTRL 0x38 4275 #define QUALCOMM_WLAN_MHICTRL_RESET_MASK 0x2 4276 4277 /* 4278 * Qualcomm WLAN device-specific reset using SoC global reset via BAR0 4279 * registers. 4280 */ 4281 static int reset_qualcomm_wlan(struct pci_dev *pdev, bool probe) 4282 { 4283 void __iomem *bar; 4284 u32 val; 4285 u16 cmd; 4286 int ret; 4287 4288 if (probe) 4289 return 0; 4290 4291 if (pdev->current_state != PCI_D0) 4292 return -EINVAL; 4293 4294 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 4295 pci_write_config_word(pdev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 4296 4297 bar = pci_iomap(pdev, 0, 0); 4298 if (!bar) { 4299 pci_write_config_word(pdev, PCI_COMMAND, cmd); 4300 return -ENODEV; 4301 } 4302 4303 val = ioread32(bar + QUALCOMM_WLAN_PCIE_SOC_GLOBAL_RESET); 4304 if (PCI_POSSIBLE_ERROR(val)) { 4305 ret = -ENODEV; 4306 goto out_restore; 4307 } 4308 val |= QUALCOMM_WLAN_PCIE_SOC_GLOBAL_RESET_V; 4309 iowrite32(val, bar + QUALCOMM_WLAN_PCIE_SOC_GLOBAL_RESET); 4310 ioread32(bar + QUALCOMM_WLAN_PCIE_SOC_GLOBAL_RESET); 4311 4312 msleep(10); 4313 4314 val &= ~QUALCOMM_WLAN_PCIE_SOC_GLOBAL_RESET_V; 4315 iowrite32(val, bar + QUALCOMM_WLAN_PCIE_SOC_GLOBAL_RESET); 4316 ioread32(bar + QUALCOMM_WLAN_PCIE_SOC_GLOBAL_RESET); 4317 4318 msleep(10); 4319 4320 ret = read_poll_timeout(ioread32, val, !PCI_POSSIBLE_ERROR(val), 4321 20 * USEC_PER_MSEC, 5 * USEC_PER_SEC, false, 4322 bar + QUALCOMM_WLAN_PCIE_SOC_GLOBAL_RESET); 4323 if (ret) { 4324 pci_err(pdev, "PCIe link failed to recover after reset\n"); 4325 goto out_restore; 4326 } 4327 4328 /* 4329 * After SOC_GLOBAL_RESET, MHISTATUS may still have SYSERR bit set 4330 * and thus need to set MHICTRL_RESET to clear SYSERR. 4331 */ 4332 iowrite32(QUALCOMM_WLAN_MHICTRL_RESET_MASK, bar + QUALCOMM_WLAN_MHICTRL); 4333 ioread32(bar + QUALCOMM_WLAN_MHICTRL); 4334 4335 msleep(10); 4336 4337 out_restore: 4338 pci_iounmap(pdev, bar); 4339 pci_write_config_word(pdev, PCI_COMMAND, cmd); 4340 4341 return ret; 4342 } 4343 4344 #define MHI_SOC_RESET_REQ_OFFSET 0xb0 4345 #define MHI_SOC_RESET_REQ BIT(0) 4346 4347 /* 4348 * Qualcomm modem device-specific reset using MHI SoC reset via BAR0 4349 * register. 4350 */ 4351 static int reset_qualcomm_modem(struct pci_dev *pdev, bool probe) 4352 { 4353 void __iomem *bar; 4354 u16 cmd; 4355 4356 if (probe) 4357 return 0; 4358 4359 if (pdev->current_state != PCI_D0) 4360 return -EINVAL; 4361 4362 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 4363 pci_write_config_word(pdev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 4364 4365 bar = pci_iomap(pdev, 0, 0); 4366 if (!bar) { 4367 pci_write_config_word(pdev, PCI_COMMAND, cmd); 4368 return -ENODEV; 4369 } 4370 4371 iowrite32(MHI_SOC_RESET_REQ, bar + MHI_SOC_RESET_REQ_OFFSET); 4372 ioread32(bar + MHI_SOC_RESET_REQ_OFFSET); 4373 4374 /* Be sure device reset has been executed */ 4375 msleep(2000); 4376 4377 pci_iounmap(pdev, bar); 4378 pci_write_config_word(pdev, PCI_COMMAND, cmd); 4379 4380 return 0; 4381 } 4382 4383 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 4384 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 4385 reset_intel_82599_sfp_virtfn }, 4386 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 4387 reset_ivb_igd }, 4388 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 4389 reset_ivb_igd }, 4390 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, 4391 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, 4392 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr }, 4393 { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr }, 4394 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4395 reset_chelsio_generic_dev }, 4396 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, 4397 reset_hinic_vf_dev }, 4398 { PCI_VENDOR_ID_QCOM, 0x0308, reset_qualcomm_modem }, /* SDX62/SDX65 modems */ 4399 { PCI_VENDOR_ID_QCOM, 0x1103, reset_qualcomm_wlan }, /* WCN6855 WLAN */ 4400 { PCI_VENDOR_ID_QCOM, 0x1107, reset_qualcomm_wlan }, /* WCN7850 WLAN */ 4401 { 0 } 4402 }; 4403 4404 static int __pci_dev_specific_reset(struct pci_dev *dev, bool probe, 4405 const struct pci_dev_reset_methods *i) 4406 { 4407 int ret; 4408 4409 ret = pci_dev_reset_iommu_prepare(dev); 4410 if (ret) { 4411 pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); 4412 return ret; 4413 } 4414 4415 ret = i->reset(dev, probe); 4416 pci_dev_reset_iommu_done(dev); 4417 return ret; 4418 } 4419 4420 /* 4421 * These device-specific reset methods are here rather than in a driver 4422 * because when a host assigns a device to a guest VM, the host may need 4423 * to reset the device but probably doesn't have a driver for it. 4424 */ 4425 int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 4426 { 4427 const struct pci_dev_reset_methods *i; 4428 4429 for (i = pci_dev_reset_methods; i->reset; i++) { 4430 if ((i->vendor == dev->vendor || 4431 i->vendor == (u16)PCI_ANY_ID) && 4432 (i->device == dev->device || 4433 i->device == (u16)PCI_ANY_ID)) 4434 return __pci_dev_specific_reset(dev, probe, i); 4435 } 4436 4437 return -ENOTTY; 4438 } 4439 4440 static void quirk_dma_func0_alias(struct pci_dev *dev) 4441 { 4442 if (PCI_FUNC(dev->devfn) != 0) 4443 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); 4444 } 4445 4446 /* 4447 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 4448 * 4449 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 4450 */ 4451 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 4452 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 4453 4454 /* Some Glenfly chips use function 0 as the PCIe Requester ID for DMA */ 4455 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d40, quirk_dma_func0_alias); 4456 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d41, quirk_dma_func0_alias); 4457 4458 static void quirk_dma_func1_alias(struct pci_dev *dev) 4459 { 4460 if (PCI_FUNC(dev->devfn) != 1) 4461 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); 4462 } 4463 4464 /* 4465 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 4466 * SKUs function 1 is present and is a legacy IDE controller, in other 4467 * SKUs this function is not present, making this a ghost requester. 4468 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 4469 */ 4470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 4471 quirk_dma_func1_alias); 4472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 4473 quirk_dma_func1_alias); 4474 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */ 4475 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, 4476 quirk_dma_func1_alias); 4477 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 4478 quirk_dma_func1_alias); 4479 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 4480 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 4481 quirk_dma_func1_alias); 4482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, 4483 quirk_dma_func1_alias); 4484 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 4485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 4486 quirk_dma_func1_alias); 4487 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 4488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 4489 quirk_dma_func1_alias); 4490 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 4491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 4492 quirk_dma_func1_alias); 4493 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ 4494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, 4495 quirk_dma_func1_alias); 4496 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 4497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 4498 quirk_dma_func1_alias); 4499 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ 4500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, 4501 quirk_dma_func1_alias); 4502 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 4503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 4504 quirk_dma_func1_alias); 4505 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 4506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 4507 quirk_dma_func1_alias); 4508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, 4509 quirk_dma_func1_alias); 4510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 4511 quirk_dma_func1_alias); 4512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 4513 quirk_dma_func1_alias); 4514 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 4515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 4516 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 4517 quirk_dma_func1_alias); 4518 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 4519 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 4520 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 4521 quirk_dma_func1_alias); 4522 4523 /* 4524 * Some devices DMA with the wrong devfn, not just the wrong function. 4525 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 4526 * the alias is "fixed" and independent of the device devfn. 4527 * 4528 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 4529 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 4530 * single device on the secondary bus. In reality, the single exposed 4531 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 4532 * that provides a bridge to the internal bus of the I/O processor. The 4533 * controller supports private devices, which can be hidden from PCI config 4534 * space. In the case of the Adaptec 3405, a private device at 01.0 4535 * appears to be the DMA engine, which therefore needs to become a DMA 4536 * alias for the device. 4537 */ 4538 static const struct pci_device_id fixed_dma_alias_tbl[] = { 4539 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4540 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 4541 .driver_data = PCI_DEVFN(1, 0) }, 4542 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4543 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 4544 .driver_data = PCI_DEVFN(1, 0) }, 4545 { 0 } 4546 }; 4547 4548 static void quirk_fixed_dma_alias(struct pci_dev *dev) 4549 { 4550 const struct pci_device_id *id; 4551 4552 id = pci_match_id(fixed_dma_alias_tbl, dev); 4553 if (id) 4554 pci_add_dma_alias(dev, id->driver_data, 1); 4555 } 4556 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 4557 4558 /* 4559 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 4560 * using the wrong DMA alias for the device. Some of these devices can be 4561 * used as either forward or reverse bridges, so we need to test whether the 4562 * device is operating in the correct mode. We could probably apply this 4563 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 4564 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 4565 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 4566 */ 4567 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 4568 { 4569 if (!pci_is_root_bus(pdev->bus) && 4570 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4571 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 4572 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 4573 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 4574 } 4575 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 4576 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 4577 quirk_use_pcie_bridge_dma_alias); 4578 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 4579 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 4580 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 4581 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 4582 /* ITE 8893 has the same problem as the 8892 */ 4583 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 4584 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 4585 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 4586 4587 /* 4588 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 4589 * be added as aliases to the DMA device in order to allow buffer access 4590 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 4591 * programmed in the EEPROM. 4592 */ 4593 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 4594 { 4595 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); 4596 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); 4597 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); 4598 } 4599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 4600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 4601 4602 /* 4603 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices 4604 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). 4605 * 4606 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access 4607 * when IOMMU is enabled. These aliases allow computational unit access to 4608 * host memory. These aliases mark the whole VCA device as one IOMMU 4609 * group. 4610 * 4611 * All possible slot numbers (0x20) are used, since we are unable to tell 4612 * what slot is used on other side. This quirk is intended for both host 4613 * and computational unit sides. The VCA devices have up to five functions 4614 * (four for DMA channels and one additional). 4615 */ 4616 static void quirk_pex_vca_alias(struct pci_dev *pdev) 4617 { 4618 const unsigned int num_pci_slots = 0x20; 4619 unsigned int slot; 4620 4621 for (slot = 0; slot < num_pci_slots; slot++) 4622 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); 4623 } 4624 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias); 4625 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias); 4626 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias); 4627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias); 4628 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias); 4629 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias); 4630 4631 /* 4632 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 4633 * associated not at the root bus, but at a bridge below. This quirk avoids 4634 * generating invalid DMA aliases. 4635 */ 4636 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 4637 { 4638 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 4639 } 4640 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 4641 quirk_bridge_cavm_thrx2_pcie_root); 4642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 4643 quirk_bridge_cavm_thrx2_pcie_root); 4644 4645 /* 4646 * AST1150 doesn't use a real PCI bus and always forwards the requester ID 4647 * from downstream devices. 4648 */ 4649 static void quirk_aspeed_pci_bridge_no_alias(struct pci_dev *pdev) 4650 { 4651 pdev->dev_flags |= PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS; 4652 } 4653 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASPEED, 0x1150, quirk_aspeed_pci_bridge_no_alias); 4654 4655 /* 4656 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 4657 * class code. Fix it. 4658 */ 4659 static void quirk_tw686x_class(struct pci_dev *pdev) 4660 { 4661 u32 class = pdev->class; 4662 4663 /* Use "Multimedia controller" class */ 4664 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4665 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4666 class, pdev->class); 4667 } 4668 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4669 quirk_tw686x_class); 4670 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4671 quirk_tw686x_class); 4672 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4673 quirk_tw686x_class); 4674 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4675 quirk_tw686x_class); 4676 4677 /* 4678 * Some devices have problems with Transaction Layer Packets with the Relaxed 4679 * Ordering Attribute set. Such devices should mark themselves and other 4680 * device drivers should check before sending TLPs with RO set. 4681 */ 4682 static void quirk_relaxedordering_disable(struct pci_dev *dev) 4683 { 4684 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4685 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4686 } 4687 4688 /* 4689 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4690 * Complex have a Flow Control Credit issue which can cause performance 4691 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4692 */ 4693 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4694 quirk_relaxedordering_disable); 4695 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4696 quirk_relaxedordering_disable); 4697 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4698 quirk_relaxedordering_disable); 4699 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4700 quirk_relaxedordering_disable); 4701 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4702 quirk_relaxedordering_disable); 4703 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4704 quirk_relaxedordering_disable); 4705 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4706 quirk_relaxedordering_disable); 4707 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4708 quirk_relaxedordering_disable); 4709 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4710 quirk_relaxedordering_disable); 4711 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4712 quirk_relaxedordering_disable); 4713 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4714 quirk_relaxedordering_disable); 4715 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4716 quirk_relaxedordering_disable); 4717 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4718 quirk_relaxedordering_disable); 4719 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4720 quirk_relaxedordering_disable); 4721 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4722 quirk_relaxedordering_disable); 4723 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4724 quirk_relaxedordering_disable); 4725 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4726 quirk_relaxedordering_disable); 4727 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4728 quirk_relaxedordering_disable); 4729 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4730 quirk_relaxedordering_disable); 4731 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4732 quirk_relaxedordering_disable); 4733 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4734 quirk_relaxedordering_disable); 4735 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4736 quirk_relaxedordering_disable); 4737 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4738 quirk_relaxedordering_disable); 4739 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4740 quirk_relaxedordering_disable); 4741 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4742 quirk_relaxedordering_disable); 4743 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4744 quirk_relaxedordering_disable); 4745 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4746 quirk_relaxedordering_disable); 4747 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4748 quirk_relaxedordering_disable); 4749 4750 /* 4751 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 4752 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4753 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4754 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4755 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4756 * November 10, 2010). As a result, on this platform we can't use Relaxed 4757 * Ordering for Upstream TLPs. 4758 */ 4759 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4760 quirk_relaxedordering_disable); 4761 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4762 quirk_relaxedordering_disable); 4763 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4764 quirk_relaxedordering_disable); 4765 4766 /* 4767 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4768 * values for the Attribute as were supplied in the header of the 4769 * corresponding Request, except as explicitly allowed when IDO is used." 4770 * 4771 * If a non-compliant device generates a completion with a different 4772 * attribute than the request, the receiver may accept it (which itself 4773 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4774 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4775 * device access timeout. 4776 * 4777 * If the non-compliant device generates completions with zero attributes 4778 * (instead of copying the attributes from the request), we can work around 4779 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4780 * upstream devices so they always generate requests with zero attributes. 4781 * 4782 * This affects other devices under the same Root Port, but since these 4783 * attributes are performance hints, there should be no functional problem. 4784 * 4785 * Note that Configuration Space accesses are never supposed to have TLP 4786 * Attributes, so we're safe waiting till after any Configuration Space 4787 * accesses to do the Root Port fixup. 4788 */ 4789 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4790 { 4791 struct pci_dev *root_port = pcie_find_root_port(pdev); 4792 4793 if (!root_port) { 4794 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4795 return; 4796 } 4797 4798 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4799 dev_name(&pdev->dev)); 4800 pcie_capability_clear_word(root_port, PCI_EXP_DEVCTL, 4801 PCI_EXP_DEVCTL_RELAX_EN | 4802 PCI_EXP_DEVCTL_NOSNOOP_EN); 4803 } 4804 4805 /* 4806 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4807 * Completion it generates. 4808 */ 4809 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4810 { 4811 /* 4812 * This mask/compare operation selects for Physical Function 4 on a 4813 * T5. We only need to fix up the Root Port once for any of the 4814 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4815 * 0x54xx so we use that one. 4816 */ 4817 if ((pdev->device & 0xff00) == 0x5400) 4818 quirk_disable_root_port_attributes(pdev); 4819 } 4820 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4821 quirk_chelsio_T5_disable_root_port_attributes); 4822 4823 /* 4824 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided 4825 * by a device 4826 * @acs_ctrl_req: Bitmask of desired ACS controls 4827 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by 4828 * the hardware design 4829 * 4830 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included 4831 * in @acs_ctrl_ena, i.e., the device provides all the access controls the 4832 * caller desires. Return 0 otherwise. 4833 */ 4834 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena) 4835 { 4836 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req) 4837 return 1; 4838 return 0; 4839 } 4840 4841 /* 4842 * AMD has indicated that the devices below do not support peer-to-peer 4843 * in any system where they are found in the southbridge with an AMD 4844 * IOMMU in the system. Multifunction devices that do not support 4845 * peer-to-peer between functions can claim to support a subset of ACS. 4846 * Such devices effectively enable request redirect (RR) and completion 4847 * redirect (CR) since all transactions are redirected to the upstream 4848 * root complex. 4849 * 4850 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/ 4851 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/ 4852 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/ 4853 * 4854 * 1002:4385 SBx00 SMBus Controller 4855 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4856 * 1002:4383 SBx00 Azalia (Intel HDA) 4857 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4858 * 1002:4384 SBx00 PCI to PCI Bridge 4859 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4860 * 4861 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4862 * 4863 * 1022:780f [AMD] FCH PCI Bridge 4864 * 1022:7809 [AMD] FCH USB OHCI Controller 4865 */ 4866 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4867 { 4868 #ifdef CONFIG_ACPI 4869 struct acpi_table_header *header = NULL; 4870 acpi_status status; 4871 4872 /* Targeting multifunction devices on the SB (appears on root bus) */ 4873 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4874 return -ENODEV; 4875 4876 /* The IVRS table describes the AMD IOMMU */ 4877 status = acpi_get_table("IVRS", 0, &header); 4878 if (ACPI_FAILURE(status)) 4879 return -ENODEV; 4880 4881 acpi_put_table(header); 4882 4883 /* Filter out flags not applicable to multifunction */ 4884 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4885 4886 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR); 4887 #else 4888 return -ENODEV; 4889 #endif 4890 } 4891 4892 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4893 { 4894 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4895 return false; 4896 4897 switch (dev->device) { 4898 /* 4899 * Effectively selects all downstream ports for whole ThunderX1 4900 * (which represents 8 SoCs). 4901 */ 4902 case 0xa000 ... 0xa7ff: /* ThunderX1 */ 4903 case 0xaf84: /* ThunderX2 */ 4904 case 0xb884: /* ThunderX3 */ 4905 return true; 4906 default: 4907 return false; 4908 } 4909 } 4910 4911 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4912 { 4913 if (!pci_quirk_cavium_acs_match(dev)) 4914 return -ENOTTY; 4915 4916 /* 4917 * Cavium Root Ports don't advertise an ACS capability. However, 4918 * the RTL internally implements similar protection as if ACS had 4919 * Source Validation, Request Redirection, Completion Redirection, 4920 * and Upstream Forwarding features enabled. Assert that the 4921 * hardware implements and enables equivalent ACS functionality for 4922 * these flags. 4923 */ 4924 return pci_acs_ctrl_enabled(acs_flags, 4925 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4926 } 4927 4928 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4929 { 4930 /* 4931 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4932 * transactions with others, allowing masking out these bits as if they 4933 * were unimplemented in the ACS capability. 4934 */ 4935 return pci_acs_ctrl_enabled(acs_flags, 4936 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4937 } 4938 4939 /* 4940 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability. 4941 * But the implementation could block peer-to-peer transactions between them 4942 * and provide ACS-like functionality. 4943 */ 4944 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) 4945 { 4946 if (!pci_is_pcie(dev) || 4947 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && 4948 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) 4949 return -ENOTTY; 4950 4951 /* 4952 * Future Zhaoxin Root Ports and Switch Downstream Ports will 4953 * implement ACS capability in accordance with the PCIe Spec. 4954 */ 4955 switch (dev->device) { 4956 case 0x0710 ... 0x071e: 4957 case 0x0721: 4958 case 0x0723 ... 0x0752: 4959 return pci_acs_ctrl_enabled(acs_flags, 4960 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4961 } 4962 4963 return false; 4964 } 4965 4966 /* 4967 * Many Intel PCH Root Ports do provide ACS-like features to disable peer 4968 * transactions and validate bus numbers in requests, but do not provide an 4969 * actual PCIe ACS capability. This is the list of device IDs known to fall 4970 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4971 */ 4972 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4973 /* Ibexpeak PCH */ 4974 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4975 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4976 /* Cougarpoint PCH */ 4977 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4978 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4979 /* Pantherpoint PCH */ 4980 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4981 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4982 /* Lynxpoint-H PCH */ 4983 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4984 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4985 /* Lynxpoint-LP PCH */ 4986 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4987 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4988 /* Wildcat PCH */ 4989 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4990 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4991 /* Patsburg (X79) PCH */ 4992 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4993 /* Wellsburg (X99) PCH */ 4994 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4995 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4996 /* Lynx Point (9 series) PCH */ 4997 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4998 }; 4999 5000 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 5001 { 5002 int i; 5003 5004 /* Filter out a few obvious non-matches first */ 5005 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 5006 return false; 5007 5008 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 5009 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 5010 return true; 5011 5012 return false; 5013 } 5014 5015 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 5016 { 5017 if (!pci_quirk_intel_pch_acs_match(dev)) 5018 return -ENOTTY; 5019 5020 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) 5021 return pci_acs_ctrl_enabled(acs_flags, 5022 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5023 5024 return pci_acs_ctrl_enabled(acs_flags, 0); 5025 } 5026 5027 /* 5028 * These QCOM Root Ports do provide ACS-like features to disable peer 5029 * transactions and validate bus numbers in requests, but do not provide an 5030 * actual PCIe ACS capability. Hardware supports source validation but it 5031 * will report the issue as Completer Abort instead of ACS Violation. 5032 * Hardware doesn't support peer-to-peer and each Root Port is a Root 5033 * Complex with unique segment numbers. It is not possible for one Root 5034 * Port to pass traffic to another Root Port. All PCIe transactions are 5035 * terminated inside the Root Port. 5036 */ 5037 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 5038 { 5039 return pci_acs_ctrl_enabled(acs_flags, 5040 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5041 } 5042 5043 /* 5044 * Each of these NXP Root Ports is in a Root Complex with a unique segment 5045 * number and does provide isolation features to disable peer transactions 5046 * and validate bus numbers in requests, but does not provide an ACS 5047 * capability. 5048 */ 5049 static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) 5050 { 5051 return pci_acs_ctrl_enabled(acs_flags, 5052 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5053 } 5054 5055 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) 5056 { 5057 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 5058 return -ENOTTY; 5059 5060 /* 5061 * Amazon's Annapurna Labs root ports don't include an ACS capability, 5062 * but do include ACS-like functionality. The hardware doesn't support 5063 * peer-to-peer transactions via the root port and each has a unique 5064 * segment number. 5065 * 5066 * Additionally, the root ports cannot send traffic to each other. 5067 */ 5068 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5069 5070 return acs_flags ? 0 : 1; 5071 } 5072 5073 /* 5074 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 5075 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 5076 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 5077 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 5078 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 5079 * control register is at offset 8 instead of 6 and we should probably use 5080 * dword accesses to them. This applies to the following PCI Device IDs, as 5081 * found in volume 1 of the datasheet[2]: 5082 * 5083 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 5084 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 5085 * 5086 * N.B. This doesn't fix what lspci shows. 5087 * 5088 * The 100 series chipset specification update includes this as errata #23[3]. 5089 * 5090 * The 200 series chipset (Union Point) has the same bug according to the 5091 * specification update (Intel 200 Series Chipset Family Platform Controller 5092 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 5093 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 5094 * chipset include: 5095 * 5096 * 0xa290-0xa29f PCI Express Root port #{0-16} 5097 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 5098 * 5099 * Mobile chipsets are also affected, 7th & 8th Generation 5100 * Specification update confirms ACS errata 22, status no fix: (7th Generation 5101 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 5102 * Processor Family I/O for U Quad Core Platforms Specification Update, 5103 * August 2017, Revision 002, Document#: 334660-002)[6] 5104 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 5105 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 5106 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 5107 * 5108 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 5109 * 5110 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 5111 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 5112 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 5113 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 5114 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 5115 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 5116 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 5117 */ 5118 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 5119 { 5120 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 5121 return false; 5122 5123 switch (dev->device) { 5124 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 5125 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 5126 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 5127 return true; 5128 } 5129 5130 return false; 5131 } 5132 5133 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 5134 5135 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 5136 { 5137 int pos; 5138 u32 cap, ctrl; 5139 5140 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5141 return -ENOTTY; 5142 5143 pos = dev->acs_cap; 5144 if (!pos) 5145 return -ENOTTY; 5146 5147 /* see pci_acs_flags_enabled() */ 5148 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5149 acs_flags &= (cap | PCI_ACS_EC); 5150 5151 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5152 5153 return pci_acs_ctrl_enabled(acs_flags, ctrl); 5154 } 5155 5156 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 5157 { 5158 /* 5159 * SV, TB, and UF are not relevant to multifunction endpoints. 5160 * 5161 * Multifunction devices are only required to implement RR, CR, and DT 5162 * in their ACS capability if they support peer-to-peer transactions. 5163 * Devices matching this quirk have been verified by the vendor to not 5164 * perform peer-to-peer with other functions, allowing us to mask out 5165 * these bits as if they were unimplemented in the ACS capability. 5166 */ 5167 return pci_acs_ctrl_enabled(acs_flags, 5168 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 5169 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 5170 } 5171 5172 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) 5173 { 5174 /* 5175 * Intel RCiEP's are required to allow p2p only on translated 5176 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, 5177 * "Root-Complex Peer to Peer Considerations". 5178 */ 5179 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) 5180 return -ENOTTY; 5181 5182 return pci_acs_ctrl_enabled(acs_flags, 5183 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5184 } 5185 5186 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) 5187 { 5188 /* 5189 * iProc PAXB Root Ports don't advertise an ACS capability, but 5190 * they do not allow peer-to-peer transactions between Root Ports. 5191 * Allow each Root Port to be in a separate IOMMU group by masking 5192 * SV/RR/CR/UF bits. 5193 */ 5194 return pci_acs_ctrl_enabled(acs_flags, 5195 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5196 } 5197 5198 static int pci_quirk_loongson_acs(struct pci_dev *dev, u16 acs_flags) 5199 { 5200 /* 5201 * Loongson PCIe Root Ports don't advertise an ACS capability, but 5202 * they do not allow peer-to-peer transactions between Root Ports. 5203 * Allow each Root Port to be in a separate IOMMU group by masking 5204 * SV/RR/CR/UF bits. 5205 */ 5206 return pci_acs_ctrl_enabled(acs_flags, 5207 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5208 } 5209 5210 /* 5211 * Wangxun 40G/25G/10G/1G NICs have no ACS capability, but on 5212 * multi-function devices, the hardware isolates the functions by 5213 * directing all peer-to-peer traffic upstream as though PCI_ACS_RR and 5214 * PCI_ACS_CR were set. 5215 * SFxxx 1G NICs(em). 5216 * RP1000/RP2000 10G NICs(sp). 5217 * FF5xxx 40G/25G/10G NICs(aml). 5218 */ 5219 static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags) 5220 { 5221 switch (dev->device) { 5222 case 0x0100 ... 0x010F: /* EM */ 5223 case 0x1001: case 0x2001: /* SP */ 5224 case 0x5010: case 0x5025: case 0x5040: /* AML */ 5225 case 0x5110: case 0x5125: case 0x5140: /* AML */ 5226 return pci_acs_ctrl_enabled(acs_flags, 5227 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5228 } 5229 5230 return false; 5231 } 5232 5233 static const struct pci_dev_acs_enabled { 5234 u16 vendor; 5235 u16 device; 5236 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 5237 } pci_dev_acs_enabled[] = { 5238 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 5239 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 5240 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 5241 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 5242 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 5243 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 5244 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 5245 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 5246 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 5247 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 5248 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 5249 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 5250 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 5251 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 5252 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 5253 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 5254 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 5255 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 5256 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 5257 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 5258 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 5259 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 5260 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 5261 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 5262 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 5263 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 5264 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 5265 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 5266 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 5267 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 5268 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 5269 /* 82580 */ 5270 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 5271 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 5272 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 5273 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 5274 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 5275 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 5276 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 5277 /* 82576 */ 5278 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 5279 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 5280 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 5281 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 5282 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 5283 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 5284 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 5285 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 5286 /* 82575 */ 5287 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 5288 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 5289 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 5290 /* I350 */ 5291 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 5292 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 5293 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 5294 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 5295 /* 82571 (Quads omitted due to non-ACS switch) */ 5296 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 5297 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 5298 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 5299 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 5300 /* I219 */ 5301 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 5302 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 5303 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, 5304 /* QCOM QDF2xxx root ports */ 5305 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 5306 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 5307 /* QCOM SA8775P root port */ 5308 { PCI_VENDOR_ID_QCOM, 0x0115, pci_quirk_qcom_rp_acs }, 5309 /* QCOM Hamoa root port */ 5310 { PCI_VENDOR_ID_QCOM, 0x0111, pci_quirk_qcom_rp_acs }, 5311 /* QCOM Glymur root port */ 5312 { PCI_VENDOR_ID_QCOM, 0x0120, pci_quirk_qcom_rp_acs }, 5313 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 5314 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 5315 /* Intel PCH root ports */ 5316 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 5317 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 5318 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 5319 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 5320 /* Cavium ThunderX */ 5321 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 5322 /* Cavium multi-function devices */ 5323 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs }, 5324 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs }, 5325 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs }, 5326 /* APM X-Gene */ 5327 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 5328 /* Ampere Computing */ 5329 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 5330 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 5331 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 5332 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 5333 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 5334 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 5335 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 5336 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 5337 /* Broadcom multi-function device */ 5338 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, 5339 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs }, 5340 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs }, 5341 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs }, 5342 { PCI_VENDOR_ID_BROADCOM, 0x1760, pci_quirk_mf_endpoint_acs }, 5343 { PCI_VENDOR_ID_BROADCOM, 0x1761, pci_quirk_mf_endpoint_acs }, 5344 { PCI_VENDOR_ID_BROADCOM, 0x1762, pci_quirk_mf_endpoint_acs }, 5345 { PCI_VENDOR_ID_BROADCOM, 0x1763, pci_quirk_mf_endpoint_acs }, 5346 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, 5347 /* Loongson PCIe Root Ports */ 5348 { PCI_VENDOR_ID_LOONGSON, 0x3C09, pci_quirk_loongson_acs }, 5349 { PCI_VENDOR_ID_LOONGSON, 0x3C19, pci_quirk_loongson_acs }, 5350 { PCI_VENDOR_ID_LOONGSON, 0x3C29, pci_quirk_loongson_acs }, 5351 { PCI_VENDOR_ID_LOONGSON, 0x7A09, pci_quirk_loongson_acs }, 5352 { PCI_VENDOR_ID_LOONGSON, 0x7A19, pci_quirk_loongson_acs }, 5353 { PCI_VENDOR_ID_LOONGSON, 0x7A29, pci_quirk_loongson_acs }, 5354 { PCI_VENDOR_ID_LOONGSON, 0x7A39, pci_quirk_loongson_acs }, 5355 { PCI_VENDOR_ID_LOONGSON, 0x7A49, pci_quirk_loongson_acs }, 5356 { PCI_VENDOR_ID_LOONGSON, 0x7A59, pci_quirk_loongson_acs }, 5357 { PCI_VENDOR_ID_LOONGSON, 0x7A69, pci_quirk_loongson_acs }, 5358 /* Amazon Annapurna Labs */ 5359 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, 5360 /* Zhaoxin multi-function devices */ 5361 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs }, 5362 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs }, 5363 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs }, 5364 /* NXP root ports, xx=16, 12, or 08 cores */ 5365 /* LX2xx0A : without security features + CAN-FD */ 5366 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs }, 5367 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs }, 5368 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs }, 5369 /* LX2xx0C : security features + CAN-FD */ 5370 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs }, 5371 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs }, 5372 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs }, 5373 /* LX2xx0E : security features + CAN */ 5374 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs }, 5375 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs }, 5376 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs }, 5377 /* LX2xx0N : without security features + CAN */ 5378 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs }, 5379 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs }, 5380 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs }, 5381 /* LX2xx2A : without security features + CAN-FD */ 5382 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs }, 5383 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs }, 5384 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs }, 5385 /* LX2xx2C : security features + CAN-FD */ 5386 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs }, 5387 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs }, 5388 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs }, 5389 /* LX2xx2E : security features + CAN */ 5390 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs }, 5391 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs }, 5392 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs }, 5393 /* LX2xx2N : without security features + CAN */ 5394 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs }, 5395 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs }, 5396 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs }, 5397 /* Zhaoxin Root/Downstream Ports */ 5398 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs }, 5399 /* Wangxun nics */ 5400 { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs }, 5401 { 0 } 5402 }; 5403 5404 /* 5405 * pci_dev_specific_acs_enabled - check whether device provides ACS controls 5406 * @dev: PCI device 5407 * @acs_flags: Bitmask of desired ACS controls 5408 * 5409 * Returns: 5410 * -ENOTTY: No quirk applies to this device; we can't tell whether the 5411 * device provides the desired controls 5412 * 0: Device does not provide all the desired controls 5413 * >0: Device provides all the controls in @acs_flags 5414 */ 5415 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 5416 { 5417 const struct pci_dev_acs_enabled *i; 5418 int ret; 5419 5420 /* 5421 * Allow devices that do not expose standard PCIe ACS capabilities 5422 * or control to indicate their support here. Multi-function express 5423 * devices which do not allow internal peer-to-peer between functions, 5424 * but do not implement PCIe ACS may wish to return true here. 5425 */ 5426 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 5427 if ((i->vendor == dev->vendor || 5428 i->vendor == (u16)PCI_ANY_ID) && 5429 (i->device == dev->device || 5430 i->device == (u16)PCI_ANY_ID)) { 5431 ret = i->acs_enabled(dev, acs_flags); 5432 if (ret >= 0) 5433 return ret; 5434 } 5435 } 5436 5437 return -ENOTTY; 5438 } 5439 5440 /* Config space offset of Root Complex Base Address register */ 5441 #define INTEL_LPC_RCBA_REG 0xf0 5442 /* 31:14 RCBA address */ 5443 #define INTEL_LPC_RCBA_MASK 0xffffc000 5444 /* RCBA Enable */ 5445 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 5446 5447 /* Backbone Scratch Pad Register */ 5448 #define INTEL_BSPR_REG 0x1104 5449 /* Backbone Peer Non-Posted Disable */ 5450 #define INTEL_BSPR_REG_BPNPD (1 << 8) 5451 /* Backbone Peer Posted Disable */ 5452 #define INTEL_BSPR_REG_BPPD (1 << 9) 5453 5454 /* Upstream Peer Decode Configuration Register */ 5455 #define INTEL_UPDCR_REG 0x1014 5456 /* 5:0 Peer Decode Enable bits */ 5457 #define INTEL_UPDCR_REG_MASK 0x3f 5458 5459 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 5460 { 5461 u32 rcba, bspr, updcr; 5462 void __iomem *rcba_mem; 5463 5464 /* 5465 * Read the RCBA register from the LPC (D31:F0). PCH root ports 5466 * are D28:F* and therefore get probed before LPC, thus we can't 5467 * use pci_get_slot()/pci_read_config_dword() here. 5468 */ 5469 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 5470 INTEL_LPC_RCBA_REG, &rcba); 5471 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 5472 return -EINVAL; 5473 5474 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK, 5475 PAGE_ALIGN(INTEL_UPDCR_REG)); 5476 if (!rcba_mem) 5477 return -ENOMEM; 5478 5479 /* 5480 * The BSPR can disallow peer cycles, but it's set by soft strap and 5481 * therefore read-only. If both posted and non-posted peer cycles are 5482 * disallowed, we're ok. If either are allowed, then we need to use 5483 * the UPDCR to disable peer decodes for each port. This provides the 5484 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5485 */ 5486 bspr = readl(rcba_mem + INTEL_BSPR_REG); 5487 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 5488 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 5489 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 5490 if (updcr & INTEL_UPDCR_REG_MASK) { 5491 pci_info(dev, "Disabling UPDCR peer decodes\n"); 5492 updcr &= ~INTEL_UPDCR_REG_MASK; 5493 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 5494 } 5495 } 5496 5497 iounmap(rcba_mem); 5498 return 0; 5499 } 5500 5501 /* Miscellaneous Port Configuration register */ 5502 #define INTEL_MPC_REG 0xd8 5503 /* MPC: Invalid Receive Bus Number Check Enable */ 5504 #define INTEL_MPC_REG_IRBNCE (1 << 26) 5505 5506 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 5507 { 5508 u32 mpc; 5509 5510 /* 5511 * When enabled, the IRBNCE bit of the MPC register enables the 5512 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 5513 * ensures that requester IDs fall within the bus number range 5514 * of the bridge. Enable if not already. 5515 */ 5516 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 5517 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 5518 pci_info(dev, "Enabling MPC IRBNCE\n"); 5519 mpc |= INTEL_MPC_REG_IRBNCE; 5520 pci_write_config_dword(dev, INTEL_MPC_REG, mpc); 5521 } 5522 } 5523 5524 /* 5525 * Currently this quirk does the equivalent of 5526 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5527 * 5528 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB, 5529 * if dev->external_facing || dev->untrusted 5530 */ 5531 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 5532 { 5533 if (!pci_quirk_intel_pch_acs_match(dev)) 5534 return -ENOTTY; 5535 5536 if (pci_quirk_enable_intel_lpc_acs(dev)) { 5537 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 5538 return 0; 5539 } 5540 5541 pci_quirk_enable_intel_rp_mpc_acs(dev); 5542 5543 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 5544 5545 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 5546 5547 return 0; 5548 } 5549 5550 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 5551 { 5552 int pos; 5553 u32 cap, ctrl; 5554 5555 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5556 return -ENOTTY; 5557 5558 pos = dev->acs_cap; 5559 if (!pos) 5560 return -ENOTTY; 5561 5562 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5563 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5564 5565 ctrl |= (cap & PCI_ACS_SV); 5566 ctrl |= (cap & PCI_ACS_RR); 5567 ctrl |= (cap & PCI_ACS_CR); 5568 ctrl |= (cap & PCI_ACS_UF); 5569 5570 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) 5571 ctrl |= (cap & PCI_ACS_TB); 5572 5573 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5574 5575 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 5576 5577 return 0; 5578 } 5579 5580 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) 5581 { 5582 int pos; 5583 u32 cap, ctrl; 5584 5585 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5586 return -ENOTTY; 5587 5588 pos = dev->acs_cap; 5589 if (!pos) 5590 return -ENOTTY; 5591 5592 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5593 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5594 5595 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); 5596 5597 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5598 5599 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); 5600 5601 return 0; 5602 } 5603 5604 static const struct pci_dev_acs_ops { 5605 u16 vendor; 5606 u16 device; 5607 int (*enable_acs)(struct pci_dev *dev); 5608 int (*disable_acs_redir)(struct pci_dev *dev); 5609 } pci_dev_acs_ops[] = { 5610 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5611 .enable_acs = pci_quirk_enable_intel_pch_acs, 5612 }, 5613 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5614 .enable_acs = pci_quirk_enable_intel_spt_pch_acs, 5615 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, 5616 }, 5617 }; 5618 5619 int pci_dev_specific_enable_acs(struct pci_dev *dev) 5620 { 5621 const struct pci_dev_acs_ops *p; 5622 int i, ret; 5623 5624 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5625 p = &pci_dev_acs_ops[i]; 5626 if ((p->vendor == dev->vendor || 5627 p->vendor == (u16)PCI_ANY_ID) && 5628 (p->device == dev->device || 5629 p->device == (u16)PCI_ANY_ID) && 5630 p->enable_acs) { 5631 ret = p->enable_acs(dev); 5632 if (ret >= 0) 5633 return ret; 5634 } 5635 } 5636 5637 return -ENOTTY; 5638 } 5639 5640 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 5641 { 5642 const struct pci_dev_acs_ops *p; 5643 int i, ret; 5644 5645 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5646 p = &pci_dev_acs_ops[i]; 5647 if ((p->vendor == dev->vendor || 5648 p->vendor == (u16)PCI_ANY_ID) && 5649 (p->device == dev->device || 5650 p->device == (u16)PCI_ANY_ID) && 5651 p->disable_acs_redir) { 5652 ret = p->disable_acs_redir(dev); 5653 if (ret >= 0) 5654 return ret; 5655 } 5656 } 5657 5658 return -ENOTTY; 5659 } 5660 5661 /* 5662 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 5663 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 5664 * Next Capability pointer in the MSI Capability Structure should point to 5665 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 5666 * the list. 5667 */ 5668 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 5669 { 5670 int pos, i = 0, ret; 5671 u8 next_cap; 5672 u16 reg16, *cap; 5673 struct pci_cap_saved_state *state; 5674 5675 /* Bail if the hardware bug is fixed */ 5676 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 5677 return; 5678 5679 /* Bail if MSI Capability Structure is not found for some reason */ 5680 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 5681 if (!pos) 5682 return; 5683 5684 /* 5685 * Bail if Next Capability pointer in the MSI Capability Structure 5686 * is not the expected incorrect 0x00. 5687 */ 5688 pci_read_config_byte(pdev, pos + 1, &next_cap); 5689 if (next_cap) 5690 return; 5691 5692 /* 5693 * PCIe Capability Structure is expected to be at 0x50 and should 5694 * terminate the list (Next Capability pointer is 0x00). Verify 5695 * Capability Id and Next Capability pointer is as expected. 5696 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 5697 * to correctly set kernel data structures which have already been 5698 * set incorrectly due to the hardware bug. 5699 */ 5700 pos = 0x50; 5701 pci_read_config_word(pdev, pos, ®16); 5702 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 5703 u32 status; 5704 #ifndef PCI_EXP_SAVE_REGS 5705 #define PCI_EXP_SAVE_REGS 7 5706 #endif 5707 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 5708 5709 pdev->pcie_cap = pos; 5710 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 5711 pdev->pcie_flags_reg = reg16; 5712 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 5713 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 5714 5715 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 5716 ret = pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status); 5717 if ((ret != PCIBIOS_SUCCESSFUL) || (PCI_POSSIBLE_ERROR(status))) 5718 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 5719 5720 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 5721 return; 5722 5723 /* Save PCIe cap */ 5724 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 5725 if (!state) 5726 return; 5727 5728 state->cap.cap_nr = PCI_CAP_ID_EXP; 5729 state->cap.cap_extended = 0; 5730 state->cap.size = size; 5731 cap = (u16 *)&state->cap.data[0]; 5732 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 5733 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 5734 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 5735 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 5736 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 5737 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 5738 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 5739 hlist_add_head(&state->next, &pdev->saved_cap_space); 5740 } 5741 } 5742 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 5743 5744 /* 5745 * FLR may cause the following to devices to hang: 5746 * 5747 * AMD Starship/Matisse HD Audio Controller 0x1487 5748 * AMD Starship USB 3.0 Host Controller 0x148c 5749 * AMD Matisse USB 3.0 Host Controller 0x149c 5750 * AMD Neural Processing Unit 0x1502 0x17f0 5751 * Intel 82579LM Gigabit Ethernet Controller 0x1502 5752 * Intel 82579V Gigabit Ethernet Controller 0x1503 5753 * Intel DG1 Discrete Graphics Adapter 0x4905 5754 * Mediatek MT7922 802.11ax PCI Express Wireless Network Adapter 5755 * Mediatek MT7925 802.11be PCI Express Wireless Network Adapter 5756 */ 5757 static void quirk_no_flr(struct pci_dev *dev) 5758 { 5759 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 5760 } 5761 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); 5762 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); 5763 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); 5764 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); 5765 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1502, quirk_no_flr); 5766 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x17f0, quirk_no_flr); 5767 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); 5768 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); 5769 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x4905, quirk_no_flr); 5770 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MEDIATEK, 0x0616, quirk_no_flr); 5771 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MEDIATEK, 0x7925, quirk_no_flr); 5772 5773 /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */ 5774 static void quirk_no_flr_snet(struct pci_dev *dev) 5775 { 5776 if (dev->revision == 0x1) 5777 quirk_no_flr(dev); 5778 } 5779 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet); 5780 5781 /* Some Samsung SSDs advertise Immediate Readiness but aren't ready after FLR */ 5782 static void quirk_no_imm_ready(struct pci_dev *dev) 5783 { 5784 if (!dev->imm_ready) 5785 return; 5786 5787 pci_info(dev, "Ignoring incorrectly advertised Immediate Readiness support\n"); 5788 dev->imm_ready = 0; 5789 } 5790 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa80c, quirk_no_imm_ready); 5791 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa80d, quirk_no_imm_ready); 5792 5793 static void quirk_no_ext_tags(struct pci_dev *pdev) 5794 { 5795 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 5796 5797 if (!bridge) 5798 return; 5799 5800 bridge->no_ext_tags = 1; 5801 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 5802 5803 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 5804 } 5805 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags); 5806 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1005, quirk_no_ext_tags); 5807 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 5808 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 5809 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 5810 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 5811 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 5812 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 5813 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 5814 5815 #ifdef CONFIG_PCI_ATS 5816 static void quirk_no_ats(struct pci_dev *pdev) 5817 { 5818 pci_info(pdev, "disabling ATS\n"); 5819 pdev->ats_cap = 0; 5820 } 5821 5822 /* 5823 * Some devices require additional driver setup to enable ATS. Don't use 5824 * ATS for those devices as ATS will be enabled before the driver has had a 5825 * chance to load and configure the device. 5826 */ 5827 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) 5828 { 5829 if (pdev->device == 0x15d8) { 5830 if (pdev->revision == 0xcf && 5831 pdev->subsystem_vendor == 0xea50 && 5832 (pdev->subsystem_device == 0xce19 || 5833 pdev->subsystem_device == 0xcc10 || 5834 pdev->subsystem_device == 0xcc08)) 5835 quirk_no_ats(pdev); 5836 } else { 5837 quirk_no_ats(pdev); 5838 } 5839 } 5840 5841 /* AMD Stoney platform GPU */ 5842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); 5843 /* AMD Iceland dGPU */ 5844 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); 5845 /* AMD Navi10 dGPU */ 5846 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats); 5847 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); 5848 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats); 5849 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats); 5850 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats); 5851 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats); 5852 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats); 5853 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats); 5854 /* AMD Navi14 dGPU */ 5855 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); 5856 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats); 5857 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats); 5858 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats); 5859 /* AMD Raven platform iGPU */ 5860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); 5861 5862 /* 5863 * Intel IPU E2000 revisions before C0 implement incorrect endianness 5864 * in ATS Invalidate Request message body. Disable ATS for those devices. 5865 */ 5866 static void quirk_intel_e2000_no_ats(struct pci_dev *pdev) 5867 { 5868 if (pdev->revision < 0x20) 5869 quirk_no_ats(pdev); 5870 } 5871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats); 5872 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats); 5873 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats); 5874 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats); 5875 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats); 5876 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats); 5877 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats); 5878 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats); 5879 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats); 5880 5881 static bool quirk_nvidia_gpu_ats_required(struct pci_dev *pdev) 5882 { 5883 switch (pdev->device) { 5884 case 0x2e00 ... 0x2e3f: /* GB20B */ 5885 return true; 5886 } 5887 return false; 5888 } 5889 5890 static const struct pci_dev_ats_required { 5891 u16 vendor; 5892 u16 device; 5893 bool (*ats_required)(struct pci_dev *dev); 5894 } pci_dev_ats_required[] = { 5895 /* NVIDIA GPUs */ 5896 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, quirk_nvidia_gpu_ats_required }, 5897 /* NVIDIA CX10 Family NVlink-C2C */ 5898 { PCI_VENDOR_ID_MELLANOX, 0x2101, NULL }, 5899 { 0 } 5900 }; 5901 5902 /* 5903 * Some NVIDIA devices do not implement CXL config space, but present as PCIe 5904 * devices that can issue CXL-like cache operations like CXL.cache. Thus, they 5905 * require ATS to obtain host physical addresses, like pci_cxl_ats_required(). 5906 */ 5907 bool pci_dev_specific_ats_required(struct pci_dev *pdev) 5908 { 5909 const struct pci_dev_ats_required *i; 5910 5911 for (i = pci_dev_ats_required; i->vendor; i++) { 5912 if (i->vendor != pdev->vendor) 5913 continue; 5914 if (i->ats_required && i->ats_required(pdev)) 5915 return true; 5916 if (!i->ats_required && i->device == pdev->device) 5917 return true; 5918 } 5919 5920 return false; 5921 } 5922 #endif /* CONFIG_PCI_ATS */ 5923 5924 /* Freescale PCIe doesn't support MSI in RC mode */ 5925 static void quirk_fsl_no_msi(struct pci_dev *pdev) 5926 { 5927 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 5928 pdev->no_msi = 1; 5929 } 5930 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 5931 5932 /* 5933 * Although not allowed by the spec, some multi-function devices have 5934 * dependencies of one function (consumer) on another (supplier). For the 5935 * consumer to work in D0, the supplier must also be in D0. Create a 5936 * device link from the consumer to the supplier to enforce this 5937 * dependency. Runtime PM is allowed by default on the consumer to prevent 5938 * it from permanently keeping the supplier awake. 5939 */ 5940 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer, 5941 unsigned int supplier, unsigned int class, 5942 unsigned int class_shift) 5943 { 5944 struct pci_dev *supplier_pdev; 5945 5946 if (PCI_FUNC(pdev->devfn) != consumer) 5947 return; 5948 5949 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 5950 pdev->bus->number, 5951 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); 5952 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { 5953 pci_dev_put(supplier_pdev); 5954 return; 5955 } 5956 5957 if (device_link_add(&pdev->dev, &supplier_pdev->dev, 5958 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 5959 pci_info(pdev, "D0 power state depends on %s\n", 5960 pci_name(supplier_pdev)); 5961 else 5962 pci_err(pdev, "Cannot enforce power dependency on %s\n", 5963 pci_name(supplier_pdev)); 5964 5965 pm_runtime_allow(&pdev->dev); 5966 pci_dev_put(supplier_pdev); 5967 } 5968 5969 /* 5970 * Create device link for GPUs with integrated HDA controller for streaming 5971 * audio to attached displays. 5972 */ 5973 static void quirk_gpu_hda(struct pci_dev *hda) 5974 { 5975 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); 5976 } 5977 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5978 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5979 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 5980 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5981 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5982 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5983 5984 /* 5985 * Create device link for GPUs with integrated USB xHCI Host 5986 * controller to VGA. 5987 */ 5988 static void quirk_gpu_usb(struct pci_dev *usb) 5989 { 5990 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); 5991 } 5992 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5993 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5994 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5995 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5996 5997 /* 5998 * Create device link for GPUs with integrated Type-C UCSI controller 5999 * to VGA. Currently there is no class code defined for UCSI device over PCI 6000 * so using UNKNOWN class for now and it will be updated when UCSI 6001 * over PCI gets a class code. 6002 */ 6003 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 6004 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) 6005 { 6006 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); 6007 } 6008 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 6009 PCI_CLASS_SERIAL_UNKNOWN, 8, 6010 quirk_gpu_usb_typec_ucsi); 6011 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 6012 PCI_CLASS_SERIAL_UNKNOWN, 8, 6013 quirk_gpu_usb_typec_ucsi); 6014 6015 /* 6016 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it 6017 * disabled. https://devtalk.nvidia.com/default/topic/1024022 6018 */ 6019 static void quirk_nvidia_hda(struct pci_dev *gpu) 6020 { 6021 u8 hdr_type; 6022 u32 val; 6023 6024 /* There was no integrated HDA controller before MCP89 */ 6025 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) 6026 return; 6027 6028 /* Bit 25 at offset 0x488 enables the HDA controller */ 6029 pci_read_config_dword(gpu, 0x488, &val); 6030 if (val & BIT(25)) 6031 return; 6032 6033 pci_info(gpu, "Enabling HDA controller\n"); 6034 pci_write_config_dword(gpu, 0x488, val | BIT(25)); 6035 6036 /* The GPU becomes a multi-function device when the HDA is enabled */ 6037 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); 6038 gpu->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr_type); 6039 } 6040 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 6041 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 6042 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 6043 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 6044 6045 /* 6046 * Some IDT switches incorrectly flag an ACS Source Validation error on 6047 * completions for config read requests even though PCIe r7.0, sec 6048 * 6.12.1.1, says that completions are never affected by ACS Source 6049 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 6050 * 6051 * Item #36 - Downstream port applies ACS Source Validation to Completions 6052 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that 6053 * completions are never affected by ACS Source Validation. However, 6054 * completions received by a downstream port of the PCIe switch from a 6055 * device that has not yet captured a PCIe bus number are incorrectly 6056 * dropped by ACS Source Validation by the switch downstream port. 6057 * 6058 * The workaround suggested by IDT is to issue a config write to the 6059 * downstream device before issuing the first config read. This allows the 6060 * downstream device to capture its bus and device numbers (see PCIe r7.0, 6061 * sec 2.2.9.1), thus avoiding the ACS error on the completion. 6062 * 6063 * However, we don't know when the device is ready to accept the config 6064 * write, and the issue affects resets of the switch as well as enumeration, 6065 * so disable use of ACS SV for these devices altogether. 6066 */ 6067 void pci_disable_broken_acs_cap(struct pci_dev *pdev) 6068 { 6069 if (pdev->vendor == PCI_VENDOR_ID_IDT && 6070 (pdev->device == 0x80b5 || pdev->device == 0x8090)) { 6071 pci_info(pdev, "Disabling broken ACS SV; downstream device isolation reduced\n"); 6072 pdev->acs_capabilities &= ~PCI_ACS_SV; 6073 } 6074 } 6075 6076 /* 6077 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between 6078 * NT endpoints via the internal switch fabric. These IDs replace the 6079 * originating Requester ID TLPs which access host memory on peer NTB 6080 * ports. Therefore, all proxy IDs must be aliased to the NTB device 6081 * to permit access when the IOMMU is turned on. 6082 */ 6083 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) 6084 { 6085 void __iomem *mmio; 6086 struct ntb_info_regs __iomem *mmio_ntb; 6087 struct ntb_ctrl_regs __iomem *mmio_ctrl; 6088 u64 partition_map; 6089 u8 partition; 6090 int pp; 6091 6092 if (pci_enable_device(pdev)) { 6093 pci_err(pdev, "Cannot enable Switchtec device\n"); 6094 return; 6095 } 6096 6097 mmio = pci_iomap(pdev, 0, 0); 6098 if (mmio == NULL) { 6099 pci_disable_device(pdev); 6100 pci_err(pdev, "Cannot iomap Switchtec device\n"); 6101 return; 6102 } 6103 6104 pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); 6105 6106 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; 6107 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; 6108 6109 partition = ioread8(&mmio_ntb->partition_id); 6110 6111 partition_map = ioread32(&mmio_ntb->ep_map); 6112 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; 6113 partition_map &= ~(1ULL << partition); 6114 6115 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { 6116 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 6117 u32 table_sz = 0; 6118 int te; 6119 6120 if (!(partition_map & (1ULL << pp))) 6121 continue; 6122 6123 pci_dbg(pdev, "Processing partition %d\n", pp); 6124 6125 mmio_peer_ctrl = &mmio_ctrl[pp]; 6126 6127 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); 6128 if (!table_sz) { 6129 pci_warn(pdev, "Partition %d table_sz 0\n", pp); 6130 continue; 6131 } 6132 6133 if (table_sz > 512) { 6134 pci_warn(pdev, 6135 "Invalid Switchtec partition %d table_sz %d\n", 6136 pp, table_sz); 6137 continue; 6138 } 6139 6140 for (te = 0; te < table_sz; te++) { 6141 u32 rid_entry; 6142 u8 devfn; 6143 6144 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); 6145 devfn = (rid_entry >> 1) & 0xFF; 6146 pci_dbg(pdev, 6147 "Aliasing Partition %d Proxy ID %02x.%d\n", 6148 pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); 6149 pci_add_dma_alias(pdev, devfn, 1); 6150 } 6151 } 6152 6153 pci_iounmap(pdev, mmio); 6154 pci_disable_device(pdev); 6155 } 6156 #define SWITCHTEC_QUIRK(vid) \ 6157 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ 6158 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 6159 6160 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ 6161 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ 6162 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ 6163 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ 6164 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ 6165 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ 6166 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ 6167 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ 6168 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ 6169 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ 6170 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ 6171 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ 6172 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ 6173 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ 6174 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ 6175 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ 6176 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ 6177 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ 6178 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ 6179 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ 6180 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ 6181 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ 6182 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ 6183 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ 6184 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ 6185 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ 6186 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ 6187 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ 6188 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ 6189 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ 6190 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */ 6191 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */ 6192 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */ 6193 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */ 6194 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */ 6195 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */ 6196 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */ 6197 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */ 6198 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */ 6199 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */ 6200 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */ 6201 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */ 6202 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */ 6203 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */ 6204 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */ 6205 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */ 6206 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */ 6207 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */ 6208 SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */ 6209 SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */ 6210 SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */ 6211 SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */ 6212 SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */ 6213 SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */ 6214 SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */ 6215 SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */ 6216 SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */ 6217 SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */ 6218 SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */ 6219 SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */ 6220 SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */ 6221 SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */ 6222 SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */ 6223 SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */ 6224 SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */ 6225 SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */ 6226 SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */ 6227 SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */ 6228 SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */ 6229 SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */ 6230 SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */ 6231 SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */ 6232 SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */ 6233 SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */ 6234 SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */ 6235 SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */ 6236 SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */ 6237 SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */ 6238 SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */ 6239 SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */ 6240 SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */ 6241 SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */ 6242 SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */ 6243 SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */ 6244 SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */ 6245 SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */ 6246 SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */ 6247 SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */ 6248 SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */ 6249 SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */ 6250 SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */ 6251 SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */ 6252 SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */ 6253 6254 #define SWITCHTEC_PCI100X_QUIRK(vid) \ 6255 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_EFAR, vid, \ 6256 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 6257 SWITCHTEC_PCI100X_QUIRK(0x1001); /* PCI1001XG4 */ 6258 SWITCHTEC_PCI100X_QUIRK(0x1002); /* PCI1002XG4 */ 6259 SWITCHTEC_PCI100X_QUIRK(0x1003); /* PCI1003XG4 */ 6260 SWITCHTEC_PCI100X_QUIRK(0x1004); /* PCI1004XG4 */ 6261 SWITCHTEC_PCI100X_QUIRK(0x1005); /* PCI1005XG4 */ 6262 SWITCHTEC_PCI100X_QUIRK(0x1006); /* PCI1006XG4 */ 6263 SWITCHTEC_PCI100X_QUIRK(0x1008); /* PCI1008XG4 */ 6264 6265 6266 /* 6267 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. 6268 * These IDs are used to forward responses to the originator on the other 6269 * side of the NTB. Alias all possible IDs to the NTB to permit access when 6270 * the IOMMU is turned on. 6271 */ 6272 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) 6273 { 6274 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); 6275 /* PLX NTB may use all 256 devfns */ 6276 pci_add_dma_alias(pdev, 0, 256); 6277 } 6278 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); 6279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); 6280 6281 /* 6282 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does 6283 * not always reset the secondary Nvidia GPU between reboots if the system 6284 * is configured to use Hybrid Graphics mode. This results in the GPU 6285 * being left in whatever state it was in during the *previous* boot, which 6286 * causes spurious interrupts from the GPU, which in turn causes us to 6287 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, 6288 * this also completely breaks nouveau. 6289 * 6290 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a 6291 * clean state and fixes all these issues. 6292 * 6293 * When the machine is configured in Dedicated display mode, the issue 6294 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this 6295 * mode, so we can detect that and avoid resetting it. 6296 */ 6297 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) 6298 { 6299 void __iomem *map; 6300 int ret; 6301 6302 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || 6303 pdev->subsystem_device != 0x222e || 6304 !pci_reset_supported(pdev)) 6305 return; 6306 6307 if (pci_enable_device_mem(pdev)) 6308 return; 6309 6310 /* 6311 * Based on nvkm_device_ctor() in 6312 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 6313 */ 6314 map = pci_iomap(pdev, 0, 0x23000); 6315 if (!map) { 6316 pci_err(pdev, "Can't map MMIO space\n"); 6317 goto out_disable; 6318 } 6319 6320 /* 6321 * Make sure the GPU looks like it's been POSTed before resetting 6322 * it. 6323 */ 6324 if (ioread32(map + 0x2240c) & 0x2) { 6325 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); 6326 ret = pci_reset_bus(pdev); 6327 if (ret < 0) 6328 pci_err(pdev, "Failed to reset GPU: %d\n", ret); 6329 } 6330 6331 iounmap(map); 6332 out_disable: 6333 pci_disable_device(pdev); 6334 } 6335 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, 6336 PCI_CLASS_DISPLAY_VGA, 8, 6337 quirk_reset_lenovo_thinkpad_p50_nvgpu); 6338 6339 /* 6340 * Device [1b21:2142] 6341 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device. 6342 */ 6343 static void pci_fixup_no_d0_pme(struct pci_dev *dev) 6344 { 6345 pci_info(dev, "PME# does not work under D0, disabling it\n"); 6346 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); 6347 } 6348 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); 6349 6350 /* 6351 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] 6352 * 6353 * These devices advertise PME# support in all power states but don't 6354 * reliably assert it. 6355 * 6356 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) 6357 * says "The MSI Function is not implemented on this device" in chapters 6358 * 7.3.27, 7.3.29-7.3.31. 6359 */ 6360 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) 6361 { 6362 #ifdef CONFIG_PCI_MSI 6363 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); 6364 dev->no_msi = 1; 6365 #endif 6366 pci_info(dev, "PME# is unreliable, disabling it\n"); 6367 dev->pme_support = 0; 6368 } 6369 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); 6370 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); 6371 6372 static void apex_pci_fixup_class(struct pci_dev *pdev) 6373 { 6374 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; 6375 } 6376 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, 6377 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); 6378 6379 /* 6380 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 - 6381 * ACS P2P Request Redirect is not functional 6382 * 6383 * When ACS P2P Request Redirect is enabled and bandwidth is not balanced 6384 * between upstream and downstream ports, packets are queued in an internal 6385 * buffer until CPLD packet. The workaround is to use the switch in store and 6386 * forward mode. 6387 */ 6388 #define PI7C9X2Gxxx_MODE_REG 0x74 6389 #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0) 6390 static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev) 6391 { 6392 struct pci_dev *upstream; 6393 u16 val; 6394 6395 /* Downstream ports only */ 6396 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) 6397 return; 6398 6399 /* Check for ACS P2P Request Redirect use */ 6400 if (!pdev->acs_cap) 6401 return; 6402 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); 6403 if (!(val & PCI_ACS_RR)) 6404 return; 6405 6406 upstream = pci_upstream_bridge(pdev); 6407 if (!upstream) 6408 return; 6409 6410 pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val); 6411 if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) { 6412 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); 6413 pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val | 6414 PI7C9X2Gxxx_STORE_FORWARD_MODE); 6415 } 6416 } 6417 /* 6418 * Apply fixup on enable and on resume, in order to apply the fix up whenever 6419 * ACS configuration changes or switch mode is reset 6420 */ 6421 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404, 6422 pci_fixup_pericom_acs_store_forward); 6423 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404, 6424 pci_fixup_pericom_acs_store_forward); 6425 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304, 6426 pci_fixup_pericom_acs_store_forward); 6427 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304, 6428 pci_fixup_pericom_acs_store_forward); 6429 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303, 6430 pci_fixup_pericom_acs_store_forward); 6431 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303, 6432 pci_fixup_pericom_acs_store_forward); 6433 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0xb304, 6434 pci_fixup_pericom_acs_store_forward); 6435 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0xb304, 6436 pci_fixup_pericom_acs_store_forward); 6437 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0xb404, 6438 pci_fixup_pericom_acs_store_forward); 6439 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0xb404, 6440 pci_fixup_pericom_acs_store_forward); 6441 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2608, 6442 pci_fixup_pericom_acs_store_forward); 6443 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2608, 6444 pci_fixup_pericom_acs_store_forward); 6445 6446 static void nvidia_ion_ahci_fixup(struct pci_dev *pdev) 6447 { 6448 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; 6449 } 6450 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); 6451 6452 static void rom_bar_overlap_defect(struct pci_dev *dev) 6453 { 6454 pci_info(dev, "working around ROM BAR overlap defect\n"); 6455 dev->rom_bar_overlap = 1; 6456 } 6457 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect); 6458 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect); 6459 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect); 6460 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect); 6461 6462 #ifdef CONFIG_PCIEASPM 6463 /* 6464 * Several Intel DG2 graphics devices advertise that they can only tolerate 6465 * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1 6466 * from being enabled. But in fact these devices can tolerate unlimited 6467 * latency. Override their Device Capabilities value to allow ASPM L1 to 6468 * be enabled. 6469 */ 6470 static void aspm_l1_acceptable_latency(struct pci_dev *dev) 6471 { 6472 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); 6473 6474 if (l1_lat < 7) { 6475 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); 6476 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", 6477 l1_lat); 6478 } 6479 } 6480 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency); 6481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency); 6482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency); 6483 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency); 6484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency); 6485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency); 6486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency); 6487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency); 6488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency); 6489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency); 6490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency); 6491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency); 6492 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency); 6493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency); 6494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency); 6495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency); 6496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency); 6497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency); 6498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency); 6499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency); 6500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency); 6501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency); 6502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency); 6503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency); 6504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); 6505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); 6506 #endif 6507 6508 #ifdef CONFIG_PCIE_DPC 6509 /* 6510 * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears 6511 * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root 6512 * Ports. 6513 */ 6514 static void dpc_log_size(struct pci_dev *dev) 6515 { 6516 u16 dpc, val; 6517 6518 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); 6519 if (!dpc) 6520 return; 6521 6522 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val); 6523 if (!(val & PCI_EXP_DPC_CAP_RP_EXT)) 6524 return; 6525 6526 if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) { 6527 pci_info(dev, "Overriding RP PIO Log Size to %d\n", 6528 PCIE_STD_NUM_TLP_HEADERLOG); 6529 dev->dpc_rp_log_size = PCIE_STD_NUM_TLP_HEADERLOG; 6530 } 6531 } 6532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size); 6533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size); 6534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size); 6535 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size); 6536 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size); 6537 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size); 6538 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size); 6539 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size); 6540 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size); 6541 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size); 6542 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size); 6543 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size); 6544 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size); 6545 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); 6546 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); 6547 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); 6548 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa72f, dpc_log_size); 6549 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa73f, dpc_log_size); 6550 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size); 6551 #endif 6552 6553 /* 6554 * For a PCI device with multiple downstream devices, its driver may use 6555 * a flattened device tree to describe the downstream devices. 6556 * To overlay the flattened device tree, the PCI device and all its ancestor 6557 * devices need to have device tree nodes on system base device tree. Thus, 6558 * before driver probing, it might need to add a device tree node as the final 6559 * fixup. 6560 */ 6561 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); 6562 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node); 6563 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node); 6564 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node); 6565 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA, 0x0220, of_pci_make_dev_node); 6566 6567 /* 6568 * Devices known to require a longer delay before first config space access 6569 * after reset recovery or resume from D3cold: 6570 * 6571 * VideoPropulsion (aka Genroco) Torrent QN16e MPEG QAM Modulator 6572 */ 6573 static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev) 6574 { 6575 pdev->d3cold_delay = 1000; 6576 } 6577 DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec); 6578 6579 #ifdef CONFIG_PCIEAER 6580 static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) 6581 { 6582 struct pci_dev *parent = pci_upstream_bridge(pdev); 6583 u32 val; 6584 6585 if (!parent || !parent->aer_cap) 6586 return; 6587 6588 pci_info(parent, "mask Replay Timer Timeout Correctable Errors due to %s hardware defect", 6589 pci_name(pdev)); 6590 6591 pci_read_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, &val); 6592 val |= PCI_ERR_COR_REP_TIMER; 6593 pci_write_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, val); 6594 } 6595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); 6596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); 6597 #endif 6598