1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
2 /*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef KFD_PRIV_H_INCLUDED
25 #define KFD_PRIV_H_INCLUDED
26
27 #include <linux/hashtable.h>
28 #include <linux/mmu_notifier.h>
29 #include <linux/memremap.h>
30 #include <linux/mutex.h>
31 #include <linux/types.h>
32 #include <linux/atomic.h>
33 #include <linux/workqueue.h>
34 #include <linux/spinlock.h>
35 #include <linux/iosys-map.h>
36 #include <uapi/linux/kfd_ioctl.h>
37 #include <linux/idr.h>
38 #include <linux/kfifo.h>
39 #include <linux/seq_file.h>
40 #include <linux/kref.h>
41 #include <linux/sysfs.h>
42 #include <linux/device_cgroup.h>
43 #include <drm/drm_file.h>
44 #include <drm/drm_drv.h>
45 #include <drm/drm_device.h>
46 #include <drm/drm_ioctl.h>
47 #include <kgd_kfd_interface.h>
48 #include <linux/swap.h>
49
50 #include "amd_shared.h"
51 #include "amdgpu.h"
52
53 #define KFD_MAX_RING_ENTRY_SIZE 8
54
55 #define KFD_SYSFS_FILE_MODE 0444
56
57 /* GPU ID hash width in bits */
58 #define KFD_GPU_ID_HASH_WIDTH 16
59
60 /* Use upper bits of mmap offset to store KFD driver specific information.
61 * BITS[63:62] - Encode MMAP type
62 * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to
63 * BITS[45:0] - MMAP offset value
64 *
65 * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these
66 * defines are w.r.t to PAGE_SIZE
67 */
68 #define KFD_MMAP_TYPE_SHIFT 62
69 #define KFD_MMAP_TYPE_MASK (0x3ULL << KFD_MMAP_TYPE_SHIFT)
70 #define KFD_MMAP_TYPE_DOORBELL (0x3ULL << KFD_MMAP_TYPE_SHIFT)
71 #define KFD_MMAP_TYPE_EVENTS (0x2ULL << KFD_MMAP_TYPE_SHIFT)
72 #define KFD_MMAP_TYPE_RESERVED_MEM (0x1ULL << KFD_MMAP_TYPE_SHIFT)
73 #define KFD_MMAP_TYPE_MMIO (0x0ULL << KFD_MMAP_TYPE_SHIFT)
74
75 #define KFD_MMAP_GPU_ID_SHIFT 46
76 #define KFD_MMAP_GPU_ID_MASK (((1ULL << KFD_GPU_ID_HASH_WIDTH) - 1) \
77 << KFD_MMAP_GPU_ID_SHIFT)
78 #define KFD_MMAP_GPU_ID(gpu_id) ((((uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT)\
79 & KFD_MMAP_GPU_ID_MASK)
80 #define KFD_MMAP_GET_GPU_ID(offset) ((offset & KFD_MMAP_GPU_ID_MASK) \
81 >> KFD_MMAP_GPU_ID_SHIFT)
82
83 /*
84 * When working with cp scheduler we should assign the HIQ manually or via
85 * the amdgpu driver to a fixed hqd slot, here are the fixed HIQ hqd slot
86 * definitions for Kaveri. In Kaveri only the first ME queues participates
87 * in the cp scheduling taking that in mind we set the HIQ slot in the
88 * second ME.
89 */
90 #define KFD_CIK_HIQ_PIPE 4
91 #define KFD_CIK_HIQ_QUEUE 0
92
93 /* Macro for allocating structures */
94 #define kfd_alloc_struct(ptr_to_struct) \
95 ((typeof(ptr_to_struct)) kzalloc_obj(*ptr_to_struct))
96
97 #define KFD_MAX_NUM_OF_PROCESSES 512
98 #define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS 1024
99
100 /*
101 * Size of the per-process TBA+TMA buffer: 2 pages
102 *
103 * The first chunk is the TBA used for the CWSR ISA code. The second
104 * chunk is used as TMA for user-mode trap handler setup in daisy-chain mode.
105 */
106 #define KFD_CWSR_TBA_TMA_SIZE (AMDGPU_GPU_PAGE_SIZE * 2)
107 #define KFD_CWSR_TMA_OFFSET (AMDGPU_GPU_PAGE_SIZE + 2048)
108
109 #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE \
110 (KFD_MAX_NUM_OF_PROCESSES * \
111 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS)
112
113 #define KFD_KERNEL_QUEUE_SIZE 2048
114
115 /* KFD_UNMAP_LATENCY_MS is the timeout CP waiting for SDMA preemption. One XCC
116 * can be associated to 2 SDMA engines. queue_preemption_timeout_ms is the time
117 * driver waiting for CP returning the UNMAP_QUEUE fence. Thus the math is
118 * queue_preemption_timeout_ms = sdma_preemption_time * 2 + cp workload
119 * The format here makes CP workload 10% of total timeout
120 */
121 #define KFD_UNMAP_LATENCY_MS \
122 ((queue_preemption_timeout_ms - queue_preemption_timeout_ms / 10) >> 1)
123
124 #define KFD_MAX_SDMA_QUEUES 128
125
126 /*
127 * 512 = 0x200
128 * The doorbell index distance between SDMA RLC (2*i) and (2*i+1) in the
129 * same SDMA engine on SOC15, which has 8-byte doorbells for SDMA.
130 * 512 8-byte doorbell distance (i.e. one page away) ensures that SDMA RLC
131 * (2*i+1) doorbells (in terms of the lower 12 bit address) lie exactly in
132 * the OFFSET and SIZE set in registers like BIF_SDMA0_DOORBELL_RANGE.
133 */
134 #define KFD_QUEUE_DOORBELL_MIRROR_OFFSET 512
135
136 /*
137 * On GC 9.4.3, 9.4.4 and 9.5.0, doorbell writes issued from shaders are
138 * routed to an SDMA engine at 32-byte granularity, i.e. 4 indices with the
139 * 8-byte SDMA doorbells used on SOC15.
140 */
141 #define KFD_SDMA_SHADER_DOORBELL_GRANULARITY 4
142
143 /**
144 * enum kfd_ioctl_flags - KFD ioctl flags
145 * Various flags that can be set in &amdkfd_ioctl_desc.flags to control how
146 * userspace can use a given ioctl.
147 */
148 enum kfd_ioctl_flags {
149 /*
150 * @KFD_IOC_FLAG_CHECKPOINT_RESTORE:
151 * Certain KFD ioctls such as AMDKFD_IOC_CRIU_OP can potentially
152 * perform privileged operations and load arbitrary data into MQDs and
153 * eventually HQD registers when the queue is mapped by HWS. In order to
154 * prevent this we should perform additional security checks.
155 *
156 * This is equivalent to callers with the CHECKPOINT_RESTORE capability.
157 *
158 * Note: Since earlier versions of docker do not support CHECKPOINT_RESTORE,
159 * we also allow ioctls with SYS_ADMIN capability.
160 */
161 KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0),
162 };
163 /*
164 * Kernel module parameter to specify maximum number of supported queues per
165 * device
166 */
167 extern int max_num_of_queues_per_device;
168
169
170 /* Kernel module parameter to specify the scheduling policy */
171 extern int sched_policy;
172
173 /*
174 * Kernel module parameter to specify the maximum process
175 * number per HW scheduler
176 */
177 extern int hws_max_conc_proc;
178
179 extern int cwsr_enable;
180
181 /*
182 * Kernel module parameter to specify whether to send sigterm to HSA process on
183 * unhandled exception
184 */
185 extern int send_sigterm;
186
187 /*
188 * This kernel module is used to simulate large bar machine on non-large bar
189 * enabled machines.
190 */
191 extern int debug_largebar;
192
193 /* Set sh_mem_config.retry_disable on GFX v9 */
194 extern int amdgpu_noretry;
195
196 /* Halt if HWS hang is detected */
197 extern int halt_if_hws_hang;
198
199 /* Whether MEC FW support GWS barriers */
200 extern bool hws_gws_support;
201
202 /* Queue preemption timeout in ms */
203 extern int queue_preemption_timeout_ms;
204
205 /*
206 * Don't evict process queues on vm fault
207 */
208 extern int amdgpu_no_queue_eviction_on_vm_fault;
209
210 /* Enable eviction debug messages */
211 extern bool debug_evictions;
212
213 extern struct mutex kfd_processes_mutex;
214
215 enum cache_policy {
216 cache_policy_coherent,
217 cache_policy_noncoherent
218 };
219
220 #define KFD_GC_VERSION(dev) (amdgpu_ip_version((dev)->adev, GC_HWIP, 0))
221 #define KFD_IS_SOC15(dev) ((KFD_GC_VERSION(dev)) >= (IP_VERSION(9, 0, 1)))
222 #define KFD_SUPPORT_XNACK_PER_PROCESS(dev)\
223 ((KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) || \
224 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) || \
225 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) || \
226 (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)))
227
228 struct kfd_node;
229
230 struct kfd_event_interrupt_class {
231 bool (*interrupt_isr)(struct kfd_node *dev,
232 const uint32_t *ih_ring_entry, uint32_t *patched_ihre,
233 bool *patched_flag);
234 void (*interrupt_wq)(struct kfd_node *dev,
235 const uint32_t *ih_ring_entry);
236 };
237
238 struct kfd_device_info {
239 uint32_t gfx_target_version;
240 const struct kfd_event_interrupt_class *event_interrupt_class;
241 unsigned int max_pasid_bits;
242 unsigned int max_no_of_hqd;
243 unsigned int doorbell_size;
244 size_t ih_ring_entry_size;
245 uint8_t num_of_watch_points;
246 uint16_t mqd_size_aligned;
247 bool supports_cwsr;
248 bool needs_pci_atomics;
249 uint32_t no_atomic_fw_version;
250 unsigned int num_sdma_queues_per_engine;
251 unsigned int num_reserved_sdma_queues_per_engine;
252 };
253
254 unsigned int kfd_get_num_sdma_engines(struct kfd_node *kdev);
255 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *kdev);
256
257 struct kfd_mem_obj {
258 uint32_t range_start;
259 uint32_t range_end;
260 uint64_t gpu_addr;
261 uint32_t *cpu_ptr;
262 void *mem;
263 };
264
265 struct kfd_vmid_info {
266 uint32_t first_vmid_kfd;
267 uint32_t last_vmid_kfd;
268 uint32_t vmid_num_kfd;
269 };
270
271 #define MAX_KFD_NODES 8
272
273 struct kfd_dev;
274
275 struct kfd_node {
276 unsigned int node_id;
277 struct amdgpu_device *adev; /* Duplicated here along with keeping
278 * a copy in kfd_dev to save a hop
279 */
280 const struct kfd2kgd_calls *kfd2kgd; /* Duplicated here along with
281 * keeping a copy in kfd_dev to
282 * save a hop
283 */
284 struct kfd_vmid_info vm_info;
285 unsigned int id; /* topology stub index */
286 uint32_t xcc_mask; /* Instance mask of XCCs present */
287 struct amdgpu_xcp *xcp;
288
289 /* Interrupts */
290 struct kfifo ih_fifo;
291 struct work_struct interrupt_work;
292 spinlock_t interrupt_lock;
293
294 /*
295 * Interrupts of interest to KFD are copied
296 * from the HW ring into a SW ring.
297 */
298 bool interrupts_active;
299 uint32_t interrupt_bitmap; /* Only used for GFX 9.4.3 */
300
301 /* QCM Device instance */
302 struct device_queue_manager *dqm;
303
304 /* Global GWS resource shared between processes */
305 void *gws;
306
307 /* Clients watching SMI events */
308 struct list_head smi_clients;
309 spinlock_t smi_lock;
310 uint32_t reset_seq_num;
311
312 /* SRAM ECC flag */
313 atomic_t sram_ecc_flag;
314
315 /*spm process id */
316 unsigned int spm_pasid;
317
318 /* Maximum process number mapped to HW scheduler */
319 unsigned int max_proc_per_quantum;
320
321 unsigned int compute_vmid_bitmap;
322
323 struct kfd_local_mem_info local_mem_info;
324
325 struct kfd_dev *kfd;
326
327 /* Track per device allocated watch points */
328 uint32_t alloc_watch_ids;
329 spinlock_t watch_points_lock;
330 };
331
332 struct kfd_dev {
333 struct amdgpu_device *adev;
334
335 struct kfd_device_info device_info;
336
337 u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells
338 * page used by kernel queue
339 */
340
341 struct kgd2kfd_shared_resources shared_resources;
342
343 const struct kfd2kgd_calls *kfd2kgd;
344 struct mutex doorbell_mutex;
345
346 void *gtt_mem;
347 uint64_t gtt_start_gpu_addr;
348 void *gtt_start_cpu_ptr;
349 void *gtt_sa_bitmap;
350 struct mutex gtt_sa_lock;
351 unsigned int gtt_sa_chunk_size;
352 unsigned int gtt_sa_num_of_chunks;
353
354 bool init_complete;
355
356 /* Firmware versions */
357 uint16_t mec_fw_version;
358 uint16_t mec2_fw_version;
359 uint16_t sdma_fw_version;
360
361 /* CWSR */
362 bool cwsr_enabled;
363 const void *cwsr_isa;
364 unsigned int cwsr_isa_size;
365
366 /* xGMI */
367 uint64_t hive_id;
368
369 bool pci_atomic_requested;
370
371 /* Compute Profile ref. count */
372 atomic_t compute_profile;
373
374 struct ida doorbell_ida;
375 unsigned int max_doorbell_slices;
376
377 int noretry;
378
379 struct kfd_node *nodes[MAX_KFD_NODES];
380 unsigned int num_nodes;
381
382 struct workqueue_struct *ih_wq;
383
384 /* Kernel doorbells for KFD device */
385 struct amdgpu_bo *doorbells;
386
387 /* bitmap for dynamic doorbell allocation from doorbell object */
388 unsigned long *doorbell_bitmap;
389
390 /* for dynamic partitioning */
391 int kfd_dev_lock;
392
393 atomic_t kfd_processes_count;
394
395 /* Lock for profiler process */
396 struct mutex profiler_lock;
397 /* Process currently holding the lock */
398 struct kfd_process *profiler_process;
399 };
400
401 enum kfd_mempool {
402 KFD_MEMPOOL_SYSTEM_CACHEABLE = 1,
403 KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2,
404 KFD_MEMPOOL_FRAMEBUFFER = 3,
405 };
406
407 /* Character device interface */
408 int kfd_chardev_init(void);
409 void kfd_chardev_exit(void);
410 void kfd_dev_unmap_mapping_range(loff_t const holebegin, loff_t const holelen);
411
412 /**
413 * enum kfd_unmap_queues_filter - Enum for queue filters.
414 *
415 * @KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES: Preempts all queues in the
416 * running queues list.
417 *
418 * @KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES: Preempts all non-static queues
419 * in the run list.
420 *
421 * @KFD_UNMAP_QUEUES_FILTER_BY_PASID: Preempts queues that belongs to
422 * specific process.
423 *
424 */
425 enum kfd_unmap_queues_filter {
426 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES = 1,
427 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES = 2,
428 KFD_UNMAP_QUEUES_FILTER_BY_PASID = 3
429 };
430
431 /**
432 * enum kfd_queue_type - Enum for various queue types.
433 *
434 * @KFD_QUEUE_TYPE_COMPUTE: Regular user mode queue type.
435 *
436 * @KFD_QUEUE_TYPE_SDMA: SDMA user mode queue type.
437 *
438 * @KFD_QUEUE_TYPE_HIQ: HIQ queue type.
439 *
440 * @KFD_QUEUE_TYPE_DIQ: DIQ queue type.
441 *
442 * @KFD_QUEUE_TYPE_SDMA_XGMI: Special SDMA queue for XGMI interface.
443 *
444 * @KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: SDMA user mode queue with target SDMA engine ID.
445 */
446 enum kfd_queue_type {
447 KFD_QUEUE_TYPE_COMPUTE,
448 KFD_QUEUE_TYPE_SDMA,
449 KFD_QUEUE_TYPE_HIQ,
450 KFD_QUEUE_TYPE_SDMA_XGMI,
451 KFD_QUEUE_TYPE_SDMA_BY_ENG_ID,
452 KFD_QUEUE_TYPE_MAX,
453 };
454
455 enum kfd_queue_format {
456 KFD_QUEUE_FORMAT_PM4,
457 KFD_QUEUE_FORMAT_AQL
458 };
459
460 enum KFD_QUEUE_PRIORITY {
461 KFD_QUEUE_PRIORITY_MINIMUM = 0,
462 KFD_QUEUE_PRIORITY_MAXIMUM = 15
463 };
464
465 /**
466 * struct queue_properties
467 *
468 * @type: The queue type.
469 *
470 * @queue_id: Queue identifier.
471 *
472 * @queue_address: Queue ring buffer address.
473 *
474 * @queue_size: Queue ring buffer size.
475 *
476 * @priority: Defines the queue priority relative to other queues in the
477 * process.
478 * This is just an indication and HW scheduling may override the priority as
479 * necessary while keeping the relative prioritization.
480 * the priority granularity is from 0 to f which f is the highest priority.
481 * currently all queues are initialized with the highest priority.
482 *
483 * @queue_percent: This field is partially implemented and currently a zero in
484 * this field defines that the queue is non active.
485 *
486 * @read_ptr: User space address which points to the number of dwords the
487 * cp read from the ring buffer. This field updates automatically by the H/W.
488 *
489 * @write_ptr: Defines the number of dwords written to the ring buffer.
490 *
491 * @doorbell_ptr: Notifies the H/W of new packet written to the queue ring
492 * buffer. This field should be similar to write_ptr and the user should
493 * update this field after updating the write_ptr.
494 *
495 * @doorbell_off: The doorbell offset in the doorbell pci-bar.
496 *
497 * @is_interop: Defines if this is a interop queue. Interop queue means that
498 * the queue can access both graphics and compute resources.
499 *
500 * @is_evicted: Defines if the queue is evicted. Only active queues
501 * are evicted, rendering them inactive.
502 *
503 * @is_active: Defines if the queue is active or not. @is_active and
504 * @is_evicted are protected by the DQM lock.
505 *
506 * @is_gws: Defines if the queue has been updated to be GWS-capable or not.
507 * @is_gws should be protected by the DQM lock, since changing it can yield the
508 * possibility of updating DQM state on number of GWS queues.
509 *
510 * @vmid: If the scheduling mode is no cp scheduling the field defines the vmid
511 * of the queue.
512 *
513 * This structure represents the queue properties for each queue no matter if
514 * it's user mode or kernel mode queue.
515 *
516 */
517
518 struct queue_properties {
519 enum kfd_queue_type type;
520 enum kfd_queue_format format;
521 unsigned int queue_id;
522 uint64_t queue_address;
523 uint64_t queue_size;
524 uint64_t metadata_queue_size;
525 uint32_t priority;
526 uint32_t queue_percent;
527 void __user *read_ptr;
528 void __user *write_ptr;
529 void __iomem *doorbell_ptr;
530 uint32_t doorbell_off;
531 bool is_interop;
532 bool is_evicted;
533 bool is_suspended;
534 bool is_being_destroyed;
535 bool is_active;
536 bool is_gws;
537 uint32_t pm4_target_xcc;
538 bool is_dbg_wa;
539 bool is_user_cu_masked;
540 bool is_reset;
541 /* Not relevant for user mode queues in cp scheduling */
542 unsigned int vmid;
543 /* Relevant only for sdma queues*/
544 uint32_t sdma_engine_id;
545 uint32_t sdma_queue_id;
546 uint32_t sdma_vm_addr;
547 /* Relevant only for VI */
548 uint64_t eop_ring_buffer_address;
549 uint32_t eop_ring_buffer_size;
550 uint64_t ctx_save_restore_area_address;
551 uint32_t ctx_save_restore_area_size;
552 uint32_t ctl_stack_size;
553 uint64_t tba_addr;
554 uint64_t tma_addr;
555 uint64_t exception_status;
556
557 struct amdgpu_bo *wptr_bo;
558 struct amdgpu_bo *rptr_bo;
559 struct amdgpu_bo *ring_bo;
560 struct amdgpu_bo *eop_buf_bo;
561 struct amdgpu_bo *cwsr_bo;
562 };
563
564 #define QUEUE_IS_ACTIVE(q) ((q).queue_size > 0 && \
565 (q).queue_address != 0 && \
566 (q).queue_percent > 0 && \
567 !(q).is_evicted && \
568 !(q).is_suspended)
569
570 enum mqd_update_flag {
571 UPDATE_FLAG_DBG_WA_ENABLE = 1,
572 UPDATE_FLAG_DBG_WA_DISABLE = 2,
573 UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */
574 UPDATE_FLAG_PERFCOUNT_ENABLE = 5,
575 UPDATE_FLAG_PERFCOUNT_DISABLE = 6,
576 };
577
578 struct mqd_update_info {
579 union {
580 struct {
581 uint32_t count; /* Must be a multiple of 32 */
582 uint32_t *ptr;
583 } cu_mask;
584 };
585 enum mqd_update_flag update_flag;
586 };
587
588 /**
589 * struct queue
590 *
591 * @list: Queue linked list.
592 *
593 * @mqd: The queue MQD (memory queue descriptor).
594 *
595 * @mqd_mem_obj: The MQD local gpu memory object.
596 *
597 * @gart_mqd_addr: The MQD gart mc address.
598 *
599 * @properties: The queue properties.
600 *
601 * @mec: Used only in no cp scheduling mode and identifies to micro engine id
602 * that the queue should be executed on.
603 *
604 * @pipe: Used only in no cp scheduling mode and identifies the queue's pipe
605 * id.
606 *
607 * @queue: Used only in no cp scheduliong mode and identifies the queue's slot.
608 *
609 * @process: The kfd process that created this queue.
610 *
611 * @device: The kfd device that created this queue.
612 *
613 * @gws: Pointing to gws kgd_mem if this is a gws control queue; NULL
614 * otherwise.
615 *
616 * This structure represents user mode compute queues.
617 * It contains all the necessary data to handle such queues.
618 *
619 */
620
621 struct queue {
622 struct list_head list;
623 void *mqd;
624 struct kfd_mem_obj *mqd_mem_obj;
625 uint64_t gart_mqd_addr;
626 struct queue_properties properties;
627
628 uint32_t mec;
629 uint32_t pipe;
630 uint32_t queue;
631
632 unsigned int sdma_id;
633 unsigned int doorbell_id;
634
635 struct kfd_process *process;
636 struct kfd_node *device;
637 void *gws;
638
639 /* procfs */
640 struct kobject kobj;
641
642 void *gang_ctx_bo;
643 uint64_t gang_ctx_gpu_addr;
644 void *gang_ctx_cpu_ptr;
645 uint32_t gang_ctx_array_index;
646
647 struct amdgpu_bo *wptr_bo_gart;
648
649 /* The VRAM-resident MQD BO (mqd_on_vram()) is unpinned at S4 suspend so
650 * TTM evicts it into the hibernation image, and repinned on resume. Set
651 * while the BO is unpinned so the resume path knows to repin it.
652 */
653 bool needs_mqd_repin;
654 };
655
656 enum KFD_MQD_TYPE {
657 KFD_MQD_TYPE_HIQ = 0, /* for hiq */
658 KFD_MQD_TYPE_CP, /* for cp queues and diq */
659 KFD_MQD_TYPE_SDMA, /* for sdma queues */
660 KFD_MQD_TYPE_DIQ, /* for diq */
661 KFD_MQD_TYPE_MAX
662 };
663
664 enum KFD_PIPE_PRIORITY {
665 KFD_PIPE_PRIORITY_CS_LOW = 0,
666 KFD_PIPE_PRIORITY_CS_MEDIUM,
667 KFD_PIPE_PRIORITY_CS_HIGH
668 };
669
670 struct scheduling_resources {
671 unsigned int vmid_mask;
672 enum kfd_queue_type type;
673 uint64_t queue_mask;
674 uint64_t gws_mask;
675 uint32_t oac_mask;
676 uint32_t gds_heap_base;
677 uint32_t gds_heap_size;
678 };
679
680 struct process_queue_manager {
681 /* data */
682 struct kfd_process *process;
683 struct list_head queues;
684 unsigned long *queue_slot_bitmap;
685 };
686
687 struct qcm_process_device {
688 /* The Device Queue Manager that owns this data */
689 struct device_queue_manager *dqm;
690 struct process_queue_manager *pqm;
691 /* Queues list */
692 struct list_head queues_list;
693 struct list_head priv_queue_list;
694
695 unsigned int queue_count;
696 unsigned int vmid;
697 bool is_debug;
698 unsigned int evicted; /* eviction counter, 0=active */
699
700 /* This flag tells if we should reset all wavefronts on
701 * process termination
702 */
703 bool reset_wavefronts;
704
705 /* This flag tells us if this process has a GWS-capable
706 * queue that will be mapped into the runlist. It's
707 * possible to request a GWS BO, but not have the queue
708 * currently mapped, and this changes how the MAP_PROCESS
709 * PM4 packet is configured.
710 */
711 bool mapped_gws_queue;
712
713 /* All the memory management data should be here too */
714 uint64_t gds_context_area;
715 /* Contains page table flags such as AMDGPU_PTE_VALID since gfx9 */
716 uint64_t page_table_base;
717 uint32_t sh_mem_config;
718 uint32_t sh_mem_bases;
719 uint32_t sh_mem_ape1_base;
720 uint32_t sh_mem_ape1_limit;
721 uint32_t gds_size;
722 uint32_t num_gws;
723 uint32_t num_oac;
724 uint32_t sh_hidden_private_base;
725 uint32_t vm_cntx_cntl;
726
727 /* CWSR memory */
728 struct kgd_mem *cwsr_mem;
729 struct iosys_map cwsr_map;
730 uint64_t cwsr_base;
731 uint64_t tba_addr;
732 uint64_t tma_addr;
733
734 /* IB memory */
735 struct kgd_mem *ib_mem;
736 uint64_t ib_base;
737 void *ib_kaddr;
738
739 /* doorbells for kfd process */
740 struct amdgpu_bo *proc_doorbells;
741
742 /* bitmap for dynamic doorbell allocation from the bo */
743 unsigned long *doorbell_bitmap;
744 };
745
746 /* KFD Memory Eviction */
747
748 /* Approx. wait time before attempting to restore evicted BOs */
749 #define PROCESS_RESTORE_TIME_MS 100
750 /* Approx. back off time if restore fails due to lack of memory */
751 #define PROCESS_BACK_OFF_TIME_MS 100
752 /* Approx. time before evicting the process again */
753 #define PROCESS_ACTIVE_TIME_MS 10
754
755 /* 8 byte handle containing GPU ID in the most significant 4 bytes and
756 * idr_handle in the least significant 4 bytes
757 */
758 #define MAKE_HANDLE(gpu_id, idr_handle) \
759 (((uint64_t)(gpu_id) << 32) + idr_handle)
760 #define GET_GPU_ID(handle) (handle >> 32)
761 #define GET_IDR_HANDLE(handle) (handle & 0xFFFFFFFF)
762
763 enum kfd_pdd_bound {
764 PDD_UNBOUND = 0,
765 PDD_BOUND,
766 PDD_BOUND_SUSPENDED,
767 };
768
769 #define MAX_SYSFS_FILENAME_LEN 15
770
771 /*
772 * SDMA counter runs at 100MHz frequency.
773 * We display SDMA activity in microsecond granularity in sysfs.
774 * As a result, the divisor is 100.
775 */
776 #define SDMA_ACTIVITY_DIVISOR 100
777
778 /* Data that is per-process-per device. */
779 struct kfd_process_device {
780 /* The device that owns this data. */
781 struct kfd_node *dev;
782
783 /* The process that owns this kfd_process_device. */
784 struct kfd_process *process;
785
786 /* per-process-per device QCM data structure */
787 struct qcm_process_device qpd;
788
789 /*Apertures*/
790 uint64_t lds_base;
791 uint64_t lds_limit;
792 uint64_t gpuvm_base;
793 uint64_t gpuvm_limit;
794 uint64_t scratch_base;
795 uint64_t scratch_limit;
796
797 /* VM context for GPUVM allocations */
798 struct file *drm_file;
799 void *drm_priv;
800
801 /* GPUVM allocations storage */
802 struct idr alloc_idr;
803
804 /* Flag used to tell the pdd has dequeued from the dqm.
805 * This is used to prevent dev->dqm->ops.process_termination() from
806 * being called twice when it is already called in IOMMU callback
807 * function.
808 */
809 bool already_dequeued;
810 bool runtime_inuse;
811
812 /* Is this process/pasid bound to this device? (amd_iommu_bind_pasid) */
813 enum kfd_pdd_bound bound;
814
815 /* VRAM usage */
816 atomic64_t vram_usage;
817 struct attribute attr_vram;
818 char vram_filename[MAX_SYSFS_FILENAME_LEN];
819
820 /* SDMA activity tracking */
821 uint64_t sdma_past_activity_counter;
822 struct attribute attr_sdma;
823 char sdma_filename[MAX_SYSFS_FILENAME_LEN];
824
825 /* Eviction activity tracking */
826 uint64_t last_evict_timestamp;
827 atomic64_t evict_duration_counter;
828 struct attribute attr_evict;
829
830 struct kobject *kobj_stats;
831
832 /*
833 * @cu_occupancy: Reports occupancy of Compute Units (CU) of a process
834 * that is associated with device encoded by "this" struct instance. The
835 * value reflects CU usage by all of the waves launched by this process
836 * on this device. A very important property of occupancy parameter is
837 * that its value is a snapshot of current use.
838 *
839 * Following is to be noted regarding how this parameter is reported:
840 *
841 * The number of waves that a CU can launch is limited by couple of
842 * parameters. These are encoded by struct amdgpu_cu_info instance
843 * that is part of every device definition. For GFX9 devices this
844 * translates to 40 waves (simd_per_cu * max_waves_per_simd) when waves
845 * do not use scratch memory and 32 waves (max_scratch_slots_per_cu)
846 * when they do use scratch memory. This could change for future
847 * devices and therefore this example should be considered as a guide.
848 *
849 * All CU's of a device are available for the process. This may not be true
850 * under certain conditions - e.g. CU masking.
851 *
852 * Finally number of CU's that are occupied by a process is affected by both
853 * number of CU's a device has along with number of other competing processes
854 */
855 struct attribute attr_cu_occupancy;
856
857 /* sysfs counters for GPU retry fault and page migration tracking */
858 struct kobject *kobj_counters;
859 struct attribute attr_faults;
860 struct attribute attr_page_in;
861 struct attribute attr_page_out;
862 uint64_t faults;
863 uint64_t page_in;
864 uint64_t page_out;
865
866 /* Exception code status*/
867 uint64_t exception_status;
868 void *vm_fault_exc_data;
869 size_t vm_fault_exc_data_size;
870
871 /* Tracks debug per-vmid request settings */
872 uint32_t spi_dbg_override;
873 uint32_t spi_dbg_launch_mode;
874 uint32_t watch_points[4];
875 uint32_t alloc_watch_ids;
876
877 /*
878 * If this process has been checkpointed before, then the user
879 * application will use the original gpu_id on the
880 * checkpointed node to refer to this device.
881 */
882 uint32_t user_gpu_id;
883
884 void *proc_ctx_bo;
885 uint64_t proc_ctx_gpu_addr;
886 void *proc_ctx_cpu_ptr;
887
888 uint32_t proc_ctx_array_index;
889
890 /* Tracks queue reset status */
891 bool has_reset_queue;
892
893 u32 pasid;
894 /* Indicates this process has requested PTL stay disabled */
895 bool ptl_disable_req;
896 };
897
898 #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd)
899
900 struct svm_range_list {
901 struct mutex lock;
902 struct rb_root_cached objects;
903 struct list_head list;
904 struct work_struct deferred_list_work;
905 struct list_head deferred_range_list;
906 struct list_head criu_svm_metadata_list;
907 spinlock_t deferred_list_lock;
908 atomic_t evicted_ranges;
909 atomic_t drain_pagefaults;
910 struct delayed_work restore_work;
911 DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE);
912 struct task_struct *faulting_task;
913 /* check point ts decides if page fault recovery need be dropped */
914 atomic64_t checkpoint_ts[MAX_GPU_INSTANCE];
915
916 /* Default granularity to use in buffer migration
917 * and restoration of backing memory while handling
918 * recoverable page faults
919 */
920 uint8_t default_granularity;
921 };
922
923 /* Process data */
924 struct kfd_process {
925 /*
926 * kfd_process are stored in an mm_struct*->kfd_process*
927 * hash table (kfd_processes in kfd_process.c)
928 */
929 struct hlist_node kfd_processes;
930
931 /*
932 * Opaque pointer to mm_struct. We don't hold a reference to
933 * it so it should never be dereferenced from here. This is
934 * only used for looking up processes by their mm.
935 */
936 void *mm;
937
938 struct kref ref;
939 struct work_struct release_work;
940
941 struct mutex mutex;
942
943 /*
944 * In any process, the thread that started main() is the lead
945 * thread and outlives the rest.
946 * It is here because amd_iommu_bind_pasid wants a task_struct.
947 * It can also be used for safely getting a reference to the
948 * mm_struct of the process.
949 */
950 struct task_struct *lead_thread;
951
952 /* We want to receive a notification when the mm_struct is destroyed */
953 struct mmu_notifier mmu_notifier;
954
955 /*
956 * Array of kfd_process_device pointers,
957 * one for each device the process is using.
958 */
959 struct kfd_process_device *pdds[MAX_GPU_INSTANCE];
960 uint32_t n_pdds;
961
962 struct process_queue_manager pqm;
963
964 /*Is the user space process 32 bit?*/
965 bool is_32bit_user_mode;
966
967 /* Event-related data */
968 struct mutex event_mutex;
969 /* Event ID allocator and lookup */
970 struct idr event_idr;
971 /* Event page */
972 u64 signal_handle;
973 /*
974 * Each signal event needs a 64-bit signal slot where the signaler will
975 * write a 1 before sending an interrupt. (This is needed because some
976 * interrupts do not contain enough spare data bits to identify an
977 * event.) The signal page is allocated in user mode and mapped to the
978 * kernel; individual signal events use their event_id as slot index.
979 */
980 uint64_t *signal_page;
981 size_t signal_mapped_size;
982 size_t signal_event_count;
983 bool signal_event_limit_reached;
984
985 /**
986 * @kfd_sigbus_delay_ms: Per-process KFD SIGBUS delivery option for
987 * poison/RAS events (set via DRM_IOCTL_AMDGPU_PROC_OPTIONS /
988 * AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY).
989 *
990 * 0 - send SIGBUS immediately (default)
991 * 0xFFFFFFFF - suppress SIGBUS delivery
992 * other - delay SIGBUS delivery by this many milliseconds
993 */
994 atomic_t kfd_sigbus_delay_ms;
995
996 /* Delayed signal delivery to user */
997 struct delayed_work signal_work;
998
999 /* Information used for memory eviction */
1000 void *kgd_process_info;
1001 /* Eviction fence that is attached to all the BOs of this process. The
1002 * fence will be triggered during eviction and new one will be created
1003 * during restore
1004 */
1005 struct dma_fence __rcu *ef;
1006
1007 /* Work items for evicting and restoring BOs */
1008 struct delayed_work eviction_work;
1009 struct delayed_work restore_work;
1010 /* seqno of the last scheduled eviction */
1011 unsigned int last_eviction_seqno;
1012 /* Approx. the last timestamp (in jiffies) when the process was
1013 * restored after an eviction
1014 */
1015 unsigned long last_restore_timestamp;
1016
1017 /* Indicates device process is debug attached with reserved vmid. */
1018 bool debug_trap_enabled;
1019
1020 /* per-process-per device debug event fd file */
1021 struct file *dbg_ev_file;
1022
1023 /* If the process is a kfd debugger, we need to know so we can clean
1024 * up at exit time. If a process enables debugging on itself, it does
1025 * its own clean-up, so we don't set the flag here. We track this by
1026 * counting the number of processes this process is debugging.
1027 */
1028 atomic_t debugged_process_count;
1029
1030 /* If the process is a debugged, this is the debugger process */
1031 struct kfd_process *debugger_process;
1032
1033 /* Kobj for our procfs */
1034 struct kobject *kobj;
1035 struct kobject *kobj_queues;
1036 struct attribute attr_pasid;
1037
1038 /* Exception code enable mask and status */
1039 uint64_t exception_enable_mask;
1040 uint64_t exception_status;
1041
1042 /* Used to drain stale interrupts */
1043 wait_queue_head_t wait_irq_drain;
1044 bool irq_drain_is_open;
1045
1046 /* shared virtual memory registered by this process */
1047 struct svm_range_list svms;
1048
1049 bool xnack_enabled;
1050
1051 /* Work area for debugger event writer worker. */
1052 struct work_struct debug_event_workarea;
1053
1054 /* Tracks debug per-vmid request for debug flags */
1055 u32 dbg_flags;
1056
1057 atomic_t poison;
1058 /* Queues are in paused stated because we are in the process of doing a CRIU checkpoint */
1059 bool queues_paused;
1060
1061 /* Tracks runtime enable status */
1062 struct semaphore runtime_enable_sema;
1063 bool is_runtime_retry;
1064 struct kfd_runtime_info runtime_info;
1065
1066 /* if gpu page fault sent to KFD */
1067 bool gpu_page_fault;
1068
1069 /*kfd context id */
1070 u16 context_id;
1071
1072 /* The primary kfd_process allocating IDs for its secondary kfd_process, 0 for primary kfd_process */
1073 struct ida id_table;
1074
1075 };
1076
1077 #define KFD_PROCESS_TABLE_SIZE 8 /* bits: 256 entries */
1078 #define KFD_CONTEXT_ID_PRIMARY 0xFFFF
1079 #define KFD_CONTEXT_ID_MIN 0
1080
1081 extern DECLARE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE);
1082 extern struct srcu_struct kfd_processes_srcu;
1083
1084 /**
1085 * typedef amdkfd_ioctl_t - typedef for ioctl function pointer.
1086 *
1087 * @filep: pointer to file structure.
1088 * @p: amdkfd process pointer.
1089 * @data: pointer to arg that was copied from user.
1090 *
1091 * Return: returns ioctl completion code.
1092 */
1093 typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p,
1094 void *data);
1095
1096 typedef int amdkfd_ioctl_validate_t(void *kdata, unsigned int usize);
1097
1098 struct amdkfd_ioctl_desc {
1099 unsigned int cmd;
1100 int flags;
1101 amdkfd_ioctl_t *func;
1102 amdkfd_ioctl_validate_t *validate;
1103 unsigned int cmd_drv;
1104 const char *name;
1105 };
1106 bool kfd_dev_is_large_bar(struct kfd_node *dev);
1107
1108 struct kfd_process *create_process(const struct task_struct *thread, bool primary);
1109 int kfd_process_create_wq(void);
1110 void kfd_process_destroy_wq(void);
1111 void kfd_cleanup_processes(void);
1112 struct kfd_process *kfd_create_process(struct task_struct *thread);
1113 int kfd_create_process_sysfs(struct kfd_process *process);
1114 struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid,
1115 struct kfd_process_device **pdd);
1116 struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm);
1117 struct kfd_process *kfd_lookup_process_by_id(const struct mm_struct *mm, u16 id);
1118
1119 int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id);
1120 int kfd_process_gpuid_from_node(struct kfd_process *p, struct kfd_node *node,
1121 uint32_t *gpuid, uint32_t *gpuidx);
kfd_process_gpuid_from_gpuidx(struct kfd_process * p,uint32_t gpuidx,uint32_t * gpuid)1122 static inline int kfd_process_gpuid_from_gpuidx(struct kfd_process *p,
1123 uint32_t gpuidx, uint32_t *gpuid) {
1124 return gpuidx < p->n_pdds ? p->pdds[gpuidx]->dev->id : -EINVAL;
1125 }
kfd_process_device_from_gpuidx(struct kfd_process * p,uint32_t gpuidx)1126 static inline struct kfd_process_device *kfd_process_device_from_gpuidx(
1127 struct kfd_process *p, uint32_t gpuidx) {
1128 return gpuidx < p->n_pdds ? p->pdds[gpuidx] : NULL;
1129 }
1130
1131 void kfd_unref_process(struct kfd_process *p);
1132 int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger);
1133 int kfd_process_restore_queues(struct kfd_process *p);
1134 void kfd_suspend_all_processes(void);
1135 int kfd_resume_all_processes(void);
1136
1137 struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *process,
1138 uint32_t gpu_id);
1139
1140 int kfd_process_get_user_gpu_id(struct kfd_process *p, uint32_t actual_gpu_id);
1141
1142 int kfd_process_device_init_vm(struct kfd_process_device *pdd,
1143 struct file *drm_file);
1144 struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev,
1145 struct kfd_process *p);
1146 struct kfd_process_device *kfd_get_process_device_data(struct kfd_node *dev,
1147 struct kfd_process *p);
1148 struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev,
1149 struct kfd_process *p);
1150
1151 bool kfd_process_xnack_mode(struct kfd_process *p, bool supported);
1152
1153 void kfd_process_notifier_release_internal(struct kfd_process *p);
1154
1155 /* KFD process API for creating and translating handles */
1156 int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd,
1157 void *mem);
1158 void *kfd_process_device_translate_handle(struct kfd_process_device *p,
1159 int handle);
1160 void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd,
1161 int handle);
1162 struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid);
1163
1164 /* PASIDs */
1165 int kfd_pasid_init(void);
1166 void kfd_pasid_exit(void);
1167 u32 kfd_pasid_alloc(void);
1168 void kfd_pasid_free(u32 pasid);
1169
1170 /* Doorbells */
1171 size_t kfd_doorbell_process_slice(struct kfd_dev *kfd);
1172 int kfd_doorbell_init(struct kfd_dev *kfd);
1173 void kfd_doorbell_fini(struct kfd_dev *kfd);
1174 int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process,
1175 struct vm_area_struct *vma);
1176 void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd,
1177 unsigned int *doorbell_off);
1178 void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr);
1179 u32 read_kernel_doorbell(u32 __iomem *db);
1180 void write_kernel_doorbell(void __iomem *db, u32 value);
1181 void write_kernel_doorbell64(void __iomem *db, u64 value);
1182 unsigned int kfd_get_doorbell_dw_offset_in_bar(struct kfd_dev *kfd,
1183 struct kfd_process_device *pdd,
1184 unsigned int doorbell_id);
1185 phys_addr_t kfd_get_process_doorbells(struct kfd_process_device *pdd);
1186 int kfd_alloc_process_doorbells(struct kfd_dev *kfd,
1187 struct kfd_process_device *pdd);
1188 void kfd_free_process_doorbells(struct kfd_dev *kfd,
1189 struct kfd_process_device *pdd);
1190 /* GTT Sub-Allocator */
1191
1192 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size,
1193 struct kfd_mem_obj **mem_obj);
1194
1195 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj);
1196
1197 extern struct device *kfd_device;
1198
1199 /* KFD's procfs */
1200 void kfd_procfs_init(void);
1201 void kfd_procfs_shutdown(void);
1202 int kfd_procfs_add_queue(struct queue *q);
1203 void kfd_procfs_del_queue(struct queue *q);
1204
1205 /* Topology */
1206 int kfd_topology_init(void);
1207 void kfd_topology_shutdown(void);
1208 int kfd_topology_add_device(struct kfd_node *gpu);
1209 int kfd_topology_remove_device(struct kfd_node *gpu);
1210 struct kfd_topology_device *kfd_topology_device_by_proximity_domain(
1211 uint32_t proximity_domain);
1212 struct kfd_topology_device *kfd_topology_device_by_proximity_domain_no_lock(
1213 uint32_t proximity_domain);
1214 struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id);
1215 struct kfd_node *kfd_device_by_id(uint32_t gpu_id);
kfd_irq_is_from_node(struct kfd_node * node,uint32_t node_id,uint32_t vmid)1216 static inline bool kfd_irq_is_from_node(struct kfd_node *node, uint32_t node_id,
1217 uint32_t vmid)
1218 {
1219 return (node->interrupt_bitmap & (1 << node_id)) != 0 &&
1220 (node->compute_vmid_bitmap & (1 << vmid)) != 0;
1221 }
kfd_node_by_irq_ids(struct amdgpu_device * adev,uint32_t node_id,uint32_t vmid)1222 static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev,
1223 uint32_t node_id, uint32_t vmid) {
1224 struct kfd_dev *dev = adev->kfd.dev;
1225 uint32_t i;
1226
1227 /*
1228 * On multi-aid system, attempt per-node matching. Otherwise,
1229 * fall back to the first node.
1230 */
1231 if (!amdgpu_is_multi_aid(adev))
1232 return dev->nodes[0];
1233
1234 for (i = 0; i < dev->num_nodes; i++)
1235 if (kfd_irq_is_from_node(dev->nodes[i], node_id, vmid))
1236 return dev->nodes[i];
1237
1238 return NULL;
1239 }
1240 int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev);
1241 uint32_t kfd_topology_get_num_devices(void);
1242 int kfd_numa_node_to_apic_id(int numa_node_id);
1243 uint32_t kfd_gpu_node_num(void);
1244
1245 /* Interrupts */
1246 #define KFD_IRQ_FENCE_CLIENTID 0xff
1247 #define KFD_IRQ_FENCE_SOURCEID 0xff
1248 #define KFD_IRQ_IS_FENCE(client, source) \
1249 ((client) == KFD_IRQ_FENCE_CLIENTID && \
1250 (source) == KFD_IRQ_FENCE_SOURCEID)
1251 int kfd_interrupt_init(struct kfd_node *dev);
1252 void kfd_interrupt_exit(struct kfd_node *dev);
1253 bool enqueue_ih_ring_entry(struct kfd_node *kfd, const void *ih_ring_entry);
1254 bool interrupt_is_wanted(struct kfd_node *dev,
1255 const uint32_t *ih_ring_entry,
1256 uint32_t *patched_ihre, bool *flag);
1257 int kfd_process_drain_interrupts(struct kfd_process_device *pdd);
1258 void kfd_process_close_interrupt_drain(unsigned int pasid);
1259
1260 /* amdkfd Apertures */
1261 int kfd_init_apertures(struct kfd_process *process);
1262
1263 void kfd_process_set_trap_handler(struct qcm_process_device *qpd,
1264 uint64_t tba_addr,
1265 uint64_t tma_addr);
1266 void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd,
1267 bool enabled);
1268
1269 /* CRIU */
1270 /*
1271 * Need to increment KFD_CRIU_PRIV_VERSION each time a change is made to any of the CRIU private
1272 * structures:
1273 * kfd_criu_process_priv_data
1274 * kfd_criu_device_priv_data
1275 * kfd_criu_bo_priv_data
1276 * kfd_criu_queue_priv_data
1277 * kfd_criu_event_priv_data
1278 * kfd_criu_svm_range_priv_data
1279 */
1280
1281 #define KFD_CRIU_PRIV_VERSION 1
1282
1283 struct kfd_criu_process_priv_data {
1284 uint32_t version;
1285 uint32_t xnack_mode;
1286 };
1287
1288 struct kfd_criu_device_priv_data {
1289 /* For future use */
1290 uint64_t reserved;
1291 };
1292
1293 struct kfd_criu_bo_priv_data {
1294 uint64_t user_addr;
1295 uint32_t idr_handle;
1296 uint32_t mapped_gpuids[MAX_GPU_INSTANCE];
1297 };
1298
1299 /*
1300 * The first 4 bytes of kfd_criu_queue_priv_data, kfd_criu_event_priv_data,
1301 * kfd_criu_svm_range_priv_data is the object type
1302 */
1303 enum kfd_criu_object_type {
1304 KFD_CRIU_OBJECT_TYPE_QUEUE,
1305 KFD_CRIU_OBJECT_TYPE_EVENT,
1306 KFD_CRIU_OBJECT_TYPE_SVM_RANGE,
1307 };
1308
1309 struct kfd_criu_svm_range_priv_data {
1310 uint32_t object_type;
1311 uint64_t start_addr;
1312 uint64_t size;
1313 /* Variable length array of attributes */
1314 struct kfd_ioctl_svm_attribute attrs[];
1315 };
1316
1317 struct kfd_criu_queue_priv_data {
1318 uint32_t object_type;
1319 uint64_t q_address;
1320 uint64_t q_size;
1321 uint64_t read_ptr_addr;
1322 uint64_t write_ptr_addr;
1323 uint64_t doorbell_off;
1324 uint64_t eop_ring_buffer_address;
1325 uint64_t ctx_save_restore_area_address;
1326 uint32_t gpu_id;
1327 uint32_t type;
1328 uint32_t format;
1329 uint32_t q_id;
1330 uint32_t priority;
1331 uint32_t q_percent;
1332 uint32_t doorbell_id;
1333 uint32_t gws;
1334 uint32_t sdma_id;
1335 uint32_t eop_ring_buffer_size;
1336 uint32_t ctx_save_restore_area_size;
1337 uint32_t ctl_stack_size;
1338 uint32_t mqd_size;
1339 };
1340
1341 struct kfd_criu_event_priv_data {
1342 uint32_t object_type;
1343 uint64_t user_handle;
1344 uint32_t event_id;
1345 uint32_t auto_reset;
1346 uint32_t type;
1347 uint32_t signaled;
1348
1349 union {
1350 struct kfd_hsa_memory_exception_data memory_exception_data;
1351 struct kfd_hsa_hw_exception_data hw_exception_data;
1352 };
1353 };
1354
1355 int kfd_process_get_queue_info(struct kfd_process *p,
1356 uint32_t *num_queues,
1357 uint64_t *priv_data_sizes);
1358
1359 int kfd_criu_checkpoint_queues(struct kfd_process *p,
1360 uint8_t __user *user_priv_data,
1361 uint64_t *priv_data_offset);
1362
1363 int kfd_criu_restore_queue(struct kfd_process *p,
1364 uint8_t __user *user_priv_data,
1365 uint64_t *priv_data_offset,
1366 uint64_t max_priv_data_size);
1367
1368 int kfd_criu_checkpoint_events(struct kfd_process *p,
1369 uint8_t __user *user_priv_data,
1370 uint64_t *priv_data_offset);
1371
1372 int kfd_criu_restore_event(struct file *devkfd,
1373 struct kfd_process *p,
1374 uint8_t __user *user_priv_data,
1375 uint64_t *priv_data_offset,
1376 uint64_t max_priv_data_size);
1377 /* CRIU - End */
1378
1379 /* Queue Context Management */
1380 int init_queue(struct queue **q, const struct queue_properties *properties);
1381 void uninit_queue(struct queue *q);
1382 void print_queue_properties(struct queue_properties *q);
1383 void print_queue(struct queue *q);
1384 int kfd_queue_buffer_get(struct amdgpu_vm *vm, void __user *addr, struct amdgpu_bo **pbo,
1385 u64 expected_size);
1386 void kfd_queue_buffer_put(struct amdgpu_bo **bo);
1387 int kfd_queue_acquire_buffers(struct kfd_process_device *pdd, struct queue_properties *properties);
1388 int kfd_queue_release_buffers(struct kfd_process_device *pdd, struct queue_properties *properties);
1389 void kfd_queue_unref_bo_va(struct amdgpu_vm *vm, struct amdgpu_bo **bo);
1390 int kfd_queue_unref_bo_vas(struct kfd_process_device *pdd,
1391 struct queue_properties *properties);
1392 void kfd_queue_ctx_save_restore_size(struct kfd_topology_device *dev);
1393
1394 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
1395 struct kfd_node *dev);
1396 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
1397 struct kfd_node *dev);
1398 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
1399 struct kfd_node *dev);
1400 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
1401 struct kfd_node *dev);
1402 struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type,
1403 struct kfd_node *dev);
1404 struct mqd_manager *mqd_manager_init_v12(enum KFD_MQD_TYPE type,
1405 struct kfd_node *dev);
1406 struct mqd_manager *mqd_manager_init_v12_1(enum KFD_MQD_TYPE type,
1407 struct kfd_node *dev);
1408 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev);
1409 void device_queue_manager_uninit(struct device_queue_manager *dqm);
1410 struct kernel_queue *kernel_queue_init(struct kfd_node *dev,
1411 enum kfd_queue_type type);
1412 void kernel_queue_uninit(struct kernel_queue *kq);
1413 int kfd_evict_process_device(struct kfd_process_device *pdd);
1414 int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id);
1415
1416 /* Process Queue Manager */
1417 struct process_queue_node {
1418 struct queue *q;
1419 struct kernel_queue *kq;
1420 struct list_head process_queue_list;
1421 };
1422
1423 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd);
1424 void kfd_process_dequeue_from_all_devices(struct kfd_process *p);
1425 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p);
1426 void pqm_uninit(struct process_queue_manager *pqm);
1427 int pqm_create_queue(struct process_queue_manager *pqm,
1428 struct kfd_node *dev,
1429 struct queue_properties *properties,
1430 unsigned int *qid,
1431 const struct kfd_criu_queue_priv_data *q_data,
1432 const void *restore_mqd,
1433 const void *restore_ctl_stack,
1434 uint32_t *p_doorbell_offset_in_process);
1435 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid);
1436 int pqm_update_queue_properties(struct process_queue_manager *pqm, unsigned int qid,
1437 struct queue_properties *p);
1438 int pqm_update_mqd(struct process_queue_manager *pqm, unsigned int qid,
1439 struct mqd_update_info *minfo);
1440 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid,
1441 void *gws);
1442 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm,
1443 unsigned int qid);
1444 int pqm_get_wave_state(struct process_queue_manager *pqm,
1445 unsigned int qid,
1446 void __user *ctl_stack,
1447 u32 *ctl_stack_used_size,
1448 u32 *save_area_used_size);
1449 int pqm_get_queue_snapshot(struct process_queue_manager *pqm,
1450 uint64_t exception_clear_mask,
1451 void __user *buf,
1452 int *num_qss_entries,
1453 uint32_t *entry_size);
1454
1455 int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm,
1456 uint64_t fence_value,
1457 unsigned int timeout_ms);
1458
1459 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm,
1460 unsigned int qid,
1461 u32 *mqd_size,
1462 u32 *ctl_stack_size);
1463 /* Packet Manager */
1464
1465 #define KFD_FENCE_COMPLETED (100)
1466 #define KFD_FENCE_INIT (10)
1467
1468 /**
1469 * enum kfd_config_dequeue_wait_counts_cmd - Command for configuring
1470 * dequeue wait counts.
1471 *
1472 * @KFD_DEQUEUE_WAIT_INIT: Set optimized dequeue wait counts for a
1473 * certain ASICs. For these ASICs, this is default value used by RESET
1474 * @KFD_DEQUEUE_WAIT_RESET: Reset dequeue wait counts to the optimized value
1475 * for certain ASICs. For others set it to default hardware reset value
1476 * @KFD_DEQUEUE_WAIT_SET_SCH_WAVE: Set context switch latency wait
1477 *
1478 */
1479 enum kfd_config_dequeue_wait_counts_cmd {
1480 KFD_DEQUEUE_WAIT_INIT = 1,
1481 KFD_DEQUEUE_WAIT_RESET = 2,
1482 KFD_DEQUEUE_WAIT_SET_SCH_WAVE = 3
1483 };
1484
1485
1486 struct packet_manager {
1487 struct device_queue_manager *dqm;
1488 struct kernel_queue *priv_queue;
1489 struct mutex lock;
1490 bool allocated;
1491 struct kfd_mem_obj *ib_buffer_obj;
1492 unsigned int ib_size_bytes;
1493 bool is_over_subscription;
1494
1495 const struct packet_manager_funcs *pmf;
1496 };
1497
1498 struct packet_manager_funcs {
1499 /* Support ASIC-specific packet formats for PM4 packets */
1500 int (*map_process)(struct packet_manager *pm, uint32_t *buffer,
1501 struct qcm_process_device *qpd);
1502 int (*runlist)(struct packet_manager *pm, uint32_t *buffer,
1503 uint64_t ib, size_t ib_size_in_dwords, bool chain);
1504 int (*set_resources)(struct packet_manager *pm, uint32_t *buffer,
1505 struct scheduling_resources *res);
1506 int (*map_queues)(struct packet_manager *pm, uint32_t *buffer,
1507 struct queue *q, bool is_static);
1508 int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer,
1509 enum kfd_unmap_queues_filter mode,
1510 uint32_t filter_param, bool reset);
1511 int (*config_dequeue_wait_counts)(struct packet_manager *pm, uint32_t *buffer,
1512 enum kfd_config_dequeue_wait_counts_cmd cmd, uint32_t value);
1513 int (*query_status)(struct packet_manager *pm, uint32_t *buffer,
1514 uint64_t fence_address, uint64_t fence_value);
1515 int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer);
1516
1517 /* Packet sizes */
1518 int map_process_size;
1519 int runlist_size;
1520 int set_resources_size;
1521 int map_queues_size;
1522 int unmap_queues_size;
1523 int config_dequeue_wait_counts_size;
1524 int query_status_size;
1525 int release_mem_size;
1526 };
1527
1528 extern const struct packet_manager_funcs kfd_vi_pm_funcs;
1529 extern const struct packet_manager_funcs kfd_v9_pm_funcs;
1530 extern const struct packet_manager_funcs kfd_aldebaran_pm_funcs;
1531
1532 int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm);
1533 void pm_uninit(struct packet_manager *pm);
1534 int pm_send_set_resources(struct packet_manager *pm,
1535 struct scheduling_resources *res);
1536 int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues);
1537 int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address,
1538 uint64_t fence_value);
1539
1540 int pm_send_unmap_queue(struct packet_manager *pm,
1541 enum kfd_unmap_queues_filter mode,
1542 uint32_t filter_param, bool reset);
1543
1544 void pm_release_ib(struct packet_manager *pm);
1545
1546 int pm_config_dequeue_wait_counts(struct packet_manager *pm,
1547 enum kfd_config_dequeue_wait_counts_cmd cmd,
1548 uint32_t wait_counts_config);
1549
1550 /* Following PM funcs can be shared among VI and AI */
1551 unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size);
1552
1553 uint64_t kfd_get_number_elems(struct kfd_dev *kfd);
1554
1555 /* Events */
1556 extern const struct kfd_event_interrupt_class event_interrupt_class_cik;
1557 extern const struct kfd_event_interrupt_class event_interrupt_class_v9;
1558 extern const struct kfd_event_interrupt_class event_interrupt_class_v9_4_3;
1559 extern const struct kfd_event_interrupt_class event_interrupt_class_v10;
1560 extern const struct kfd_event_interrupt_class event_interrupt_class_v11;
1561 extern const struct kfd_event_interrupt_class event_interrupt_class_v12_1;
1562
1563 extern const struct kfd_device_global_init_class device_global_init_class_cik;
1564
1565 int kfd_event_init_process(struct kfd_process *p);
1566 void kfd_event_free_process(struct kfd_process *p);
1567 int kfd_wait_on_events(struct kfd_process *p,
1568 uint32_t num_events, void __user *data,
1569 bool all, uint32_t *user_timeout_ms,
1570 uint32_t *wait_result);
1571 void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id,
1572 uint32_t valid_id_bits, bool signal_mailbox_updated);
1573 void kfd_signal_hw_exception_event(u32 pasid);
1574 int kfd_set_event(struct kfd_process *p, uint32_t event_id);
1575 int kfd_reset_event(struct kfd_process *p, uint32_t event_id);
1576 int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset);
1577
1578 int kfd_event_create(struct file *devkfd, struct kfd_process *p,
1579 uint32_t event_type, bool auto_reset, uint32_t node_id,
1580 uint32_t *event_id, uint32_t *event_trigger_data,
1581 uint64_t *event_page_offset, uint32_t *event_slot_index);
1582
1583 int kfd_get_num_events(struct kfd_process *p);
1584 int kfd_event_destroy(struct kfd_process *p, uint32_t event_id);
1585
1586 void kfd_signal_vm_fault_event_with_userptr(struct kfd_process *p, uint64_t gpu_va);
1587
1588 void kfd_signal_vm_fault_event(struct kfd_process_device *pdd,
1589 struct kfd_vm_fault_info *info,
1590 struct kfd_hsa_memory_exception_data *data);
1591
1592 void kfd_signal_reset_event(struct kfd_node *dev);
1593
1594 void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid);
1595 void kfd_signal_sigbus_delayed_fn(struct work_struct *work);
1596 void kfd_signal_process_terminate_event(struct kfd_process *p);
1597
kfd_flush_tlb(struct kfd_process_device * pdd)1598 static inline void kfd_flush_tlb(struct kfd_process_device *pdd)
1599 {
1600 struct amdgpu_device *adev = pdd->dev->adev;
1601 struct amdgpu_vm *vm = drm_priv_to_vm(pdd->drm_priv);
1602
1603 amdgpu_vm_flush_compute_tlb(adev, vm, TLB_FLUSH_HEAVYWEIGHT,
1604 pdd->dev->xcc_mask);
1605 }
1606
kfd_flush_tlb_after_unmap(struct kfd_dev * dev)1607 static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev)
1608 {
1609 return KFD_GC_VERSION(dev) >= IP_VERSION(9, 4, 2) ||
1610 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) && dev->sdma_fw_version >= 18) ||
1611 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0);
1612 }
1613
1614 int kfd_send_exception_to_runtime(struct kfd_process *p,
1615 unsigned int queue_id,
1616 uint64_t error_reason);
1617 bool kfd_is_locked(struct kfd_dev *kfd);
1618
1619 /* Compute profile */
1620 void kfd_inc_compute_active(struct kfd_node *dev);
1621 void kfd_dec_compute_active(struct kfd_node *dev);
1622
1623 /* Cgroup Support */
1624 /* Check with device cgroup if @kfd device is accessible */
kfd_devcgroup_check_permission(struct kfd_node * node)1625 static inline int kfd_devcgroup_check_permission(struct kfd_node *node)
1626 {
1627 #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF)
1628 struct drm_device *ddev;
1629
1630 if (node->xcp)
1631 ddev = node->xcp->ddev;
1632 else
1633 ddev = adev_to_drm(node->adev);
1634
1635 return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR,
1636 ddev->render->index,
1637 DEVCG_ACC_WRITE | DEVCG_ACC_READ);
1638 #else
1639 return 0;
1640 #endif
1641 }
1642
kfd_is_first_node(struct kfd_node * node)1643 static inline bool kfd_is_first_node(struct kfd_node *node)
1644 {
1645 return (node == node->kfd->nodes[0]);
1646 }
1647
1648 /* PTL support */
1649 int kfd_ptl_disable_request(struct kfd_process_device *pdd,
1650 struct kfd_process *p);
1651 int kfd_ptl_disable_release(struct kfd_process_device *pdd,
1652 struct kfd_process *p);
1653
1654 /* Debugfs */
1655 #if defined(CONFIG_DEBUG_FS)
1656
1657 void kfd_debugfs_init(void);
1658 void kfd_debugfs_fini(void);
1659 int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data);
1660 int pqm_debugfs_mqds(struct seq_file *m, void *data);
1661 int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data);
1662 int dqm_debugfs_hqds(struct seq_file *m, void *data);
1663 int kfd_debugfs_rls_by_device(struct seq_file *m, void *data);
1664 int pm_debugfs_runlist(struct seq_file *m, void *data);
1665
1666 int kfd_debugfs_hang_hws(struct kfd_node *dev);
1667 int pm_debugfs_hang_hws(struct packet_manager *pm);
1668 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm);
1669
1670 int kfd_debugfs_add_process(struct kfd_process *p);
1671 void kfd_debugfs_remove_process(struct kfd_process *p);
1672
1673 #else
1674
kfd_debugfs_init(void)1675 static inline void kfd_debugfs_init(void) {}
kfd_debugfs_fini(void)1676 static inline void kfd_debugfs_fini(void) {}
kfd_debugfs_add_process(struct kfd_process * p)1677 static inline int kfd_debugfs_add_process(struct kfd_process *p) { return 0; }
kfd_debugfs_remove_process(struct kfd_process * p)1678 static inline void kfd_debugfs_remove_process(struct kfd_process *p) {}
1679
1680 #endif
1681
1682 #endif
1683