1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCA953x 4/8/16/24/40 bit I/O ports 4 * 5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> 6 * Copyright (C) 2007 Marvell International Ltd. 7 * 8 * Derived from drivers/i2c/chips/pca9539.c 9 */ 10 11 #include <linux/atomic.h> 12 #include <linux/bitmap.h> 13 #include <linux/cleanup.h> 14 #include <linux/device.h> 15 #include <linux/errno.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/module.h> 22 #include <linux/mutex.h> 23 #include <linux/pm.h> 24 #include <linux/regmap.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/seq_file.h> 27 #include <linux/slab.h> 28 29 #include <linux/gpio/consumer.h> 30 #include <linux/gpio/driver.h> 31 32 #include <linux/pinctrl/pinconf-generic.h> 33 34 #include <linux/platform_data/pca953x.h> 35 36 #define PCA953X_INPUT 0x00 37 #define PCA953X_OUTPUT 0x01 38 #define PCA953X_INVERT 0x02 39 #define PCA953X_DIRECTION 0x03 40 41 #define TCA6418_INPUT 0x14 42 #define TCA6418_OUTPUT 0x17 43 #define TCA6418_DIRECTION 0x23 44 45 #define REG_ADDR_MASK GENMASK(5, 0) 46 #define REG_ADDR_EXT BIT(6) 47 #define REG_ADDR_AI BIT(7) 48 49 #define PCA957X_IN 0x00 50 #define PCA957X_INVRT 0x01 51 #define PCA957X_BKEN 0x02 52 #define PCA957X_PUPD 0x03 53 #define PCA957X_CFG 0x04 54 #define PCA957X_OUT 0x05 55 #define PCA957X_MSK 0x06 56 #define PCA957X_INTS 0x07 57 58 #define PCAL953X_OUT_STRENGTH 0x20 59 #define PCAL953X_IN_LATCH 0x22 60 #define PCAL953X_PULL_EN 0x23 61 #define PCAL953X_PULL_SEL 0x24 62 #define PCAL953X_INT_MASK 0x25 63 #define PCAL953X_INT_STAT 0x26 64 #define PCAL953X_OUT_CONF 0x27 65 66 #define PCAL6524_INT_EDGE 0x28 67 #define PCAL6524_INT_CLR 0x2a 68 #define PCAL6524_IN_STATUS 0x2b 69 #define PCAL6524_OUT_INDCONF 0x2c 70 #define PCAL6524_DEBOUNCE 0x2d 71 72 #define PCA_GPIO_MASK GENMASK(7, 0) 73 74 #define PCAL_GPIO_MASK GENMASK(4, 0) 75 #define PCAL_PINCTRL_MASK GENMASK(6, 5) 76 77 #define PCA_INT BIT(8) 78 #define PCA_PCAL BIT(9) 79 #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) 80 #define PCA953X_TYPE BIT(12) 81 #define PCA957X_TYPE BIT(13) 82 #define PCAL653X_TYPE BIT(14) 83 #define TCA6418_TYPE BIT(16) 84 #define PCA_TYPE_MASK GENMASK(16, 12) 85 86 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) 87 88 static const struct i2c_device_id pca953x_id[] = { 89 { "pca6408", 8 | PCA953X_TYPE | PCA_INT, }, 90 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, }, 91 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, 92 { "pca9506", 40 | PCA953X_TYPE | PCA_INT, }, 93 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, 94 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, 95 { "pca9536", 4 | PCA953X_TYPE, }, 96 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, 97 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, 98 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, 99 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, 100 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, 101 { "pca9556", 8 | PCA953X_TYPE, }, 102 { "pca9557", 8 | PCA953X_TYPE, }, 103 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, 104 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, 105 { "pca9698", 40 | PCA953X_TYPE, }, 106 107 { "pcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, 108 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 109 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, }, 110 { "pcal6534", 34 | PCAL653X_TYPE | PCA_LATCH_INT, }, 111 { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 112 { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, 113 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 114 115 { "max7310", 8 | PCA953X_TYPE, }, 116 { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, 117 { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, 118 { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, 119 { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, 120 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, 121 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, 122 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, 123 { "tca6418", 18 | TCA6418_TYPE | PCA_INT, }, 124 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, 125 { "tca9538", 8 | PCA953X_TYPE | PCA_INT, }, 126 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, 127 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, 128 { "xra1202", 8 | PCA953X_TYPE }, 129 { } 130 }; 131 MODULE_DEVICE_TABLE(i2c, pca953x_id); 132 133 #ifdef CONFIG_GPIO_PCA953X_IRQ 134 135 #include <linux/acpi.h> 136 #include <linux/dmi.h> 137 138 static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true }; 139 140 static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = { 141 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, 142 { } 143 }; 144 145 static int pca953x_acpi_get_irq(struct device *dev) 146 { 147 int ret; 148 149 ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios); 150 if (ret) 151 dev_warn(dev, "can't add GPIO ACPI mapping\n"); 152 153 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq", 0); 154 if (ret < 0) 155 return ret; 156 157 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); 158 return ret; 159 } 160 161 static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = { 162 { 163 /* 164 * On Intel Galileo Gen 2 board the IRQ pin of one of 165 * the I²C GPIO expanders, which has GpioInt() resource, 166 * is provided as an absolute number instead of being 167 * relative. Since first controller (gpio-sch.c) and 168 * second (gpio-dwapb.c) are at the fixed bases, we may 169 * safely refer to the number in the global space to get 170 * an IRQ out of it. 171 */ 172 .matches = { 173 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 174 }, 175 }, 176 {} 177 }; 178 #endif 179 180 static const struct acpi_device_id pca953x_acpi_ids[] = { 181 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 182 { } 183 }; 184 MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); 185 186 #define MAX_BANK 5 187 #define BANK_SZ 8 188 #define MAX_LINE (MAX_BANK * BANK_SZ) 189 190 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) 191 192 struct pca953x_reg_config { 193 int direction; 194 int output; 195 int input; 196 int invert; 197 }; 198 199 static const struct pca953x_reg_config pca953x_regs = { 200 .direction = PCA953X_DIRECTION, 201 .output = PCA953X_OUTPUT, 202 .input = PCA953X_INPUT, 203 .invert = PCA953X_INVERT, 204 }; 205 206 static const struct pca953x_reg_config pca957x_regs = { 207 .direction = PCA957X_CFG, 208 .output = PCA957X_OUT, 209 .input = PCA957X_IN, 210 .invert = PCA957X_INVRT, 211 }; 212 213 static const struct pca953x_reg_config tca6418_regs = { 214 .direction = TCA6418_DIRECTION, 215 .output = TCA6418_OUTPUT, 216 .input = TCA6418_INPUT, 217 .invert = 0xFF, /* Does not apply */ 218 }; 219 220 struct pca953x_chip { 221 unsigned gpio_start; 222 struct mutex i2c_lock; 223 struct regmap *regmap; 224 225 #ifdef CONFIG_GPIO_PCA953X_IRQ 226 struct mutex irq_lock; 227 DECLARE_BITMAP(irq_mask, MAX_LINE); 228 DECLARE_BITMAP(irq_stat, MAX_LINE); 229 DECLARE_BITMAP(irq_trig_raise, MAX_LINE); 230 DECLARE_BITMAP(irq_trig_fall, MAX_LINE); 231 DECLARE_BITMAP(irq_trig_level_high, MAX_LINE); 232 DECLARE_BITMAP(irq_trig_level_low, MAX_LINE); 233 #endif 234 atomic_t wakeup_path; 235 236 struct i2c_client *client; 237 struct gpio_chip gpio_chip; 238 unsigned long driver_data; 239 struct regulator *regulator; 240 241 const struct pca953x_reg_config *regs; 242 243 u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off); 244 bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg, 245 u32 checkbank); 246 }; 247 248 static int pca953x_bank_shift(struct pca953x_chip *chip) 249 { 250 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); 251 } 252 253 /* 254 * Helper function to get the correct bit mask for a given offset and chip type. 255 * The TCA6418's input, output, and direction banks have a peculiar bit order: 256 * the first byte uses reversed bit order, while the second byte uses standard order. 257 */ 258 static inline u8 pca953x_get_bit_mask(struct pca953x_chip *chip, unsigned int offset) 259 { 260 unsigned int bit_pos_in_bank = offset % BANK_SZ; 261 int msb = BANK_SZ - 1; 262 263 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE && offset <= msb) 264 return BIT(msb - bit_pos_in_bank); 265 266 return BIT(bit_pos_in_bank); 267 } 268 269 #define PCA953x_BANK_INPUT BIT(0) 270 #define PCA953x_BANK_OUTPUT BIT(1) 271 #define PCA953x_BANK_POLARITY BIT(2) 272 #define PCA953x_BANK_CONFIG BIT(3) 273 274 #define PCA957x_BANK_INPUT BIT(0) 275 #define PCA957x_BANK_POLARITY BIT(1) 276 #define PCA957x_BANK_BUSHOLD BIT(2) 277 #define PCA957x_BANK_CONFIG BIT(4) 278 #define PCA957x_BANK_OUTPUT BIT(5) 279 280 #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) 281 #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) 282 #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) 283 #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) 284 #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) 285 286 /* 287 * We care about the following registers: 288 * - Standard set, below 0x40, each port can be replicated up to 8 times 289 * - PCA953x standard 290 * Input port 0x00 + 0 * bank_size R 291 * Output port 0x00 + 1 * bank_size RW 292 * Polarity Inversion port 0x00 + 2 * bank_size RW 293 * Configuration port 0x00 + 3 * bank_size RW 294 * - PCA957x with mixed up registers 295 * Input port 0x00 + 0 * bank_size R 296 * Polarity Inversion port 0x00 + 1 * bank_size RW 297 * Bus hold port 0x00 + 2 * bank_size RW 298 * Configuration port 0x00 + 4 * bank_size RW 299 * Output port 0x00 + 5 * bank_size RW 300 * 301 * - Extended set, above 0x40, often chip specific. 302 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: 303 * Input latch register 0x40 + 2 * bank_size RW 304 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW 305 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW 306 * Interrupt mask register 0x40 + 5 * bank_size RW 307 * Interrupt status register 0x40 + 6 * bank_size R 308 * 309 * - Registers with bit 0x80 set, the AI bit (auto increment) 310 * The bit is cleared and the registers fall into one of the 311 * categories above. 312 */ 313 314 static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, 315 u32 checkbank) 316 { 317 int bank_shift = pca953x_bank_shift(chip); 318 int bank = (reg & REG_ADDR_MASK) >> bank_shift; 319 int offset = reg & (BIT(bank_shift) - 1); 320 321 /* Special PCAL extended register check. */ 322 if (reg & REG_ADDR_EXT) { 323 if (!(chip->driver_data & PCA_PCAL)) 324 return false; 325 bank += 8; 326 } 327 328 /* Register is not in the matching bank. */ 329 if (!(BIT(bank) & checkbank)) 330 return false; 331 332 /* Register is not within allowed range of bank. */ 333 if (offset >= NBANK(chip)) 334 return false; 335 336 return true; 337 } 338 339 /* 340 * Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the 341 * same register layout as the PCAL6524, the spacing of the registers has been 342 * fundamentally altered by compacting them and thus does not obey the same 343 * rules, including being able to use bit shifting to determine bank. These 344 * chips hence need special handling here. 345 */ 346 static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg, 347 u32 checkbank) 348 { 349 int bank_shift; 350 int bank; 351 int offset; 352 353 if (reg >= 0x54) { 354 /* 355 * Handle lack of reserved registers after output port 356 * configuration register to form a bank. 357 */ 358 reg -= 0x54; 359 bank_shift = 16; 360 } else if (reg >= 0x30) { 361 /* 362 * Reserved block between 14h and 2Fh does not align on 363 * expected bank boundaries like other devices. 364 */ 365 reg -= 0x30; 366 bank_shift = 8; 367 } else { 368 bank_shift = 0; 369 } 370 371 bank = bank_shift + reg / NBANK(chip); 372 offset = reg % NBANK(chip); 373 374 /* Register is not in the matching bank. */ 375 if (!(BIT(bank) & checkbank)) 376 return false; 377 378 /* Register is not within allowed range of bank. */ 379 if (offset >= NBANK(chip)) 380 return false; 381 382 return true; 383 } 384 385 /* TCA6418 breaks the PCA953x register order rule */ 386 static bool tca6418_check_register(struct pca953x_chip *chip, unsigned int reg, 387 u32 access_type_mask) 388 { 389 /* Valid Input Registers - BIT(0) for readable access */ 390 if (reg >= TCA6418_INPUT && reg < (TCA6418_INPUT + NBANK(chip))) 391 return (access_type_mask & BIT(0)); 392 393 /* Valid Output Registers - BIT(1) for writeable access */ 394 if (reg >= TCA6418_OUTPUT && reg < (TCA6418_OUTPUT + NBANK(chip))) 395 return (access_type_mask & (BIT(0) | BIT(1))); 396 397 /* Valid Direction Registers - BIT(2) for volatile access */ 398 if (reg >= TCA6418_DIRECTION && reg < (TCA6418_DIRECTION + NBANK(chip))) 399 return (access_type_mask & (BIT(0) | BIT(1))); 400 401 return false; 402 } 403 404 static bool pca953x_readable_register(struct device *dev, unsigned int reg) 405 { 406 struct pca953x_chip *chip = dev_get_drvdata(dev); 407 u32 bank; 408 409 switch (PCA_CHIP_TYPE(chip->driver_data)) { 410 case PCA957X_TYPE: 411 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | 412 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | 413 PCA957x_BANK_BUSHOLD; 414 break; 415 case TCA6418_TYPE: 416 /* BIT(0) to indicate read access */ 417 return tca6418_check_register(chip, reg, BIT(0)); 418 default: 419 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | 420 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; 421 break; 422 } 423 424 if (chip->driver_data & PCA_PCAL) { 425 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 426 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | 427 PCAL9xxx_BANK_IRQ_STAT; 428 } 429 430 return chip->check_reg(chip, reg, bank); 431 } 432 433 static bool pca953x_writeable_register(struct device *dev, unsigned int reg) 434 { 435 struct pca953x_chip *chip = dev_get_drvdata(dev); 436 u32 bank; 437 438 switch (PCA_CHIP_TYPE(chip->driver_data)) { 439 case PCA957X_TYPE: 440 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | 441 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; 442 break; 443 case TCA6418_TYPE: 444 /* BIT(1) for write access */ 445 return tca6418_check_register(chip, reg, BIT(1)); 446 default: 447 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | 448 PCA953x_BANK_CONFIG; 449 break; 450 } 451 452 if (chip->driver_data & PCA_PCAL) 453 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 454 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; 455 456 return chip->check_reg(chip, reg, bank); 457 } 458 459 static bool pca953x_volatile_register(struct device *dev, unsigned int reg) 460 { 461 struct pca953x_chip *chip = dev_get_drvdata(dev); 462 u32 bank; 463 464 switch (PCA_CHIP_TYPE(chip->driver_data)) { 465 case PCA957X_TYPE: 466 bank = PCA957x_BANK_INPUT; 467 break; 468 case TCA6418_TYPE: 469 /* BIT(2) for volatile access */ 470 return tca6418_check_register(chip, reg, BIT(2)); 471 default: 472 bank = PCA953x_BANK_INPUT; 473 break; 474 } 475 476 if (chip->driver_data & PCA_PCAL) 477 bank |= PCAL9xxx_BANK_IRQ_STAT; 478 479 return chip->check_reg(chip, reg, bank); 480 } 481 482 static const struct regmap_config pca953x_i2c_regmap = { 483 .reg_bits = 8, 484 .val_bits = 8, 485 486 .use_single_read = true, 487 .use_single_write = true, 488 489 .readable_reg = pca953x_readable_register, 490 .writeable_reg = pca953x_writeable_register, 491 .volatile_reg = pca953x_volatile_register, 492 493 .disable_locking = true, 494 .cache_type = REGCACHE_MAPLE, 495 .max_register = 0x7f, 496 }; 497 498 static const struct regmap_config pca953x_ai_i2c_regmap = { 499 .reg_bits = 8, 500 .val_bits = 8, 501 502 .read_flag_mask = REG_ADDR_AI, 503 .write_flag_mask = REG_ADDR_AI, 504 505 .readable_reg = pca953x_readable_register, 506 .writeable_reg = pca953x_writeable_register, 507 .volatile_reg = pca953x_volatile_register, 508 509 .disable_locking = true, 510 .cache_type = REGCACHE_MAPLE, 511 .max_register = 0x7f, 512 }; 513 514 static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off) 515 { 516 int bank_shift = pca953x_bank_shift(chip); 517 int addr = (reg & PCAL_GPIO_MASK) << bank_shift; 518 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; 519 u8 regaddr = pinctrl | addr | (off / BANK_SZ); 520 521 return regaddr; 522 } 523 524 /* 525 * The PCAL6534 and compatible chips have altered bank alignment that doesn't 526 * fit within the bit shifting scheme used for other devices. 527 */ 528 static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off) 529 { 530 int addr; 531 int pinctrl; 532 533 addr = (reg & PCAL_GPIO_MASK) * NBANK(chip); 534 535 switch (reg) { 536 case PCAL953X_OUT_STRENGTH: 537 case PCAL953X_IN_LATCH: 538 case PCAL953X_PULL_EN: 539 case PCAL953X_PULL_SEL: 540 case PCAL953X_INT_MASK: 541 case PCAL953X_INT_STAT: 542 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20; 543 break; 544 case PCAL6524_INT_EDGE: 545 case PCAL6524_INT_CLR: 546 case PCAL6524_IN_STATUS: 547 case PCAL6524_OUT_INDCONF: 548 case PCAL6524_DEBOUNCE: 549 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c; 550 break; 551 default: 552 pinctrl = 0; 553 break; 554 } 555 556 return pinctrl + addr + (off / BANK_SZ); 557 } 558 559 static u8 tca6418_recalc_addr(struct pca953x_chip *chip, int reg_base, int offset) 560 { 561 /* 562 * reg_base will be TCA6418_INPUT, TCA6418_OUTPUT, or TCA6418_DIRECTION 563 * offset is the global GPIO line offset (0-17) 564 * BANK_SZ is 8 for TCA6418 (8 bits per register bank) 565 */ 566 return reg_base + (offset / BANK_SZ); 567 } 568 569 static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 570 { 571 u8 regaddr = chip->recalc_addr(chip, reg, 0); 572 u8 value[MAX_BANK]; 573 int i, ret; 574 575 for (i = 0; i < NBANK(chip); i++) 576 value[i] = bitmap_get_value8(val, i * BANK_SZ); 577 578 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip)); 579 if (ret < 0) { 580 dev_err(&chip->client->dev, "failed writing register: %d\n", ret); 581 return ret; 582 } 583 584 return 0; 585 } 586 587 static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 588 { 589 u8 regaddr = chip->recalc_addr(chip, reg, 0); 590 u8 value[MAX_BANK]; 591 int i, ret; 592 593 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip)); 594 if (ret < 0) { 595 dev_err(&chip->client->dev, "failed reading register: %d\n", ret); 596 return ret; 597 } 598 599 for (i = 0; i < NBANK(chip); i++) 600 bitmap_set_value8(val, value[i], i * BANK_SZ); 601 602 return 0; 603 } 604 605 static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) 606 { 607 struct pca953x_chip *chip = gpiochip_get_data(gc); 608 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 609 u8 bit = pca953x_get_bit_mask(chip, off); 610 611 guard(mutex)(&chip->i2c_lock); 612 613 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE) 614 return regmap_update_bits(chip->regmap, dirreg, bit, 0); 615 616 return regmap_update_bits(chip->regmap, dirreg, bit, bit); 617 } 618 619 static int pca953x_gpio_direction_output(struct gpio_chip *gc, 620 unsigned off, int val) 621 { 622 struct pca953x_chip *chip = gpiochip_get_data(gc); 623 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 624 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 625 u8 bit = pca953x_get_bit_mask(chip, off); 626 int ret; 627 628 guard(mutex)(&chip->i2c_lock); 629 630 /* set output level */ 631 ret = regmap_update_bits(chip->regmap, outreg, bit, val ? bit : 0); 632 if (ret) 633 return ret; 634 635 /* 636 * then direction 637 * (in/out logic is inverted on TCA6418) 638 */ 639 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE) 640 return regmap_update_bits(chip->regmap, dirreg, bit, bit); 641 642 return regmap_update_bits(chip->regmap, dirreg, bit, 0); 643 } 644 645 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) 646 { 647 struct pca953x_chip *chip = gpiochip_get_data(gc); 648 u8 inreg = chip->recalc_addr(chip, chip->regs->input, off); 649 u8 bit = pca953x_get_bit_mask(chip, off); 650 u32 reg_val; 651 int ret; 652 653 scoped_guard(mutex, &chip->i2c_lock) 654 ret = regmap_read(chip->regmap, inreg, ®_val); 655 if (ret < 0) 656 return ret; 657 658 return !!(reg_val & bit); 659 } 660 661 static int pca953x_gpio_set_value(struct gpio_chip *gc, unsigned int off, 662 int val) 663 { 664 struct pca953x_chip *chip = gpiochip_get_data(gc); 665 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 666 u8 bit = pca953x_get_bit_mask(chip, off); 667 668 guard(mutex)(&chip->i2c_lock); 669 670 return regmap_update_bits(chip->regmap, outreg, bit, val ? bit : 0); 671 } 672 673 static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) 674 { 675 struct pca953x_chip *chip = gpiochip_get_data(gc); 676 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 677 u8 bit = pca953x_get_bit_mask(chip, off); 678 u32 reg_val; 679 int ret; 680 681 scoped_guard(mutex, &chip->i2c_lock) 682 ret = regmap_read(chip->regmap, dirreg, ®_val); 683 if (ret < 0) 684 return ret; 685 686 /* (in/out logic is inverted on TCA6418) */ 687 if (reg_val & bit) { 688 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE) 689 return GPIO_LINE_DIRECTION_OUT; 690 691 return GPIO_LINE_DIRECTION_IN; 692 } 693 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE) 694 return GPIO_LINE_DIRECTION_IN; 695 696 return GPIO_LINE_DIRECTION_OUT; 697 } 698 699 static int pca953x_gpio_get_multiple(struct gpio_chip *gc, 700 unsigned long *mask, unsigned long *bits) 701 { 702 struct pca953x_chip *chip = gpiochip_get_data(gc); 703 DECLARE_BITMAP(reg_val, MAX_LINE); 704 int ret; 705 706 scoped_guard(mutex, &chip->i2c_lock) 707 ret = pca953x_read_regs(chip, chip->regs->input, reg_val); 708 if (ret) 709 return ret; 710 711 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio); 712 return 0; 713 } 714 715 static int pca953x_gpio_set_multiple(struct gpio_chip *gc, 716 unsigned long *mask, unsigned long *bits) 717 { 718 struct pca953x_chip *chip = gpiochip_get_data(gc); 719 DECLARE_BITMAP(reg_val, MAX_LINE); 720 int ret; 721 722 guard(mutex)(&chip->i2c_lock); 723 724 ret = pca953x_read_regs(chip, chip->regs->output, reg_val); 725 if (ret) 726 return ret; 727 728 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio); 729 730 return pca953x_write_regs(chip, chip->regs->output, reg_val); 731 } 732 733 static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, 734 unsigned int offset, 735 unsigned long config) 736 { 737 enum pin_config_param param = pinconf_to_config_param(config); 738 u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset); 739 u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset); 740 u8 bit = BIT(offset % BANK_SZ); 741 int ret; 742 743 /* 744 * pull-up/pull-down configuration requires PCAL extended 745 * registers 746 */ 747 if (!(chip->driver_data & PCA_PCAL)) 748 return -ENOTSUPP; 749 750 guard(mutex)(&chip->i2c_lock); 751 752 /* Configure pull-up/pull-down */ 753 if (param == PIN_CONFIG_BIAS_PULL_UP) 754 ret = regmap_update_bits(chip->regmap, pull_sel_reg, bit, bit); 755 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 756 ret = regmap_update_bits(chip->regmap, pull_sel_reg, bit, 0); 757 else 758 ret = 0; 759 if (ret) 760 return ret; 761 762 /* Disable/Enable pull-up/pull-down */ 763 if (param == PIN_CONFIG_BIAS_DISABLE) 764 return regmap_update_bits(chip->regmap, pull_en_reg, bit, 0); 765 else 766 return regmap_update_bits(chip->regmap, pull_en_reg, bit, bit); 767 } 768 769 static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 770 unsigned long config) 771 { 772 struct pca953x_chip *chip = gpiochip_get_data(gc); 773 774 switch (pinconf_to_config_param(config)) { 775 case PIN_CONFIG_BIAS_PULL_UP: 776 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 777 case PIN_CONFIG_BIAS_PULL_DOWN: 778 case PIN_CONFIG_BIAS_DISABLE: 779 return pca953x_gpio_set_pull_up_down(chip, offset, config); 780 default: 781 return -ENOTSUPP; 782 } 783 } 784 785 static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) 786 { 787 struct gpio_chip *gc = &chip->gpio_chip; 788 789 gc->direction_input = pca953x_gpio_direction_input; 790 gc->direction_output = pca953x_gpio_direction_output; 791 gc->get = pca953x_gpio_get_value; 792 gc->set = pca953x_gpio_set_value; 793 gc->get_direction = pca953x_gpio_get_direction; 794 gc->get_multiple = pca953x_gpio_get_multiple; 795 gc->set_multiple = pca953x_gpio_set_multiple; 796 gc->set_config = pca953x_gpio_set_config; 797 gc->can_sleep = true; 798 799 gc->base = chip->gpio_start; 800 gc->ngpio = gpios; 801 gc->label = dev_name(&chip->client->dev); 802 gc->parent = &chip->client->dev; 803 gc->owner = THIS_MODULE; 804 } 805 806 #ifdef CONFIG_GPIO_PCA953X_IRQ 807 static void pca953x_irq_mask(struct irq_data *d) 808 { 809 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 810 struct pca953x_chip *chip = gpiochip_get_data(gc); 811 irq_hw_number_t hwirq = irqd_to_hwirq(d); 812 813 clear_bit(hwirq, chip->irq_mask); 814 gpiochip_disable_irq(gc, hwirq); 815 } 816 817 static void pca953x_irq_unmask(struct irq_data *d) 818 { 819 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 820 struct pca953x_chip *chip = gpiochip_get_data(gc); 821 irq_hw_number_t hwirq = irqd_to_hwirq(d); 822 823 gpiochip_enable_irq(gc, hwirq); 824 set_bit(hwirq, chip->irq_mask); 825 } 826 827 static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) 828 { 829 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 830 struct pca953x_chip *chip = gpiochip_get_data(gc); 831 832 if (on) 833 atomic_inc(&chip->wakeup_path); 834 else 835 atomic_dec(&chip->wakeup_path); 836 837 return irq_set_irq_wake(chip->client->irq, on); 838 } 839 840 static void pca953x_irq_bus_lock(struct irq_data *d) 841 { 842 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 843 struct pca953x_chip *chip = gpiochip_get_data(gc); 844 845 mutex_lock(&chip->irq_lock); 846 } 847 848 static void pca953x_irq_bus_sync_unlock(struct irq_data *d) 849 { 850 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 851 struct pca953x_chip *chip = gpiochip_get_data(gc); 852 DECLARE_BITMAP(irq_mask, MAX_LINE); 853 DECLARE_BITMAP(reg_direction, MAX_LINE); 854 int level; 855 856 if (chip->driver_data & PCA_PCAL) { 857 DECLARE_BITMAP(latched_inputs, MAX_LINE); 858 guard(mutex)(&chip->i2c_lock); 859 860 /* Enable latch on edge-triggered interrupt-enabled inputs */ 861 bitmap_or(latched_inputs, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio); 862 bitmap_and(latched_inputs, latched_inputs, chip->irq_mask, gc->ngpio); 863 pca953x_write_regs(chip, PCAL953X_IN_LATCH, latched_inputs); 864 865 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio); 866 867 /* Unmask enabled interrupts */ 868 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask); 869 } 870 871 /* Switch direction to input if needed */ 872 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 873 874 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio); 875 bitmap_or(irq_mask, irq_mask, chip->irq_trig_level_high, gc->ngpio); 876 bitmap_or(irq_mask, irq_mask, chip->irq_trig_level_low, gc->ngpio); 877 bitmap_complement(reg_direction, reg_direction, gc->ngpio); 878 bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio); 879 880 /* Look for any newly setup interrupt */ 881 for_each_set_bit(level, irq_mask, gc->ngpio) 882 pca953x_gpio_direction_input(&chip->gpio_chip, level); 883 884 mutex_unlock(&chip->irq_lock); 885 } 886 887 static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) 888 { 889 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 890 struct pca953x_chip *chip = gpiochip_get_data(gc); 891 struct device *dev = &chip->client->dev; 892 irq_hw_number_t hwirq = irqd_to_hwirq(d); 893 894 if (!(type & IRQ_TYPE_SENSE_MASK)) { 895 dev_err(dev, "irq %d: unsupported type %d\n", d->irq, type); 896 return -EINVAL; 897 } 898 899 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING); 900 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING); 901 assign_bit(hwirq, chip->irq_trig_level_low, type & IRQ_TYPE_LEVEL_LOW); 902 assign_bit(hwirq, chip->irq_trig_level_high, type & IRQ_TYPE_LEVEL_HIGH); 903 904 return 0; 905 } 906 907 static void pca953x_irq_shutdown(struct irq_data *d) 908 { 909 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 910 struct pca953x_chip *chip = gpiochip_get_data(gc); 911 irq_hw_number_t hwirq = irqd_to_hwirq(d); 912 913 clear_bit(hwirq, chip->irq_trig_raise); 914 clear_bit(hwirq, chip->irq_trig_fall); 915 clear_bit(hwirq, chip->irq_trig_level_low); 916 clear_bit(hwirq, chip->irq_trig_level_high); 917 } 918 919 static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p) 920 { 921 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 922 923 seq_puts(p, dev_name(gc->parent)); 924 } 925 926 static const struct irq_chip pca953x_irq_chip = { 927 .irq_mask = pca953x_irq_mask, 928 .irq_unmask = pca953x_irq_unmask, 929 .irq_set_wake = pca953x_irq_set_wake, 930 .irq_bus_lock = pca953x_irq_bus_lock, 931 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, 932 .irq_set_type = pca953x_irq_set_type, 933 .irq_shutdown = pca953x_irq_shutdown, 934 .irq_print_chip = pca953x_irq_print_chip, 935 .flags = IRQCHIP_IMMUTABLE, 936 GPIOCHIP_IRQ_RESOURCE_HELPERS, 937 }; 938 939 static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending) 940 { 941 struct gpio_chip *gc = &chip->gpio_chip; 942 DECLARE_BITMAP(reg_direction, MAX_LINE); 943 DECLARE_BITMAP(old_stat, MAX_LINE); 944 DECLARE_BITMAP(cur_stat, MAX_LINE); 945 DECLARE_BITMAP(new_stat, MAX_LINE); 946 DECLARE_BITMAP(trigger, MAX_LINE); 947 DECLARE_BITMAP(edges, MAX_LINE); 948 int ret; 949 950 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 951 if (ret) 952 return false; 953 954 /* Remove output pins from the equation */ 955 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 956 957 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio); 958 959 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio); 960 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio); 961 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio); 962 963 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio); 964 965 if (bitmap_empty(chip->irq_trig_level_high, gc->ngpio) && 966 bitmap_empty(chip->irq_trig_level_low, gc->ngpio)) { 967 if (bitmap_empty(trigger, gc->ngpio)) 968 return false; 969 } 970 971 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio); 972 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio); 973 bitmap_or(edges, old_stat, cur_stat, gc->ngpio); 974 bitmap_and(pending, edges, trigger, gc->ngpio); 975 976 bitmap_and(cur_stat, new_stat, chip->irq_trig_level_high, gc->ngpio); 977 bitmap_and(cur_stat, cur_stat, chip->irq_mask, gc->ngpio); 978 bitmap_or(pending, pending, cur_stat, gc->ngpio); 979 980 bitmap_complement(cur_stat, new_stat, gc->ngpio); 981 bitmap_and(cur_stat, cur_stat, reg_direction, gc->ngpio); 982 bitmap_and(old_stat, cur_stat, chip->irq_trig_level_low, gc->ngpio); 983 bitmap_and(old_stat, old_stat, chip->irq_mask, gc->ngpio); 984 bitmap_or(pending, pending, old_stat, gc->ngpio); 985 986 return !bitmap_empty(pending, gc->ngpio); 987 } 988 989 static irqreturn_t pca953x_irq_handler(int irq, void *devid) 990 { 991 struct pca953x_chip *chip = devid; 992 struct gpio_chip *gc = &chip->gpio_chip; 993 DECLARE_BITMAP(pending, MAX_LINE); 994 int level; 995 bool ret; 996 997 bitmap_zero(pending, MAX_LINE); 998 999 scoped_guard(mutex, &chip->i2c_lock) 1000 ret = pca953x_irq_pending(chip, pending); 1001 if (ret) { 1002 ret = 0; 1003 1004 for_each_set_bit(level, pending, gc->ngpio) { 1005 int nested_irq = irq_find_mapping(gc->irq.domain, level); 1006 1007 if (unlikely(nested_irq <= 0)) { 1008 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); 1009 continue; 1010 } 1011 1012 handle_nested_irq(nested_irq); 1013 ret = 1; 1014 } 1015 } 1016 1017 return IRQ_RETVAL(ret); 1018 } 1019 1020 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) 1021 { 1022 struct i2c_client *client = chip->client; 1023 struct device *dev = &client->dev; 1024 DECLARE_BITMAP(reg_direction, MAX_LINE); 1025 DECLARE_BITMAP(irq_stat, MAX_LINE); 1026 struct gpio_chip *gc = &chip->gpio_chip; 1027 struct gpio_irq_chip *girq; 1028 int ret; 1029 1030 if (dmi_first_match(pca953x_dmi_acpi_irq_info)) { 1031 ret = pca953x_acpi_get_irq(dev); 1032 if (ret > 0) 1033 client->irq = ret; 1034 } 1035 1036 if (!client->irq) 1037 return 0; 1038 1039 if (irq_base == -1) 1040 return 0; 1041 1042 if (!(chip->driver_data & PCA_INT)) 1043 return 0; 1044 1045 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat); 1046 if (ret) 1047 return ret; 1048 1049 /* 1050 * There is no way to know which GPIO line generated the 1051 * interrupt. We have to rely on the previous read for 1052 * this purpose. 1053 */ 1054 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 1055 bitmap_and(chip->irq_stat, irq_stat, reg_direction, gc->ngpio); 1056 mutex_init(&chip->irq_lock); 1057 1058 girq = &chip->gpio_chip.irq; 1059 gpio_irq_chip_set_chip(girq, &pca953x_irq_chip); 1060 /* This will let us handle the parent IRQ in the driver */ 1061 girq->parent_handler = NULL; 1062 girq->num_parents = 0; 1063 girq->parents = NULL; 1064 girq->default_type = IRQ_TYPE_NONE; 1065 girq->handler = handle_simple_irq; 1066 girq->threaded = true; 1067 girq->first = irq_base; /* FIXME: get rid of this */ 1068 1069 ret = devm_request_threaded_irq(dev, client->irq, NULL, pca953x_irq_handler, 1070 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), 1071 chip); 1072 if (ret) 1073 return dev_err_probe(dev, ret, "failed to request irq\n"); 1074 1075 return 0; 1076 } 1077 1078 #else /* CONFIG_GPIO_PCA953X_IRQ */ 1079 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) 1080 { 1081 struct i2c_client *client = chip->client; 1082 struct device *dev = &client->dev; 1083 1084 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) 1085 dev_warn(dev, "interrupt support not compiled in\n"); 1086 1087 return 0; 1088 } 1089 #endif 1090 1091 static int device_pca95xx_init(struct pca953x_chip *chip) 1092 { 1093 DECLARE_BITMAP(val, MAX_LINE); 1094 u8 regaddr; 1095 int ret; 1096 1097 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 1098 ret = regcache_sync_region(chip->regmap, regaddr, 1099 regaddr + NBANK(chip) - 1); 1100 if (ret) 1101 return ret; 1102 1103 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1104 ret = regcache_sync_region(chip->regmap, regaddr, 1105 regaddr + NBANK(chip) - 1); 1106 if (ret) 1107 return ret; 1108 1109 /* clear polarity inversion */ 1110 bitmap_zero(val, MAX_LINE); 1111 1112 return pca953x_write_regs(chip, chip->regs->invert, val); 1113 } 1114 1115 static int device_pca957x_init(struct pca953x_chip *chip) 1116 { 1117 DECLARE_BITMAP(val, MAX_LINE); 1118 unsigned int i; 1119 int ret; 1120 1121 ret = device_pca95xx_init(chip); 1122 if (ret) 1123 return ret; 1124 1125 /* To enable register 6, 7 to control pull up and pull down */ 1126 for (i = 0; i < NBANK(chip); i++) 1127 bitmap_set_value8(val, 0x02, i * BANK_SZ); 1128 1129 return pca953x_write_regs(chip, PCA957X_BKEN, val); 1130 } 1131 1132 static void pca953x_disable_regulator(void *reg) 1133 { 1134 regulator_disable(reg); 1135 } 1136 1137 static int pca953x_get_and_enable_regulator(struct pca953x_chip *chip) 1138 { 1139 struct device *dev = &chip->client->dev; 1140 struct regulator *reg = chip->regulator; 1141 int ret; 1142 1143 reg = devm_regulator_get(dev, "vcc"); 1144 if (IS_ERR(reg)) 1145 return dev_err_probe(dev, PTR_ERR(reg), "reg get err\n"); 1146 1147 ret = regulator_enable(reg); 1148 if (ret) 1149 return dev_err_probe(dev, ret, "reg en err\n"); 1150 1151 ret = devm_add_action_or_reset(dev, pca953x_disable_regulator, reg); 1152 if (ret) 1153 return ret; 1154 1155 chip->regulator = reg; 1156 return 0; 1157 } 1158 1159 static int pca953x_probe(struct i2c_client *client) 1160 { 1161 struct device *dev = &client->dev; 1162 struct pca953x_platform_data *pdata; 1163 struct pca953x_chip *chip; 1164 int irq_base; 1165 int ret; 1166 const struct regmap_config *regmap_config; 1167 1168 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 1169 if (chip == NULL) 1170 return -ENOMEM; 1171 1172 pdata = dev_get_platdata(dev); 1173 if (pdata) { 1174 irq_base = pdata->irq_base; 1175 chip->gpio_start = pdata->gpio_base; 1176 } else { 1177 struct gpio_desc *reset_gpio; 1178 1179 chip->gpio_start = -1; 1180 irq_base = 0; 1181 1182 /* 1183 * See if we need to de-assert a reset pin. 1184 * 1185 * There is no known ACPI-enabled platforms that are 1186 * using "reset" GPIO. Otherwise any of those platform 1187 * must use _DSD method with corresponding property. 1188 */ 1189 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1190 if (IS_ERR(reset_gpio)) 1191 return dev_err_probe(dev, PTR_ERR(reset_gpio), 1192 "Failed to get reset gpio\n"); 1193 } 1194 1195 chip->client = client; 1196 chip->driver_data = (uintptr_t)i2c_get_match_data(client); 1197 if (!chip->driver_data) 1198 return -ENODEV; 1199 1200 ret = pca953x_get_and_enable_regulator(chip); 1201 if (ret) 1202 return ret; 1203 1204 i2c_set_clientdata(client, chip); 1205 1206 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); 1207 1208 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 1209 dev_info(dev, "using auto increment\n"); 1210 regmap_config = &pca953x_ai_i2c_regmap; 1211 } else { 1212 dev_info(dev, "using no auto increment\n"); 1213 regmap_config = &pca953x_i2c_regmap; 1214 } 1215 1216 switch (PCA_CHIP_TYPE(chip->driver_data)) { 1217 case PCAL653X_TYPE: 1218 chip->recalc_addr = pcal6534_recalc_addr; 1219 chip->check_reg = pcal6534_check_register; 1220 break; 1221 case TCA6418_TYPE: 1222 chip->recalc_addr = tca6418_recalc_addr; 1223 /* 1224 * We don't assign chip->check_reg = tca6418_check_register directly here. 1225 * Instead, the wrappers handle the dispatch based on PCA_CHIP_TYPE. 1226 */ 1227 break; 1228 default: 1229 chip->recalc_addr = pca953x_recalc_addr; 1230 chip->check_reg = pca953x_check_register; 1231 break; 1232 } 1233 1234 chip->regmap = devm_regmap_init_i2c(client, regmap_config); 1235 if (IS_ERR(chip->regmap)) 1236 return PTR_ERR(chip->regmap); 1237 1238 regcache_mark_dirty(chip->regmap); 1239 1240 mutex_init(&chip->i2c_lock); 1241 /* 1242 * In case we have an i2c-mux controlled by a GPIO provided by an 1243 * expander using the same driver higher on the device tree, read the 1244 * i2c adapter nesting depth and use the retrieved value as lockdep 1245 * subclass for chip->i2c_lock. 1246 * 1247 * REVISIT: This solution is not complete. It protects us from lockdep 1248 * false positives when the expander controlling the i2c-mux is on 1249 * a different level on the device tree, but not when it's on the same 1250 * level on a different branch (in which case the subclass number 1251 * would be the same). 1252 * 1253 * TODO: Once a correct solution is developed, a similar fix should be 1254 * applied to all other i2c-controlled GPIO expanders (and potentially 1255 * regmap-i2c). 1256 */ 1257 lockdep_set_subclass(&chip->i2c_lock, 1258 i2c_adapter_depth(client->adapter)); 1259 1260 /* 1261 * initialize cached registers from their original values. 1262 * we can't share this chip with another i2c master. 1263 */ 1264 switch (PCA_CHIP_TYPE(chip->driver_data)) { 1265 case PCA957X_TYPE: 1266 chip->regs = &pca957x_regs; 1267 ret = device_pca957x_init(chip); 1268 break; 1269 case TCA6418_TYPE: 1270 chip->regs = &tca6418_regs; 1271 break; 1272 default: 1273 chip->regs = &pca953x_regs; 1274 ret = device_pca95xx_init(chip); 1275 break; 1276 } 1277 if (ret) 1278 return ret; 1279 1280 ret = pca953x_irq_setup(chip, irq_base); 1281 if (ret) 1282 return ret; 1283 1284 return devm_gpiochip_add_data(dev, &chip->gpio_chip, chip); 1285 } 1286 1287 static int pca953x_regcache_sync(struct pca953x_chip *chip) 1288 { 1289 struct device *dev = &chip->client->dev; 1290 int ret; 1291 u8 regaddr; 1292 1293 /* 1294 * The ordering between direction and output is important, 1295 * sync these registers first and only then sync the rest. 1296 */ 1297 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1298 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1299 if (ret) { 1300 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); 1301 return ret; 1302 } 1303 1304 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 1305 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1306 if (ret) { 1307 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); 1308 return ret; 1309 } 1310 1311 #ifdef CONFIG_GPIO_PCA953X_IRQ 1312 if (chip->driver_data & PCA_PCAL) { 1313 regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0); 1314 ret = regcache_sync_region(chip->regmap, regaddr, 1315 regaddr + NBANK(chip) - 1); 1316 if (ret) { 1317 dev_err(dev, "Failed to sync INT latch registers: %d\n", 1318 ret); 1319 return ret; 1320 } 1321 1322 regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0); 1323 ret = regcache_sync_region(chip->regmap, regaddr, 1324 regaddr + NBANK(chip) - 1); 1325 if (ret) { 1326 dev_err(dev, "Failed to sync INT mask registers: %d\n", 1327 ret); 1328 return ret; 1329 } 1330 } 1331 #endif 1332 1333 return 0; 1334 } 1335 1336 static int pca953x_restore_context(struct pca953x_chip *chip) 1337 { 1338 int ret; 1339 1340 guard(mutex)(&chip->i2c_lock); 1341 1342 if (chip->client->irq > 0) 1343 enable_irq(chip->client->irq); 1344 regcache_cache_only(chip->regmap, false); 1345 regcache_mark_dirty(chip->regmap); 1346 ret = pca953x_regcache_sync(chip); 1347 if (ret) 1348 return ret; 1349 1350 return regcache_sync(chip->regmap); 1351 } 1352 1353 static void pca953x_save_context(struct pca953x_chip *chip) 1354 { 1355 guard(mutex)(&chip->i2c_lock); 1356 1357 /* Disable IRQ to prevent early triggering while regmap "cache only" is on */ 1358 if (chip->client->irq > 0) 1359 disable_irq(chip->client->irq); 1360 regcache_cache_only(chip->regmap, true); 1361 } 1362 1363 static int pca953x_suspend(struct device *dev) 1364 { 1365 struct pca953x_chip *chip = dev_get_drvdata(dev); 1366 1367 pca953x_save_context(chip); 1368 1369 if (atomic_read(&chip->wakeup_path)) 1370 device_set_wakeup_path(dev); 1371 else 1372 regulator_disable(chip->regulator); 1373 1374 return 0; 1375 } 1376 1377 static int pca953x_resume(struct device *dev) 1378 { 1379 struct pca953x_chip *chip = dev_get_drvdata(dev); 1380 int ret; 1381 1382 if (!atomic_read(&chip->wakeup_path)) { 1383 ret = regulator_enable(chip->regulator); 1384 if (ret) { 1385 dev_err(dev, "Failed to enable regulator: %d\n", ret); 1386 return 0; 1387 } 1388 } 1389 1390 ret = pca953x_restore_context(chip); 1391 if (ret) 1392 dev_err(dev, "Failed to restore register map: %d\n", ret); 1393 1394 return ret; 1395 } 1396 1397 static DEFINE_SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); 1398 1399 /* convenience to stop overlong match-table lines */ 1400 #define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int)) 1401 #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) 1402 #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) 1403 1404 static const struct of_device_id pca953x_dt_ids[] = { 1405 { .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), }, 1406 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, 1407 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, 1408 { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), }, 1409 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, 1410 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, 1411 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, 1412 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, 1413 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, 1414 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, 1415 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, 1416 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, 1417 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, 1418 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, 1419 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, 1420 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, 1421 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, 1422 1423 { .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), }, 1424 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1425 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, 1426 { .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), }, 1427 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), }, 1428 { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), }, 1429 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, 1430 1431 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, 1432 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, 1433 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, 1434 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, 1435 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, 1436 1437 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, 1438 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, 1439 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, 1440 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, 1441 { .compatible = "ti,tca6418", .data = (void *)(18 | TCA6418_TYPE | PCA_INT), }, 1442 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, 1443 { .compatible = "ti,tca9535", .data = OF_953X(16, PCA_INT), }, 1444 { .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), }, 1445 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, 1446 1447 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, 1448 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, 1449 { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), }, 1450 1451 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, 1452 { } 1453 }; 1454 1455 MODULE_DEVICE_TABLE(of, pca953x_dt_ids); 1456 1457 static struct i2c_driver pca953x_driver = { 1458 .driver = { 1459 .name = "pca953x", 1460 .pm = pm_sleep_ptr(&pca953x_pm_ops), 1461 .of_match_table = pca953x_dt_ids, 1462 .acpi_match_table = pca953x_acpi_ids, 1463 }, 1464 .probe = pca953x_probe, 1465 .id_table = pca953x_id, 1466 }; 1467 1468 static int __init pca953x_init(void) 1469 { 1470 return i2c_add_driver(&pca953x_driver); 1471 } 1472 1473 /* 1474 * register after i2c postcore initcall and before 1475 * subsys initcalls that may rely on these GPIOs 1476 */ 1477 subsys_initcall(pca953x_init); 1478 1479 static void __exit pca953x_exit(void) 1480 { 1481 i2c_del_driver(&pca953x_driver); 1482 } 1483 module_exit(pca953x_exit); 1484 1485 MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); 1486 MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); 1487 MODULE_LICENSE("GPL"); 1488