1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (C) 2013--2024 Intel Corporation */ 3 4 #ifndef IPU6_FW_ISYS_H 5 #define IPU6_FW_ISYS_H 6 7 #include <linux/types.h> 8 9 struct device; 10 struct ipu6_isys; 11 struct ipu6_isys_video; 12 struct isys_fw_msgs; 13 struct ipu6_isys_stream; 14 struct ipu6_isys_buffer_list; 15 16 /* Max number of Input/Output Pins */ 17 #define IPU6_MAX_IPINS 4 18 19 #define IPU6_MAX_OPINS ((IPU6_MAX_IPINS) + 1) 20 21 #define IPU6_STREAM_ID_MAX 16 22 #define IPU6_NONSECURE_STREAM_ID_MAX 12 23 #define IPU6_DEV_SEND_QUEUE_SIZE (IPU6_STREAM_ID_MAX) 24 #define IPU6_NOF_SRAM_BLOCKS_MAX (IPU6_STREAM_ID_MAX) 25 #define IPU6_N_MAX_MSG_SEND_QUEUES (IPU6_STREAM_ID_MAX) 26 #define IPU6SE_STREAM_ID_MAX 8 27 #define IPU6SE_NONSECURE_STREAM_ID_MAX 4 28 #define IPU6SE_DEV_SEND_QUEUE_SIZE (IPU6SE_STREAM_ID_MAX) 29 #define IPU6SE_NOF_SRAM_BLOCKS_MAX (IPU6SE_STREAM_ID_MAX) 30 #define IPU6SE_N_MAX_MSG_SEND_QUEUES (IPU6SE_STREAM_ID_MAX) 31 32 /* Single return queue for all streams/commands type */ 33 #define IPU6_N_MAX_MSG_RECV_QUEUES 1 34 /* Single device queue for high priority commands (bypass in-order queue) */ 35 #define IPU6_N_MAX_DEV_SEND_QUEUES 1 36 /* Single dedicated send queue for proxy interface */ 37 #define IPU6_N_MAX_PROXY_SEND_QUEUES 1 38 /* Single dedicated recv queue for proxy interface */ 39 #define IPU6_N_MAX_PROXY_RECV_QUEUES 1 40 /* Send queues layout */ 41 #define IPU6_BASE_PROXY_SEND_QUEUES 0 42 #define IPU6_BASE_DEV_SEND_QUEUES \ 43 (IPU6_BASE_PROXY_SEND_QUEUES + IPU6_N_MAX_PROXY_SEND_QUEUES) 44 #define IPU6_BASE_MSG_SEND_QUEUES \ 45 (IPU6_BASE_DEV_SEND_QUEUES + IPU6_N_MAX_DEV_SEND_QUEUES) 46 /* Recv queues layout */ 47 #define IPU6_BASE_PROXY_RECV_QUEUES 0 48 #define IPU6_BASE_MSG_RECV_QUEUES \ 49 (IPU6_BASE_PROXY_RECV_QUEUES + IPU6_N_MAX_PROXY_RECV_QUEUES) 50 #define IPU6_N_MAX_RECV_QUEUES \ 51 (IPU6_BASE_MSG_RECV_QUEUES + IPU6_N_MAX_MSG_RECV_QUEUES) 52 53 #define IPU6_N_MAX_SEND_QUEUES \ 54 (IPU6_BASE_MSG_SEND_QUEUES + IPU6_N_MAX_MSG_SEND_QUEUES) 55 #define IPU6SE_N_MAX_SEND_QUEUES \ 56 (IPU6_BASE_MSG_SEND_QUEUES + IPU6SE_N_MAX_MSG_SEND_QUEUES) 57 58 /* Max number of planes for frame formats supported by the FW */ 59 #define IPU6_PIN_PLANES_MAX 4 60 61 #define IPU6_FW_ISYS_SENSOR_TYPE_START 14 62 #define IPU6_FW_ISYS_SENSOR_TYPE_END 19 63 #define IPU6SE_FW_ISYS_SENSOR_TYPE_START 6 64 #define IPU6SE_FW_ISYS_SENSOR_TYPE_END 11 65 /* 66 * Device close takes some time from last ack message to actual stopping 67 * of the SP processor. As long as the SP processor runs we can't proceed with 68 * clean up of resources. 69 */ 70 #define IPU6_ISYS_OPEN_RETRY 2000 71 #define IPU6_ISYS_CLOSE_RETRY 2000 72 #define IPU6_FW_CALL_TIMEOUT_JIFFIES msecs_to_jiffies(2000) 73 74 enum ipu6_fw_isys_resp_type { 75 IPU6_FW_ISYS_RESP_TYPE_STREAM_OPEN_DONE = 0, 76 IPU6_FW_ISYS_RESP_TYPE_STREAM_START_ACK, 77 IPU6_FW_ISYS_RESP_TYPE_STREAM_START_AND_CAPTURE_ACK, 78 IPU6_FW_ISYS_RESP_TYPE_STREAM_CAPTURE_ACK, 79 IPU6_FW_ISYS_RESP_TYPE_STREAM_STOP_ACK, 80 IPU6_FW_ISYS_RESP_TYPE_STREAM_FLUSH_ACK, 81 IPU6_FW_ISYS_RESP_TYPE_STREAM_CLOSE_ACK, 82 IPU6_FW_ISYS_RESP_TYPE_PIN_DATA_READY, 83 IPU6_FW_ISYS_RESP_TYPE_PIN_DATA_WATERMARK, 84 IPU6_FW_ISYS_RESP_TYPE_FRAME_SOF, 85 IPU6_FW_ISYS_RESP_TYPE_FRAME_EOF, 86 IPU6_FW_ISYS_RESP_TYPE_STREAM_START_AND_CAPTURE_DONE, 87 IPU6_FW_ISYS_RESP_TYPE_STREAM_CAPTURE_DONE, 88 IPU6_FW_ISYS_RESP_TYPE_PIN_DATA_SKIPPED, 89 IPU6_FW_ISYS_RESP_TYPE_STREAM_CAPTURE_SKIPPED, 90 IPU6_FW_ISYS_RESP_TYPE_FRAME_SOF_DISCARDED, 91 IPU6_FW_ISYS_RESP_TYPE_FRAME_EOF_DISCARDED, 92 IPU6_FW_ISYS_RESP_TYPE_STATS_DATA_READY, 93 N_IPU6_FW_ISYS_RESP_TYPE 94 }; 95 96 enum ipu6_fw_isys_send_type { 97 IPU6_FW_ISYS_SEND_TYPE_STREAM_OPEN = 0, 98 IPU6_FW_ISYS_SEND_TYPE_STREAM_START, 99 IPU6_FW_ISYS_SEND_TYPE_STREAM_START_AND_CAPTURE, 100 IPU6_FW_ISYS_SEND_TYPE_STREAM_CAPTURE, 101 IPU6_FW_ISYS_SEND_TYPE_STREAM_STOP, 102 IPU6_FW_ISYS_SEND_TYPE_STREAM_FLUSH, 103 IPU6_FW_ISYS_SEND_TYPE_STREAM_CLOSE, 104 N_IPU6_FW_ISYS_SEND_TYPE 105 }; 106 107 enum ipu6_fw_isys_queue_type { 108 IPU6_FW_ISYS_QUEUE_TYPE_PROXY = 0, 109 IPU6_FW_ISYS_QUEUE_TYPE_DEV, 110 IPU6_FW_ISYS_QUEUE_TYPE_MSG, 111 N_IPU6_FW_ISYS_QUEUE_TYPE 112 }; 113 114 enum ipu6_fw_isys_stream_source { 115 IPU6_FW_ISYS_STREAM_SRC_PORT_0 = 0, 116 IPU6_FW_ISYS_STREAM_SRC_PORT_1, 117 IPU6_FW_ISYS_STREAM_SRC_PORT_2, 118 IPU6_FW_ISYS_STREAM_SRC_PORT_3, 119 IPU6_FW_ISYS_STREAM_SRC_PORT_4, 120 IPU6_FW_ISYS_STREAM_SRC_PORT_5, 121 IPU6_FW_ISYS_STREAM_SRC_PORT_6, 122 IPU6_FW_ISYS_STREAM_SRC_PORT_7, 123 IPU6_FW_ISYS_STREAM_SRC_PORT_8, 124 IPU6_FW_ISYS_STREAM_SRC_PORT_9, 125 IPU6_FW_ISYS_STREAM_SRC_PORT_10, 126 IPU6_FW_ISYS_STREAM_SRC_PORT_11, 127 IPU6_FW_ISYS_STREAM_SRC_PORT_12, 128 IPU6_FW_ISYS_STREAM_SRC_PORT_13, 129 IPU6_FW_ISYS_STREAM_SRC_PORT_14, 130 IPU6_FW_ISYS_STREAM_SRC_PORT_15, 131 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_0, 132 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_1, 133 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_2, 134 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_3, 135 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_4, 136 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_5, 137 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_6, 138 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_7, 139 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_8, 140 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_9, 141 N_IPU6_FW_ISYS_STREAM_SRC 142 }; 143 144 #define IPU6_FW_ISYS_STREAM_SRC_CSI2_PORT0 IPU6_FW_ISYS_STREAM_SRC_PORT_0 145 #define IPU6_FW_ISYS_STREAM_SRC_CSI2_PORT1 IPU6_FW_ISYS_STREAM_SRC_PORT_1 146 #define IPU6_FW_ISYS_STREAM_SRC_CSI2_PORT2 IPU6_FW_ISYS_STREAM_SRC_PORT_2 147 #define IPU6_FW_ISYS_STREAM_SRC_CSI2_PORT3 IPU6_FW_ISYS_STREAM_SRC_PORT_3 148 149 #define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_PORTA IPU6_FW_ISYS_STREAM_SRC_PORT_4 150 #define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_PORTB IPU6_FW_ISYS_STREAM_SRC_PORT_5 151 #define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT0 \ 152 IPU6_FW_ISYS_STREAM_SRC_PORT_6 153 #define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT1 \ 154 IPU6_FW_ISYS_STREAM_SRC_PORT_7 155 #define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT2 \ 156 IPU6_FW_ISYS_STREAM_SRC_PORT_8 157 #define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT3 \ 158 IPU6_FW_ISYS_STREAM_SRC_PORT_9 159 160 #define IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_PORT0 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_0 161 #define IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_PORT1 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_1 162 163 /* 164 * enum ipu6_fw_isys_mipi_vc: MIPI csi2 spec 165 * supports up to 4 virtual per physical channel 166 */ 167 enum ipu6_fw_isys_mipi_vc { 168 IPU6_FW_ISYS_MIPI_VC_0 = 0, 169 IPU6_FW_ISYS_MIPI_VC_1, 170 IPU6_FW_ISYS_MIPI_VC_2, 171 IPU6_FW_ISYS_MIPI_VC_3, 172 N_IPU6_FW_ISYS_MIPI_VC 173 }; 174 175 enum ipu6_fw_isys_frame_format_type { 176 IPU6_FW_ISYS_FRAME_FORMAT_NV11 = 0, /* 12 bit YUV 411, Y, UV plane */ 177 IPU6_FW_ISYS_FRAME_FORMAT_NV12, /* 12 bit YUV 420, Y, UV plane */ 178 IPU6_FW_ISYS_FRAME_FORMAT_NV12_16, /* 16 bit YUV 420, Y, UV plane */ 179 /* 12 bit YUV 420, Intel proprietary tiled format */ 180 IPU6_FW_ISYS_FRAME_FORMAT_NV12_TILEY, 181 182 IPU6_FW_ISYS_FRAME_FORMAT_NV16, /* 16 bit YUV 422, Y, UV plane */ 183 IPU6_FW_ISYS_FRAME_FORMAT_NV21, /* 12 bit YUV 420, Y, VU plane */ 184 IPU6_FW_ISYS_FRAME_FORMAT_NV61, /* 16 bit YUV 422, Y, VU plane */ 185 IPU6_FW_ISYS_FRAME_FORMAT_YV12, /* 12 bit YUV 420, Y, V, U plane */ 186 IPU6_FW_ISYS_FRAME_FORMAT_YV16, /* 16 bit YUV 422, Y, V, U plane */ 187 IPU6_FW_ISYS_FRAME_FORMAT_YUV420, /* 12 bit YUV 420, Y, U, V plane */ 188 IPU6_FW_ISYS_FRAME_FORMAT_YUV420_10, /* yuv420, 10 bits per subpixel */ 189 IPU6_FW_ISYS_FRAME_FORMAT_YUV420_12, /* yuv420, 12 bits per subpixel */ 190 IPU6_FW_ISYS_FRAME_FORMAT_YUV420_14, /* yuv420, 14 bits per subpixel */ 191 IPU6_FW_ISYS_FRAME_FORMAT_YUV420_16, /* yuv420, 16 bits per subpixel */ 192 IPU6_FW_ISYS_FRAME_FORMAT_YUV422, /* 16 bit YUV 422, Y, U, V plane */ 193 IPU6_FW_ISYS_FRAME_FORMAT_YUV422_16, /* yuv422, 16 bits per subpixel */ 194 IPU6_FW_ISYS_FRAME_FORMAT_UYVY, /* 16 bit YUV 422, UYVY interleaved */ 195 IPU6_FW_ISYS_FRAME_FORMAT_YUYV, /* 16 bit YUV 422, YUYV interleaved */ 196 IPU6_FW_ISYS_FRAME_FORMAT_YUV444, /* 24 bit YUV 444, Y, U, V plane */ 197 /* Internal format, 2 y lines followed by a uvinterleaved line */ 198 IPU6_FW_ISYS_FRAME_FORMAT_YUV_LINE, 199 IPU6_FW_ISYS_FRAME_FORMAT_RAW8, /* RAW8, 1 plane */ 200 IPU6_FW_ISYS_FRAME_FORMAT_RAW10, /* RAW10, 1 plane */ 201 IPU6_FW_ISYS_FRAME_FORMAT_RAW12, /* RAW12, 1 plane */ 202 IPU6_FW_ISYS_FRAME_FORMAT_RAW14, /* RAW14, 1 plane */ 203 IPU6_FW_ISYS_FRAME_FORMAT_RAW16, /* RAW16, 1 plane */ 204 /** 205 * 16 bit RGB, 1 plane. Each 3 sub pixels are packed into one 16 bit 206 * value, 5 bits for R, 6 bits for G and 5 bits for B. 207 */ 208 IPU6_FW_ISYS_FRAME_FORMAT_RGB565, 209 IPU6_FW_ISYS_FRAME_FORMAT_PLANAR_RGB888, /* 24 bit RGB, 3 planes */ 210 IPU6_FW_ISYS_FRAME_FORMAT_RGBA888, /* 32 bit RGBA, 1 plane, A=Alpha */ 211 IPU6_FW_ISYS_FRAME_FORMAT_QPLANE6, /* Internal, for advanced ISP */ 212 IPU6_FW_ISYS_FRAME_FORMAT_BINARY_8, /* byte stream, used for jpeg. */ 213 N_IPU6_FW_ISYS_FRAME_FORMAT 214 }; 215 216 enum ipu6_fw_isys_pin_type { 217 /* captured as MIPI packets */ 218 IPU6_FW_ISYS_PIN_TYPE_MIPI = 0, 219 /* captured through the SoC path */ 220 IPU6_FW_ISYS_PIN_TYPE_RAW_SOC = 3, 221 }; 222 223 /* 224 * enum ipu6_fw_isys_mipi_store_mode. Describes if long MIPI packets reach 225 * MIPI SRAM with the long packet header or 226 * if not, then only option is to capture it with pin type MIPI. 227 */ 228 enum ipu6_fw_isys_mipi_store_mode { 229 IPU6_FW_ISYS_MIPI_STORE_MODE_NORMAL = 0, 230 IPU6_FW_ISYS_MIPI_STORE_MODE_DISCARD_LONG_HEADER, 231 N_IPU6_FW_ISYS_MIPI_STORE_MODE 232 }; 233 234 enum ipu6_fw_isys_capture_mode { 235 IPU6_FW_ISYS_CAPTURE_MODE_REGULAR = 0, 236 IPU6_FW_ISYS_CAPTURE_MODE_BURST, 237 N_IPU6_FW_ISYS_CAPTURE_MODE, 238 }; 239 240 enum ipu6_fw_isys_sensor_mode { 241 IPU6_FW_ISYS_SENSOR_MODE_NORMAL = 0, 242 IPU6_FW_ISYS_SENSOR_MODE_TOBII, 243 N_IPU6_FW_ISYS_SENSOR_MODE, 244 }; 245 246 enum ipu6_fw_isys_error { 247 IPU6_FW_ISYS_ERROR_NONE = 0, 248 IPU6_FW_ISYS_ERROR_FW_INTERNAL_CONSISTENCY, 249 IPU6_FW_ISYS_ERROR_HW_CONSISTENCY, 250 IPU6_FW_ISYS_ERROR_DRIVER_INVALID_COMMAND_SEQUENCE, 251 IPU6_FW_ISYS_ERROR_DRIVER_INVALID_DEVICE_CONFIGURATION, 252 IPU6_FW_ISYS_ERROR_DRIVER_INVALID_STREAM_CONFIGURATION, 253 IPU6_FW_ISYS_ERROR_DRIVER_INVALID_FRAME_CONFIGURATION, 254 IPU6_FW_ISYS_ERROR_INSUFFICIENT_RESOURCES, 255 IPU6_FW_ISYS_ERROR_HW_REPORTED_STR2MMIO, 256 IPU6_FW_ISYS_ERROR_HW_REPORTED_SIG2CIO, 257 IPU6_FW_ISYS_ERROR_SENSOR_FW_SYNC, 258 IPU6_FW_ISYS_ERROR_STREAM_IN_SUSPENSION, 259 IPU6_FW_ISYS_ERROR_RESPONSE_QUEUE_FULL, 260 N_IPU6_FW_ISYS_ERROR 261 }; 262 263 enum ipu6_fw_proxy_error { 264 IPU6_FW_PROXY_ERROR_NONE = 0, 265 IPU6_FW_PROXY_ERROR_INVALID_WRITE_REGION, 266 IPU6_FW_PROXY_ERROR_INVALID_WRITE_OFFSET, 267 N_IPU6_FW_PROXY_ERROR 268 }; 269 270 /* firmware ABI structure below are aligned in firmware, no need pack */ 271 struct ipu6_fw_isys_buffer_partition_abi { 272 u32 num_gda_pages[IPU6_STREAM_ID_MAX]; 273 }; 274 275 struct ipu6_fw_isys_fw_config { 276 struct ipu6_fw_isys_buffer_partition_abi buffer_partition; 277 u32 num_send_queues[N_IPU6_FW_ISYS_QUEUE_TYPE]; 278 u32 num_recv_queues[N_IPU6_FW_ISYS_QUEUE_TYPE]; 279 }; 280 281 /* 282 * struct ipu6_fw_isys_resolution_abi: Generic resolution structure. 283 */ 284 struct ipu6_fw_isys_resolution_abi { 285 u32 width; 286 u32 height; 287 }; 288 289 /** 290 * struct ipu6_fw_isys_output_pin_payload_abi - ISYS output pin buffer 291 * @out_buf_id: Points to output pin buffer - buffer identifier 292 * @addr: Points to output pin buffer - CSS Virtual Address 293 * @compress: Request frame compression (1), or not (0) 294 */ 295 struct ipu6_fw_isys_output_pin_payload_abi { 296 u64 out_buf_id; 297 u32 addr; 298 u32 compress; 299 }; 300 301 /** 302 * struct ipu6_fw_isys_output_pin_info_abi - ISYS output pin info 303 * @output_res: output pin resolution 304 * @stride: output stride in Bytes (not valid for statistics) 305 * @watermark_in_lines: pin watermark level in lines 306 * @payload_buf_size: minimum size in Bytes of all buffers that will be 307 * supplied for capture on this pin 308 * @ts_offsets: ts_offsets 309 * @s2m_pixel_soc_pixel_remapping: pixel soc remapping (see the definition of 310 * S2M_PIXEL_SOC_PIXEL_REMAPPING_FLAG_NO_REMAPPING) 311 * @csi_be_soc_pixel_remapping: see s2m_pixel_soc_pixel_remapping 312 * @send_irq: assert if pin event should trigger irq 313 * @input_pin_id: related input pin id 314 * @pt: pin type -real format "enum ipu6_fw_isys_pin_type" 315 * @ft: frame format type -real format "enum ipu6_fw_isys_frame_format_type" 316 * @reserved: a reserved field 317 * @reserve_compression: reserve compression resources for pin 318 * @snoopable: snoopable 319 * @error_handling_enable: enable error handling 320 * @sensor_type: sensor_type 321 */ 322 struct ipu6_fw_isys_output_pin_info_abi { 323 struct ipu6_fw_isys_resolution_abi output_res; 324 u32 stride; 325 u32 watermark_in_lines; 326 u32 payload_buf_size; 327 u32 ts_offsets[IPU6_PIN_PLANES_MAX]; 328 u32 s2m_pixel_soc_pixel_remapping; 329 u32 csi_be_soc_pixel_remapping; 330 u8 send_irq; 331 u8 input_pin_id; 332 u8 pt; 333 u8 ft; 334 u8 reserved; 335 u8 reserve_compression; 336 u8 snoopable; 337 u8 error_handling_enable; 338 u32 sensor_type; 339 }; 340 341 /** 342 * struct ipu6_fw_isys_input_pin_info_abi - ISYS input pin info 343 * @input_res: input resolution 344 * @dt: mipi data type ((enum ipu6_fw_isys_mipi_data_type) 345 * @mipi_store_mode: defines if legacy long packet header will be stored or 346 * discarded if discarded, output pin type for this 347 * input pin can only be MIPI 348 * (enum ipu6_fw_isys_mipi_store_mode) 349 * @bits_per_pix: native bits per pixel 350 * @mapped_dt: actual data type from sensor 351 * @mipi_decompression: defines which compression will be in mipi backend 352 * @crop_first_and_last_lines: Control whether to crop the first and last line 353 * of the input image. Crop done by HW device. 354 * @capture_mode: mode of capture, regular or burst, default value is regular 355 * @reserved: a reserved field 356 */ 357 struct ipu6_fw_isys_input_pin_info_abi { 358 struct ipu6_fw_isys_resolution_abi input_res; 359 u8 dt; 360 u8 mipi_store_mode; 361 u8 bits_per_pix; 362 u8 mapped_dt; 363 u8 mipi_decompression; 364 u8 crop_first_and_last_lines; 365 u8 capture_mode; 366 u8 reserved; 367 }; 368 369 /** 370 * struct ipu6_fw_isys_cropping_abi - ISYS cropping coordinates 371 * @top_offset: Top offset 372 * @left_offset: Left offset 373 * @bottom_offset: Bottom offset 374 * @right_offset: Right offset 375 */ 376 struct ipu6_fw_isys_cropping_abi { 377 s32 top_offset; 378 s32 left_offset; 379 s32 bottom_offset; 380 s32 right_offset; 381 }; 382 383 /** 384 * struct ipu6_fw_isys_stream_cfg_data_abi - ISYS stream configuration data 385 * ISYS stream configuration data structure 386 * @crop: for extended use and is not used in FW currently 387 * @input_pins: input pin descriptors 388 * @output_pins: output pin descriptors 389 * @compfmt: de-compression setting for User Defined Data 390 * @nof_input_pins: number of input pins 391 * @nof_output_pins: number of output pins 392 * @send_irq_sof_discarded: send irq on discarded frame sof response 393 * - if '1' it will override the send_resp_sof_discarded 394 * and send the response 395 * - if '0' the send_resp_sof_discarded will determine 396 * whether to send the response 397 * @send_irq_eof_discarded: send irq on discarded frame eof response 398 * - if '1' it will override the send_resp_eof_discarded 399 * and send the response 400 * - if '0' the send_resp_eof_discarded will determine 401 * whether to send the response 402 * @send_resp_sof_discarded: send response for discarded frame sof detected, 403 * used only when send_irq_sof_discarded is '0' 404 * @send_resp_eof_discarded: send response for discarded frame eof detected, 405 * used only when send_irq_eof_discarded is '0' 406 * @src: Stream source index e.g. MIPI_generator_0, CSI2-rx_1 407 * @vc: MIPI Virtual Channel (up to 4 virtual per physical channel) 408 * @isl_use: indicates whether stream requires ISL and how 409 * @sensor_type: type of connected sensor, tobii or others, default is 0 410 * @reserved: a reserved field 411 * @reserved2: a reserved field 412 */ 413 struct ipu6_fw_isys_stream_cfg_data_abi { 414 struct ipu6_fw_isys_cropping_abi crop; 415 struct ipu6_fw_isys_input_pin_info_abi input_pins[IPU6_MAX_IPINS]; 416 struct ipu6_fw_isys_output_pin_info_abi output_pins[IPU6_MAX_OPINS]; 417 u32 compfmt; 418 u8 nof_input_pins; 419 u8 nof_output_pins; 420 u8 send_irq_sof_discarded; 421 u8 send_irq_eof_discarded; 422 u8 send_resp_sof_discarded; 423 u8 send_resp_eof_discarded; 424 u8 src; 425 u8 vc; 426 u8 isl_use; 427 u8 sensor_type; 428 u8 reserved; 429 u8 reserved2; 430 }; 431 432 /** 433 * struct ipu6_fw_isys_frame_buff_set_abi - ISYS frame buffer set (request) 434 * @output_pins: output pin addresses 435 * @send_irq_sof: send irq on frame sof response 436 * - if '1' it will override the send_resp_sof and 437 * send the response 438 * - if '0' the send_resp_sof will determine whether to 439 * send the response 440 * @send_irq_eof: send irq on frame eof response 441 * - if '1' it will override the send_resp_eof and 442 * send the response 443 * - if '0' the send_resp_eof will determine whether to 444 * send the response 445 * @send_irq_capture_ack: send irq on capture ack 446 * @send_irq_capture_done: send irq on capture done 447 * @send_resp_sof: send response for frame sof detected, 448 * used only when send_irq_sof is '0' 449 * @send_resp_eof: send response for frame eof detected, 450 * used only when send_irq_eof is '0' 451 * @send_resp_capture_ack: send response for capture ack event 452 * @send_resp_capture_done: send response for capture done event 453 * @reserved: a reserved field 454 */ 455 struct ipu6_fw_isys_frame_buff_set_abi { 456 struct ipu6_fw_isys_output_pin_payload_abi output_pins[IPU6_MAX_OPINS]; 457 u8 send_irq_sof; 458 u8 send_irq_eof; 459 u8 send_irq_capture_ack; 460 u8 send_irq_capture_done; 461 u8 send_resp_sof; 462 u8 send_resp_eof; 463 u8 send_resp_capture_ack; 464 u8 send_resp_capture_done; 465 u8 reserved[8]; 466 }; 467 468 /** 469 * struct ipu6_fw_isys_error_info_abi - ISYS error information 470 * @error: error code if something went wrong 471 * @error_details: depending on error code, it may contain additional error info 472 */ 473 struct ipu6_fw_isys_error_info_abi { 474 u32 error; 475 u32 error_details; 476 }; 477 478 /** 479 * struct ipu6_fw_isys_resp_info_abi - ISYS firmware response 480 * @buf_id: buffer ID 481 * @pin: this var is only valid for pin event related responses, 482 * contains pin addresses 483 * @error_info: error information from the FW 484 * @timestamp: Time information for event if available 485 * @stream_handle: stream id the response corresponds to 486 * @type: response type (enum ipu6_fw_isys_resp_type) 487 * @pin_id: pin id that the pin payload corresponds to 488 * @reserved: a reserved field 489 * @reserved2: a reserved field 490 */ 491 struct ipu6_fw_isys_resp_info_abi { 492 u64 buf_id; 493 struct ipu6_fw_isys_output_pin_payload_abi pin; 494 struct ipu6_fw_isys_error_info_abi error_info; 495 u32 timestamp[2]; 496 u8 stream_handle; 497 u8 type; 498 u8 pin_id; 499 u8 reserved; 500 u32 reserved2; 501 }; 502 503 /** 504 * struct ipu6_fw_isys_proxy_error_info_abi - ISYS proxy error 505 * @error: error code if something went wrong 506 * @error_details: depending on error code, it may contain additional error info 507 */ 508 struct ipu6_fw_isys_proxy_error_info_abi { 509 u32 error; 510 u32 error_details; 511 }; 512 513 struct ipu6_fw_isys_proxy_resp_info_abi { 514 u32 request_id; 515 struct ipu6_fw_isys_proxy_error_info_abi error_info; 516 }; 517 518 /** 519 * struct ipu6_fw_resp_queue_token - ISYS response queue token 520 * @resp_info: response info 521 */ 522 struct ipu6_fw_resp_queue_token { 523 struct ipu6_fw_isys_resp_info_abi resp_info; 524 }; 525 526 /** 527 * struct ipu6_fw_send_queue_token - ISYS send queue token 528 * @buf_handle: buffer handle 529 * @payload: payload 530 * @send_type: send_type 531 * @stream_id: stream_id 532 */ 533 struct ipu6_fw_send_queue_token { 534 u64 buf_handle; 535 u32 payload; 536 u16 send_type; 537 u16 stream_id; 538 }; 539 540 /** 541 * struct ipu6_fw_proxy_resp_queue_token - ISYS proxy response queue token 542 * @proxy_resp_info: proxy response info 543 */ 544 struct ipu6_fw_proxy_resp_queue_token { 545 struct ipu6_fw_isys_proxy_resp_info_abi proxy_resp_info; 546 }; 547 548 /** 549 * struct ipu6_fw_proxy_send_queue_token - SYS proxy send queue token 550 * @request_id: request_id 551 * @region_index: region_index 552 * @offset: offset 553 * @value: value 554 */ 555 struct ipu6_fw_proxy_send_queue_token { 556 u32 request_id; 557 u32 region_index; 558 u32 offset; 559 u32 value; 560 }; 561 562 int ipu6_fw_isys_send_proxy_token(struct ipu6_isys *isys, unsigned int req_id, 563 unsigned int index, unsigned int offset, 564 u32 value); 565 int ipu6_isys_isr_one(struct ipu6_bus_device *adev); 566 irqreturn_t ipu6_isys_isr(struct ipu6_bus_device *adev); 567 568 #endif 569