1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2006-2007 PA Semi, Inc
4 *
5 * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
6 */
7
8 #include <linux/module.h>
9 #include <linux/pci.h>
10 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/dmaengine.h>
13 #include <linux/delay.h>
14 #include <linux/hex.h>
15 #include <linux/netdevice.h>
16 #include <linux/of_mdio.h>
17 #include <linux/etherdevice.h>
18 #include <asm/dma-mapping.h>
19 #include <linux/in.h>
20 #include <linux/skbuff.h>
21
22 #include <linux/ip.h>
23 #include <net/checksum.h>
24 #include <linux/prefetch.h>
25
26 #include <asm/irq.h>
27 #include <asm/firmware.h>
28 #include <asm/pasemi_dma.h>
29
30 #include "pasemi_mac.h"
31
32 /* We have our own align, since ppc64 in general has it at 0 because
33 * of design flaws in some of the server bridge chips. However, for
34 * PWRficient doing the unaligned copies is more expensive than doing
35 * unaligned DMA, so make sure the data is aligned instead.
36 */
37 #define LOCAL_SKB_ALIGN 2
38
39 /* TODO list
40 *
41 * - Multicast support
42 * - Large MTU support
43 * - Multiqueue RX/TX
44 */
45
46 #define PE_MIN_MTU (ETH_ZLEN + ETH_HLEN)
47 #define PE_MAX_MTU 9000
48 #define PE_DEF_MTU ETH_DATA_LEN
49
50 #define DEFAULT_MSG_ENABLE \
51 (NETIF_MSG_DRV | \
52 NETIF_MSG_PROBE | \
53 NETIF_MSG_LINK | \
54 NETIF_MSG_TIMER | \
55 NETIF_MSG_IFDOWN | \
56 NETIF_MSG_IFUP | \
57 NETIF_MSG_RX_ERR | \
58 NETIF_MSG_TX_ERR)
59
60 MODULE_LICENSE("GPL");
61 MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
62 MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
63
64 static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */
65 module_param(debug, int, 0);
66 MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value");
67
68 extern const struct ethtool_ops pasemi_mac_ethtool_ops;
69
translation_enabled(void)70 static int translation_enabled(void)
71 {
72 #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE)
73 return 1;
74 #else
75 return firmware_has_feature(FW_FEATURE_LPAR);
76 #endif
77 }
78
write_iob_reg(unsigned int reg,unsigned int val)79 static void write_iob_reg(unsigned int reg, unsigned int val)
80 {
81 pasemi_write_iob_reg(reg, val);
82 }
83
read_mac_reg(const struct pasemi_mac * mac,unsigned int reg)84 static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg)
85 {
86 return pasemi_read_mac_reg(mac->dma_if, reg);
87 }
88
write_mac_reg(const struct pasemi_mac * mac,unsigned int reg,unsigned int val)89 static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg,
90 unsigned int val)
91 {
92 pasemi_write_mac_reg(mac->dma_if, reg, val);
93 }
94
read_dma_reg(unsigned int reg)95 static unsigned int read_dma_reg(unsigned int reg)
96 {
97 return pasemi_read_dma_reg(reg);
98 }
99
write_dma_reg(unsigned int reg,unsigned int val)100 static void write_dma_reg(unsigned int reg, unsigned int val)
101 {
102 pasemi_write_dma_reg(reg, val);
103 }
104
rx_ring(const struct pasemi_mac * mac)105 static struct pasemi_mac_rxring *rx_ring(const struct pasemi_mac *mac)
106 {
107 return mac->rx;
108 }
109
tx_ring(const struct pasemi_mac * mac)110 static struct pasemi_mac_txring *tx_ring(const struct pasemi_mac *mac)
111 {
112 return mac->tx;
113 }
114
prefetch_skb(const struct sk_buff * skb)115 static inline void prefetch_skb(const struct sk_buff *skb)
116 {
117 const void *d = skb;
118
119 prefetch(d);
120 prefetch(d+64);
121 prefetch(d+128);
122 prefetch(d+192);
123 }
124
mac_to_intf(struct pasemi_mac * mac)125 static int mac_to_intf(struct pasemi_mac *mac)
126 {
127 struct pci_dev *pdev = mac->pdev;
128 u32 tmp;
129 int nintf, off, i, j;
130 int devfn = pdev->devfn;
131
132 tmp = read_dma_reg(PAS_DMA_CAP_IFI);
133 nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S;
134 off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S;
135
136 /* IOFF contains the offset to the registers containing the
137 * DMA interface-to-MAC-pci-id mappings, and NIN contains number
138 * of total interfaces. Each register contains 4 devfns.
139 * Just do a linear search until we find the devfn of the MAC
140 * we're trying to look up.
141 */
142
143 for (i = 0; i < (nintf+3)/4; i++) {
144 tmp = read_dma_reg(off+4*i);
145 for (j = 0; j < 4; j++) {
146 if (((tmp >> (8*j)) & 0xff) == devfn)
147 return i*4 + j;
148 }
149 }
150 return -1;
151 }
152
pasemi_mac_intf_disable(struct pasemi_mac * mac)153 static void pasemi_mac_intf_disable(struct pasemi_mac *mac)
154 {
155 unsigned int flags;
156
157 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
158 flags &= ~PAS_MAC_CFG_PCFG_PE;
159 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
160 }
161
pasemi_mac_intf_enable(struct pasemi_mac * mac)162 static void pasemi_mac_intf_enable(struct pasemi_mac *mac)
163 {
164 unsigned int flags;
165
166 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
167 flags |= PAS_MAC_CFG_PCFG_PE;
168 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
169 }
170
pasemi_get_mac_addr(struct pasemi_mac * mac)171 static int pasemi_get_mac_addr(struct pasemi_mac *mac)
172 {
173 struct pci_dev *pdev = mac->pdev;
174 struct device_node *dn = pci_device_to_OF_node(pdev);
175 int len;
176 const u8 *maddr;
177 u8 addr[ETH_ALEN];
178
179 if (!dn) {
180 dev_dbg(&pdev->dev,
181 "No device node for mac, not configuring\n");
182 return -ENOENT;
183 }
184
185 maddr = of_get_property(dn, "local-mac-address", &len);
186
187 if (maddr && len == ETH_ALEN) {
188 memcpy(mac->mac_addr, maddr, ETH_ALEN);
189 return 0;
190 }
191
192 /* Some old versions of firmware mistakenly uses mac-address
193 * (and as a string) instead of a byte array in local-mac-address.
194 */
195
196 if (maddr == NULL)
197 maddr = of_get_property(dn, "mac-address", NULL);
198
199 if (maddr == NULL) {
200 dev_warn(&pdev->dev,
201 "no mac address in device tree, not configuring\n");
202 return -ENOENT;
203 }
204
205 if (!mac_pton(maddr, addr)) {
206 dev_warn(&pdev->dev,
207 "can't parse mac address, not configuring\n");
208 return -EINVAL;
209 }
210
211 memcpy(mac->mac_addr, addr, ETH_ALEN);
212
213 return 0;
214 }
215
pasemi_mac_set_mac_addr(struct net_device * dev,void * p)216 static int pasemi_mac_set_mac_addr(struct net_device *dev, void *p)
217 {
218 struct pasemi_mac *mac = netdev_priv(dev);
219 struct sockaddr *addr = p;
220 unsigned int adr0, adr1;
221
222 if (!is_valid_ether_addr(addr->sa_data))
223 return -EADDRNOTAVAIL;
224
225 eth_hw_addr_set(dev, addr->sa_data);
226
227 adr0 = dev->dev_addr[2] << 24 |
228 dev->dev_addr[3] << 16 |
229 dev->dev_addr[4] << 8 |
230 dev->dev_addr[5];
231 adr1 = read_mac_reg(mac, PAS_MAC_CFG_ADR1);
232 adr1 &= ~0xffff;
233 adr1 |= dev->dev_addr[0] << 8 | dev->dev_addr[1];
234
235 pasemi_mac_intf_disable(mac);
236 write_mac_reg(mac, PAS_MAC_CFG_ADR0, adr0);
237 write_mac_reg(mac, PAS_MAC_CFG_ADR1, adr1);
238 pasemi_mac_intf_enable(mac);
239
240 return 0;
241 }
242
pasemi_mac_unmap_tx_skb(struct pasemi_mac * mac,const int nfrags,struct sk_buff * skb,const dma_addr_t * dmas)243 static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac,
244 const int nfrags,
245 struct sk_buff *skb,
246 const dma_addr_t *dmas)
247 {
248 int f;
249 struct pci_dev *pdev = mac->dma_pdev;
250
251 dma_unmap_single(&pdev->dev, dmas[0], skb_headlen(skb), DMA_TO_DEVICE);
252
253 for (f = 0; f < nfrags; f++) {
254 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
255
256 dma_unmap_page(&pdev->dev, dmas[f + 1], skb_frag_size(frag),
257 DMA_TO_DEVICE);
258 }
259 dev_kfree_skb_irq(skb);
260
261 /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs,
262 * aligned up to a power of 2
263 */
264 return (nfrags + 3) & ~1;
265 }
266
pasemi_mac_setup_csring(struct pasemi_mac * mac)267 static struct pasemi_mac_csring *pasemi_mac_setup_csring(struct pasemi_mac *mac)
268 {
269 struct pasemi_mac_csring *ring;
270 u32 val;
271 unsigned int cfg;
272 int chno;
273
274 ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_csring),
275 offsetof(struct pasemi_mac_csring, chan));
276
277 if (!ring) {
278 dev_err(&mac->pdev->dev, "Can't allocate checksum channel\n");
279 goto out_chan;
280 }
281
282 chno = ring->chan.chno;
283
284 ring->size = CS_RING_SIZE;
285 ring->next_to_fill = 0;
286
287 /* Allocate descriptors */
288 if (pasemi_dma_alloc_ring(&ring->chan, CS_RING_SIZE))
289 goto out_ring_desc;
290
291 write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno),
292 PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma));
293 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32);
294 val |= PAS_DMA_TXCHAN_BASEU_SIZ(CS_RING_SIZE >> 3);
295
296 write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val);
297
298 ring->events[0] = pasemi_dma_alloc_flag();
299 ring->events[1] = pasemi_dma_alloc_flag();
300 if (ring->events[0] < 0 || ring->events[1] < 0)
301 goto out_flags;
302
303 pasemi_dma_clear_flag(ring->events[0]);
304 pasemi_dma_clear_flag(ring->events[1]);
305
306 ring->fun = pasemi_dma_alloc_fun();
307 if (ring->fun < 0)
308 goto out_fun;
309
310 cfg = PAS_DMA_TXCHAN_CFG_TY_FUNC | PAS_DMA_TXCHAN_CFG_UP |
311 PAS_DMA_TXCHAN_CFG_TATTR(ring->fun) |
312 PAS_DMA_TXCHAN_CFG_LPSQ | PAS_DMA_TXCHAN_CFG_LPDQ;
313
314 if (translation_enabled())
315 cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
316
317 write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg);
318
319 /* enable channel */
320 pasemi_dma_start_chan(&ring->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ |
321 PAS_DMA_TXCHAN_TCMDSTA_DB |
322 PAS_DMA_TXCHAN_TCMDSTA_DE |
323 PAS_DMA_TXCHAN_TCMDSTA_DA);
324
325 return ring;
326
327 out_fun:
328 out_flags:
329 if (ring->events[0] >= 0)
330 pasemi_dma_free_flag(ring->events[0]);
331 if (ring->events[1] >= 0)
332 pasemi_dma_free_flag(ring->events[1]);
333 pasemi_dma_free_ring(&ring->chan);
334 out_ring_desc:
335 pasemi_dma_free_chan(&ring->chan);
336 out_chan:
337
338 return NULL;
339 }
340
pasemi_mac_setup_csrings(struct pasemi_mac * mac)341 static void pasemi_mac_setup_csrings(struct pasemi_mac *mac)
342 {
343 int i;
344 mac->cs[0] = pasemi_mac_setup_csring(mac);
345 if (mac->type == MAC_TYPE_XAUI)
346 mac->cs[1] = pasemi_mac_setup_csring(mac);
347 else
348 mac->cs[1] = 0;
349
350 for (i = 0; i < MAX_CS; i++)
351 if (mac->cs[i])
352 mac->num_cs++;
353 }
354
pasemi_mac_free_csring(struct pasemi_mac_csring * csring)355 static void pasemi_mac_free_csring(struct pasemi_mac_csring *csring)
356 {
357 pasemi_dma_stop_chan(&csring->chan);
358 pasemi_dma_free_flag(csring->events[0]);
359 pasemi_dma_free_flag(csring->events[1]);
360 pasemi_dma_free_ring(&csring->chan);
361 pasemi_dma_free_chan(&csring->chan);
362 pasemi_dma_free_fun(csring->fun);
363 }
364
pasemi_mac_setup_rx_resources(const struct net_device * dev)365 static int pasemi_mac_setup_rx_resources(const struct net_device *dev)
366 {
367 struct pasemi_mac_rxring *ring;
368 struct pasemi_mac *mac = netdev_priv(dev);
369 int chno;
370 unsigned int cfg;
371
372 ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring),
373 offsetof(struct pasemi_mac_rxring, chan));
374
375 if (!ring) {
376 dev_err(&mac->pdev->dev, "Can't allocate RX channel\n");
377 goto out_chan;
378 }
379 chno = ring->chan.chno;
380
381 spin_lock_init(&ring->lock);
382
383 ring->size = RX_RING_SIZE;
384 ring->ring_info = kzalloc_objs(struct pasemi_mac_buffer, RX_RING_SIZE);
385
386 if (!ring->ring_info)
387 goto out_ring_info;
388
389 /* Allocate descriptors */
390 if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE))
391 goto out_ring_desc;
392
393 ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
394 RX_RING_SIZE * sizeof(u64),
395 &ring->buf_dma, GFP_KERNEL);
396 if (!ring->buffers)
397 goto out_ring_desc;
398
399 write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno),
400 PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma));
401
402 write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno),
403 PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) |
404 PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3));
405
406 cfg = PAS_DMA_RXCHAN_CFG_HBU(2);
407
408 if (translation_enabled())
409 cfg |= PAS_DMA_RXCHAN_CFG_CTR;
410
411 write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg);
412
413 write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if),
414 PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma));
415
416 write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if),
417 PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) |
418 PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
419
420 cfg = PAS_DMA_RXINT_CFG_DHL(2) | PAS_DMA_RXINT_CFG_L2 |
421 PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP |
422 PAS_DMA_RXINT_CFG_HEN;
423
424 if (translation_enabled())
425 cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR;
426
427 write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg);
428
429 ring->next_to_fill = 0;
430 ring->next_to_clean = 0;
431 ring->mac = mac;
432 mac->rx = ring;
433
434 return 0;
435
436 out_ring_desc:
437 kfree(ring->ring_info);
438 out_ring_info:
439 pasemi_dma_free_chan(&ring->chan);
440 out_chan:
441 return -ENOMEM;
442 }
443
444 static struct pasemi_mac_txring *
pasemi_mac_setup_tx_resources(const struct net_device * dev)445 pasemi_mac_setup_tx_resources(const struct net_device *dev)
446 {
447 struct pasemi_mac *mac = netdev_priv(dev);
448 u32 val;
449 struct pasemi_mac_txring *ring;
450 unsigned int cfg;
451 int chno;
452
453 ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring),
454 offsetof(struct pasemi_mac_txring, chan));
455
456 if (!ring) {
457 dev_err(&mac->pdev->dev, "Can't allocate TX channel\n");
458 goto out_chan;
459 }
460
461 chno = ring->chan.chno;
462
463 spin_lock_init(&ring->lock);
464
465 ring->size = TX_RING_SIZE;
466 ring->ring_info = kzalloc_objs(struct pasemi_mac_buffer, TX_RING_SIZE);
467 if (!ring->ring_info)
468 goto out_ring_info;
469
470 /* Allocate descriptors */
471 if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE))
472 goto out_ring_desc;
473
474 write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno),
475 PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma));
476 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32);
477 val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3);
478
479 write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val);
480
481 cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE |
482 PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
483 PAS_DMA_TXCHAN_CFG_UP |
484 PAS_DMA_TXCHAN_CFG_WT(4);
485
486 if (translation_enabled())
487 cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
488
489 write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg);
490
491 ring->next_to_fill = 0;
492 ring->next_to_clean = 0;
493 ring->mac = mac;
494
495 return ring;
496
497 out_ring_desc:
498 kfree(ring->ring_info);
499 out_ring_info:
500 pasemi_dma_free_chan(&ring->chan);
501 out_chan:
502 return NULL;
503 }
504
pasemi_mac_free_tx_resources(struct pasemi_mac * mac)505 static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac)
506 {
507 struct pasemi_mac_txring *txring = tx_ring(mac);
508 unsigned int i, j;
509 struct pasemi_mac_buffer *info;
510 dma_addr_t dmas[MAX_SKB_FRAGS+1];
511 int freed, nfrags;
512 int start, limit;
513
514 start = txring->next_to_clean;
515 limit = txring->next_to_fill;
516
517 /* Compensate for when fill has wrapped and clean has not */
518 if (start > limit)
519 limit += TX_RING_SIZE;
520
521 for (i = start; i < limit; i += freed) {
522 info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)];
523 if (info->dma && info->skb) {
524 nfrags = skb_shinfo(info->skb)->nr_frags;
525 for (j = 0; j <= nfrags; j++)
526 dmas[j] = txring->ring_info[(i+1+j) &
527 (TX_RING_SIZE-1)].dma;
528 freed = pasemi_mac_unmap_tx_skb(mac, nfrags,
529 info->skb, dmas);
530 } else {
531 freed = 2;
532 }
533 }
534
535 kfree(txring->ring_info);
536 pasemi_dma_free_chan(&txring->chan);
537
538 }
539
pasemi_mac_free_rx_buffers(struct pasemi_mac * mac)540 static void pasemi_mac_free_rx_buffers(struct pasemi_mac *mac)
541 {
542 struct pasemi_mac_rxring *rx = rx_ring(mac);
543 unsigned int i;
544 struct pasemi_mac_buffer *info;
545
546 for (i = 0; i < RX_RING_SIZE; i++) {
547 info = &RX_DESC_INFO(rx, i);
548 if (info->skb && info->dma) {
549 dma_unmap_single(&mac->dma_pdev->dev, info->dma,
550 info->skb->len, DMA_FROM_DEVICE);
551 dev_kfree_skb_any(info->skb);
552 }
553 info->dma = 0;
554 info->skb = NULL;
555 }
556
557 for (i = 0; i < RX_RING_SIZE; i++)
558 RX_BUFF(rx, i) = 0;
559 }
560
pasemi_mac_free_rx_resources(struct pasemi_mac * mac)561 static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac)
562 {
563 pasemi_mac_free_rx_buffers(mac);
564
565 dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
566 rx_ring(mac)->buffers, rx_ring(mac)->buf_dma);
567
568 kfree(rx_ring(mac)->ring_info);
569 pasemi_dma_free_chan(&rx_ring(mac)->chan);
570 mac->rx = NULL;
571 }
572
pasemi_mac_replenish_rx_ring(struct net_device * dev,const int limit)573 static void pasemi_mac_replenish_rx_ring(struct net_device *dev,
574 const int limit)
575 {
576 const struct pasemi_mac *mac = netdev_priv(dev);
577 struct pasemi_mac_rxring *rx = rx_ring(mac);
578 int fill, count;
579
580 if (limit <= 0)
581 return;
582
583 fill = rx_ring(mac)->next_to_fill;
584 for (count = 0; count < limit; count++) {
585 struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill);
586 u64 *buff = &RX_BUFF(rx, fill);
587 struct sk_buff *skb;
588 dma_addr_t dma;
589
590 /* Entry in use? */
591 WARN_ON(*buff);
592
593 skb = netdev_alloc_skb(dev, mac->bufsz);
594 skb_reserve(skb, LOCAL_SKB_ALIGN);
595
596 if (unlikely(!skb))
597 break;
598
599 dma = dma_map_single(&mac->dma_pdev->dev, skb->data,
600 mac->bufsz - LOCAL_SKB_ALIGN,
601 DMA_FROM_DEVICE);
602
603 if (dma_mapping_error(&mac->dma_pdev->dev, dma)) {
604 dev_kfree_skb_irq(info->skb);
605 break;
606 }
607
608 info->skb = skb;
609 info->dma = dma;
610 *buff = XCT_RXB_LEN(mac->bufsz) | XCT_RXB_ADDR(dma);
611 fill++;
612 }
613
614 wmb();
615
616 write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count);
617
618 rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) &
619 (RX_RING_SIZE - 1);
620 }
621
pasemi_mac_restart_rx_intr(const struct pasemi_mac * mac)622 static void pasemi_mac_restart_rx_intr(const struct pasemi_mac *mac)
623 {
624 struct pasemi_mac_rxring *rx = rx_ring(mac);
625 unsigned int reg, pcnt;
626 /* Re-enable packet count interrupts: finally
627 * ack the packet count interrupt we got in rx_intr.
628 */
629
630 pcnt = *rx->chan.status & PAS_STATUS_PCNT_M;
631
632 reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC;
633
634 if (*rx->chan.status & PAS_STATUS_TIMER)
635 reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
636
637 write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg);
638 }
639
pasemi_mac_restart_tx_intr(const struct pasemi_mac * mac)640 static void pasemi_mac_restart_tx_intr(const struct pasemi_mac *mac)
641 {
642 unsigned int reg, pcnt;
643
644 /* Re-enable packet count interrupts */
645 pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M;
646
647 reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
648
649 write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg);
650 }
651
652
pasemi_mac_rx_error(const struct pasemi_mac * mac,const u64 macrx)653 static inline void pasemi_mac_rx_error(const struct pasemi_mac *mac,
654 const u64 macrx)
655 {
656 unsigned int rcmdsta, ccmdsta;
657 struct pasemi_dmachan *chan = &rx_ring(mac)->chan;
658
659 if (!netif_msg_rx_err(mac))
660 return;
661
662 rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
663 ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno));
664
665 printk(KERN_ERR "pasemi_mac: rx error. macrx %016llx, rx status %llx\n",
666 macrx, *chan->status);
667
668 printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n",
669 rcmdsta, ccmdsta);
670 }
671
pasemi_mac_tx_error(const struct pasemi_mac * mac,const u64 mactx)672 static inline void pasemi_mac_tx_error(const struct pasemi_mac *mac,
673 const u64 mactx)
674 {
675 unsigned int cmdsta;
676 struct pasemi_dmachan *chan = &tx_ring(mac)->chan;
677
678 if (!netif_msg_tx_err(mac))
679 return;
680
681 cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno));
682
683 printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016llx, "\
684 "tx status 0x%016llx\n", mactx, *chan->status);
685
686 printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta);
687 }
688
pasemi_mac_clean_rx(struct pasemi_mac_rxring * rx,const int limit)689 static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx,
690 const int limit)
691 {
692 const struct pasemi_dmachan *chan = &rx->chan;
693 struct pasemi_mac *mac = rx->mac;
694 struct pci_dev *pdev = mac->dma_pdev;
695 unsigned int n;
696 int count, buf_index, tot_bytes, packets;
697 struct pasemi_mac_buffer *info;
698 struct sk_buff *skb;
699 unsigned int len;
700 u64 macrx, eval;
701 dma_addr_t dma;
702
703 tot_bytes = 0;
704 packets = 0;
705
706 spin_lock(&rx->lock);
707
708 n = rx->next_to_clean;
709
710 prefetch(&RX_DESC(rx, n));
711
712 for (count = 0; count < limit; count++) {
713 macrx = RX_DESC(rx, n);
714 prefetch(&RX_DESC(rx, n+4));
715
716 if ((macrx & XCT_MACRX_E) ||
717 (*chan->status & PAS_STATUS_ERROR))
718 pasemi_mac_rx_error(mac, macrx);
719
720 if (!(macrx & XCT_MACRX_O))
721 break;
722
723 info = NULL;
724
725 BUG_ON(!(macrx & XCT_MACRX_RR_8BRES));
726
727 eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >>
728 XCT_RXRES_8B_EVAL_S;
729 buf_index = eval-1;
730
731 dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M);
732 info = &RX_DESC_INFO(rx, buf_index);
733
734 skb = info->skb;
735
736 prefetch_skb(skb);
737
738 len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
739
740 dma_unmap_single(&pdev->dev, dma,
741 mac->bufsz - LOCAL_SKB_ALIGN,
742 DMA_FROM_DEVICE);
743
744 if (macrx & XCT_MACRX_CRC) {
745 /* CRC error flagged */
746 mac->netdev->stats.rx_errors++;
747 mac->netdev->stats.rx_crc_errors++;
748 /* No need to free skb, it'll be reused */
749 goto next;
750 }
751
752 info->skb = NULL;
753 info->dma = 0;
754
755 if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) {
756 skb->ip_summed = CHECKSUM_UNNECESSARY;
757 skb->csum = (macrx & XCT_MACRX_CSUM_M) >>
758 XCT_MACRX_CSUM_S;
759 } else {
760 skb_checksum_none_assert(skb);
761 }
762
763 packets++;
764 tot_bytes += len;
765
766 /* Don't include CRC */
767 skb_put(skb, len-4);
768
769 skb->protocol = eth_type_trans(skb, mac->netdev);
770 napi_gro_receive(&mac->napi, skb);
771
772 next:
773 RX_DESC(rx, n) = 0;
774 RX_DESC(rx, n+1) = 0;
775
776 /* Need to zero it out since hardware doesn't, since the
777 * replenish loop uses it to tell when it's done.
778 */
779 RX_BUFF(rx, buf_index) = 0;
780
781 n += 4;
782 }
783
784 if (n > RX_RING_SIZE) {
785 /* Errata 5971 workaround: L2 target of headers */
786 write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0);
787 n &= (RX_RING_SIZE-1);
788 }
789
790 rx_ring(mac)->next_to_clean = n;
791
792 /* Increase is in number of 16-byte entries, and since each descriptor
793 * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with
794 * count*2.
795 */
796 write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1);
797
798 pasemi_mac_replenish_rx_ring(mac->netdev, count);
799
800 mac->netdev->stats.rx_bytes += tot_bytes;
801 mac->netdev->stats.rx_packets += packets;
802
803 spin_unlock(&rx_ring(mac)->lock);
804
805 return count;
806 }
807
808 /* Can't make this too large or we blow the kernel stack limits */
809 #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS)
810
pasemi_mac_clean_tx(struct pasemi_mac_txring * txring)811 static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring)
812 {
813 struct pasemi_dmachan *chan = &txring->chan;
814 struct pasemi_mac *mac = txring->mac;
815 int i, j;
816 unsigned int start, descr_count, buf_count, batch_limit;
817 unsigned int ring_limit;
818 unsigned int total_count;
819 unsigned long flags;
820 struct sk_buff *skbs[TX_CLEAN_BATCHSIZE];
821 dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1];
822 int nf[TX_CLEAN_BATCHSIZE];
823 int nr_frags;
824
825 total_count = 0;
826 batch_limit = TX_CLEAN_BATCHSIZE;
827 restart:
828 spin_lock_irqsave(&txring->lock, flags);
829
830 start = txring->next_to_clean;
831 ring_limit = txring->next_to_fill;
832
833 prefetch(&TX_DESC_INFO(txring, start+1).skb);
834
835 /* Compensate for when fill has wrapped but clean has not */
836 if (start > ring_limit)
837 ring_limit += TX_RING_SIZE;
838
839 buf_count = 0;
840 descr_count = 0;
841
842 for (i = start;
843 descr_count < batch_limit && i < ring_limit;
844 i += buf_count) {
845 u64 mactx = TX_DESC(txring, i);
846 struct sk_buff *skb;
847
848 if ((mactx & XCT_MACTX_E) ||
849 (*chan->status & PAS_STATUS_ERROR))
850 pasemi_mac_tx_error(mac, mactx);
851
852 /* Skip over control descriptors */
853 if (!(mactx & XCT_MACTX_LLEN_M)) {
854 TX_DESC(txring, i) = 0;
855 TX_DESC(txring, i+1) = 0;
856 buf_count = 2;
857 continue;
858 }
859
860 skb = TX_DESC_INFO(txring, i+1).skb;
861 nr_frags = TX_DESC_INFO(txring, i).dma;
862
863 if (unlikely(mactx & XCT_MACTX_O))
864 /* Not yet transmitted */
865 break;
866
867 buf_count = 2 + nr_frags;
868 /* Since we always fill with an even number of entries, make
869 * sure we skip any unused one at the end as well.
870 */
871 if (buf_count & 1)
872 buf_count++;
873
874 for (j = 0; j <= nr_frags; j++)
875 dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma;
876
877 skbs[descr_count] = skb;
878 nf[descr_count] = nr_frags;
879
880 TX_DESC(txring, i) = 0;
881 TX_DESC(txring, i+1) = 0;
882
883 descr_count++;
884 }
885 txring->next_to_clean = i & (TX_RING_SIZE-1);
886
887 spin_unlock_irqrestore(&txring->lock, flags);
888 netif_wake_queue(mac->netdev);
889
890 for (i = 0; i < descr_count; i++)
891 pasemi_mac_unmap_tx_skb(mac, nf[i], skbs[i], dmas[i]);
892
893 total_count += descr_count;
894
895 /* If the batch was full, try to clean more */
896 if (descr_count == batch_limit)
897 goto restart;
898
899 return total_count;
900 }
901
902
pasemi_mac_rx_intr(int irq,void * data)903 static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
904 {
905 const struct pasemi_mac_rxring *rxring = data;
906 struct pasemi_mac *mac = rxring->mac;
907 const struct pasemi_dmachan *chan = &rxring->chan;
908 unsigned int reg;
909
910 if (!(*chan->status & PAS_STATUS_CAUSE_M))
911 return IRQ_NONE;
912
913 /* Don't reset packet count so it won't fire again but clear
914 * all others.
915 */
916
917 reg = 0;
918 if (*chan->status & PAS_STATUS_SOFT)
919 reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
920 if (*chan->status & PAS_STATUS_ERROR)
921 reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
922
923 napi_schedule(&mac->napi);
924
925 write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg);
926
927 return IRQ_HANDLED;
928 }
929
930 #define TX_CLEAN_INTERVAL HZ
931
pasemi_mac_tx_timer(struct timer_list * t)932 static void pasemi_mac_tx_timer(struct timer_list *t)
933 {
934 struct pasemi_mac_txring *txring = timer_container_of(txring, t,
935 clean_timer);
936 struct pasemi_mac *mac = txring->mac;
937
938 pasemi_mac_clean_tx(txring);
939
940 mod_timer(&txring->clean_timer, jiffies + TX_CLEAN_INTERVAL);
941
942 pasemi_mac_restart_tx_intr(mac);
943 }
944
pasemi_mac_tx_intr(int irq,void * data)945 static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
946 {
947 struct pasemi_mac_txring *txring = data;
948 const struct pasemi_dmachan *chan = &txring->chan;
949 struct pasemi_mac *mac = txring->mac;
950 unsigned int reg;
951
952 if (!(*chan->status & PAS_STATUS_CAUSE_M))
953 return IRQ_NONE;
954
955 reg = 0;
956
957 if (*chan->status & PAS_STATUS_SOFT)
958 reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
959 if (*chan->status & PAS_STATUS_ERROR)
960 reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
961
962 mod_timer(&txring->clean_timer, jiffies + (TX_CLEAN_INTERVAL)*2);
963
964 napi_schedule(&mac->napi);
965
966 if (reg)
967 write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg);
968
969 return IRQ_HANDLED;
970 }
971
pasemi_adjust_link(struct net_device * dev)972 static void pasemi_adjust_link(struct net_device *dev)
973 {
974 struct pasemi_mac *mac = netdev_priv(dev);
975 int msg;
976 unsigned int flags;
977 unsigned int new_flags;
978
979 if (!dev->phydev->link) {
980 /* If no link, MAC speed settings don't matter. Just report
981 * link down and return.
982 */
983 if (mac->link && netif_msg_link(mac))
984 printk(KERN_INFO "%s: Link is down.\n", dev->name);
985
986 netif_carrier_off(dev);
987 pasemi_mac_intf_disable(mac);
988 mac->link = 0;
989
990 return;
991 } else {
992 pasemi_mac_intf_enable(mac);
993 netif_carrier_on(dev);
994 }
995
996 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
997 new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M |
998 PAS_MAC_CFG_PCFG_TSR_M);
999
1000 if (!dev->phydev->duplex)
1001 new_flags |= PAS_MAC_CFG_PCFG_HD;
1002
1003 switch (dev->phydev->speed) {
1004 case 1000:
1005 new_flags |= PAS_MAC_CFG_PCFG_SPD_1G |
1006 PAS_MAC_CFG_PCFG_TSR_1G;
1007 break;
1008 case 100:
1009 new_flags |= PAS_MAC_CFG_PCFG_SPD_100M |
1010 PAS_MAC_CFG_PCFG_TSR_100M;
1011 break;
1012 case 10:
1013 new_flags |= PAS_MAC_CFG_PCFG_SPD_10M |
1014 PAS_MAC_CFG_PCFG_TSR_10M;
1015 break;
1016 default:
1017 printk("Unsupported speed %d\n", dev->phydev->speed);
1018 }
1019
1020 /* Print on link or speed/duplex change */
1021 msg = mac->link != dev->phydev->link || flags != new_flags;
1022
1023 mac->duplex = dev->phydev->duplex;
1024 mac->speed = dev->phydev->speed;
1025 mac->link = dev->phydev->link;
1026
1027 if (new_flags != flags)
1028 write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags);
1029
1030 if (msg && netif_msg_link(mac))
1031 printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n",
1032 dev->name, mac->speed, mac->duplex ? "full" : "half");
1033 }
1034
pasemi_mac_phy_init(struct net_device * dev)1035 static int pasemi_mac_phy_init(struct net_device *dev)
1036 {
1037 struct pasemi_mac *mac = netdev_priv(dev);
1038 struct device_node *dn, *phy_dn;
1039 struct phy_device *phydev;
1040
1041 dn = pci_device_to_OF_node(mac->pdev);
1042 phy_dn = of_parse_phandle(dn, "phy-handle", 0);
1043
1044 mac->link = 0;
1045 mac->speed = 0;
1046 mac->duplex = -1;
1047
1048 phydev = of_phy_connect(dev, phy_dn, &pasemi_adjust_link, 0,
1049 PHY_INTERFACE_MODE_SGMII);
1050
1051 of_node_put(phy_dn);
1052 if (!phydev) {
1053 printk(KERN_ERR "%s: Could not attach to phy\n", dev->name);
1054 return -ENODEV;
1055 }
1056
1057 return 0;
1058 }
1059
1060
pasemi_mac_open(struct net_device * dev)1061 static int pasemi_mac_open(struct net_device *dev)
1062 {
1063 struct pasemi_mac *mac = netdev_priv(dev);
1064 unsigned int flags;
1065 int i, ret;
1066
1067 flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
1068 PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
1069 PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
1070
1071 write_mac_reg(mac, PAS_MAC_CFG_TXP, flags);
1072
1073 ret = pasemi_mac_setup_rx_resources(dev);
1074 if (ret)
1075 goto out_rx_resources;
1076
1077 mac->tx = pasemi_mac_setup_tx_resources(dev);
1078
1079 if (!mac->tx) {
1080 ret = -ENOMEM;
1081 goto out_tx_ring;
1082 }
1083
1084 /* We might already have allocated rings in case mtu was changed
1085 * before interface was brought up.
1086 */
1087 if (dev->mtu > 1500 && !mac->num_cs) {
1088 pasemi_mac_setup_csrings(mac);
1089 if (!mac->num_cs) {
1090 ret = -ENOMEM;
1091 goto out_tx_ring;
1092 }
1093 }
1094
1095 /* Zero out rmon counters */
1096 for (i = 0; i < 32; i++)
1097 write_mac_reg(mac, PAS_MAC_RMON(i), 0);
1098
1099 /* 0x3ff with 33MHz clock is about 31us */
1100 write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG,
1101 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff));
1102
1103 write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno),
1104 PAS_IOB_DMA_RXCH_CFG_CNTTH(256));
1105
1106 write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno),
1107 PAS_IOB_DMA_TXCH_CFG_CNTTH(32));
1108
1109 write_mac_reg(mac, PAS_MAC_IPC_CHNL,
1110 PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) |
1111 PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno));
1112
1113 /* enable rx if */
1114 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
1115 PAS_DMA_RXINT_RCMDSTA_EN |
1116 PAS_DMA_RXINT_RCMDSTA_DROPS_M |
1117 PAS_DMA_RXINT_RCMDSTA_BP |
1118 PAS_DMA_RXINT_RCMDSTA_OO |
1119 PAS_DMA_RXINT_RCMDSTA_BT);
1120
1121 /* enable rx channel */
1122 pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU |
1123 PAS_DMA_RXCHAN_CCMDSTA_OD |
1124 PAS_DMA_RXCHAN_CCMDSTA_FD |
1125 PAS_DMA_RXCHAN_CCMDSTA_DT);
1126
1127 /* enable tx channel */
1128 pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ |
1129 PAS_DMA_TXCHAN_TCMDSTA_DB |
1130 PAS_DMA_TXCHAN_TCMDSTA_DE |
1131 PAS_DMA_TXCHAN_TCMDSTA_DA);
1132
1133 pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE);
1134
1135 write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno),
1136 RX_RING_SIZE>>1);
1137
1138 /* Clear out any residual packet count state from firmware */
1139 pasemi_mac_restart_rx_intr(mac);
1140 pasemi_mac_restart_tx_intr(mac);
1141
1142 flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
1143
1144 if (mac->type == MAC_TYPE_GMAC)
1145 flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
1146 else
1147 flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G;
1148
1149 /* Enable interface in MAC */
1150 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
1151
1152 ret = pasemi_mac_phy_init(dev);
1153 if (ret) {
1154 /* Since we won't get link notification, just enable RX */
1155 pasemi_mac_intf_enable(mac);
1156 if (mac->type == MAC_TYPE_GMAC) {
1157 /* Warn for missing PHY on SGMII (1Gig) ports */
1158 dev_warn(&mac->pdev->dev,
1159 "PHY init failed: %d.\n", ret);
1160 dev_warn(&mac->pdev->dev,
1161 "Defaulting to 1Gbit full duplex\n");
1162 }
1163 }
1164
1165 netif_start_queue(dev);
1166 napi_enable(&mac->napi);
1167
1168 snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx",
1169 dev->name);
1170
1171 ret = request_irq(mac->tx->chan.irq, pasemi_mac_tx_intr, 0,
1172 mac->tx_irq_name, mac->tx);
1173 if (ret) {
1174 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
1175 mac->tx->chan.irq, ret);
1176 goto out_tx_int;
1177 }
1178
1179 snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx",
1180 dev->name);
1181
1182 ret = request_irq(mac->rx->chan.irq, pasemi_mac_rx_intr, 0,
1183 mac->rx_irq_name, mac->rx);
1184 if (ret) {
1185 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
1186 mac->rx->chan.irq, ret);
1187 goto out_rx_int;
1188 }
1189
1190 if (dev->phydev)
1191 phy_start(dev->phydev);
1192
1193 timer_setup(&mac->tx->clean_timer, pasemi_mac_tx_timer, 0);
1194 mod_timer(&mac->tx->clean_timer, jiffies + HZ);
1195
1196 return 0;
1197
1198 out_rx_int:
1199 free_irq(mac->tx->chan.irq, mac->tx);
1200 out_tx_int:
1201 napi_disable(&mac->napi);
1202 netif_stop_queue(dev);
1203 out_tx_ring:
1204 if (mac->tx)
1205 pasemi_mac_free_tx_resources(mac);
1206 pasemi_mac_free_rx_resources(mac);
1207 out_rx_resources:
1208
1209 return ret;
1210 }
1211
1212 #define MAX_RETRIES 5000
1213
pasemi_mac_pause_txchan(struct pasemi_mac * mac)1214 static void pasemi_mac_pause_txchan(struct pasemi_mac *mac)
1215 {
1216 unsigned int sta, retries;
1217 int txch = tx_ring(mac)->chan.chno;
1218
1219 write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch),
1220 PAS_DMA_TXCHAN_TCMDSTA_ST);
1221
1222 for (retries = 0; retries < MAX_RETRIES; retries++) {
1223 sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch));
1224 if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT))
1225 break;
1226 cond_resched();
1227 }
1228
1229 if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)
1230 dev_err(&mac->dma_pdev->dev,
1231 "Failed to stop tx channel, tcmdsta %08x\n", sta);
1232
1233 write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0);
1234 }
1235
pasemi_mac_pause_rxchan(struct pasemi_mac * mac)1236 static void pasemi_mac_pause_rxchan(struct pasemi_mac *mac)
1237 {
1238 unsigned int sta, retries;
1239 int rxch = rx_ring(mac)->chan.chno;
1240
1241 write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch),
1242 PAS_DMA_RXCHAN_CCMDSTA_ST);
1243 for (retries = 0; retries < MAX_RETRIES; retries++) {
1244 sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
1245 if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT))
1246 break;
1247 cond_resched();
1248 }
1249
1250 if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)
1251 dev_err(&mac->dma_pdev->dev,
1252 "Failed to stop rx channel, ccmdsta 08%x\n", sta);
1253 write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0);
1254 }
1255
pasemi_mac_pause_rxint(struct pasemi_mac * mac)1256 static void pasemi_mac_pause_rxint(struct pasemi_mac *mac)
1257 {
1258 unsigned int sta, retries;
1259
1260 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
1261 PAS_DMA_RXINT_RCMDSTA_ST);
1262 for (retries = 0; retries < MAX_RETRIES; retries++) {
1263 sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
1264 if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT))
1265 break;
1266 cond_resched();
1267 }
1268
1269 if (sta & PAS_DMA_RXINT_RCMDSTA_ACT)
1270 dev_err(&mac->dma_pdev->dev,
1271 "Failed to stop rx interface, rcmdsta %08x\n", sta);
1272 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
1273 }
1274
pasemi_mac_close(struct net_device * dev)1275 static int pasemi_mac_close(struct net_device *dev)
1276 {
1277 struct pasemi_mac *mac = netdev_priv(dev);
1278 unsigned int sta;
1279 int rxch, txch, i;
1280
1281 rxch = rx_ring(mac)->chan.chno;
1282 txch = tx_ring(mac)->chan.chno;
1283
1284 if (dev->phydev) {
1285 phy_stop(dev->phydev);
1286 phy_disconnect(dev->phydev);
1287 }
1288
1289 timer_delete_sync(&mac->tx->clean_timer);
1290
1291 netif_stop_queue(dev);
1292 napi_disable(&mac->napi);
1293
1294 sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
1295 if (sta & (PAS_DMA_RXINT_RCMDSTA_BP |
1296 PAS_DMA_RXINT_RCMDSTA_OO |
1297 PAS_DMA_RXINT_RCMDSTA_BT))
1298 printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta);
1299
1300 sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
1301 if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU |
1302 PAS_DMA_RXCHAN_CCMDSTA_OD |
1303 PAS_DMA_RXCHAN_CCMDSTA_FD |
1304 PAS_DMA_RXCHAN_CCMDSTA_DT))
1305 printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta);
1306
1307 sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch));
1308 if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB |
1309 PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA))
1310 printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta);
1311
1312 /* Clean out any pending buffers */
1313 pasemi_mac_clean_tx(tx_ring(mac));
1314 pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE);
1315
1316 pasemi_mac_pause_txchan(mac);
1317 pasemi_mac_pause_rxint(mac);
1318 pasemi_mac_pause_rxchan(mac);
1319 pasemi_mac_intf_disable(mac);
1320
1321 free_irq(mac->tx->chan.irq, mac->tx);
1322 free_irq(mac->rx->chan.irq, mac->rx);
1323
1324 for (i = 0; i < mac->num_cs; i++) {
1325 pasemi_mac_free_csring(mac->cs[i]);
1326 mac->cs[i] = NULL;
1327 }
1328
1329 mac->num_cs = 0;
1330
1331 /* Free resources */
1332 pasemi_mac_free_rx_resources(mac);
1333 pasemi_mac_free_tx_resources(mac);
1334
1335 return 0;
1336 }
1337
pasemi_mac_queue_csdesc(const struct sk_buff * skb,const dma_addr_t * map,const unsigned int * map_size,struct pasemi_mac_txring * txring,struct pasemi_mac_csring * csring)1338 static void pasemi_mac_queue_csdesc(const struct sk_buff *skb,
1339 const dma_addr_t *map,
1340 const unsigned int *map_size,
1341 struct pasemi_mac_txring *txring,
1342 struct pasemi_mac_csring *csring)
1343 {
1344 u64 fund;
1345 dma_addr_t cs_dest;
1346 const int nh_off = skb_network_offset(skb);
1347 const int nh_len = skb_network_header_len(skb);
1348 const int nfrags = skb_shinfo(skb)->nr_frags;
1349 int cs_size, i, fill, hdr, evt;
1350 dma_addr_t csdma;
1351
1352 fund = XCT_FUN_ST | XCT_FUN_RR_8BRES |
1353 XCT_FUN_O | XCT_FUN_FUN(csring->fun) |
1354 XCT_FUN_CRM_SIG | XCT_FUN_LLEN(skb->len - nh_off) |
1355 XCT_FUN_SHL(nh_len >> 2) | XCT_FUN_SE;
1356
1357 switch (ip_hdr(skb)->protocol) {
1358 case IPPROTO_TCP:
1359 fund |= XCT_FUN_SIG_TCP4;
1360 /* TCP checksum is 16 bytes into the header */
1361 cs_dest = map[0] + skb_transport_offset(skb) + 16;
1362 break;
1363 case IPPROTO_UDP:
1364 fund |= XCT_FUN_SIG_UDP4;
1365 /* UDP checksum is 6 bytes into the header */
1366 cs_dest = map[0] + skb_transport_offset(skb) + 6;
1367 break;
1368 default:
1369 BUG();
1370 }
1371
1372 /* Do the checksum offloaded */
1373 fill = csring->next_to_fill;
1374 hdr = fill;
1375
1376 CS_DESC(csring, fill++) = fund;
1377 /* Room for 8BRES. Checksum result is really 2 bytes into it */
1378 csdma = csring->chan.ring_dma + (fill & (CS_RING_SIZE-1)) * 8 + 2;
1379 CS_DESC(csring, fill++) = 0;
1380
1381 CS_DESC(csring, fill) = XCT_PTR_LEN(map_size[0]-nh_off) | XCT_PTR_ADDR(map[0]+nh_off);
1382 for (i = 1; i <= nfrags; i++)
1383 CS_DESC(csring, fill+i) = XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
1384
1385 fill += i;
1386 if (fill & 1)
1387 fill++;
1388
1389 /* Copy the result into the TCP packet */
1390 CS_DESC(csring, fill++) = XCT_FUN_O | XCT_FUN_FUN(csring->fun) |
1391 XCT_FUN_LLEN(2) | XCT_FUN_SE;
1392 CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(cs_dest) | XCT_PTR_T;
1393 CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(csdma);
1394 fill++;
1395
1396 evt = !csring->last_event;
1397 csring->last_event = evt;
1398
1399 /* Event handshaking with MAC TX */
1400 CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1401 CTRL_CMD_ETYPE_SET | CTRL_CMD_REG(csring->events[evt]);
1402 CS_DESC(csring, fill++) = 0;
1403 CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1404 CTRL_CMD_ETYPE_WCLR | CTRL_CMD_REG(csring->events[!evt]);
1405 CS_DESC(csring, fill++) = 0;
1406 csring->next_to_fill = fill & (CS_RING_SIZE-1);
1407
1408 cs_size = fill - hdr;
1409 write_dma_reg(PAS_DMA_TXCHAN_INCR(csring->chan.chno), (cs_size) >> 1);
1410
1411 /* TX-side event handshaking */
1412 fill = txring->next_to_fill;
1413 TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1414 CTRL_CMD_ETYPE_WSET | CTRL_CMD_REG(csring->events[evt]);
1415 TX_DESC(txring, fill++) = 0;
1416 TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1417 CTRL_CMD_ETYPE_CLR | CTRL_CMD_REG(csring->events[!evt]);
1418 TX_DESC(txring, fill++) = 0;
1419 txring->next_to_fill = fill;
1420
1421 write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), 2);
1422 }
1423
pasemi_mac_start_tx(struct sk_buff * skb,struct net_device * dev)1424 static netdev_tx_t pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
1425 {
1426 struct pasemi_mac * const mac = netdev_priv(dev);
1427 struct pasemi_mac_txring * const txring = tx_ring(mac);
1428 struct pasemi_mac_csring *csring;
1429 u64 dflags = 0;
1430 u64 mactx;
1431 dma_addr_t map[MAX_SKB_FRAGS+1];
1432 unsigned int map_size[MAX_SKB_FRAGS+1];
1433 unsigned long flags;
1434 int i, nfrags;
1435 int fill;
1436 const int nh_off = skb_network_offset(skb);
1437 const int nh_len = skb_network_header_len(skb);
1438
1439 prefetch(&txring->ring_info);
1440
1441 dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD;
1442
1443 nfrags = skb_shinfo(skb)->nr_frags;
1444
1445 map[0] = dma_map_single(&mac->dma_pdev->dev, skb->data,
1446 skb_headlen(skb), DMA_TO_DEVICE);
1447 map_size[0] = skb_headlen(skb);
1448 if (dma_mapping_error(&mac->dma_pdev->dev, map[0]))
1449 goto out_err_nolock;
1450
1451 for (i = 0; i < nfrags; i++) {
1452 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1453
1454 map[i + 1] = skb_frag_dma_map(&mac->dma_pdev->dev, frag, 0,
1455 skb_frag_size(frag), DMA_TO_DEVICE);
1456 map_size[i+1] = skb_frag_size(frag);
1457 if (dma_mapping_error(&mac->dma_pdev->dev, map[i + 1])) {
1458 nfrags = i;
1459 goto out_err_nolock;
1460 }
1461 }
1462
1463 if (skb->ip_summed == CHECKSUM_PARTIAL && skb->len <= 1540) {
1464 switch (ip_hdr(skb)->protocol) {
1465 case IPPROTO_TCP:
1466 dflags |= XCT_MACTX_CSUM_TCP;
1467 dflags |= XCT_MACTX_IPH(nh_len >> 2);
1468 dflags |= XCT_MACTX_IPO(nh_off);
1469 break;
1470 case IPPROTO_UDP:
1471 dflags |= XCT_MACTX_CSUM_UDP;
1472 dflags |= XCT_MACTX_IPH(nh_len >> 2);
1473 dflags |= XCT_MACTX_IPO(nh_off);
1474 break;
1475 default:
1476 WARN_ON(1);
1477 }
1478 }
1479
1480 mactx = dflags | XCT_MACTX_LLEN(skb->len);
1481
1482 spin_lock_irqsave(&txring->lock, flags);
1483
1484 /* Avoid stepping on the same cache line that the DMA controller
1485 * is currently about to send, so leave at least 8 words available.
1486 * Total free space needed is mactx + fragments + 8
1487 */
1488 if (RING_AVAIL(txring) < nfrags + 14) {
1489 /* no room -- stop the queue and wait for tx intr */
1490 netif_stop_queue(dev);
1491 goto out_err;
1492 }
1493
1494 /* Queue up checksum + event descriptors, if needed */
1495 if (mac->num_cs && skb->ip_summed == CHECKSUM_PARTIAL && skb->len > 1540) {
1496 csring = mac->cs[mac->last_cs];
1497 mac->last_cs = (mac->last_cs + 1) % mac->num_cs;
1498
1499 pasemi_mac_queue_csdesc(skb, map, map_size, txring, csring);
1500 }
1501
1502 fill = txring->next_to_fill;
1503 TX_DESC(txring, fill) = mactx;
1504 TX_DESC_INFO(txring, fill).dma = nfrags;
1505 fill++;
1506 TX_DESC_INFO(txring, fill).skb = skb;
1507 for (i = 0; i <= nfrags; i++) {
1508 TX_DESC(txring, fill+i) =
1509 XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
1510 TX_DESC_INFO(txring, fill+i).dma = map[i];
1511 }
1512
1513 /* We have to add an even number of 8-byte entries to the ring
1514 * even if the last one is unused. That means always an odd number
1515 * of pointers + one mactx descriptor.
1516 */
1517 if (nfrags & 1)
1518 nfrags++;
1519
1520 txring->next_to_fill = (fill + nfrags + 1) & (TX_RING_SIZE-1);
1521
1522 dev->stats.tx_packets++;
1523 dev->stats.tx_bytes += skb->len;
1524
1525 spin_unlock_irqrestore(&txring->lock, flags);
1526
1527 write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1);
1528
1529 return NETDEV_TX_OK;
1530
1531 out_err:
1532 spin_unlock_irqrestore(&txring->lock, flags);
1533 out_err_nolock:
1534 while (nfrags--)
1535 dma_unmap_single(&mac->dma_pdev->dev, map[nfrags],
1536 map_size[nfrags], DMA_TO_DEVICE);
1537
1538 return NETDEV_TX_BUSY;
1539 }
1540
pasemi_mac_set_rx_mode(struct net_device * dev)1541 static void pasemi_mac_set_rx_mode(struct net_device *dev)
1542 {
1543 const struct pasemi_mac *mac = netdev_priv(dev);
1544 unsigned int flags;
1545
1546 flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
1547
1548 /* Set promiscuous */
1549 if (dev->flags & IFF_PROMISC)
1550 flags |= PAS_MAC_CFG_PCFG_PR;
1551 else
1552 flags &= ~PAS_MAC_CFG_PCFG_PR;
1553
1554 write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
1555 }
1556
1557
pasemi_mac_poll(struct napi_struct * napi,int budget)1558 static int pasemi_mac_poll(struct napi_struct *napi, int budget)
1559 {
1560 struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi);
1561 int pkts;
1562
1563 pasemi_mac_clean_tx(tx_ring(mac));
1564 pkts = pasemi_mac_clean_rx(rx_ring(mac), budget);
1565 if (pkts < budget) {
1566 /* all done, no more packets present */
1567 napi_complete_done(napi, pkts);
1568
1569 pasemi_mac_restart_rx_intr(mac);
1570 pasemi_mac_restart_tx_intr(mac);
1571 }
1572 return pkts;
1573 }
1574
1575 #ifdef CONFIG_NET_POLL_CONTROLLER
1576 /*
1577 * Polling 'interrupt' - used by things like netconsole to send skbs
1578 * without having to re-enable interrupts. It's not called while
1579 * the interrupt routine is executing.
1580 */
pasemi_mac_netpoll(struct net_device * dev)1581 static void pasemi_mac_netpoll(struct net_device *dev)
1582 {
1583 const struct pasemi_mac *mac = netdev_priv(dev);
1584
1585 disable_irq(mac->tx->chan.irq);
1586 pasemi_mac_tx_intr(mac->tx->chan.irq, mac->tx);
1587 enable_irq(mac->tx->chan.irq);
1588
1589 disable_irq(mac->rx->chan.irq);
1590 pasemi_mac_rx_intr(mac->rx->chan.irq, mac->rx);
1591 enable_irq(mac->rx->chan.irq);
1592 }
1593 #endif
1594
pasemi_mac_change_mtu(struct net_device * dev,int new_mtu)1595 static int pasemi_mac_change_mtu(struct net_device *dev, int new_mtu)
1596 {
1597 struct pasemi_mac *mac = netdev_priv(dev);
1598 unsigned int reg;
1599 unsigned int rcmdsta = 0;
1600 int running;
1601 int ret = 0;
1602
1603 running = netif_running(dev);
1604
1605 if (running) {
1606 /* Need to stop the interface, clean out all already
1607 * received buffers, free all unused buffers on the RX
1608 * interface ring, then finally re-fill the rx ring with
1609 * the new-size buffers and restart.
1610 */
1611
1612 napi_disable(&mac->napi);
1613 netif_tx_disable(dev);
1614 pasemi_mac_intf_disable(mac);
1615
1616 rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
1617 pasemi_mac_pause_rxint(mac);
1618 pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE);
1619 pasemi_mac_free_rx_buffers(mac);
1620
1621 }
1622
1623 /* Setup checksum channels if large MTU and none already allocated */
1624 if (new_mtu > PE_DEF_MTU && !mac->num_cs) {
1625 pasemi_mac_setup_csrings(mac);
1626 if (!mac->num_cs) {
1627 ret = -ENOMEM;
1628 goto out;
1629 }
1630 }
1631
1632 /* Change maxf, i.e. what size frames are accepted.
1633 * Need room for ethernet header and CRC word
1634 */
1635 reg = read_mac_reg(mac, PAS_MAC_CFG_MACCFG);
1636 reg &= ~PAS_MAC_CFG_MACCFG_MAXF_M;
1637 reg |= PAS_MAC_CFG_MACCFG_MAXF(new_mtu + ETH_HLEN + 4);
1638 write_mac_reg(mac, PAS_MAC_CFG_MACCFG, reg);
1639
1640 WRITE_ONCE(dev->mtu, new_mtu);
1641 /* MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
1642 mac->bufsz = new_mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128;
1643
1644 out:
1645 if (running) {
1646 write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
1647 rcmdsta | PAS_DMA_RXINT_RCMDSTA_EN);
1648
1649 rx_ring(mac)->next_to_fill = 0;
1650 pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE-1);
1651
1652 napi_enable(&mac->napi);
1653 netif_start_queue(dev);
1654 pasemi_mac_intf_enable(mac);
1655 }
1656
1657 return ret;
1658 }
1659
1660 static const struct net_device_ops pasemi_netdev_ops = {
1661 .ndo_open = pasemi_mac_open,
1662 .ndo_stop = pasemi_mac_close,
1663 .ndo_start_xmit = pasemi_mac_start_tx,
1664 .ndo_set_rx_mode = pasemi_mac_set_rx_mode,
1665 .ndo_set_mac_address = pasemi_mac_set_mac_addr,
1666 .ndo_change_mtu = pasemi_mac_change_mtu,
1667 .ndo_validate_addr = eth_validate_addr,
1668 #ifdef CONFIG_NET_POLL_CONTROLLER
1669 .ndo_poll_controller = pasemi_mac_netpoll,
1670 #endif
1671 };
1672
1673 static int
pasemi_mac_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1674 pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1675 {
1676 struct net_device *dev;
1677 struct pasemi_mac *mac;
1678 int err, ret;
1679
1680 err = pci_enable_device(pdev);
1681 if (err)
1682 return err;
1683
1684 dev = alloc_etherdev(sizeof(struct pasemi_mac));
1685 if (dev == NULL) {
1686 err = -ENOMEM;
1687 goto out_disable_device;
1688 }
1689
1690 pci_set_drvdata(pdev, dev);
1691 SET_NETDEV_DEV(dev, &pdev->dev);
1692
1693 mac = netdev_priv(dev);
1694
1695 mac->pdev = pdev;
1696 mac->netdev = dev;
1697
1698 netif_napi_add(dev, &mac->napi, pasemi_mac_poll);
1699
1700 dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA |
1701 NETIF_F_GSO;
1702 dev->lltx = true;
1703
1704 mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
1705 if (!mac->dma_pdev) {
1706 dev_err(&mac->pdev->dev, "Can't find DMA Controller\n");
1707 err = -ENODEV;
1708 goto out;
1709 }
1710 dma_set_mask(&mac->dma_pdev->dev, DMA_BIT_MASK(64));
1711
1712 mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
1713 if (!mac->iob_pdev) {
1714 dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n");
1715 err = -ENODEV;
1716 goto out;
1717 }
1718
1719 /* get mac addr from device tree */
1720 if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
1721 err = -ENODEV;
1722 goto out;
1723 }
1724 eth_hw_addr_set(dev, mac->mac_addr);
1725
1726 ret = mac_to_intf(mac);
1727 if (ret < 0) {
1728 dev_err(&mac->pdev->dev, "Can't map DMA interface\n");
1729 err = -ENODEV;
1730 goto out;
1731 }
1732 mac->dma_if = ret;
1733
1734 switch (pdev->device) {
1735 case 0xa005:
1736 mac->type = MAC_TYPE_GMAC;
1737 break;
1738 case 0xa006:
1739 mac->type = MAC_TYPE_XAUI;
1740 break;
1741 default:
1742 err = -ENODEV;
1743 goto out;
1744 }
1745
1746 dev->netdev_ops = &pasemi_netdev_ops;
1747 dev->mtu = PE_DEF_MTU;
1748
1749 /* MTU range: 64 - 9000 */
1750 dev->min_mtu = PE_MIN_MTU;
1751 dev->max_mtu = PE_MAX_MTU;
1752
1753 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
1754 mac->bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128;
1755
1756 dev->ethtool_ops = &pasemi_mac_ethtool_ops;
1757
1758 if (err)
1759 goto out;
1760
1761 mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1762
1763 /* Enable most messages by default */
1764 mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1765
1766 err = register_netdev(dev);
1767
1768 if (err) {
1769 dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
1770 err);
1771 goto out;
1772 } else if (netif_msg_probe(mac)) {
1773 printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %pM\n",
1774 dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
1775 mac->dma_if, dev->dev_addr);
1776 }
1777
1778 return err;
1779
1780 out:
1781 pci_dev_put(mac->iob_pdev);
1782 pci_dev_put(mac->dma_pdev);
1783
1784 free_netdev(dev);
1785 out_disable_device:
1786 pci_disable_device(pdev);
1787 return err;
1788
1789 }
1790
pasemi_mac_remove(struct pci_dev * pdev)1791 static void pasemi_mac_remove(struct pci_dev *pdev)
1792 {
1793 struct net_device *netdev = pci_get_drvdata(pdev);
1794 struct pasemi_mac *mac;
1795
1796 if (!netdev)
1797 return;
1798
1799 mac = netdev_priv(netdev);
1800
1801 unregister_netdev(netdev);
1802
1803 pci_disable_device(pdev);
1804 pci_dev_put(mac->dma_pdev);
1805 pci_dev_put(mac->iob_pdev);
1806
1807 pasemi_dma_free_chan(&mac->tx->chan);
1808 pasemi_dma_free_chan(&mac->rx->chan);
1809
1810 free_netdev(netdev);
1811 }
1812
1813 static const struct pci_device_id pasemi_mac_pci_tbl[] = {
1814 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
1815 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
1816 { },
1817 };
1818
1819 MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
1820
1821 static struct pci_driver pasemi_mac_driver = {
1822 .name = "pasemi_mac",
1823 .id_table = pasemi_mac_pci_tbl,
1824 .probe = pasemi_mac_probe,
1825 .remove = pasemi_mac_remove,
1826 };
1827
pasemi_mac_cleanup_module(void)1828 static void __exit pasemi_mac_cleanup_module(void)
1829 {
1830 pci_unregister_driver(&pasemi_mac_driver);
1831 }
1832
pasemi_mac_init_module(void)1833 static int pasemi_mac_init_module(void)
1834 {
1835 int err;
1836
1837 err = pasemi_dma_init();
1838 if (err)
1839 return err;
1840
1841 return pci_register_driver(&pasemi_mac_driver);
1842 }
1843
1844 module_init(pasemi_mac_init_module);
1845 module_exit(pasemi_mac_cleanup_module);
1846