1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Ke Yu
25 * Kevin Tian <kevin.tian@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Ping Gao <ping.a.gao@intel.com>
31 * Tina Zhang <tina.zhang@intel.com>
32 * Yulei Zhang <yulei.zhang@intel.com>
33 * Zhi Wang <zhi.a.wang@intel.com>
34 *
35 */
36
37 #include <linux/slab.h>
38
39 #include <drm/drm_print.h>
40
41 #include "display/i9xx_plane_regs.h"
42 #include "display/intel_display_regs.h"
43 #include "display/intel_sprite_regs.h"
44
45 #include "gem/i915_gem_context.h"
46 #include "gem/i915_gem_pm.h"
47
48 #include "gt/intel_context.h"
49 #include "gt/intel_engine_regs.h"
50 #include "gt/intel_gpu_commands.h"
51 #include "gt/intel_gt_regs.h"
52 #include "gt/intel_gt_requests.h"
53 #include "gt/intel_lrc.h"
54 #include "gt/intel_ring.h"
55 #include "gt/shmem_utils.h"
56
57 #include "display_helpers.h"
58 #include "gvt.h"
59 #include "i915_drv.h"
60 #include "i915_pvinfo.h"
61 #include "i915_reg.h"
62 #include "trace.h"
63
64 #define INVALID_OP (~0U)
65
66 #define OP_LEN_MI 9
67 #define OP_LEN_2D 10
68 #define OP_LEN_3D_MEDIA 16
69 #define OP_LEN_MFX_VC 16
70 #define OP_LEN_VEBOX 16
71
72 #define CMD_TYPE(cmd) (((cmd) >> 29) & 7)
73
74 struct sub_op_bits {
75 int hi;
76 int low;
77 };
78 struct decode_info {
79 const char *name;
80 int op_len;
81 int nr_sub_op;
82 const struct sub_op_bits *sub_op;
83 };
84
85 #define MAX_CMD_BUDGET 0x7fffffff
86 #define MI_WAIT_FOR_PLANE_C_FLIP_PENDING (1<<15)
87 #define MI_WAIT_FOR_PLANE_B_FLIP_PENDING (1<<9)
88 #define MI_WAIT_FOR_PLANE_A_FLIP_PENDING (1<<1)
89
90 #define MI_WAIT_FOR_SPRITE_C_FLIP_PENDING (1<<20)
91 #define MI_WAIT_FOR_SPRITE_B_FLIP_PENDING (1<<10)
92 #define MI_WAIT_FOR_SPRITE_A_FLIP_PENDING (1<<2)
93
94 /* Render Command Map */
95
96 /* MI_* command Opcode (28:23) */
97 #define OP_MI_NOOP 0x0
98 #define OP_MI_SET_PREDICATE 0x1 /* HSW+ */
99 #define OP_MI_USER_INTERRUPT 0x2
100 #define OP_MI_WAIT_FOR_EVENT 0x3
101 #define OP_MI_FLUSH 0x4
102 #define OP_MI_ARB_CHECK 0x5
103 #define OP_MI_RS_CONTROL 0x6 /* HSW+ */
104 #define OP_MI_REPORT_HEAD 0x7
105 #define OP_MI_ARB_ON_OFF 0x8
106 #define OP_MI_URB_ATOMIC_ALLOC 0x9 /* HSW+ */
107 #define OP_MI_BATCH_BUFFER_END 0xA
108 #define OP_MI_SUSPEND_FLUSH 0xB
109 #define OP_MI_PREDICATE 0xC /* IVB+ */
110 #define OP_MI_TOPOLOGY_FILTER 0xD /* IVB+ */
111 #define OP_MI_SET_APPID 0xE /* IVB+ */
112 #define OP_MI_RS_CONTEXT 0xF /* HSW+ */
113 #define OP_MI_LOAD_SCAN_LINES_INCL 0x12 /* HSW+ */
114 #define OP_MI_DISPLAY_FLIP 0x14
115 #define OP_MI_SEMAPHORE_MBOX 0x16
116 #define OP_MI_SET_CONTEXT 0x18
117 #define OP_MI_MATH 0x1A
118 #define OP_MI_URB_CLEAR 0x19
119 #define OP_MI_SEMAPHORE_SIGNAL 0x1B /* BDW+ */
120 #define OP_MI_SEMAPHORE_WAIT 0x1C /* BDW+ */
121
122 #define OP_MI_STORE_DATA_IMM 0x20
123 #define OP_MI_STORE_DATA_INDEX 0x21
124 #define OP_MI_LOAD_REGISTER_IMM 0x22
125 #define OP_MI_UPDATE_GTT 0x23
126 #define OP_MI_STORE_REGISTER_MEM 0x24
127 #define OP_MI_FLUSH_DW 0x26
128 #define OP_MI_CLFLUSH 0x27
129 #define OP_MI_REPORT_PERF_COUNT 0x28
130 #define OP_MI_LOAD_REGISTER_MEM 0x29 /* HSW+ */
131 #define OP_MI_LOAD_REGISTER_REG 0x2A /* HSW+ */
132 #define OP_MI_RS_STORE_DATA_IMM 0x2B /* HSW+ */
133 #define OP_MI_LOAD_URB_MEM 0x2C /* HSW+ */
134 #define OP_MI_STORE_URM_MEM 0x2D /* HSW+ */
135 #define OP_MI_2E 0x2E /* BDW+ */
136 #define OP_MI_2F 0x2F /* BDW+ */
137 #define OP_MI_BATCH_BUFFER_START 0x31
138
139 /* Bit definition for dword 0 */
140 #define _CMDBIT_BB_START_IN_PPGTT (1UL << 8)
141
142 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END 0x36
143
144 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
145 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
146 #define BATCH_BUFFER_ADR_SPACE_BIT(x) (((x) >> 8) & 1U)
147 #define BATCH_BUFFER_2ND_LEVEL_BIT(x) ((x) >> 22 & 1U)
148
149 /* 2D command: Opcode (28:22) */
150 #define OP_2D(x) ((2<<7) | x)
151
152 #define OP_XY_SETUP_BLT OP_2D(0x1)
153 #define OP_XY_SETUP_CLIP_BLT OP_2D(0x3)
154 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT OP_2D(0x11)
155 #define OP_XY_PIXEL_BLT OP_2D(0x24)
156 #define OP_XY_SCANLINES_BLT OP_2D(0x25)
157 #define OP_XY_TEXT_BLT OP_2D(0x26)
158 #define OP_XY_TEXT_IMMEDIATE_BLT OP_2D(0x31)
159 #define OP_XY_COLOR_BLT OP_2D(0x50)
160 #define OP_XY_PAT_BLT OP_2D(0x51)
161 #define OP_XY_MONO_PAT_BLT OP_2D(0x52)
162 #define OP_XY_SRC_COPY_BLT OP_2D(0x53)
163 #define OP_XY_MONO_SRC_COPY_BLT OP_2D(0x54)
164 #define OP_XY_FULL_BLT OP_2D(0x55)
165 #define OP_XY_FULL_MONO_SRC_BLT OP_2D(0x56)
166 #define OP_XY_FULL_MONO_PATTERN_BLT OP_2D(0x57)
167 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT OP_2D(0x58)
168 #define OP_XY_MONO_PAT_FIXED_BLT OP_2D(0x59)
169 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT OP_2D(0x71)
170 #define OP_XY_PAT_BLT_IMMEDIATE OP_2D(0x72)
171 #define OP_XY_SRC_COPY_CHROMA_BLT OP_2D(0x73)
172 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT OP_2D(0x74)
173 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT OP_2D(0x75)
174 #define OP_XY_PAT_CHROMA_BLT OP_2D(0x76)
175 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE OP_2D(0x77)
176
177 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
178 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
179 ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
180
181 #define OP_STATE_PREFETCH OP_3D_MEDIA(0x0, 0x0, 0x03)
182
183 #define OP_STATE_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x01)
184 #define OP_STATE_SIP OP_3D_MEDIA(0x0, 0x1, 0x02)
185 #define OP_3D_MEDIA_0_1_4 OP_3D_MEDIA(0x0, 0x1, 0x04)
186 #define OP_SWTESS_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x03)
187
188 #define OP_3DSTATE_VF_STATISTICS_GM45 OP_3D_MEDIA(0x1, 0x0, 0x0B)
189
190 #define OP_PIPELINE_SELECT OP_3D_MEDIA(0x1, 0x1, 0x04)
191
192 #define OP_MEDIA_VFE_STATE OP_3D_MEDIA(0x2, 0x0, 0x0)
193 #define OP_MEDIA_CURBE_LOAD OP_3D_MEDIA(0x2, 0x0, 0x1)
194 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD OP_3D_MEDIA(0x2, 0x0, 0x2)
195 #define OP_MEDIA_GATEWAY_STATE OP_3D_MEDIA(0x2, 0x0, 0x3)
196 #define OP_MEDIA_STATE_FLUSH OP_3D_MEDIA(0x2, 0x0, 0x4)
197 #define OP_MEDIA_POOL_STATE OP_3D_MEDIA(0x2, 0x0, 0x5)
198
199 #define OP_MEDIA_OBJECT OP_3D_MEDIA(0x2, 0x1, 0x0)
200 #define OP_MEDIA_OBJECT_PRT OP_3D_MEDIA(0x2, 0x1, 0x2)
201 #define OP_MEDIA_OBJECT_WALKER OP_3D_MEDIA(0x2, 0x1, 0x3)
202 #define OP_GPGPU_WALKER OP_3D_MEDIA(0x2, 0x1, 0x5)
203
204 #define OP_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
205 #define OP_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
206 #define OP_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
207 #define OP_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
208 #define OP_3DSTATE_VERTEX_BUFFERS OP_3D_MEDIA(0x3, 0x0, 0x08)
209 #define OP_3DSTATE_VERTEX_ELEMENTS OP_3D_MEDIA(0x3, 0x0, 0x09)
210 #define OP_3DSTATE_INDEX_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x0A)
211 #define OP_3DSTATE_VF_STATISTICS OP_3D_MEDIA(0x3, 0x0, 0x0B)
212 #define OP_3DSTATE_VF OP_3D_MEDIA(0x3, 0x0, 0x0C) /* HSW+ */
213 #define OP_3DSTATE_CC_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0E)
214 #define OP_3DSTATE_SCISSOR_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0F)
215 #define OP_3DSTATE_VS OP_3D_MEDIA(0x3, 0x0, 0x10)
216 #define OP_3DSTATE_GS OP_3D_MEDIA(0x3, 0x0, 0x11)
217 #define OP_3DSTATE_CLIP OP_3D_MEDIA(0x3, 0x0, 0x12)
218 #define OP_3DSTATE_SF OP_3D_MEDIA(0x3, 0x0, 0x13)
219 #define OP_3DSTATE_WM OP_3D_MEDIA(0x3, 0x0, 0x14)
220 #define OP_3DSTATE_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x15)
221 #define OP_3DSTATE_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x16)
222 #define OP_3DSTATE_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x17)
223 #define OP_3DSTATE_SAMPLE_MASK OP_3D_MEDIA(0x3, 0x0, 0x18)
224 #define OP_3DSTATE_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
225 #define OP_3DSTATE_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
226 #define OP_3DSTATE_HS OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
227 #define OP_3DSTATE_TE OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
228 #define OP_3DSTATE_DS OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
229 #define OP_3DSTATE_STREAMOUT OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
230 #define OP_3DSTATE_SBE OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
231 #define OP_3DSTATE_PS OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
232 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
233 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
234 #define OP_3DSTATE_BLEND_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
235 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
236 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
237 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
238 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
239 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
240 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
241 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
242 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
243 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
244 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
245 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
246 #define OP_3DSTATE_URB_VS OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
247 #define OP_3DSTATE_URB_HS OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
248 #define OP_3DSTATE_URB_DS OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
249 #define OP_3DSTATE_URB_GS OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
250 #define OP_3DSTATE_GATHER_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
251 #define OP_3DSTATE_GATHER_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
252 #define OP_3DSTATE_GATHER_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
253 #define OP_3DSTATE_GATHER_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
254 #define OP_3DSTATE_GATHER_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
255 #define OP_3DSTATE_DX9_CONSTANTF_VS OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
256 #define OP_3DSTATE_DX9_CONSTANTF_PS OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
257 #define OP_3DSTATE_DX9_CONSTANTI_VS OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
258 #define OP_3DSTATE_DX9_CONSTANTI_PS OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
259 #define OP_3DSTATE_DX9_CONSTANTB_VS OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
260 #define OP_3DSTATE_DX9_CONSTANTB_PS OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
261 #define OP_3DSTATE_DX9_LOCAL_VALID_VS OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
262 #define OP_3DSTATE_DX9_LOCAL_VALID_PS OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
263 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
264 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
265 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
266 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
267 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
268 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
269 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
270
271 #define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
272 #define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
273 #define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
274 #define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
275 #define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
276 #define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
277 #define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
278 #define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
279 #define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
280 #define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
281 #define OP_3DSTATE_COMPONENT_PACKING OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
282
283 #define OP_3DSTATE_DRAWING_RECTANGLE OP_3D_MEDIA(0x3, 0x1, 0x00)
284 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0 OP_3D_MEDIA(0x3, 0x1, 0x02)
285 #define OP_3DSTATE_CHROMA_KEY OP_3D_MEDIA(0x3, 0x1, 0x04)
286 #define OP_SNB_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x05)
287 #define OP_3DSTATE_POLY_STIPPLE_OFFSET OP_3D_MEDIA(0x3, 0x1, 0x06)
288 #define OP_3DSTATE_POLY_STIPPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x07)
289 #define OP_3DSTATE_LINE_STIPPLE OP_3D_MEDIA(0x3, 0x1, 0x08)
290 #define OP_3DSTATE_AA_LINE_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x0A)
291 #define OP_3DSTATE_GS_SVB_INDEX OP_3D_MEDIA(0x3, 0x1, 0x0B)
292 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1 OP_3D_MEDIA(0x3, 0x1, 0x0C)
293 #define OP_3DSTATE_MULTISAMPLE_BDW OP_3D_MEDIA(0x3, 0x0, 0x0D)
294 #define OP_SNB_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0E)
295 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0F)
296 #define OP_SNB_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x10)
297 #define OP_3DSTATE_MONOFILTER_SIZE OP_3D_MEDIA(0x3, 0x1, 0x11)
298 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
299 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
300 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
301 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
302 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
303 #define OP_3DSTATE_SO_DECL_LIST OP_3D_MEDIA(0x3, 0x1, 0x17)
304 #define OP_3DSTATE_SO_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x18)
305 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
306 #define OP_3DSTATE_GATHER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
307 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
308 #define OP_3DSTATE_SAMPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x1C)
309 #define OP_PIPE_CONTROL OP_3D_MEDIA(0x3, 0x2, 0x00)
310 #define OP_3DPRIMITIVE OP_3D_MEDIA(0x3, 0x3, 0x00)
311
312 /* VCCP Command Parser */
313
314 /*
315 * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
316 * git://anongit.freedesktop.org/vaapi/intel-driver
317 * src/i965_defines.h
318 *
319 */
320
321 #define OP_MFX(pipeline, op, sub_opa, sub_opb) \
322 (3 << 13 | \
323 (pipeline) << 11 | \
324 (op) << 8 | \
325 (sub_opa) << 5 | \
326 (sub_opb))
327
328 #define OP_MFX_PIPE_MODE_SELECT OP_MFX(2, 0, 0, 0) /* ALL */
329 #define OP_MFX_SURFACE_STATE OP_MFX(2, 0, 0, 1) /* ALL */
330 #define OP_MFX_PIPE_BUF_ADDR_STATE OP_MFX(2, 0, 0, 2) /* ALL */
331 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE OP_MFX(2, 0, 0, 3) /* ALL */
332 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE OP_MFX(2, 0, 0, 4) /* ALL */
333 #define OP_2_0_0_5 OP_MFX(2, 0, 0, 5) /* ALL */
334 #define OP_MFX_STATE_POINTER OP_MFX(2, 0, 0, 6) /* ALL */
335 #define OP_MFX_QM_STATE OP_MFX(2, 0, 0, 7) /* IVB+ */
336 #define OP_MFX_FQM_STATE OP_MFX(2, 0, 0, 8) /* IVB+ */
337 #define OP_MFX_PAK_INSERT_OBJECT OP_MFX(2, 0, 2, 8) /* IVB+ */
338 #define OP_MFX_STITCH_OBJECT OP_MFX(2, 0, 2, 0xA) /* IVB+ */
339
340 #define OP_MFD_IT_OBJECT OP_MFX(2, 0, 1, 9) /* ALL */
341
342 #define OP_MFX_WAIT OP_MFX(1, 0, 0, 0) /* IVB+ */
343 #define OP_MFX_AVC_IMG_STATE OP_MFX(2, 1, 0, 0) /* ALL */
344 #define OP_MFX_AVC_QM_STATE OP_MFX(2, 1, 0, 1) /* ALL */
345 #define OP_MFX_AVC_DIRECTMODE_STATE OP_MFX(2, 1, 0, 2) /* ALL */
346 #define OP_MFX_AVC_SLICE_STATE OP_MFX(2, 1, 0, 3) /* ALL */
347 #define OP_MFX_AVC_REF_IDX_STATE OP_MFX(2, 1, 0, 4) /* ALL */
348 #define OP_MFX_AVC_WEIGHTOFFSET_STATE OP_MFX(2, 1, 0, 5) /* ALL */
349 #define OP_MFD_AVC_PICID_STATE OP_MFX(2, 1, 1, 5) /* HSW+ */
350 #define OP_MFD_AVC_DPB_STATE OP_MFX(2, 1, 1, 6) /* IVB+ */
351 #define OP_MFD_AVC_SLICEADDR OP_MFX(2, 1, 1, 7) /* IVB+ */
352 #define OP_MFD_AVC_BSD_OBJECT OP_MFX(2, 1, 1, 8) /* ALL */
353 #define OP_MFC_AVC_PAK_OBJECT OP_MFX(2, 1, 2, 9) /* ALL */
354
355 #define OP_MFX_VC1_PRED_PIPE_STATE OP_MFX(2, 2, 0, 1) /* ALL */
356 #define OP_MFX_VC1_DIRECTMODE_STATE OP_MFX(2, 2, 0, 2) /* ALL */
357 #define OP_MFD_VC1_SHORT_PIC_STATE OP_MFX(2, 2, 1, 0) /* IVB+ */
358 #define OP_MFD_VC1_LONG_PIC_STATE OP_MFX(2, 2, 1, 1) /* IVB+ */
359 #define OP_MFD_VC1_BSD_OBJECT OP_MFX(2, 2, 1, 8) /* ALL */
360
361 #define OP_MFX_MPEG2_PIC_STATE OP_MFX(2, 3, 0, 0) /* ALL */
362 #define OP_MFX_MPEG2_QM_STATE OP_MFX(2, 3, 0, 1) /* ALL */
363 #define OP_MFD_MPEG2_BSD_OBJECT OP_MFX(2, 3, 1, 8) /* ALL */
364 #define OP_MFC_MPEG2_SLICEGROUP_STATE OP_MFX(2, 3, 2, 3) /* ALL */
365 #define OP_MFC_MPEG2_PAK_OBJECT OP_MFX(2, 3, 2, 9) /* ALL */
366
367 #define OP_MFX_2_6_0_0 OP_MFX(2, 6, 0, 0) /* IVB+ */
368 #define OP_MFX_2_6_0_8 OP_MFX(2, 6, 0, 8) /* IVB+ */
369 #define OP_MFX_2_6_0_9 OP_MFX(2, 6, 0, 9) /* IVB+ */
370
371 #define OP_MFX_JPEG_PIC_STATE OP_MFX(2, 7, 0, 0)
372 #define OP_MFX_JPEG_HUFF_TABLE_STATE OP_MFX(2, 7, 0, 2)
373 #define OP_MFD_JPEG_BSD_OBJECT OP_MFX(2, 7, 1, 8)
374
375 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
376 (3 << 13 | \
377 (pipeline) << 11 | \
378 (op) << 8 | \
379 (sub_opa) << 5 | \
380 (sub_opb))
381
382 #define OP_VEB_SURFACE_STATE OP_VEB(2, 4, 0, 0)
383 #define OP_VEB_STATE OP_VEB(2, 4, 0, 2)
384 #define OP_VEB_DNDI_IECP_STATE OP_VEB(2, 4, 0, 3)
385
386 struct parser_exec_state;
387
388 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
389
390 #define GVT_CMD_HASH_BITS 7
391
392 /* which DWords need address fix */
393 #define ADDR_FIX_1(x1) (1 << (x1))
394 #define ADDR_FIX_2(x1, x2) (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
395 #define ADDR_FIX_3(x1, x2, x3) (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
396 #define ADDR_FIX_4(x1, x2, x3, x4) (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
397 #define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
398
399 #define DWORD_FIELD(dword, end, start) \
400 FIELD_GET(GENMASK(end, start), cmd_val(s, dword))
401
402 #define OP_LENGTH_BIAS 2
403 #define CMD_LEN(value) (value + OP_LENGTH_BIAS)
404
gvt_check_valid_cmd_length(int len,int valid_len)405 static int gvt_check_valid_cmd_length(int len, int valid_len)
406 {
407 if (valid_len != len) {
408 gvt_err("len is not valid: len=%u valid_len=%u\n",
409 len, valid_len);
410 return -EFAULT;
411 }
412 return 0;
413 }
414
415 struct cmd_info {
416 const char *name;
417 u32 opcode;
418
419 #define F_LEN_MASK 3U
420 #define F_LEN_CONST 1U
421 #define F_LEN_VAR 0U
422 /* value is const although LEN maybe variable */
423 #define F_LEN_VAR_FIXED (1<<1)
424
425 /*
426 * command has its own ip advance logic
427 * e.g. MI_BATCH_START, MI_BATCH_END
428 */
429 #define F_IP_ADVANCE_CUSTOM (1<<2)
430 u32 flag;
431
432 #define R_RCS BIT(RCS0)
433 #define R_VCS1 BIT(VCS0)
434 #define R_VCS2 BIT(VCS1)
435 #define R_VCS (R_VCS1 | R_VCS2)
436 #define R_BCS BIT(BCS0)
437 #define R_VECS BIT(VECS0)
438 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
439 /* rings that support this cmd: BLT/RCS/VCS/VECS */
440 intel_engine_mask_t rings;
441
442 /* devices that support this cmd: SNB/IVB/HSW/... */
443 u16 devices;
444
445 /* which DWords are address that need fix up.
446 * bit 0 means a 32-bit non address operand in command
447 * bit 1 means address operand, which could be 32-bit
448 * or 64-bit depending on different architectures.(
449 * defined by "gmadr_bytes_in_cmd" in intel_gvt.
450 * No matter the address length, each address only takes
451 * one bit in the bitmap.
452 */
453 u16 addr_bitmap;
454
455 /* flag == F_LEN_CONST : command length
456 * flag == F_LEN_VAR : length bias bits
457 * Note: length is in DWord
458 */
459 u32 len;
460
461 parser_cmd_handler handler;
462
463 /* valid length in DWord */
464 u32 valid_len;
465 };
466
467 struct cmd_entry {
468 struct hlist_node hlist;
469 const struct cmd_info *info;
470 };
471
472 enum {
473 RING_BUFFER_INSTRUCTION,
474 BATCH_BUFFER_INSTRUCTION,
475 BATCH_BUFFER_2ND_LEVEL,
476 RING_BUFFER_CTX,
477 };
478
479 enum {
480 GTT_BUFFER,
481 PPGTT_BUFFER
482 };
483
484 struct parser_exec_state {
485 struct intel_vgpu *vgpu;
486 const struct intel_engine_cs *engine;
487
488 int buf_type;
489
490 /* batch buffer address type */
491 int buf_addr_type;
492
493 /* graphics memory address of ring buffer start */
494 unsigned long ring_start;
495 unsigned long ring_size;
496 unsigned long ring_head;
497 unsigned long ring_tail;
498
499 /* instruction graphics memory address */
500 unsigned long ip_gma;
501
502 /* mapped va of the instr_gma */
503 void *ip_va;
504 void *rb_va;
505
506 void *ret_bb_va;
507 /* next instruction when return from batch buffer to ring buffer */
508 unsigned long ret_ip_gma_ring;
509
510 /* next instruction when return from 2nd batch buffer to batch buffer */
511 unsigned long ret_ip_gma_bb;
512
513 /* batch buffer address type (GTT or PPGTT)
514 * used when ret from 2nd level batch buffer
515 */
516 int saved_buf_addr_type;
517 bool is_ctx_wa;
518 bool is_init_ctx;
519
520 const struct cmd_info *info;
521
522 struct intel_vgpu_workload *workload;
523 };
524
525 #define gmadr_dw_number(s) \
526 (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
527
528 static unsigned long bypass_scan_mask = 0;
529
530 /* ring ALL, type = 0 */
531 static const struct sub_op_bits sub_op_mi[] = {
532 {31, 29},
533 {28, 23},
534 };
535
536 static const struct decode_info decode_info_mi = {
537 "MI",
538 OP_LEN_MI,
539 ARRAY_SIZE(sub_op_mi),
540 sub_op_mi,
541 };
542
543 /* ring RCS, command type 2 */
544 static const struct sub_op_bits sub_op_2d[] = {
545 {31, 29},
546 {28, 22},
547 };
548
549 static const struct decode_info decode_info_2d = {
550 "2D",
551 OP_LEN_2D,
552 ARRAY_SIZE(sub_op_2d),
553 sub_op_2d,
554 };
555
556 /* ring RCS, command type 3 */
557 static const struct sub_op_bits sub_op_3d_media[] = {
558 {31, 29},
559 {28, 27},
560 {26, 24},
561 {23, 16},
562 };
563
564 static const struct decode_info decode_info_3d_media = {
565 "3D_Media",
566 OP_LEN_3D_MEDIA,
567 ARRAY_SIZE(sub_op_3d_media),
568 sub_op_3d_media,
569 };
570
571 /* ring VCS, command type 3 */
572 static const struct sub_op_bits sub_op_mfx_vc[] = {
573 {31, 29},
574 {28, 27},
575 {26, 24},
576 {23, 21},
577 {20, 16},
578 };
579
580 static const struct decode_info decode_info_mfx_vc = {
581 "MFX_VC",
582 OP_LEN_MFX_VC,
583 ARRAY_SIZE(sub_op_mfx_vc),
584 sub_op_mfx_vc,
585 };
586
587 /* ring VECS, command type 3 */
588 static const struct sub_op_bits sub_op_vebox[] = {
589 {31, 29},
590 {28, 27},
591 {26, 24},
592 {23, 21},
593 {20, 16},
594 };
595
596 static const struct decode_info decode_info_vebox = {
597 "VEBOX",
598 OP_LEN_VEBOX,
599 ARRAY_SIZE(sub_op_vebox),
600 sub_op_vebox,
601 };
602
603 static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
604 [RCS0] = {
605 &decode_info_mi,
606 NULL,
607 NULL,
608 &decode_info_3d_media,
609 NULL,
610 NULL,
611 NULL,
612 NULL,
613 },
614
615 [VCS0] = {
616 &decode_info_mi,
617 NULL,
618 NULL,
619 &decode_info_mfx_vc,
620 NULL,
621 NULL,
622 NULL,
623 NULL,
624 },
625
626 [BCS0] = {
627 &decode_info_mi,
628 NULL,
629 &decode_info_2d,
630 NULL,
631 NULL,
632 NULL,
633 NULL,
634 NULL,
635 },
636
637 [VECS0] = {
638 &decode_info_mi,
639 NULL,
640 NULL,
641 &decode_info_vebox,
642 NULL,
643 NULL,
644 NULL,
645 NULL,
646 },
647
648 [VCS1] = {
649 &decode_info_mi,
650 NULL,
651 NULL,
652 &decode_info_mfx_vc,
653 NULL,
654 NULL,
655 NULL,
656 NULL,
657 },
658 };
659
get_opcode(u32 cmd,const struct intel_engine_cs * engine)660 static inline u32 get_opcode(u32 cmd, const struct intel_engine_cs *engine)
661 {
662 const struct decode_info *d_info;
663
664 d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
665 if (d_info == NULL)
666 return INVALID_OP;
667
668 return cmd >> (32 - d_info->op_len);
669 }
670
671 static inline const struct cmd_info *
find_cmd_entry(struct intel_gvt * gvt,unsigned int opcode,const struct intel_engine_cs * engine)672 find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode,
673 const struct intel_engine_cs *engine)
674 {
675 struct cmd_entry *e;
676
677 hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
678 if (opcode == e->info->opcode &&
679 e->info->rings & engine->mask)
680 return e->info;
681 }
682 return NULL;
683 }
684
685 static inline const struct cmd_info *
get_cmd_info(struct intel_gvt * gvt,u32 cmd,const struct intel_engine_cs * engine)686 get_cmd_info(struct intel_gvt *gvt, u32 cmd,
687 const struct intel_engine_cs *engine)
688 {
689 u32 opcode;
690
691 opcode = get_opcode(cmd, engine);
692 if (opcode == INVALID_OP)
693 return NULL;
694
695 return find_cmd_entry(gvt, opcode, engine);
696 }
697
sub_op_val(u32 cmd,u32 hi,u32 low)698 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
699 {
700 return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
701 }
702
print_opcode(u32 cmd,const struct intel_engine_cs * engine)703 static inline void print_opcode(u32 cmd, const struct intel_engine_cs *engine)
704 {
705 const struct decode_info *d_info;
706 int i;
707
708 d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
709 if (d_info == NULL)
710 return;
711
712 gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
713 cmd >> (32 - d_info->op_len), d_info->name);
714
715 for (i = 0; i < d_info->nr_sub_op; i++)
716 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
717 d_info->sub_op[i].low));
718
719 pr_err("\n");
720 }
721
cmd_ptr(struct parser_exec_state * s,int index)722 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
723 {
724 return s->ip_va + (index << 2);
725 }
726
cmd_val(struct parser_exec_state * s,int index)727 static inline u32 cmd_val(struct parser_exec_state *s, int index)
728 {
729 return *cmd_ptr(s, index);
730 }
731
is_init_ctx(struct parser_exec_state * s)732 static inline bool is_init_ctx(struct parser_exec_state *s)
733 {
734 return (s->buf_type == RING_BUFFER_CTX && s->is_init_ctx);
735 }
736
parser_exec_state_dump(struct parser_exec_state * s)737 static void parser_exec_state_dump(struct parser_exec_state *s)
738 {
739 int cnt = 0;
740 int i;
741
742 gvt_dbg_cmd(" vgpu%d RING%s: ring_start(%08lx) ring_end(%08lx)"
743 " ring_head(%08lx) ring_tail(%08lx)\n",
744 s->vgpu->id, s->engine->name,
745 s->ring_start, s->ring_start + s->ring_size,
746 s->ring_head, s->ring_tail);
747
748 gvt_dbg_cmd(" %s %s ip_gma(%08lx) ",
749 s->buf_type == RING_BUFFER_INSTRUCTION ?
750 "RING_BUFFER" : ((s->buf_type == RING_BUFFER_CTX) ?
751 "CTX_BUFFER" : "BATCH_BUFFER"),
752 s->buf_addr_type == GTT_BUFFER ?
753 "GTT" : "PPGTT", s->ip_gma);
754
755 if (s->ip_va == NULL) {
756 gvt_dbg_cmd(" ip_va(NULL)");
757 return;
758 }
759
760 gvt_dbg_cmd(" ip_va=%p: %08x %08x %08x %08x\n",
761 s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
762 cmd_val(s, 2), cmd_val(s, 3));
763
764 print_opcode(cmd_val(s, 0), s->engine);
765
766 s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
767
768 while (cnt < 1024) {
769 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
770 for (i = 0; i < 8; i++)
771 gvt_dbg_cmd("%08x ", cmd_val(s, i));
772 gvt_dbg_cmd("\n");
773
774 s->ip_va += 8 * sizeof(u32);
775 cnt += 8;
776 }
777 }
778
update_ip_va(struct parser_exec_state * s)779 static inline void update_ip_va(struct parser_exec_state *s)
780 {
781 unsigned long len = 0;
782
783 if (WARN_ON(s->ring_head == s->ring_tail))
784 return;
785
786 if (s->buf_type == RING_BUFFER_INSTRUCTION ||
787 s->buf_type == RING_BUFFER_CTX) {
788 unsigned long ring_top = s->ring_start + s->ring_size;
789
790 if (s->ring_head > s->ring_tail) {
791 if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
792 len = (s->ip_gma - s->ring_head);
793 else if (s->ip_gma >= s->ring_start &&
794 s->ip_gma <= s->ring_tail)
795 len = (ring_top - s->ring_head) +
796 (s->ip_gma - s->ring_start);
797 } else
798 len = (s->ip_gma - s->ring_head);
799
800 s->ip_va = s->rb_va + len;
801 } else {/* shadow batch buffer */
802 s->ip_va = s->ret_bb_va;
803 }
804 }
805
ip_gma_set(struct parser_exec_state * s,unsigned long ip_gma)806 static inline int ip_gma_set(struct parser_exec_state *s,
807 unsigned long ip_gma)
808 {
809 WARN_ON(!IS_ALIGNED(ip_gma, 4));
810
811 s->ip_gma = ip_gma;
812 update_ip_va(s);
813 return 0;
814 }
815
ip_gma_advance(struct parser_exec_state * s,unsigned int dw_len)816 static inline int ip_gma_advance(struct parser_exec_state *s,
817 unsigned int dw_len)
818 {
819 s->ip_gma += (dw_len << 2);
820
821 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
822 if (s->ip_gma >= s->ring_start + s->ring_size)
823 s->ip_gma -= s->ring_size;
824 update_ip_va(s);
825 } else {
826 s->ip_va += (dw_len << 2);
827 }
828
829 return 0;
830 }
831
get_cmd_length(const struct cmd_info * info,u32 cmd)832 static inline int get_cmd_length(const struct cmd_info *info, u32 cmd)
833 {
834 if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
835 return info->len;
836 else
837 return (cmd & ((1U << info->len) - 1)) + 2;
838 return 0;
839 }
840
cmd_length(struct parser_exec_state * s)841 static inline int cmd_length(struct parser_exec_state *s)
842 {
843 return get_cmd_length(s->info, cmd_val(s, 0));
844 }
845
846 /* do not remove this, some platform may need clflush here */
847 #define patch_value(s, addr, val) do { \
848 *addr = val; \
849 } while (0)
850
is_mocs_mmio(unsigned int offset)851 static inline bool is_mocs_mmio(unsigned int offset)
852 {
853 return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
854 ((offset >= 0xb020) && (offset <= 0xb0a0));
855 }
856
is_cmd_update_pdps(unsigned int offset,struct parser_exec_state * s)857 static int is_cmd_update_pdps(unsigned int offset,
858 struct parser_exec_state *s)
859 {
860 u32 base = s->workload->engine->mmio_base;
861 return i915_mmio_reg_equal(_MMIO(offset), GEN8_RING_PDP_UDW(base, 0));
862 }
863
cmd_pdp_mmio_update_handler(struct parser_exec_state * s,unsigned int offset,unsigned int index)864 static int cmd_pdp_mmio_update_handler(struct parser_exec_state *s,
865 unsigned int offset, unsigned int index)
866 {
867 struct intel_vgpu *vgpu = s->vgpu;
868 struct intel_vgpu_mm *shadow_mm = s->workload->shadow_mm;
869 struct intel_vgpu_mm *mm;
870 u64 pdps[GEN8_3LVL_PDPES];
871
872 if (shadow_mm->ppgtt_mm.root_entry_type ==
873 GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
874 pdps[0] = (u64)cmd_val(s, 2) << 32;
875 pdps[0] |= cmd_val(s, 4);
876
877 mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
878 if (!mm) {
879 gvt_vgpu_err("failed to get the 4-level shadow vm\n");
880 return -EINVAL;
881 }
882 intel_vgpu_mm_get(mm);
883 list_add_tail(&mm->ppgtt_mm.link,
884 &s->workload->lri_shadow_mm);
885 *cmd_ptr(s, 2) = upper_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
886 *cmd_ptr(s, 4) = lower_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
887 } else {
888 /* Currently all guests use PML4 table and now can't
889 * have a guest with 3-level table but uses LRI for
890 * PPGTT update. So this is simply un-testable. */
891 GEM_BUG_ON(1);
892 gvt_vgpu_err("invalid shared shadow vm type\n");
893 return -EINVAL;
894 }
895 return 0;
896 }
897
cmd_reg_handler(struct parser_exec_state * s,unsigned int offset,unsigned int index,char * cmd)898 static int cmd_reg_handler(struct parser_exec_state *s,
899 unsigned int offset, unsigned int index, char *cmd)
900 {
901 struct intel_vgpu *vgpu = s->vgpu;
902 struct intel_gvt *gvt = vgpu->gvt;
903 u32 ctx_sr_ctl;
904 u32 *vreg, vreg_old;
905
906 if (offset + 4 > gvt->device_info.mmio_size) {
907 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
908 cmd, offset);
909 return -EFAULT;
910 }
911
912 if (is_init_ctx(s)) {
913 struct intel_gvt_mmio_info *mmio_info;
914
915 intel_gvt_mmio_set_cmd_accessible(gvt, offset);
916 mmio_info = intel_gvt_find_mmio_info(gvt, offset);
917 if (mmio_info && mmio_info->write)
918 intel_gvt_mmio_set_cmd_write_patch(gvt, offset);
919 return 0;
920 }
921
922 if (!intel_gvt_mmio_is_cmd_accessible(gvt, offset)) {
923 gvt_vgpu_err("%s access to non-render register (%x)\n",
924 cmd, offset);
925 return -EBADRQC;
926 }
927
928 if (!strncmp(cmd, "srm", 3) ||
929 !strncmp(cmd, "lrm", 3)) {
930 if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||
931 offset == 0x21f0 ||
932 (IS_BROADWELL(gvt->gt->i915) &&
933 offset == i915_mmio_reg_offset(INSTPM)))
934 return 0;
935 else {
936 gvt_vgpu_err("%s access to register (%x)\n",
937 cmd, offset);
938 return -EPERM;
939 }
940 }
941
942 if (!strncmp(cmd, "lrr-src", 7) ||
943 !strncmp(cmd, "lrr-dst", 7)) {
944 if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c)
945 return 0;
946 else {
947 gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset);
948 return -EPERM;
949 }
950 }
951
952 if (!strncmp(cmd, "pipe_ctrl", 9)) {
953 /* TODO: add LRI POST logic here */
954 return 0;
955 }
956
957 if (strncmp(cmd, "lri", 3))
958 return -EPERM;
959
960 /* below are all lri handlers */
961 vreg = &vgpu_vreg(s->vgpu, offset);
962
963 if (is_cmd_update_pdps(offset, s) &&
964 cmd_pdp_mmio_update_handler(s, offset, index))
965 return -EINVAL;
966
967 if (offset == i915_mmio_reg_offset(DERRMR) ||
968 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
969 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
970 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
971 }
972
973 if (is_mocs_mmio(offset))
974 *vreg = cmd_val(s, index + 1);
975
976 vreg_old = *vreg;
977
978 if (intel_gvt_mmio_is_cmd_write_patch(gvt, offset)) {
979 u32 cmdval_new, cmdval;
980 struct intel_gvt_mmio_info *mmio_info;
981
982 cmdval = cmd_val(s, index + 1);
983
984 mmio_info = intel_gvt_find_mmio_info(gvt, offset);
985 if (!mmio_info) {
986 cmdval_new = cmdval;
987 } else {
988 u64 ro_mask = mmio_info->ro_mask;
989 int ret;
990
991 if (likely(!ro_mask))
992 ret = mmio_info->write(s->vgpu, offset,
993 &cmdval, 4);
994 else {
995 gvt_vgpu_err("try to write RO reg %x\n",
996 offset);
997 ret = -EBADRQC;
998 }
999 if (ret)
1000 return ret;
1001 cmdval_new = *vreg;
1002 }
1003 if (cmdval_new != cmdval)
1004 patch_value(s, cmd_ptr(s, index+1), cmdval_new);
1005 }
1006
1007 /* only patch cmd. restore vreg value if changed in mmio write handler*/
1008 *vreg = vreg_old;
1009
1010 /* TODO
1011 * In order to let workload with inhibit context to generate
1012 * correct image data into memory, vregs values will be loaded to
1013 * hw via LRIs in the workload with inhibit context. But as
1014 * indirect context is loaded prior to LRIs in workload, we don't
1015 * want reg values specified in indirect context overwritten by
1016 * LRIs in workloads. So, when scanning an indirect context, we
1017 * update reg values in it into vregs, so LRIs in workload with
1018 * inhibit context will restore with correct values
1019 */
1020 if (GRAPHICS_VER(s->engine->i915) == 9 &&
1021 intel_gvt_mmio_is_sr_in_ctx(gvt, offset) &&
1022 !strncmp(cmd, "lri", 3)) {
1023 intel_gvt_read_gpa(s->vgpu,
1024 s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
1025 /* check inhibit context */
1026 if (ctx_sr_ctl & 1) {
1027 u32 data = cmd_val(s, index + 1);
1028
1029 if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
1030 intel_vgpu_mask_mmio_write(vgpu,
1031 offset, &data, 4);
1032 else
1033 vgpu_vreg(vgpu, offset) = data;
1034 }
1035 }
1036
1037 return 0;
1038 }
1039
1040 #define cmd_reg(s, i) \
1041 (cmd_val(s, i) & GENMASK(22, 2))
1042
1043 #define cmd_reg_inhibit(s, i) \
1044 (cmd_val(s, i) & GENMASK(22, 18))
1045
1046 #define cmd_gma(s, i) \
1047 (cmd_val(s, i) & GENMASK(31, 2))
1048
1049 #define cmd_gma_hi(s, i) \
1050 (cmd_val(s, i) & GENMASK(15, 0))
1051
cmd_handler_lri(struct parser_exec_state * s)1052 static int cmd_handler_lri(struct parser_exec_state *s)
1053 {
1054 int i, ret = 0;
1055 int cmd_len = cmd_length(s);
1056
1057 for (i = 1; i < cmd_len; i += 2) {
1058 if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) {
1059 if (s->engine->id == BCS0 &&
1060 cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))
1061 ret |= 0;
1062 else
1063 ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0;
1064 }
1065 if (ret)
1066 break;
1067 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
1068 if (ret)
1069 break;
1070 }
1071 return ret;
1072 }
1073
cmd_handler_lrr(struct parser_exec_state * s)1074 static int cmd_handler_lrr(struct parser_exec_state *s)
1075 {
1076 int i, ret = 0;
1077 int cmd_len = cmd_length(s);
1078
1079 for (i = 1; i < cmd_len; i += 2) {
1080 if (IS_BROADWELL(s->engine->i915))
1081 ret |= ((cmd_reg_inhibit(s, i) ||
1082 (cmd_reg_inhibit(s, i + 1)))) ?
1083 -EBADRQC : 0;
1084 if (ret)
1085 break;
1086 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
1087 if (ret)
1088 break;
1089 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
1090 if (ret)
1091 break;
1092 }
1093 return ret;
1094 }
1095
1096 static inline int cmd_address_audit(struct parser_exec_state *s,
1097 unsigned long guest_gma, int op_size, bool index_mode);
1098
cmd_handler_lrm(struct parser_exec_state * s)1099 static int cmd_handler_lrm(struct parser_exec_state *s)
1100 {
1101 struct intel_gvt *gvt = s->vgpu->gvt;
1102 int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
1103 unsigned long gma;
1104 int i, ret = 0;
1105 int cmd_len = cmd_length(s);
1106
1107 for (i = 1; i < cmd_len;) {
1108 if (IS_BROADWELL(s->engine->i915))
1109 ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
1110 if (ret)
1111 break;
1112 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
1113 if (ret)
1114 break;
1115 if (cmd_val(s, 0) & (1 << 22)) {
1116 gma = cmd_gma(s, i + 1);
1117 if (gmadr_bytes == 8)
1118 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1119 ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1120 if (ret)
1121 break;
1122 }
1123 i += gmadr_dw_number(s) + 1;
1124 }
1125 return ret;
1126 }
1127
cmd_handler_srm(struct parser_exec_state * s)1128 static int cmd_handler_srm(struct parser_exec_state *s)
1129 {
1130 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1131 unsigned long gma;
1132 int i, ret = 0;
1133 int cmd_len = cmd_length(s);
1134
1135 for (i = 1; i < cmd_len;) {
1136 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1137 if (ret)
1138 break;
1139 if (cmd_val(s, 0) & (1 << 22)) {
1140 gma = cmd_gma(s, i + 1);
1141 if (gmadr_bytes == 8)
1142 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1143 ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1144 if (ret)
1145 break;
1146 }
1147 i += gmadr_dw_number(s) + 1;
1148 }
1149 return ret;
1150 }
1151
1152 struct cmd_interrupt_event {
1153 int pipe_control_notify;
1154 int mi_flush_dw;
1155 int mi_user_interrupt;
1156 };
1157
1158 static const struct cmd_interrupt_event cmd_interrupt_events[] = {
1159 [RCS0] = {
1160 .pipe_control_notify = RCS_PIPE_CONTROL,
1161 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1162 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1163 },
1164 [BCS0] = {
1165 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1166 .mi_flush_dw = BCS_MI_FLUSH_DW,
1167 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1168 },
1169 [VCS0] = {
1170 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1171 .mi_flush_dw = VCS_MI_FLUSH_DW,
1172 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1173 },
1174 [VCS1] = {
1175 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1176 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1177 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1178 },
1179 [VECS0] = {
1180 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1181 .mi_flush_dw = VECS_MI_FLUSH_DW,
1182 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1183 },
1184 };
1185
cmd_handler_pipe_control(struct parser_exec_state * s)1186 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1187 {
1188 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1189 unsigned long gma;
1190 bool index_mode = false;
1191 unsigned int post_sync;
1192 int ret = 0;
1193 u32 hws_pga, val;
1194
1195 post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1196
1197 /* LRI post sync */
1198 if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1199 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1200 /* post sync */
1201 else if (post_sync) {
1202 if (post_sync == 2)
1203 ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1204 else if (post_sync == 3)
1205 ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1206 else if (post_sync == 1) {
1207 /* check ggtt*/
1208 if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1209 gma = cmd_val(s, 2) & GENMASK(31, 3);
1210 if (gmadr_bytes == 8)
1211 gma |= (cmd_gma_hi(s, 3)) << 32;
1212 /* Store Data Index */
1213 if (cmd_val(s, 1) & (1 << 21))
1214 index_mode = true;
1215 ret |= cmd_address_audit(s, gma, sizeof(u64),
1216 index_mode);
1217 if (ret)
1218 return ret;
1219 if (index_mode) {
1220 hws_pga = s->vgpu->hws_pga[s->engine->id];
1221 gma = hws_pga + gma;
1222 patch_value(s, cmd_ptr(s, 2), gma);
1223 val = cmd_val(s, 1) & (~(1 << 21));
1224 patch_value(s, cmd_ptr(s, 1), val);
1225 }
1226 }
1227 }
1228 }
1229
1230 if (ret)
1231 return ret;
1232
1233 if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1234 set_bit(cmd_interrupt_events[s->engine->id].pipe_control_notify,
1235 s->workload->pending_events);
1236 return 0;
1237 }
1238
cmd_handler_mi_user_interrupt(struct parser_exec_state * s)1239 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1240 {
1241 set_bit(cmd_interrupt_events[s->engine->id].mi_user_interrupt,
1242 s->workload->pending_events);
1243 patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1244 return 0;
1245 }
1246
cmd_advance_default(struct parser_exec_state * s)1247 static int cmd_advance_default(struct parser_exec_state *s)
1248 {
1249 return ip_gma_advance(s, cmd_length(s));
1250 }
1251
cmd_handler_mi_batch_buffer_end(struct parser_exec_state * s)1252 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1253 {
1254 int ret;
1255
1256 if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1257 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1258 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1259 s->buf_addr_type = s->saved_buf_addr_type;
1260 } else if (s->buf_type == RING_BUFFER_CTX) {
1261 ret = ip_gma_set(s, s->ring_tail);
1262 } else {
1263 s->buf_type = RING_BUFFER_INSTRUCTION;
1264 s->buf_addr_type = GTT_BUFFER;
1265 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1266 s->ret_ip_gma_ring -= s->ring_size;
1267 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1268 }
1269 return ret;
1270 }
1271
1272 struct mi_display_flip_command_info {
1273 int pipe;
1274 int plane;
1275 int event;
1276 i915_reg_t stride_reg;
1277 i915_reg_t ctrl_reg;
1278 i915_reg_t surf_reg;
1279 u64 stride_val;
1280 u64 tile_val;
1281 u64 surf_val;
1282 bool async_flip;
1283 };
1284
1285 struct plane_code_mapping {
1286 int pipe;
1287 int plane;
1288 int event;
1289 };
1290
gen8_decode_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1291 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1292 struct mi_display_flip_command_info *info)
1293 {
1294 struct drm_i915_private *dev_priv = s->engine->i915;
1295 struct intel_display *display = dev_priv->display;
1296 struct plane_code_mapping gen8_plane_code[] = {
1297 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1298 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1299 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1300 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1301 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1302 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1303 };
1304 u32 dword0, dword1, dword2;
1305 u32 v;
1306
1307 dword0 = cmd_val(s, 0);
1308 dword1 = cmd_val(s, 1);
1309 dword2 = cmd_val(s, 2);
1310
1311 v = (dword0 & GENMASK(21, 19)) >> 19;
1312 if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code)))
1313 return -EBADRQC;
1314
1315 info->pipe = gen8_plane_code[v].pipe;
1316 info->plane = gen8_plane_code[v].plane;
1317 info->event = gen8_plane_code[v].event;
1318 info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1319 info->tile_val = (dword1 & 0x1);
1320 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1321 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1322
1323 if (info->plane == PLANE_A) {
1324 info->ctrl_reg = DSPCNTR(display, info->pipe);
1325 info->stride_reg = DSPSTRIDE(display, info->pipe);
1326 info->surf_reg = DSPSURF(display, info->pipe);
1327 } else if (info->plane == PLANE_B) {
1328 info->ctrl_reg = SPRCTL(info->pipe);
1329 info->stride_reg = SPRSTRIDE(info->pipe);
1330 info->surf_reg = SPRSURF(info->pipe);
1331 } else {
1332 drm_WARN_ON(&dev_priv->drm, 1);
1333 return -EBADRQC;
1334 }
1335 return 0;
1336 }
1337
skl_decode_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1338 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1339 struct mi_display_flip_command_info *info)
1340 {
1341 struct drm_i915_private *dev_priv = s->engine->i915;
1342 struct intel_display *display = dev_priv->display;
1343 struct intel_vgpu *vgpu = s->vgpu;
1344 u32 dword0 = cmd_val(s, 0);
1345 u32 dword1 = cmd_val(s, 1);
1346 u32 dword2 = cmd_val(s, 2);
1347 u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1348
1349 info->plane = PRIMARY_PLANE;
1350
1351 switch (plane) {
1352 case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1353 info->pipe = PIPE_A;
1354 info->event = PRIMARY_A_FLIP_DONE;
1355 break;
1356 case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1357 info->pipe = PIPE_B;
1358 info->event = PRIMARY_B_FLIP_DONE;
1359 break;
1360 case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1361 info->pipe = PIPE_C;
1362 info->event = PRIMARY_C_FLIP_DONE;
1363 break;
1364
1365 case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1366 info->pipe = PIPE_A;
1367 info->event = SPRITE_A_FLIP_DONE;
1368 info->plane = SPRITE_PLANE;
1369 break;
1370 case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1371 info->pipe = PIPE_B;
1372 info->event = SPRITE_B_FLIP_DONE;
1373 info->plane = SPRITE_PLANE;
1374 break;
1375 case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1376 info->pipe = PIPE_C;
1377 info->event = SPRITE_C_FLIP_DONE;
1378 info->plane = SPRITE_PLANE;
1379 break;
1380
1381 default:
1382 gvt_vgpu_err("unknown plane code %d\n", plane);
1383 return -EBADRQC;
1384 }
1385
1386 info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1387 info->tile_val = (dword1 & GENMASK(2, 0));
1388 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1389 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1390
1391 info->ctrl_reg = DSPCNTR(display, info->pipe);
1392 info->stride_reg = DSPSTRIDE(display, info->pipe);
1393 info->surf_reg = DSPSURF(display, info->pipe);
1394
1395 return 0;
1396 }
1397
gen8_check_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1398 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1399 struct mi_display_flip_command_info *info)
1400 {
1401 u32 stride, tile;
1402
1403 if (!info->async_flip)
1404 return 0;
1405
1406 if (GRAPHICS_VER(s->engine->i915) >= 9) {
1407 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1408 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1409 GENMASK(12, 10)) >> 10;
1410 } else {
1411 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1412 GENMASK(15, 6)) >> 6;
1413 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1414 }
1415
1416 if (stride != info->stride_val)
1417 gvt_dbg_cmd("cannot change stride during async flip\n");
1418
1419 if (tile != info->tile_val)
1420 gvt_dbg_cmd("cannot change tile during async flip\n");
1421
1422 return 0;
1423 }
1424
gen8_update_plane_mmio_from_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1425 static int gen8_update_plane_mmio_from_mi_display_flip(
1426 struct parser_exec_state *s,
1427 struct mi_display_flip_command_info *info)
1428 {
1429 struct drm_i915_private *dev_priv = s->engine->i915;
1430 struct intel_display *display = dev_priv->display;
1431 struct intel_vgpu *vgpu = s->vgpu;
1432
1433 set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1434 info->surf_val << 12);
1435 if (GRAPHICS_VER(dev_priv) >= 9) {
1436 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1437 info->stride_val);
1438 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1439 info->tile_val << 10);
1440 } else {
1441 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1442 info->stride_val << 6);
1443 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1444 info->tile_val << 10);
1445 }
1446
1447 if (info->plane == PLANE_PRIMARY)
1448 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, info->pipe))++;
1449
1450 if (info->async_flip)
1451 intel_vgpu_trigger_virtual_event(vgpu, info->event);
1452 else
1453 set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);
1454
1455 return 0;
1456 }
1457
decode_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1458 static int decode_mi_display_flip(struct parser_exec_state *s,
1459 struct mi_display_flip_command_info *info)
1460 {
1461 if (IS_BROADWELL(s->engine->i915))
1462 return gen8_decode_mi_display_flip(s, info);
1463 if (GRAPHICS_VER(s->engine->i915) >= 9)
1464 return skl_decode_mi_display_flip(s, info);
1465
1466 return -ENODEV;
1467 }
1468
check_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1469 static int check_mi_display_flip(struct parser_exec_state *s,
1470 struct mi_display_flip_command_info *info)
1471 {
1472 return gen8_check_mi_display_flip(s, info);
1473 }
1474
update_plane_mmio_from_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1475 static int update_plane_mmio_from_mi_display_flip(
1476 struct parser_exec_state *s,
1477 struct mi_display_flip_command_info *info)
1478 {
1479 return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1480 }
1481
cmd_handler_mi_display_flip(struct parser_exec_state * s)1482 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1483 {
1484 struct mi_display_flip_command_info info;
1485 struct intel_vgpu *vgpu = s->vgpu;
1486 int ret;
1487 int i;
1488 int len = cmd_length(s);
1489 u32 valid_len = CMD_LEN(1);
1490
1491 /* Flip Type == Stereo 3D Flip */
1492 if (DWORD_FIELD(2, 1, 0) == 2)
1493 valid_len++;
1494 ret = gvt_check_valid_cmd_length(cmd_length(s),
1495 valid_len);
1496 if (ret)
1497 return ret;
1498
1499 ret = decode_mi_display_flip(s, &info);
1500 if (ret) {
1501 gvt_vgpu_err("fail to decode MI display flip command\n");
1502 return ret;
1503 }
1504
1505 ret = check_mi_display_flip(s, &info);
1506 if (ret) {
1507 gvt_vgpu_err("invalid MI display flip command\n");
1508 return ret;
1509 }
1510
1511 ret = update_plane_mmio_from_mi_display_flip(s, &info);
1512 if (ret) {
1513 gvt_vgpu_err("fail to update plane mmio\n");
1514 return ret;
1515 }
1516
1517 for (i = 0; i < len; i++)
1518 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1519 return 0;
1520 }
1521
is_wait_for_flip_pending(u32 cmd)1522 static bool is_wait_for_flip_pending(u32 cmd)
1523 {
1524 return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1525 MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1526 MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1527 MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1528 MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1529 MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1530 }
1531
cmd_handler_mi_wait_for_event(struct parser_exec_state * s)1532 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1533 {
1534 u32 cmd = cmd_val(s, 0);
1535
1536 if (!is_wait_for_flip_pending(cmd))
1537 return 0;
1538
1539 patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1540 return 0;
1541 }
1542
get_gma_bb_from_cmd(struct parser_exec_state * s,int index)1543 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1544 {
1545 unsigned long addr;
1546 unsigned long gma_high, gma_low;
1547 struct intel_vgpu *vgpu = s->vgpu;
1548 int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1549
1550 if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1551 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1552 return INTEL_GVT_INVALID_ADDR;
1553 }
1554
1555 gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1556 if (gmadr_bytes == 4) {
1557 addr = gma_low;
1558 } else {
1559 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1560 addr = (((unsigned long)gma_high) << 32) | gma_low;
1561 }
1562 return addr;
1563 }
1564
cmd_address_audit(struct parser_exec_state * s,unsigned long guest_gma,int op_size,bool index_mode)1565 static inline int cmd_address_audit(struct parser_exec_state *s,
1566 unsigned long guest_gma, int op_size, bool index_mode)
1567 {
1568 struct intel_vgpu *vgpu = s->vgpu;
1569 u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1570 int i;
1571 int ret;
1572
1573 if (op_size > max_surface_size) {
1574 gvt_vgpu_err("command address audit fail name %s\n",
1575 s->info->name);
1576 return -EFAULT;
1577 }
1578
1579 if (index_mode) {
1580 if (guest_gma >= I915_GTT_PAGE_SIZE) {
1581 ret = -EFAULT;
1582 goto err;
1583 }
1584 } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1585 ret = -EFAULT;
1586 goto err;
1587 }
1588
1589 return 0;
1590
1591 err:
1592 gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1593 s->info->name, guest_gma, op_size);
1594
1595 pr_err("cmd dump: ");
1596 for (i = 0; i < cmd_length(s); i++) {
1597 if (!(i % 4))
1598 pr_err("\n%08x ", cmd_val(s, i));
1599 else
1600 pr_err("%08x ", cmd_val(s, i));
1601 }
1602 pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1603 vgpu->id,
1604 vgpu_aperture_gmadr_base(vgpu),
1605 vgpu_aperture_gmadr_end(vgpu),
1606 vgpu_hidden_gmadr_base(vgpu),
1607 vgpu_hidden_gmadr_end(vgpu));
1608 return ret;
1609 }
1610
cmd_handler_mi_store_data_imm(struct parser_exec_state * s)1611 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1612 {
1613 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1614 int op_size = (cmd_length(s) - 3) * sizeof(u32);
1615 int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1616 unsigned long gma, gma_low, gma_high;
1617 u32 valid_len = CMD_LEN(2);
1618 int ret = 0;
1619
1620 /* check ppggt */
1621 if (!(cmd_val(s, 0) & (1 << 22)))
1622 return 0;
1623
1624 /* check if QWORD */
1625 if (DWORD_FIELD(0, 21, 21))
1626 valid_len++;
1627 ret = gvt_check_valid_cmd_length(cmd_length(s),
1628 valid_len);
1629 if (ret)
1630 return ret;
1631
1632 gma = cmd_val(s, 2) & GENMASK(31, 2);
1633
1634 if (gmadr_bytes == 8) {
1635 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1636 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1637 gma = (gma_high << 32) | gma_low;
1638 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1639 }
1640 ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1641 return ret;
1642 }
1643
unexpected_cmd(struct parser_exec_state * s)1644 static inline int unexpected_cmd(struct parser_exec_state *s)
1645 {
1646 struct intel_vgpu *vgpu = s->vgpu;
1647
1648 gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1649
1650 return -EBADRQC;
1651 }
1652
cmd_handler_mi_semaphore_wait(struct parser_exec_state * s)1653 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1654 {
1655 return unexpected_cmd(s);
1656 }
1657
cmd_handler_mi_report_perf_count(struct parser_exec_state * s)1658 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1659 {
1660 return unexpected_cmd(s);
1661 }
1662
cmd_handler_mi_op_2e(struct parser_exec_state * s)1663 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1664 {
1665 return unexpected_cmd(s);
1666 }
1667
cmd_handler_mi_op_2f(struct parser_exec_state * s)1668 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1669 {
1670 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1671 int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1672 sizeof(u32);
1673 unsigned long gma, gma_high;
1674 u32 valid_len = CMD_LEN(1);
1675 int ret = 0;
1676
1677 if (!(cmd_val(s, 0) & (1 << 22)))
1678 return ret;
1679
1680 /* check inline data */
1681 if (cmd_val(s, 0) & BIT(18))
1682 valid_len = CMD_LEN(9);
1683 ret = gvt_check_valid_cmd_length(cmd_length(s),
1684 valid_len);
1685 if (ret)
1686 return ret;
1687
1688 gma = cmd_val(s, 1) & GENMASK(31, 2);
1689 if (gmadr_bytes == 8) {
1690 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1691 gma = (gma_high << 32) | gma;
1692 }
1693 ret = cmd_address_audit(s, gma, op_size, false);
1694 return ret;
1695 }
1696
cmd_handler_mi_store_data_index(struct parser_exec_state * s)1697 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1698 {
1699 return unexpected_cmd(s);
1700 }
1701
cmd_handler_mi_clflush(struct parser_exec_state * s)1702 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1703 {
1704 return unexpected_cmd(s);
1705 }
1706
cmd_handler_mi_conditional_batch_buffer_end(struct parser_exec_state * s)1707 static int cmd_handler_mi_conditional_batch_buffer_end(
1708 struct parser_exec_state *s)
1709 {
1710 return unexpected_cmd(s);
1711 }
1712
cmd_handler_mi_update_gtt(struct parser_exec_state * s)1713 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1714 {
1715 return unexpected_cmd(s);
1716 }
1717
cmd_handler_mi_flush_dw(struct parser_exec_state * s)1718 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1719 {
1720 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1721 unsigned long gma;
1722 bool index_mode = false;
1723 int ret = 0;
1724 u32 hws_pga, val;
1725 u32 valid_len = CMD_LEN(2);
1726
1727 ret = gvt_check_valid_cmd_length(cmd_length(s),
1728 valid_len);
1729 if (ret) {
1730 /* Check again for Qword */
1731 ret = gvt_check_valid_cmd_length(cmd_length(s),
1732 ++valid_len);
1733 return ret;
1734 }
1735
1736 /* Check post-sync and ppgtt bit */
1737 if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1738 gma = cmd_val(s, 1) & GENMASK(31, 3);
1739 if (gmadr_bytes == 8)
1740 gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1741 /* Store Data Index */
1742 if (cmd_val(s, 0) & (1 << 21))
1743 index_mode = true;
1744 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1745 if (ret)
1746 return ret;
1747 if (index_mode) {
1748 hws_pga = s->vgpu->hws_pga[s->engine->id];
1749 gma = hws_pga + gma;
1750 patch_value(s, cmd_ptr(s, 1), gma);
1751 val = cmd_val(s, 0) & (~(1 << 21));
1752 patch_value(s, cmd_ptr(s, 0), val);
1753 }
1754 }
1755 /* Check notify bit */
1756 if ((cmd_val(s, 0) & (1 << 8)))
1757 set_bit(cmd_interrupt_events[s->engine->id].mi_flush_dw,
1758 s->workload->pending_events);
1759 return ret;
1760 }
1761
addr_type_update_snb(struct parser_exec_state * s)1762 static void addr_type_update_snb(struct parser_exec_state *s)
1763 {
1764 if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1765 (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1766 s->buf_addr_type = PPGTT_BUFFER;
1767 }
1768 }
1769
1770
copy_gma_to_hva(struct intel_vgpu * vgpu,struct intel_vgpu_mm * mm,unsigned long gma,unsigned long end_gma,void * va)1771 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1772 unsigned long gma, unsigned long end_gma, void *va)
1773 {
1774 unsigned long copy_len, offset;
1775 unsigned long len = 0;
1776 unsigned long gpa;
1777
1778 while (gma != end_gma) {
1779 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1780 if (gpa == INTEL_GVT_INVALID_ADDR) {
1781 gvt_vgpu_err("invalid gma address: %lx\n", gma);
1782 return -EFAULT;
1783 }
1784
1785 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1786
1787 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1788 I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1789
1790 intel_gvt_read_gpa(vgpu, gpa, va + len, copy_len);
1791
1792 len += copy_len;
1793 gma += copy_len;
1794 }
1795 return len;
1796 }
1797
1798
1799 /*
1800 * Check whether a batch buffer needs to be scanned. Currently
1801 * the only criteria is based on privilege.
1802 */
batch_buffer_needs_scan(struct parser_exec_state * s)1803 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1804 {
1805 /* Decide privilege based on address space */
1806 if (cmd_val(s, 0) & BIT(8) &&
1807 !(s->vgpu->scan_nonprivbb & s->engine->mask))
1808 return 0;
1809
1810 return 1;
1811 }
1812
repr_addr_type(unsigned int type)1813 static const char *repr_addr_type(unsigned int type)
1814 {
1815 return type == PPGTT_BUFFER ? "ppgtt" : "ggtt";
1816 }
1817
find_bb_size(struct parser_exec_state * s,unsigned long * bb_size,unsigned long * bb_end_cmd_offset)1818 static int find_bb_size(struct parser_exec_state *s,
1819 unsigned long *bb_size,
1820 unsigned long *bb_end_cmd_offset)
1821 {
1822 unsigned long gma = 0;
1823 const struct cmd_info *info;
1824 u32 cmd_len = 0;
1825 bool bb_end = false;
1826 struct intel_vgpu *vgpu = s->vgpu;
1827 u32 cmd;
1828 struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1829 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1830
1831 *bb_size = 0;
1832 *bb_end_cmd_offset = 0;
1833
1834 /* get the start gm address of the batch buffer */
1835 gma = get_gma_bb_from_cmd(s, 1);
1836 if (gma == INTEL_GVT_INVALID_ADDR)
1837 return -EFAULT;
1838
1839 cmd = cmd_val(s, 0);
1840 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1841 if (info == NULL) {
1842 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1843 cmd, get_opcode(cmd, s->engine),
1844 repr_addr_type(s->buf_addr_type),
1845 s->engine->name, s->workload);
1846 return -EBADRQC;
1847 }
1848 do {
1849 if (copy_gma_to_hva(s->vgpu, mm,
1850 gma, gma + 4, &cmd) < 0)
1851 return -EFAULT;
1852 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1853 if (info == NULL) {
1854 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1855 cmd, get_opcode(cmd, s->engine),
1856 repr_addr_type(s->buf_addr_type),
1857 s->engine->name, s->workload);
1858 return -EBADRQC;
1859 }
1860
1861 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1862 bb_end = true;
1863 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1864 if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1865 /* chained batch buffer */
1866 bb_end = true;
1867 }
1868
1869 if (bb_end)
1870 *bb_end_cmd_offset = *bb_size;
1871
1872 cmd_len = get_cmd_length(info, cmd) << 2;
1873 *bb_size += cmd_len;
1874 gma += cmd_len;
1875 } while (!bb_end);
1876
1877 return 0;
1878 }
1879
audit_bb_end(struct parser_exec_state * s,void * va)1880 static int audit_bb_end(struct parser_exec_state *s, void *va)
1881 {
1882 struct intel_vgpu *vgpu = s->vgpu;
1883 u32 cmd = *(u32 *)va;
1884 const struct cmd_info *info;
1885
1886 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1887 if (info == NULL) {
1888 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1889 cmd, get_opcode(cmd, s->engine),
1890 repr_addr_type(s->buf_addr_type),
1891 s->engine->name, s->workload);
1892 return -EBADRQC;
1893 }
1894
1895 if ((info->opcode == OP_MI_BATCH_BUFFER_END) ||
1896 ((info->opcode == OP_MI_BATCH_BUFFER_START) &&
1897 (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)))
1898 return 0;
1899
1900 return -EBADRQC;
1901 }
1902
perform_bb_shadow(struct parser_exec_state * s)1903 static int perform_bb_shadow(struct parser_exec_state *s)
1904 {
1905 struct intel_vgpu *vgpu = s->vgpu;
1906 struct intel_vgpu_shadow_bb *bb;
1907 unsigned long gma = 0;
1908 unsigned long bb_size;
1909 unsigned long bb_end_cmd_offset;
1910 int ret = 0;
1911 struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1912 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1913 unsigned long start_offset = 0;
1914
1915 /* Get the start gm address of the batch buffer */
1916 gma = get_gma_bb_from_cmd(s, 1);
1917 if (gma == INTEL_GVT_INVALID_ADDR)
1918 return -EFAULT;
1919
1920 ret = find_bb_size(s, &bb_size, &bb_end_cmd_offset);
1921 if (ret)
1922 return ret;
1923
1924 bb = kzalloc_obj(*bb, GFP_KERNEL);
1925 if (!bb)
1926 return -ENOMEM;
1927
1928 bb->ppgtt = s->buf_addr_type != GTT_BUFFER;
1929
1930 /*
1931 * The start_offset stores the batch buffer's start gma's
1932 * offset relative to page boundary. So for non-privileged batch
1933 * buffer, the shadowed gem object holds exactly the same page
1934 * layout as original gem object. This is for the convenience of
1935 * replacing the whole non-privilged batch buffer page to this
1936 * shadowed one in PPGTT at the same gma address. (This replacing
1937 * action is not implemented yet now, but may be necessary in
1938 * future).
1939 * For prileged batch buffer, we just change start gma address to
1940 * that of shadowed page.
1941 */
1942 if (bb->ppgtt)
1943 start_offset = gma & ~I915_GTT_PAGE_MASK;
1944
1945 bb->obj = i915_gem_object_create_shmem(s->engine->i915,
1946 round_up(bb_size + start_offset,
1947 PAGE_SIZE));
1948 if (IS_ERR(bb->obj)) {
1949 ret = PTR_ERR(bb->obj);
1950 goto err_free_bb;
1951 }
1952
1953 bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1954 if (IS_ERR(bb->va)) {
1955 ret = PTR_ERR(bb->va);
1956 goto err_free_obj;
1957 }
1958
1959 ret = copy_gma_to_hva(s->vgpu, mm,
1960 gma, gma + bb_size,
1961 bb->va + start_offset);
1962 if (ret < 0) {
1963 gvt_vgpu_err("fail to copy guest ring buffer\n");
1964 ret = -EFAULT;
1965 goto err_unmap;
1966 }
1967
1968 ret = audit_bb_end(s, bb->va + start_offset + bb_end_cmd_offset);
1969 if (ret)
1970 goto err_unmap;
1971
1972 i915_gem_object_unlock(bb->obj);
1973 INIT_LIST_HEAD(&bb->list);
1974 list_add(&bb->list, &s->workload->shadow_bb);
1975
1976 bb->bb_start_cmd_va = s->ip_va;
1977
1978 if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1979 bb->bb_offset = s->ip_va - s->rb_va;
1980 else
1981 bb->bb_offset = 0;
1982
1983 /*
1984 * ip_va saves the virtual address of the shadow batch buffer, while
1985 * ip_gma saves the graphics address of the original batch buffer.
1986 * As the shadow batch buffer is just a copy from the original one,
1987 * it should be right to use shadow batch buffer'va and original batch
1988 * buffer's gma in pair. After all, we don't want to pin the shadow
1989 * buffer here (too early).
1990 */
1991 s->ip_va = bb->va + start_offset;
1992 s->ip_gma = gma;
1993 return 0;
1994 err_unmap:
1995 i915_gem_object_unpin_map(bb->obj);
1996 err_free_obj:
1997 i915_gem_object_put(bb->obj);
1998 err_free_bb:
1999 kfree(bb);
2000 return ret;
2001 }
2002
cmd_handler_mi_batch_buffer_start(struct parser_exec_state * s)2003 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
2004 {
2005 bool second_level;
2006 int ret = 0;
2007 struct intel_vgpu *vgpu = s->vgpu;
2008
2009 if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
2010 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
2011 return -EFAULT;
2012 }
2013
2014 second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
2015 if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
2016 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
2017 return -EFAULT;
2018 }
2019
2020 s->saved_buf_addr_type = s->buf_addr_type;
2021 addr_type_update_snb(s);
2022 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2023 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
2024 s->buf_type = BATCH_BUFFER_INSTRUCTION;
2025 } else if (second_level) {
2026 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
2027 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
2028 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
2029 }
2030
2031 if (batch_buffer_needs_scan(s)) {
2032 ret = perform_bb_shadow(s);
2033 if (ret < 0)
2034 gvt_vgpu_err("invalid shadow batch buffer\n");
2035 } else {
2036 /* emulate a batch buffer end to do return right */
2037 ret = cmd_handler_mi_batch_buffer_end(s);
2038 if (ret < 0)
2039 return ret;
2040 }
2041 return ret;
2042 }
2043
2044 static int mi_noop_index;
2045
2046 static const struct cmd_info cmd_info[] = {
2047 {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2048
2049 {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
2050 0, 1, NULL},
2051
2052 {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
2053 0, 1, cmd_handler_mi_user_interrupt},
2054
2055 {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
2056 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
2057
2058 {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2059
2060 {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2061 NULL},
2062
2063 {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2064 NULL},
2065
2066 {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2067 NULL},
2068
2069 {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2070 NULL},
2071
2072 {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
2073 D_ALL, 0, 1, NULL},
2074
2075 {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
2076 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2077 cmd_handler_mi_batch_buffer_end},
2078
2079 {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
2080 0, 1, NULL},
2081
2082 {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2083 NULL},
2084
2085 {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
2086 D_ALL, 0, 1, NULL},
2087
2088 {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2089 NULL},
2090
2091 {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2092 NULL},
2093
2094 {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR,
2095 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
2096
2097 {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR | F_LEN_VAR_FIXED,
2098 R_ALL, D_ALL, 0, 8, NULL, CMD_LEN(1)},
2099
2100 {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
2101
2102 {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS,
2103 D_ALL, 0, 8, NULL, CMD_LEN(0)},
2104
2105 {"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL,
2106 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, 0, 8,
2107 NULL, CMD_LEN(0)},
2108
2109 {"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT,
2110 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, ADDR_FIX_1(2),
2111 8, cmd_handler_mi_semaphore_wait, CMD_LEN(2)},
2112
2113 {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
2114 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
2115
2116 {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
2117 0, 8, cmd_handler_mi_store_data_index},
2118
2119 {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
2120 D_ALL, 0, 8, cmd_handler_lri},
2121
2122 {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
2123 cmd_handler_mi_update_gtt},
2124
2125 {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM,
2126 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2127 cmd_handler_srm, CMD_LEN(2)},
2128
2129 {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
2130 cmd_handler_mi_flush_dw},
2131
2132 {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
2133 10, cmd_handler_mi_clflush},
2134
2135 {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT,
2136 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6,
2137 cmd_handler_mi_report_perf_count, CMD_LEN(2)},
2138
2139 {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM,
2140 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2141 cmd_handler_lrm, CMD_LEN(2)},
2142
2143 {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG,
2144 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, 0, 8,
2145 cmd_handler_lrr, CMD_LEN(1)},
2146
2147 {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM,
2148 F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, D_ALL, 0,
2149 8, NULL, CMD_LEN(2)},
2150
2151 {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR | F_LEN_VAR_FIXED,
2152 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)},
2153
2154 {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
2155 ADDR_FIX_1(2), 8, NULL},
2156
2157 {"MI_OP_2E", OP_MI_2E, F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS,
2158 ADDR_FIX_2(1, 2), 8, cmd_handler_mi_op_2e, CMD_LEN(3)},
2159
2160 {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
2161 8, cmd_handler_mi_op_2f},
2162
2163 {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
2164 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
2165 cmd_handler_mi_batch_buffer_start},
2166
2167 {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
2168 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2169 cmd_handler_mi_conditional_batch_buffer_end, CMD_LEN(2)},
2170
2171 {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
2172 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
2173
2174 {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2175 ADDR_FIX_2(4, 7), 8, NULL},
2176
2177 {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2178 0, 8, NULL},
2179
2180 {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
2181 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2182
2183 {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2184
2185 {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
2186 0, 8, NULL},
2187
2188 {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2189 ADDR_FIX_1(3), 8, NULL},
2190
2191 {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
2192 D_ALL, 0, 8, NULL},
2193
2194 {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
2195 ADDR_FIX_1(4), 8, NULL},
2196
2197 {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2198 ADDR_FIX_2(4, 5), 8, NULL},
2199
2200 {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2201 ADDR_FIX_1(4), 8, NULL},
2202
2203 {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
2204 ADDR_FIX_2(4, 7), 8, NULL},
2205
2206 {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
2207 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2208
2209 {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2210
2211 {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
2212 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
2213
2214 {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
2215 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2216
2217 {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
2218 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
2219 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2220
2221 {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
2222 D_ALL, ADDR_FIX_1(4), 8, NULL},
2223
2224 {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2225 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2226
2227 {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2228 D_ALL, ADDR_FIX_1(4), 8, NULL},
2229
2230 {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2231 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2232
2233 {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2234 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2235
2236 {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2237 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2238 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2239
2240 {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2241 ADDR_FIX_2(4, 5), 8, NULL},
2242
2243 {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2244 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2245
2246 {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2247 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2248 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2249
2250 {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2251 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2252 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2253
2254 {"3DSTATE_BLEND_STATE_POINTERS",
2255 OP_3DSTATE_BLEND_STATE_POINTERS,
2256 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2257
2258 {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2259 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2260 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2261
2262 {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2263 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2264 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2265
2266 {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2267 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2268 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2269
2270 {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2271 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2272 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2273
2274 {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2275 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2276 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2277
2278 {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2279 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2280 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2281
2282 {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2283 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2284 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2285
2286 {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2287 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2288 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2289
2290 {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2291 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2292 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2293
2294 {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2295 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2296 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2297
2298 {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2299 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2300 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2301
2302 {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2303 0, 8, NULL},
2304
2305 {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2306 0, 8, NULL},
2307
2308 {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2309 0, 8, NULL},
2310
2311 {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2312 0, 8, NULL},
2313
2314 {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2315 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2316
2317 {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2318 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2319
2320 {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2321 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2322
2323 {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2324 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2325
2326 {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2327 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2328
2329 {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2330 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2331
2332 {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2333 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2334
2335 {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2336 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2337
2338 {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2339 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2340
2341 {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2342 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2343
2344 {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2345 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2346
2347 {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2348 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2349
2350 {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2351 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2352
2353 {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2354 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2355
2356 {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2357 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2358
2359 {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2360 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2361
2362 {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2363 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2364
2365 {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2366 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2367
2368 {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2369 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2370
2371 {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2372 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2373
2374 {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2375 D_BDW_PLUS, 0, 8, NULL},
2376
2377 {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2378 NULL},
2379
2380 {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2381 D_BDW_PLUS, 0, 8, NULL},
2382
2383 {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2384 D_BDW_PLUS, 0, 8, NULL},
2385
2386 {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2387 8, NULL},
2388
2389 {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2390 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2391
2392 {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2393 8, NULL},
2394
2395 {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2396 NULL},
2397
2398 {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2399 NULL},
2400
2401 {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2402 NULL},
2403
2404 {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2405 D_BDW_PLUS, 0, 8, NULL},
2406
2407 {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2408 R_RCS, D_ALL, 0, 8, NULL},
2409
2410 {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2411 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2412
2413 {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2414 R_RCS, D_ALL, 0, 1, NULL},
2415
2416 {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2417
2418 {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2419 R_RCS, D_ALL, 0, 8, NULL},
2420
2421 {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2422 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2423
2424 {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2425
2426 {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2427
2428 {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2429
2430 {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2431 D_BDW_PLUS, 0, 8, NULL},
2432
2433 {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2434 D_BDW_PLUS, 0, 8, NULL},
2435
2436 {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2437 D_ALL, 0, 8, NULL},
2438
2439 {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2440 D_BDW_PLUS, 0, 8, NULL},
2441
2442 {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2443 D_BDW_PLUS, 0, 8, NULL},
2444
2445 {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2446
2447 {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2448
2449 {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2450
2451 {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2452 D_ALL, 0, 8, NULL},
2453
2454 {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2455
2456 {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2457
2458 {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2459 R_RCS, D_ALL, 0, 8, NULL},
2460
2461 {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2462 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2463
2464 {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2465 0, 8, NULL},
2466
2467 {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2468 D_ALL, ADDR_FIX_1(2), 8, NULL},
2469
2470 {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2471 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2472
2473 {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2474 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2475
2476 {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2477 D_ALL, 0, 8, NULL},
2478
2479 {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2480 D_ALL, 0, 8, NULL},
2481
2482 {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2483 D_ALL, 0, 8, NULL},
2484
2485 {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2486 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2487
2488 {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2489 D_BDW_PLUS, 0, 8, NULL},
2490
2491 {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2492 D_ALL, ADDR_FIX_1(2), 8, NULL},
2493
2494 {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2495 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2496
2497 {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2498 R_RCS, D_ALL, 0, 8, NULL},
2499
2500 {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2501 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2502
2503 {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2504 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2505
2506 {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2507 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2508
2509 {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2510 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2511
2512 {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2513 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2514
2515 {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2516 R_RCS, D_ALL, 0, 8, NULL},
2517
2518 {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2519 D_ALL, 0, 9, NULL},
2520
2521 {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2522 ADDR_FIX_2(2, 4), 8, NULL},
2523
2524 {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2525 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2526 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2527
2528 {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2529 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2530
2531 {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2532 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2533 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2534
2535 {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2536 D_BDW_PLUS, 0, 8, NULL},
2537
2538 {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2539 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2540
2541 {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2542
2543 {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2544 1, NULL},
2545
2546 {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2547 ADDR_FIX_1(1), 8, NULL},
2548
2549 {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2550
2551 {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2552 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2553
2554 {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2555 ADDR_FIX_1(1), 8, NULL},
2556
2557 {"OP_SWTESS_BASE_ADDRESS", OP_SWTESS_BASE_ADDRESS,
2558 F_LEN_VAR, R_RCS, D_ALL, ADDR_FIX_2(1, 2), 3, NULL},
2559
2560 {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2561
2562 {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2563
2564 {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2565 0, 8, NULL},
2566
2567 {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2568 D_SKL_PLUS, 0, 8, NULL},
2569
2570 {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2571 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2572
2573 {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2574 0, 16, NULL},
2575
2576 {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2577 0, 16, NULL},
2578
2579 {"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,
2580 0, 16, NULL},
2581
2582 {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2583
2584 {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2585 0, 16, NULL},
2586
2587 {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2588 0, 16, NULL},
2589
2590 {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2591 0, 16, NULL},
2592
2593 {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2594 0, 8, NULL},
2595
2596 {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2597 NULL},
2598
2599 {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2600 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2601
2602 {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2603 R_VCS, D_ALL, 0, 12, NULL},
2604
2605 {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2606 R_VCS, D_ALL, 0, 12, NULL},
2607
2608 {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2609 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2610
2611 {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2612 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2613
2614 {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2615 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2616
2617 {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2618
2619 {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2620 R_VCS, D_ALL, 0, 12, NULL},
2621
2622 {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2623 R_VCS, D_ALL, 0, 12, NULL},
2624
2625 {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2626 R_VCS, D_ALL, 0, 12, NULL},
2627
2628 {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2629 R_VCS, D_ALL, 0, 12, NULL},
2630
2631 {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2632 R_VCS, D_ALL, 0, 12, NULL},
2633
2634 {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2635 R_VCS, D_ALL, 0, 12, NULL},
2636
2637 {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2638 R_VCS, D_ALL, 0, 6, NULL},
2639
2640 {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2641 R_VCS, D_ALL, 0, 12, NULL},
2642
2643 {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2644 R_VCS, D_ALL, 0, 12, NULL},
2645
2646 {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2647 R_VCS, D_ALL, 0, 12, NULL},
2648
2649 {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2650 R_VCS, D_ALL, 0, 12, NULL},
2651
2652 {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2653 R_VCS, D_ALL, 0, 12, NULL},
2654
2655 {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2656 R_VCS, D_ALL, 0, 12, NULL},
2657
2658 {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2659 R_VCS, D_ALL, 0, 12, NULL},
2660 {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2661 R_VCS, D_ALL, 0, 12, NULL},
2662
2663 {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2664 R_VCS, D_ALL, 0, 12, NULL},
2665
2666 {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2667 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2668
2669 {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2670 R_VCS, D_ALL, 0, 12, NULL},
2671
2672 {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2673 R_VCS, D_ALL, 0, 12, NULL},
2674
2675 {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2676 R_VCS, D_ALL, 0, 12, NULL},
2677
2678 {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2679 R_VCS, D_ALL, 0, 12, NULL},
2680
2681 {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2682 R_VCS, D_ALL, 0, 12, NULL},
2683
2684 {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2685 R_VCS, D_ALL, 0, 12, NULL},
2686
2687 {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2688 R_VCS, D_ALL, 0, 12, NULL},
2689
2690 {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2691 R_VCS, D_ALL, 0, 12, NULL},
2692
2693 {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2694 R_VCS, D_ALL, 0, 12, NULL},
2695
2696 {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2697 R_VCS, D_ALL, 0, 12, NULL},
2698
2699 {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2700 R_VCS, D_ALL, 0, 12, NULL},
2701
2702 {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2703 0, 16, NULL},
2704
2705 {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2706
2707 {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2708
2709 {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2710 R_VCS, D_ALL, 0, 12, NULL},
2711
2712 {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2713 R_VCS, D_ALL, 0, 12, NULL},
2714
2715 {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2716 R_VCS, D_ALL, 0, 12, NULL},
2717
2718 {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2719
2720 {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2721 0, 12, NULL},
2722
2723 {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2724 0, 12, NULL},
2725 };
2726
add_cmd_entry(struct intel_gvt * gvt,struct cmd_entry * e)2727 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2728 {
2729 hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2730 }
2731
2732 /* call the cmd handler, and advance ip */
cmd_parser_exec(struct parser_exec_state * s)2733 static int cmd_parser_exec(struct parser_exec_state *s)
2734 {
2735 struct intel_vgpu *vgpu = s->vgpu;
2736 const struct cmd_info *info;
2737 u32 cmd;
2738 int ret = 0;
2739
2740 cmd = cmd_val(s, 0);
2741
2742 /* fastpath for MI_NOOP */
2743 if (cmd == MI_NOOP)
2744 info = &cmd_info[mi_noop_index];
2745 else
2746 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
2747
2748 if (info == NULL) {
2749 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
2750 cmd, get_opcode(cmd, s->engine),
2751 repr_addr_type(s->buf_addr_type),
2752 s->engine->name, s->workload);
2753 return -EBADRQC;
2754 }
2755
2756 s->info = info;
2757
2758 trace_gvt_command(vgpu->id, s->engine->id, s->ip_gma, s->ip_va,
2759 cmd_length(s), s->buf_type, s->buf_addr_type,
2760 s->workload, info->name);
2761
2762 if ((info->flag & F_LEN_MASK) == F_LEN_VAR_FIXED) {
2763 ret = gvt_check_valid_cmd_length(cmd_length(s),
2764 info->valid_len);
2765 if (ret)
2766 return ret;
2767 }
2768
2769 if (info->handler) {
2770 ret = info->handler(s);
2771 if (ret < 0) {
2772 gvt_vgpu_err("%s handler error\n", info->name);
2773 return ret;
2774 }
2775 }
2776
2777 if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2778 ret = cmd_advance_default(s);
2779 if (ret) {
2780 gvt_vgpu_err("%s IP advance error\n", info->name);
2781 return ret;
2782 }
2783 }
2784 return 0;
2785 }
2786
gma_out_of_range(unsigned long gma,unsigned long gma_head,unsigned int gma_tail)2787 static inline bool gma_out_of_range(unsigned long gma,
2788 unsigned long gma_head, unsigned int gma_tail)
2789 {
2790 if (gma_tail >= gma_head)
2791 return (gma < gma_head) || (gma > gma_tail);
2792 else
2793 return (gma > gma_tail) && (gma < gma_head);
2794 }
2795
2796 /* Keep the consistent return type, e.g EBADRQC for unknown
2797 * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2798 * works as the input of VM healthy status.
2799 */
command_scan(struct parser_exec_state * s,unsigned long rb_head,unsigned long rb_tail,unsigned long rb_start,unsigned long rb_len)2800 static int command_scan(struct parser_exec_state *s,
2801 unsigned long rb_head, unsigned long rb_tail,
2802 unsigned long rb_start, unsigned long rb_len)
2803 {
2804
2805 unsigned long gma_head, gma_tail, gma_bottom;
2806 int ret = 0;
2807 struct intel_vgpu *vgpu = s->vgpu;
2808
2809 gma_head = rb_start + rb_head;
2810 gma_tail = rb_start + rb_tail;
2811 gma_bottom = rb_start + rb_len;
2812
2813 while (s->ip_gma != gma_tail) {
2814 if (s->buf_type == RING_BUFFER_INSTRUCTION ||
2815 s->buf_type == RING_BUFFER_CTX) {
2816 if (!(s->ip_gma >= rb_start) ||
2817 !(s->ip_gma < gma_bottom)) {
2818 gvt_vgpu_err("ip_gma %lx out of ring scope."
2819 "(base:0x%lx, bottom: 0x%lx)\n",
2820 s->ip_gma, rb_start,
2821 gma_bottom);
2822 parser_exec_state_dump(s);
2823 return -EFAULT;
2824 }
2825 if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2826 gvt_vgpu_err("ip_gma %lx out of range."
2827 "base 0x%lx head 0x%lx tail 0x%lx\n",
2828 s->ip_gma, rb_start,
2829 rb_head, rb_tail);
2830 parser_exec_state_dump(s);
2831 break;
2832 }
2833 }
2834 ret = cmd_parser_exec(s);
2835 if (ret) {
2836 gvt_vgpu_err("cmd parser error\n");
2837 parser_exec_state_dump(s);
2838 break;
2839 }
2840 }
2841
2842 return ret;
2843 }
2844
scan_workload(struct intel_vgpu_workload * workload)2845 static int scan_workload(struct intel_vgpu_workload *workload)
2846 {
2847 unsigned long gma_head, gma_tail;
2848 struct parser_exec_state s;
2849 int ret = 0;
2850
2851 /* ring base is page aligned */
2852 if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2853 return -EINVAL;
2854
2855 gma_head = workload->rb_start + workload->rb_head;
2856 gma_tail = workload->rb_start + workload->rb_tail;
2857
2858 s.buf_type = RING_BUFFER_INSTRUCTION;
2859 s.buf_addr_type = GTT_BUFFER;
2860 s.vgpu = workload->vgpu;
2861 s.engine = workload->engine;
2862 s.ring_start = workload->rb_start;
2863 s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2864 s.ring_head = gma_head;
2865 s.ring_tail = gma_tail;
2866 s.rb_va = workload->shadow_ring_buffer_va;
2867 s.workload = workload;
2868 s.is_ctx_wa = false;
2869
2870 if (bypass_scan_mask & workload->engine->mask || gma_head == gma_tail)
2871 return 0;
2872
2873 ret = ip_gma_set(&s, gma_head);
2874 if (ret)
2875 goto out;
2876
2877 ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2878 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2879
2880 out:
2881 return ret;
2882 }
2883
scan_wa_ctx(struct intel_shadow_wa_ctx * wa_ctx)2884 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2885 {
2886
2887 unsigned long gma_head, gma_tail, ring_size, ring_tail;
2888 struct parser_exec_state s;
2889 int ret = 0;
2890 struct intel_vgpu_workload *workload = container_of(wa_ctx,
2891 struct intel_vgpu_workload,
2892 wa_ctx);
2893
2894 /* ring base is page aligned */
2895 if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2896 I915_GTT_PAGE_SIZE)))
2897 return -EINVAL;
2898
2899 ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);
2900 ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2901 PAGE_SIZE);
2902 gma_head = wa_ctx->indirect_ctx.guest_gma;
2903 gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2904
2905 s.buf_type = RING_BUFFER_INSTRUCTION;
2906 s.buf_addr_type = GTT_BUFFER;
2907 s.vgpu = workload->vgpu;
2908 s.engine = workload->engine;
2909 s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2910 s.ring_size = ring_size;
2911 s.ring_head = gma_head;
2912 s.ring_tail = gma_tail;
2913 s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2914 s.workload = workload;
2915 s.is_ctx_wa = true;
2916
2917 ret = ip_gma_set(&s, gma_head);
2918 if (ret)
2919 goto out;
2920
2921 ret = command_scan(&s, 0, ring_tail,
2922 wa_ctx->indirect_ctx.guest_gma, ring_size);
2923 out:
2924 return ret;
2925 }
2926
shadow_workload_ring_buffer(struct intel_vgpu_workload * workload)2927 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2928 {
2929 struct intel_vgpu *vgpu = workload->vgpu;
2930 struct intel_vgpu_submission *s = &vgpu->submission;
2931 unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2932 void *shadow_ring_buffer_va;
2933 int ret;
2934
2935 guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2936
2937 /* calculate workload ring buffer size */
2938 workload->rb_len = (workload->rb_tail + guest_rb_size -
2939 workload->rb_head) % guest_rb_size;
2940
2941 gma_head = workload->rb_start + workload->rb_head;
2942 gma_tail = workload->rb_start + workload->rb_tail;
2943 gma_top = workload->rb_start + guest_rb_size;
2944
2945 if (workload->rb_len > s->ring_scan_buffer_size[workload->engine->id]) {
2946 void *p;
2947
2948 /* realloc the new ring buffer if needed */
2949 p = krealloc(s->ring_scan_buffer[workload->engine->id],
2950 workload->rb_len, GFP_KERNEL);
2951 if (!p) {
2952 gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2953 return -ENOMEM;
2954 }
2955 s->ring_scan_buffer[workload->engine->id] = p;
2956 s->ring_scan_buffer_size[workload->engine->id] = workload->rb_len;
2957 }
2958
2959 shadow_ring_buffer_va = s->ring_scan_buffer[workload->engine->id];
2960
2961 /* get shadow ring buffer va */
2962 workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2963
2964 /* head > tail --> copy head <-> top */
2965 if (gma_head > gma_tail) {
2966 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2967 gma_head, gma_top, shadow_ring_buffer_va);
2968 if (ret < 0) {
2969 gvt_vgpu_err("fail to copy guest ring buffer\n");
2970 return ret;
2971 }
2972 shadow_ring_buffer_va += ret;
2973 gma_head = workload->rb_start;
2974 }
2975
2976 /* copy head or start <-> tail */
2977 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2978 shadow_ring_buffer_va);
2979 if (ret < 0) {
2980 gvt_vgpu_err("fail to copy guest ring buffer\n");
2981 return ret;
2982 }
2983 return 0;
2984 }
2985
intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload * workload)2986 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2987 {
2988 int ret;
2989 struct intel_vgpu *vgpu = workload->vgpu;
2990
2991 ret = shadow_workload_ring_buffer(workload);
2992 if (ret) {
2993 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2994 return ret;
2995 }
2996
2997 ret = scan_workload(workload);
2998 if (ret) {
2999 gvt_vgpu_err("scan workload error\n");
3000 return ret;
3001 }
3002 return 0;
3003 }
3004
shadow_indirect_ctx(struct intel_shadow_wa_ctx * wa_ctx)3005 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3006 {
3007 int ctx_size = wa_ctx->indirect_ctx.size;
3008 unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
3009 struct intel_vgpu_workload *workload = container_of(wa_ctx,
3010 struct intel_vgpu_workload,
3011 wa_ctx);
3012 struct intel_vgpu *vgpu = workload->vgpu;
3013 struct drm_i915_gem_object *obj;
3014 int ret = 0;
3015 void *map;
3016
3017 obj = i915_gem_object_create_shmem(workload->engine->i915,
3018 roundup(ctx_size + CACHELINE_BYTES,
3019 PAGE_SIZE));
3020 if (IS_ERR(obj))
3021 return PTR_ERR(obj);
3022
3023 /* get the va of the shadow batch buffer */
3024 map = i915_gem_object_pin_map(obj, I915_MAP_WB);
3025 if (IS_ERR(map)) {
3026 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
3027 ret = PTR_ERR(map);
3028 goto put_obj;
3029 }
3030
3031 i915_gem_object_lock(obj, NULL);
3032 ret = i915_gem_object_set_to_cpu_domain(obj, false);
3033 i915_gem_object_unlock(obj);
3034 if (ret) {
3035 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
3036 goto unmap_src;
3037 }
3038
3039 ret = copy_gma_to_hva(workload->vgpu,
3040 workload->vgpu->gtt.ggtt_mm,
3041 guest_gma, guest_gma + ctx_size,
3042 map);
3043 if (ret < 0) {
3044 gvt_vgpu_err("fail to copy guest indirect ctx\n");
3045 goto unmap_src;
3046 }
3047
3048 wa_ctx->indirect_ctx.obj = obj;
3049 wa_ctx->indirect_ctx.shadow_va = map;
3050 return 0;
3051
3052 unmap_src:
3053 i915_gem_object_unpin_map(obj);
3054 put_obj:
3055 i915_gem_object_put(obj);
3056 return ret;
3057 }
3058
combine_wa_ctx(struct intel_shadow_wa_ctx * wa_ctx)3059 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3060 {
3061 u32 per_ctx_start[CACHELINE_DWORDS] = {};
3062 unsigned char *bb_start_sva;
3063
3064 if (!wa_ctx->per_ctx.valid)
3065 return 0;
3066
3067 per_ctx_start[0] = 0x18800001;
3068 per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
3069
3070 bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
3071 wa_ctx->indirect_ctx.size;
3072
3073 memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
3074
3075 return 0;
3076 }
3077
intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx * wa_ctx)3078 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3079 {
3080 int ret;
3081 struct intel_vgpu_workload *workload = container_of(wa_ctx,
3082 struct intel_vgpu_workload,
3083 wa_ctx);
3084 struct intel_vgpu *vgpu = workload->vgpu;
3085
3086 if (wa_ctx->indirect_ctx.size == 0)
3087 return 0;
3088
3089 ret = shadow_indirect_ctx(wa_ctx);
3090 if (ret) {
3091 gvt_vgpu_err("fail to shadow indirect ctx\n");
3092 return ret;
3093 }
3094
3095 combine_wa_ctx(wa_ctx);
3096
3097 ret = scan_wa_ctx(wa_ctx);
3098 if (ret) {
3099 gvt_vgpu_err("scan wa ctx error\n");
3100 return ret;
3101 }
3102
3103 return 0;
3104 }
3105
3106 /* generate dummy contexts by sending empty requests to HW, and let
3107 * the HW to fill Engine Contexts. This dummy contexts are used for
3108 * initialization purpose (update reg whitelist), so referred to as
3109 * init context here
3110 */
intel_gvt_update_reg_whitelist(struct intel_vgpu * vgpu)3111 void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu)
3112 {
3113 const unsigned long start = LRC_STATE_PN * PAGE_SIZE;
3114 struct intel_gvt *gvt = vgpu->gvt;
3115 struct intel_engine_cs *engine;
3116 enum intel_engine_id id;
3117
3118 if (gvt->is_reg_whitelist_updated)
3119 return;
3120
3121 /* scan init ctx to update cmd accessible list */
3122 for_each_engine(engine, gvt->gt, id) {
3123 struct parser_exec_state s;
3124 void *vaddr;
3125 int ret;
3126
3127 if (!engine->default_state)
3128 continue;
3129
3130 vaddr = shmem_pin_map(engine->default_state);
3131 if (!vaddr) {
3132 gvt_err("failed to map %s->default state\n",
3133 engine->name);
3134 return;
3135 }
3136
3137 s.buf_type = RING_BUFFER_CTX;
3138 s.buf_addr_type = GTT_BUFFER;
3139 s.vgpu = vgpu;
3140 s.engine = engine;
3141 s.ring_start = 0;
3142 s.ring_size = engine->context_size - start;
3143 s.ring_head = 0;
3144 s.ring_tail = s.ring_size;
3145 s.rb_va = vaddr + start;
3146 s.workload = NULL;
3147 s.is_ctx_wa = false;
3148 s.is_init_ctx = true;
3149
3150 /* skipping the first RING_CTX_SIZE(0x50) dwords */
3151 ret = ip_gma_set(&s, RING_CTX_SIZE);
3152 if (ret == 0) {
3153 ret = command_scan(&s, 0, s.ring_size, 0, s.ring_size);
3154 if (ret)
3155 gvt_err("Scan init ctx error\n");
3156 }
3157
3158 shmem_unpin_map(engine->default_state, vaddr);
3159 if (ret)
3160 return;
3161 }
3162
3163 gvt->is_reg_whitelist_updated = true;
3164 }
3165
intel_gvt_scan_engine_context(struct intel_vgpu_workload * workload)3166 int intel_gvt_scan_engine_context(struct intel_vgpu_workload *workload)
3167 {
3168 struct intel_vgpu *vgpu = workload->vgpu;
3169 unsigned long gma_head, gma_tail, gma_start, ctx_size;
3170 struct parser_exec_state s;
3171 int ring_id = workload->engine->id;
3172 struct intel_context *ce = vgpu->submission.shadow[ring_id];
3173 int ret;
3174
3175 GEM_BUG_ON(atomic_read(&ce->pin_count) < 0);
3176
3177 ctx_size = workload->engine->context_size - PAGE_SIZE;
3178
3179 /* Only ring contxt is loaded to HW for inhibit context, no need to
3180 * scan engine context
3181 */
3182 if (is_inhibit_context(ce))
3183 return 0;
3184
3185 gma_start = i915_ggtt_offset(ce->state) + LRC_STATE_PN*PAGE_SIZE;
3186 gma_head = 0;
3187 gma_tail = ctx_size;
3188
3189 s.buf_type = RING_BUFFER_CTX;
3190 s.buf_addr_type = GTT_BUFFER;
3191 s.vgpu = workload->vgpu;
3192 s.engine = workload->engine;
3193 s.ring_start = gma_start;
3194 s.ring_size = ctx_size;
3195 s.ring_head = gma_start + gma_head;
3196 s.ring_tail = gma_start + gma_tail;
3197 s.rb_va = ce->lrc_reg_state;
3198 s.workload = workload;
3199 s.is_ctx_wa = false;
3200 s.is_init_ctx = false;
3201
3202 /* don't scan the first RING_CTX_SIZE(0x50) dwords, as it's ring
3203 * context
3204 */
3205 ret = ip_gma_set(&s, gma_start + gma_head + RING_CTX_SIZE);
3206 if (ret)
3207 goto out;
3208
3209 ret = command_scan(&s, gma_head, gma_tail,
3210 gma_start, ctx_size);
3211 out:
3212 if (ret)
3213 gvt_vgpu_err("scan shadow ctx error\n");
3214
3215 return ret;
3216 }
3217
init_cmd_table(struct intel_gvt * gvt)3218 static int init_cmd_table(struct intel_gvt *gvt)
3219 {
3220 unsigned int gen_type = intel_gvt_get_device_type(gvt);
3221 int i;
3222
3223 for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
3224 struct cmd_entry *e;
3225
3226 if (!(cmd_info[i].devices & gen_type))
3227 continue;
3228
3229 e = kzalloc_obj(*e, GFP_KERNEL);
3230 if (!e)
3231 return -ENOMEM;
3232
3233 e->info = &cmd_info[i];
3234 if (cmd_info[i].opcode == OP_MI_NOOP)
3235 mi_noop_index = i;
3236
3237 INIT_HLIST_NODE(&e->hlist);
3238 add_cmd_entry(gvt, e);
3239 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
3240 e->info->name, e->info->opcode, e->info->flag,
3241 e->info->devices, e->info->rings);
3242 }
3243
3244 return 0;
3245 }
3246
clean_cmd_table(struct intel_gvt * gvt)3247 static void clean_cmd_table(struct intel_gvt *gvt)
3248 {
3249 struct hlist_node *tmp;
3250 struct cmd_entry *e;
3251 int i;
3252
3253 hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
3254 kfree(e);
3255
3256 hash_init(gvt->cmd_table);
3257 }
3258
intel_gvt_clean_cmd_parser(struct intel_gvt * gvt)3259 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
3260 {
3261 clean_cmd_table(gvt);
3262 }
3263
intel_gvt_init_cmd_parser(struct intel_gvt * gvt)3264 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
3265 {
3266 int ret;
3267
3268 ret = init_cmd_table(gvt);
3269 if (ret) {
3270 intel_gvt_clean_cmd_parser(gvt);
3271 return ret;
3272 }
3273 return 0;
3274 }
3275