1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_MAC_H__
6 #define __RTW89_MAC_H__
7
8 #include "core.h"
9 #include "fw.h"
10 #include "reg.h"
11
12 #define MAC_MEM_DUMP_PAGE_SIZE_AX 0x40000
13 #define MAC_MEM_DUMP_PAGE_SIZE_BE 0x80000
14
15 #define ADDR_CAM_ENT_SIZE 0x40
16 #define ADDR_CAM_ENT_SHORT_SIZE 0x20
17 #define BSSID_CAM_ENT_SIZE 0x08
18 #define HFC_PAGE_UNIT 64
19 #define RPWM_TRY_CNT 3
20 #define CPU_IO_RX_RETRY_CNT 3
21
22 enum rtw89_mac_hwmod_sel {
23 RTW89_DMAC_SEL = 0,
24 RTW89_CMAC_SEL = 1,
25
26 RTW89_MAC_INVALID,
27 };
28
29 enum rtw89_mac_fwd_target {
30 RTW89_FWD_DONT_CARE = 0,
31 RTW89_FWD_TO_HOST = 1,
32 RTW89_FWD_TO_WLAN_CPU = 2
33 };
34
35 enum rtw89_mac_wd_dma_intvl {
36 RTW89_MAC_WD_DMA_INTVL_0S,
37 RTW89_MAC_WD_DMA_INTVL_256NS,
38 RTW89_MAC_WD_DMA_INTVL_512NS,
39 RTW89_MAC_WD_DMA_INTVL_768NS,
40 RTW89_MAC_WD_DMA_INTVL_1US,
41 RTW89_MAC_WD_DMA_INTVL_1_5US,
42 RTW89_MAC_WD_DMA_INTVL_2US,
43 RTW89_MAC_WD_DMA_INTVL_4US,
44 RTW89_MAC_WD_DMA_INTVL_8US,
45 RTW89_MAC_WD_DMA_INTVL_16US,
46 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
47 };
48
49 enum rtw89_mac_multi_tag_num {
50 RTW89_MAC_TAG_NUM_1,
51 RTW89_MAC_TAG_NUM_2,
52 RTW89_MAC_TAG_NUM_3,
53 RTW89_MAC_TAG_NUM_4,
54 RTW89_MAC_TAG_NUM_5,
55 RTW89_MAC_TAG_NUM_6,
56 RTW89_MAC_TAG_NUM_7,
57 RTW89_MAC_TAG_NUM_8,
58 RTW89_MAC_TAG_NUM_DEF = 0xFE
59 };
60
61 enum rtw89_mac_lbc_tmr {
62 RTW89_MAC_LBC_TMR_8US = 0,
63 RTW89_MAC_LBC_TMR_16US,
64 RTW89_MAC_LBC_TMR_32US,
65 RTW89_MAC_LBC_TMR_64US,
66 RTW89_MAC_LBC_TMR_128US,
67 RTW89_MAC_LBC_TMR_256US,
68 RTW89_MAC_LBC_TMR_512US,
69 RTW89_MAC_LBC_TMR_1MS,
70 RTW89_MAC_LBC_TMR_2MS,
71 RTW89_MAC_LBC_TMR_4MS,
72 RTW89_MAC_LBC_TMR_8MS,
73 RTW89_MAC_LBC_TMR_DEF = 0xFE
74 };
75
76 enum rtw89_mac_cpuio_op_cmd_type {
77 CPUIO_OP_CMD_GET_1ST_PID = 0,
78 CPUIO_OP_CMD_GET_NEXT_PID = 1,
79 CPUIO_OP_CMD_ENQ_TO_TAIL = 4,
80 CPUIO_OP_CMD_ENQ_TO_HEAD = 5,
81 CPUIO_OP_CMD_DEQ = 8,
82 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9,
83 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12
84 };
85
86 enum rtw89_mac_wde_dle_port_id {
87 WDE_DLE_PORT_ID_DISPATCH = 0,
88 WDE_DLE_PORT_ID_PKTIN = 1,
89 WDE_DLE_PORT_ID_CMAC0 = 3,
90 WDE_DLE_PORT_ID_CMAC1 = 4,
91 WDE_DLE_PORT_ID_CPU_IO = 6,
92 WDE_DLE_PORT_ID_WDRLS = 7,
93 WDE_DLE_PORT_ID_END = 8
94 };
95
96 enum rtw89_mac_wde_dle_queid_wdrls {
97 WDE_DLE_QUEID_TXOK = 0,
98 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1,
99 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2,
100 WDE_DLE_QUEID_DROP_MACID_DROP = 3,
101 WDE_DLE_QUEID_NO_REPORT = 4
102 };
103
104 enum rtw89_mac_ple_dle_port_id {
105 PLE_DLE_PORT_ID_DISPATCH = 0,
106 PLE_DLE_PORT_ID_MPDU = 1,
107 PLE_DLE_PORT_ID_SEC = 2,
108 PLE_DLE_PORT_ID_CMAC0 = 3,
109 PLE_DLE_PORT_ID_CMAC1 = 4,
110 PLE_DLE_PORT_ID_WDRLS = 5,
111 PLE_DLE_PORT_ID_CPU_IO = 6,
112 PLE_DLE_PORT_ID_PLRLS = 7,
113 PLE_DLE_PORT_ID_END = 8
114 };
115
116 enum rtw89_mac_ple_dle_queid_plrls {
117 PLE_DLE_QUEID_NO_REPORT = 0x0
118 };
119
120 enum rtw89_machdr_frame_type {
121 RTW89_MGNT = 0,
122 RTW89_CTRL = 1,
123 RTW89_DATA = 2,
124 };
125
126 enum rtw89_mac_dle_dfi_type {
127 DLE_DFI_TYPE_FREEPG = 0,
128 DLE_DFI_TYPE_QUOTA = 1,
129 DLE_DFI_TYPE_PAGELLT = 2,
130 DLE_DFI_TYPE_PKTINFO = 3,
131 DLE_DFI_TYPE_PREPKTLLT = 4,
132 DLE_DFI_TYPE_NXTPKTLLT = 5,
133 DLE_DFI_TYPE_QLNKTBL = 6,
134 DLE_DFI_TYPE_QEMPTY = 7,
135 };
136
137 enum rtw89_mac_dle_wde_quota_id {
138 WDE_QTAID_HOST_IF = 0,
139 WDE_QTAID_WLAN_CPU = 1,
140 WDE_QTAID_DATA_CPU = 2,
141 WDE_QTAID_PKTIN = 3,
142 WDE_QTAID_CPUIO = 4,
143 };
144
145 enum rtw89_mac_dle_ple_quota_id {
146 PLE_QTAID_B0_TXPL = 0,
147 PLE_QTAID_B1_TXPL = 1,
148 PLE_QTAID_C2H = 2,
149 PLE_QTAID_H2C = 3,
150 PLE_QTAID_WLAN_CPU = 4,
151 PLE_QTAID_MPDU = 5,
152 PLE_QTAID_CMAC0_RX = 6,
153 PLE_QTAID_CMAC1_RX = 7,
154 PLE_QTAID_CMAC1_BBRPT = 8,
155 PLE_QTAID_WDRLS = 9,
156 PLE_QTAID_CPUIO = 10,
157 };
158
159 enum rtw89_mac_dle_ctrl_type {
160 DLE_CTRL_TYPE_WDE = 0,
161 DLE_CTRL_TYPE_PLE = 1,
162 DLE_CTRL_TYPE_NUM = 2,
163 };
164
165 enum rtw89_mac_ax_l0_to_l1_event {
166 MAC_AX_L0_TO_L1_CHIF_IDLE = 0,
167 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1,
168 MAC_AX_L0_TO_L1_RLS_PKID = 2,
169 MAC_AX_L0_TO_L1_PTCL_IDLE = 3,
170 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4,
171 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5,
172 MAC_AX_L0_TO_L1_PCIE_STUCK = 6,
173 MAC_AX_L0_TO_L1_EVENT_MAX = 15,
174 };
175
176 enum rtw89_mac_phy_rpt_size {
177 MAC_AX_PHY_RPT_SIZE_0 = 0,
178 MAC_AX_PHY_RPT_SIZE_8 = 1,
179 MAC_AX_PHY_RPT_SIZE_16 = 2,
180 MAC_AX_PHY_RPT_SIZE_24 = 3,
181 };
182
183 enum rtw89_mac_hdr_cnv_size {
184 MAC_AX_HDR_CNV_SIZE_0 = 0,
185 MAC_AX_HDR_CNV_SIZE_32 = 1,
186 MAC_AX_HDR_CNV_SIZE_64 = 2,
187 MAC_AX_HDR_CNV_SIZE_96 = 3,
188 };
189
190 enum rtw89_mac_wow_fw_status {
191 WOWLAN_NOT_READY = 0x00,
192 WOWLAN_SLEEP_READY = 0x01,
193 WOWLAN_RESUME_READY = 0x02,
194 };
195
196 #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32)
197
198 enum rtw89_mac_dbg_port_sel {
199 /* CMAC 0 related */
200 RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
201 RTW89_DBG_PORT_SEL_SCH_C0,
202 RTW89_DBG_PORT_SEL_TMAC_C0,
203 RTW89_DBG_PORT_SEL_RMAC_C0,
204 RTW89_DBG_PORT_SEL_RMACST_C0,
205 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0,
206 RTW89_DBG_PORT_SEL_TRXPTCL_C0,
207 RTW89_DBG_PORT_SEL_TX_INFOL_C0,
208 RTW89_DBG_PORT_SEL_TX_INFOH_C0,
209 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0,
210 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0,
211 /* CMAC 1 related */
212 RTW89_DBG_PORT_SEL_PTCL_C1,
213 RTW89_DBG_PORT_SEL_SCH_C1,
214 RTW89_DBG_PORT_SEL_TMAC_C1,
215 RTW89_DBG_PORT_SEL_RMAC_C1,
216 RTW89_DBG_PORT_SEL_RMACST_C1,
217 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1,
218 RTW89_DBG_PORT_SEL_TRXPTCL_C1,
219 RTW89_DBG_PORT_SEL_TX_INFOL_C1,
220 RTW89_DBG_PORT_SEL_TX_INFOH_C1,
221 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1,
222 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1,
223 /* DLE related */
224 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG,
225 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA,
226 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT,
227 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO,
228 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT,
229 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT,
230 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL,
231 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY,
232 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG,
233 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA,
234 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT,
235 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO,
236 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT,
237 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT,
238 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL,
239 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY,
240 RTW89_DBG_PORT_SEL_PKTINFO,
241 /* DISPATCHER related */
242 RTW89_DBG_PORT_SEL_DSPT_HDT_TX0,
243 RTW89_DBG_PORT_SEL_DSPT_HDT_TX1,
244 RTW89_DBG_PORT_SEL_DSPT_HDT_TX2,
245 RTW89_DBG_PORT_SEL_DSPT_HDT_TX3,
246 RTW89_DBG_PORT_SEL_DSPT_HDT_TX4,
247 RTW89_DBG_PORT_SEL_DSPT_HDT_TX5,
248 RTW89_DBG_PORT_SEL_DSPT_HDT_TX6,
249 RTW89_DBG_PORT_SEL_DSPT_HDT_TX7,
250 RTW89_DBG_PORT_SEL_DSPT_HDT_TX8,
251 RTW89_DBG_PORT_SEL_DSPT_HDT_TX9,
252 RTW89_DBG_PORT_SEL_DSPT_HDT_TXA,
253 RTW89_DBG_PORT_SEL_DSPT_HDT_TXB,
254 RTW89_DBG_PORT_SEL_DSPT_HDT_TXC,
255 RTW89_DBG_PORT_SEL_DSPT_HDT_TXD,
256 RTW89_DBG_PORT_SEL_DSPT_HDT_TXE,
257 RTW89_DBG_PORT_SEL_DSPT_HDT_TXF,
258 RTW89_DBG_PORT_SEL_DSPT_CDT_TX0,
259 RTW89_DBG_PORT_SEL_DSPT_CDT_TX1,
260 RTW89_DBG_PORT_SEL_DSPT_CDT_TX3,
261 RTW89_DBG_PORT_SEL_DSPT_CDT_TX4,
262 RTW89_DBG_PORT_SEL_DSPT_CDT_TX5,
263 RTW89_DBG_PORT_SEL_DSPT_CDT_TX6,
264 RTW89_DBG_PORT_SEL_DSPT_CDT_TX7,
265 RTW89_DBG_PORT_SEL_DSPT_CDT_TX8,
266 RTW89_DBG_PORT_SEL_DSPT_CDT_TX9,
267 RTW89_DBG_PORT_SEL_DSPT_CDT_TXA,
268 RTW89_DBG_PORT_SEL_DSPT_CDT_TXB,
269 RTW89_DBG_PORT_SEL_DSPT_CDT_TXC,
270 RTW89_DBG_PORT_SEL_DSPT_HDT_RX0,
271 RTW89_DBG_PORT_SEL_DSPT_HDT_RX1,
272 RTW89_DBG_PORT_SEL_DSPT_HDT_RX2,
273 RTW89_DBG_PORT_SEL_DSPT_HDT_RX3,
274 RTW89_DBG_PORT_SEL_DSPT_HDT_RX4,
275 RTW89_DBG_PORT_SEL_DSPT_HDT_RX5,
276 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0,
277 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0,
278 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1,
279 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2,
280 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1,
281 RTW89_DBG_PORT_SEL_DSPT_STF_CTRL,
282 RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL,
283 RTW89_DBG_PORT_SEL_DSPT_WDE_INTF,
284 RTW89_DBG_PORT_SEL_DSPT_PLE_INTF,
285 RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL,
286 /* PCIE related */
287 RTW89_DBG_PORT_SEL_PCIE_TXDMA,
288 RTW89_DBG_PORT_SEL_PCIE_RXDMA,
289 RTW89_DBG_PORT_SEL_PCIE_CVT,
290 RTW89_DBG_PORT_SEL_PCIE_CXPL,
291 RTW89_DBG_PORT_SEL_PCIE_IO,
292 RTW89_DBG_PORT_SEL_PCIE_MISC,
293 RTW89_DBG_PORT_SEL_PCIE_MISC2,
294
295 /* keep last */
296 RTW89_DBG_PORT_SEL_LAST,
297 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST,
298 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST,
299 };
300
301 /* SRAM mem dump */
302 #define R_AX_INDIR_ACCESS_ENTRY 0x40000
303 #define R_BE_INDIR_ACCESS_ENTRY 0x80000
304
305 #define AXIDMA_BASE_ADDR 0x18006000
306 #define STA_SCHED_BASE_ADDR 0x18808000
307 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000
308 #define SECURITY_CAM_BASE_ADDR 0x18814000
309 #define WOW_CAM_BASE_ADDR 0x18815000
310 #define CMAC_TBL_BASE_ADDR 0x18840000
311 #define ADDR_CAM_BASE_ADDR 0x18850000
312 #define BSSID_CAM_BASE_ADDR 0x18853000
313 #define BA_CAM_BASE_ADDR 0x18854000
314 #define BCN_IE_CAM0_BASE_ADDR 0x18855000
315 #define SHARED_BUF_BASE_ADDR 0x18700000
316 #define DMAC_TBL_BASE_ADDR 0x18800000
317 #define SHCUT_MACHDR_BASE_ADDR 0x18800800
318 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000
319 #define TXD_FIFO_0_BASE_ADDR 0x18856200
320 #define TXD_FIFO_1_BASE_ADDR 0x188A1080
321 #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */
322 #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */
323 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000
324 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
325 #define CPU_LOCAL_BASE_ADDR 0x18003000
326
327 #define WD_PAGE_BASE_ADDR_BE 0x0
328 #define CPU_LOCAL_BASE_ADDR_BE 0x18003000
329 #define AXIDMA_BASE_ADDR_BE 0x18006000
330 #define SHARED_BUF_BASE_ADDR_BE 0x18700000
331 #define DMAC_TBL_BASE_ADDR_BE 0x18800000
332 #define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800
333 #define STA_SCHED_BASE_ADDR_BE 0x18818000
334 #define NAT25_CAM_BASE_ADDR_BE 0x18820000
335 #define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000
336 #define SEC_CAM_BASE_ADDR_BE 0x18824000
337 #define SEC_CAM_BASE_ADDR_BE_8922D 0x1882C000
338 #define WOW_CAM_BASE_ADDR_BE 0x18828000
339 #define MLD_TBL_BASE_ADDR_BE 0x18829000
340 #define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000
341 #define CMAC_TBL_BASE_ADDR_BE 0x18840000
342 #define ADDR_CAM_BASE_ADDR_BE 0x18850000
343 #define BSSID_CAM_BASE_ADDR_BE 0x18858000
344 #define BA_CAM_BASE_ADDR_BE 0x18859000
345 #define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000
346 #define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000
347 #define TXD_FIFO_0_BASE_ADDR_BE 0x18862000
348 #define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000
349 #define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000
350 #define TXD_FIFO_1_BASE_ADDR_BE 0x18881800
351 #define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000
352
353 #define CCTL_INFO_SIZE 32
354
355 enum rtw89_mac_mem_sel {
356 RTW89_MAC_MEM_AXIDMA,
357 RTW89_MAC_MEM_SHARED_BUF,
358 RTW89_MAC_MEM_DMAC_TBL,
359 RTW89_MAC_MEM_SHCUT_MACHDR,
360 RTW89_MAC_MEM_STA_SCHED,
361 RTW89_MAC_MEM_RXPLD_FLTR_CAM,
362 RTW89_MAC_MEM_SECURITY_CAM,
363 RTW89_MAC_MEM_WOW_CAM,
364 RTW89_MAC_MEM_CMAC_TBL,
365 RTW89_MAC_MEM_ADDR_CAM,
366 RTW89_MAC_MEM_BA_CAM,
367 RTW89_MAC_MEM_BCN_IE_CAM0,
368 RTW89_MAC_MEM_BCN_IE_CAM1,
369 RTW89_MAC_MEM_TXD_FIFO_0,
370 RTW89_MAC_MEM_TXD_FIFO_1,
371 RTW89_MAC_MEM_TXDATA_FIFO_0,
372 RTW89_MAC_MEM_TXDATA_FIFO_1,
373 RTW89_MAC_MEM_CPU_LOCAL,
374 RTW89_MAC_MEM_BSSID_CAM,
375 RTW89_MAC_MEM_TXD_FIFO_0_V1,
376 RTW89_MAC_MEM_TXD_FIFO_1_V1,
377 RTW89_MAC_MEM_WD_PAGE,
378 RTW89_MAC_MEM_MLD_TBL,
379
380 /* keep last */
381 RTW89_MAC_MEM_NUM,
382 };
383
384 enum rtw89_rpwm_req_pwr_state {
385 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0,
386 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1,
387 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2,
388 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3,
389 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4,
390 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5,
391 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6,
392 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7,
393 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX,
394 };
395
396 struct rtw89_pwr_cfg {
397 u16 addr;
398 u8 cv_msk;
399 u8 intf_msk;
400 u8 base:4;
401 u8 cmd:4;
402 u8 msk;
403 u8 val;
404 };
405
406 enum rtw89_mac_c2h_ofld_func {
407 RTW89_MAC_C2H_FUNC_EFUSE_DUMP,
408 RTW89_MAC_C2H_FUNC_READ_RSP,
409 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP,
410 RTW89_MAC_C2H_FUNC_BCN_RESEND,
411 RTW89_MAC_C2H_FUNC_MACID_PAUSE,
412 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6,
413 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9,
414 RTW89_MAC_C2H_FUNC_TX_DUTY_RPT = 0xa,
415 RTW89_MAC_C2H_FUNC_BCNFLTR_RPT = 0xd,
416 RTW89_MAC_C2H_FUNC_OFLD_MAX,
417 };
418
419 enum rtw89_mac_c2h_info_func {
420 RTW89_MAC_C2H_FUNC_REC_ACK,
421 RTW89_MAC_C2H_FUNC_DONE_ACK,
422 RTW89_MAC_C2H_FUNC_C2H_LOG,
423 RTW89_MAC_C2H_FUNC_BCN_CNT,
424 RTW89_MAC_C2H_FUNC_BCN_UPD_DONE = 0x06,
425 RTW89_MAC_C2H_FUNC_INFO_MAX,
426 };
427
428 enum rtw89_mac_c2h_mcc_func {
429 RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0,
430 RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1,
431 RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2,
432 RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3,
433
434 NUM_OF_RTW89_MAC_C2H_FUNC_MCC,
435 };
436
437 enum rtw89_mac_c2h_misc_func {
438 RTW89_MAC_C2H_FUNC_TX_REPORT = 1,
439
440 NUM_OF_RTW89_MAC_C2H_FUNC_MISC,
441 };
442
443 enum rtw89_mac_c2h_mlo_func {
444 RTW89_MAC_C2H_FUNC_MLO_GET_TBL = 0x0,
445 RTW89_MAC_C2H_FUNC_MLO_EMLSR_TRANS_DONE = 0x1,
446 RTW89_MAC_C2H_FUNC_MLO_EMLSR_STA_CFG_DONE = 0x2,
447 RTW89_MAC_C2H_FUNC_MCMLO_RELINK_RPT = 0x3,
448 RTW89_MAC_C2H_FUNC_MCMLO_SN_SYNC_RPT = 0x4,
449 RTW89_MAC_C2H_FUNC_MLO_LINK_CFG_STAT = 0x5,
450 RTW89_MAC_C2H_FUNC_MLO_DM_DBG_DUMP = 0x6,
451
452 NUM_OF_RTW89_MAC_C2H_FUNC_MLO,
453 };
454
455 enum rtw89_mac_c2h_mrc_func {
456 RTW89_MAC_C2H_FUNC_MRC_TSF_RPT = 0,
457 RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT = 1,
458
459 NUM_OF_RTW89_MAC_C2H_FUNC_MRC,
460 };
461
462 enum rtw89_mac_c2h_wow_func {
463 RTW89_MAC_C2H_FUNC_AOAC_REPORT,
464
465 NUM_OF_RTW89_MAC_C2H_FUNC_WOW,
466 };
467
468 enum rtw89_mac_c2h_ap_func {
469 RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY = 0,
470
471 NUM_OF_RTW89_MAC_C2H_FUNC_AP,
472 };
473
474 enum rtw89_mac_c2h_class {
475 RTW89_MAC_C2H_CLASS_INFO = 0x0,
476 RTW89_MAC_C2H_CLASS_OFLD = 0x1,
477 RTW89_MAC_C2H_CLASS_TWT = 0x2,
478 RTW89_MAC_C2H_CLASS_WOW = 0x3,
479 RTW89_MAC_C2H_CLASS_MCC = 0x4,
480 RTW89_MAC_C2H_CLASS_FWDBG = 0x5,
481 RTW89_MAC_C2H_CLASS_MISC = 0x9,
482 RTW89_MAC_C2H_CLASS_MLO = 0xc,
483 RTW89_MAC_C2H_CLASS_MRC = 0xe,
484 RTW89_MAC_C2H_CLASS_AP = 0x18,
485 RTW89_MAC_C2H_CLASS_ROLE = 0x1b,
486 RTW89_MAC_C2H_CLASS_MAX,
487 };
488
489 enum rtw89_mac_mcc_status {
490 RTW89_MAC_MCC_ADD_ROLE_OK = 0,
491 RTW89_MAC_MCC_START_GROUP_OK = 1,
492 RTW89_MAC_MCC_STOP_GROUP_OK = 2,
493 RTW89_MAC_MCC_DEL_GROUP_OK = 3,
494 RTW89_MAC_MCC_RESET_GROUP_OK = 4,
495 RTW89_MAC_MCC_SWITCH_CH_OK = 5,
496 RTW89_MAC_MCC_TXNULL0_OK = 6,
497 RTW89_MAC_MCC_TXNULL1_OK = 7,
498
499 RTW89_MAC_MCC_SWITCH_EARLY = 10,
500 RTW89_MAC_MCC_TBTT = 11,
501 RTW89_MAC_MCC_DURATION_START = 12,
502 RTW89_MAC_MCC_DURATION_END = 13,
503
504 RTW89_MAC_MCC_ADD_ROLE_FAIL = 20,
505 RTW89_MAC_MCC_START_GROUP_FAIL = 21,
506 RTW89_MAC_MCC_STOP_GROUP_FAIL = 22,
507 RTW89_MAC_MCC_DEL_GROUP_FAIL = 23,
508 RTW89_MAC_MCC_RESET_GROUP_FAIL = 24,
509 RTW89_MAC_MCC_SWITCH_CH_FAIL = 25,
510 RTW89_MAC_MCC_TXNULL0_FAIL = 26,
511 RTW89_MAC_MCC_TXNULL1_FAIL = 27,
512 };
513
514 enum rtw89_mac_mrc_status {
515 RTW89_MAC_MRC_START_SCH_OK = 0,
516 RTW89_MAC_MRC_STOP_SCH_OK = 1,
517 RTW89_MAC_MRC_DEL_SCH_OK = 2,
518 RTW89_MAC_MRC_EMPTY_SCH_FAIL = 16,
519 RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL = 17,
520 RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL = 18,
521 RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL = 19,
522 RTW89_MAC_MRC_ALT_ROLE_FAIL = 20,
523 RTW89_MAC_MRC_ADD_PSTIMER_FAIL = 21,
524 RTW89_MAC_MRC_MALLOC_FAIL = 22,
525 RTW89_MAC_MRC_SWITCH_CH_FAIL = 23,
526 RTW89_MAC_MRC_TXNULL0_FAIL = 24,
527 RTW89_MAC_MRC_PORT_FUNC_EN_FAIL = 25,
528 };
529
530 struct rtw89_mac_ax_coex {
531 #define RTW89_MAC_AX_COEX_RTK_MODE 0
532 #define RTW89_MAC_AX_COEX_CSR_MODE 1
533 u8 pta_mode;
534 #define RTW89_MAC_AX_COEX_INNER 0
535 #define RTW89_MAC_AX_COEX_OUTPUT 1
536 #define RTW89_MAC_AX_COEX_INPUT 2
537 u8 direction;
538 };
539
540 struct rtw89_mac_ax_plt {
541 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0)
542 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1)
543 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2)
544 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3)
545 u8 band;
546 u8 tx;
547 u8 rx;
548 };
549
550 enum rtw89_mac_bf_rrsc_rate {
551 RTW89_MAC_BF_RRSC_6M = 0,
552 RTW89_MAC_BF_RRSC_9M = 1,
553 RTW89_MAC_BF_RRSC_12M,
554 RTW89_MAC_BF_RRSC_18M,
555 RTW89_MAC_BF_RRSC_24M,
556 RTW89_MAC_BF_RRSC_36M,
557 RTW89_MAC_BF_RRSC_48M,
558 RTW89_MAC_BF_RRSC_54M,
559 RTW89_MAC_BF_RRSC_HT_MSC0,
560 RTW89_MAC_BF_RRSC_HT_MSC1,
561 RTW89_MAC_BF_RRSC_HT_MSC2,
562 RTW89_MAC_BF_RRSC_HT_MSC3,
563 RTW89_MAC_BF_RRSC_HT_MSC4,
564 RTW89_MAC_BF_RRSC_HT_MSC5,
565 RTW89_MAC_BF_RRSC_HT_MSC6,
566 RTW89_MAC_BF_RRSC_HT_MSC7,
567 RTW89_MAC_BF_RRSC_VHT_MSC0,
568 RTW89_MAC_BF_RRSC_VHT_MSC1,
569 RTW89_MAC_BF_RRSC_VHT_MSC2,
570 RTW89_MAC_BF_RRSC_VHT_MSC3,
571 RTW89_MAC_BF_RRSC_VHT_MSC4,
572 RTW89_MAC_BF_RRSC_VHT_MSC5,
573 RTW89_MAC_BF_RRSC_VHT_MSC6,
574 RTW89_MAC_BF_RRSC_VHT_MSC7,
575 RTW89_MAC_BF_RRSC_HE_MSC0,
576 RTW89_MAC_BF_RRSC_HE_MSC1,
577 RTW89_MAC_BF_RRSC_HE_MSC2,
578 RTW89_MAC_BF_RRSC_HE_MSC3,
579 RTW89_MAC_BF_RRSC_HE_MSC4,
580 RTW89_MAC_BF_RRSC_HE_MSC5,
581 RTW89_MAC_BF_RRSC_HE_MSC6,
582 RTW89_MAC_BF_RRSC_HE_MSC7 = 31,
583 RTW89_MAC_BF_RRSC_MAX = 32
584 };
585
586 #define MAC_REG_POOL_COUNT 10
587 #define ACCESS_CMAC(_addr) \
588 ({typeof(_addr) __addr = (_addr); \
589 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; })
590 #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000
591 #define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000
592
593 #define PTCL_IDLE_POLL_CNT 10000
594 #define SW_CVR_DUR_US 8
595 #define SW_CVR_CNT 8
596
597 #define DLE_BOUND_UNIT (8 * 1024)
598 #define DLE_WAIT_CNT 2000
599 #define TRXCFG_WAIT_CNT 2000
600
601 #define RTW89_WDE_PG_64 64
602 #define RTW89_WDE_PG_128 128
603 #define RTW89_WDE_PG_256 256
604
605 #define S_AX_WDE_PAGE_SEL_64 0
606 #define S_AX_WDE_PAGE_SEL_128 1
607 #define S_AX_WDE_PAGE_SEL_256 2
608
609 #define RTW89_PLE_PG_64 64
610 #define RTW89_PLE_PG_128 128
611 #define RTW89_PLE_PG_256 256
612
613 #define S_AX_PLE_PAGE_SEL_64 0
614 #define S_AX_PLE_PAGE_SEL_128 1
615 #define S_AX_PLE_PAGE_SEL_256 2
616
617 #define B_CMAC0_MGQ_NORMAL BIT(2)
618 #define B_CMAC0_MGQ_NO_PWRSAV BIT(3)
619 #define B_CMAC0_CPUMGQ BIT(4)
620 #define B_CMAC1_MGQ_NORMAL BIT(10)
621 #define B_CMAC1_MGQ_NO_PWRSAV BIT(11)
622 #define B_CMAC1_CPUMGQ BIT(12)
623
624 #define B_CMAC0_MGQ_NORMAL_BE BIT(2)
625 #define B_CMAC1_MGQ_NORMAL_BE BIT(30)
626
627 #define QEMP_ACQ_GRP_MACID_NUM 8
628 #define QEMP_ACQ_GRP_QSEL_SH 4
629 #define QEMP_ACQ_GRP_QSEL_MASK 0xF
630
631 #define SDIO_LOCAL_BASE_ADDR 0x80000000
632
633 #define PWR_CMD_WRITE 0
634 #define PWR_CMD_POLL 1
635 #define PWR_CMD_DELAY 2
636 #define PWR_CMD_END 3
637
638 #define PWR_INTF_MSK_SDIO BIT(0)
639 #define PWR_INTF_MSK_USB BIT(1)
640 #define PWR_INTF_MSK_PCIE BIT(2)
641 #define PWR_INTF_MSK_ALL 0x7
642
643 #define PWR_BASE_MAC 0
644 #define PWR_BASE_USB 1
645 #define PWR_BASE_PCIE 2
646 #define PWR_BASE_SDIO 3
647
648 #define PWR_CV_MSK_A BIT(0)
649 #define PWR_CV_MSK_B BIT(1)
650 #define PWR_CV_MSK_C BIT(2)
651 #define PWR_CV_MSK_D BIT(3)
652 #define PWR_CV_MSK_E BIT(4)
653 #define PWR_CV_MSK_F BIT(5)
654 #define PWR_CV_MSK_G BIT(6)
655 #define PWR_CV_MSK_TEST BIT(7)
656 #define PWR_CV_MSK_ALL 0xFF
657
658 #define PWR_DELAY_US 0
659 #define PWR_DELAY_MS 1
660
661 /* STA scheduler */
662 #define SS_MACID_SH 8
663 #define SS_TX_LEN_MSK 0x1FFFFF
664 #define SS_CTRL1_R_TX_LEN 5
665 #define SS_CTRL1_R_NEXT_LINK 20
666 #define SS_LINK_SIZE 256
667
668 /* MAC debug port */
669 #define TMAC_DBG_SEL_C0 0xA5
670 #define RMAC_DBG_SEL_C0 0xA6
671 #define TRXPTCL_DBG_SEL_C0 0xA7
672 #define TMAC_DBG_SEL_C1 0xB5
673 #define RMAC_DBG_SEL_C1 0xB6
674 #define TRXPTCL_DBG_SEL_C1 0xB7
675 #define FW_PROG_CNTR_DBG_SEL 0xF2
676 #define PCIE_TXDMA_DBG_SEL 0x30
677 #define PCIE_RXDMA_DBG_SEL 0x31
678 #define PCIE_CVT_DBG_SEL 0x32
679 #define PCIE_CXPL_DBG_SEL 0x33
680 #define PCIE_IO_DBG_SEL 0x37
681 #define PCIE_MISC_DBG_SEL 0x38
682 #define PCIE_MISC2_DBG_SEL 0x00
683 #define MAC_DBG_SEL 1
684 #define RMAC_CMAC_DBG_SEL 1
685
686 /* TRXPTCL dbg port sel */
687 #define TRXPTRL_DBG_SEL_TMAC 0
688 #define TRXPTRL_DBG_SEL_RMAC 1
689
690 struct rtw89_cpuio_ctrl {
691 u16 pkt_num;
692 u16 start_pktid;
693 u16 end_pktid;
694 u8 cmd_type;
695 u8 macid;
696 u8 src_pid;
697 u8 src_qid;
698 u8 dst_pid;
699 u8 dst_qid;
700 u16 pktid;
701 };
702
703 struct rtw89_mac_dbg_port_info {
704 u32 sel_addr;
705 u8 sel_byte;
706 u32 sel_msk;
707 u32 srt;
708 u32 end;
709 u32 rd_addr;
710 u8 rd_byte;
711 u32 rd_msk;
712 };
713
714 #define QLNKTBL_ADDR_INFO_SEL BIT(0)
715 #define QLNKTBL_ADDR_INFO_SEL_0 0
716 #define QLNKTBL_ADDR_INFO_SEL_1 1
717 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1)
718 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0)
719
720 struct rtw89_mac_dle_dfi_ctrl {
721 enum rtw89_mac_dle_ctrl_type type;
722 u32 target;
723 u32 addr;
724 u32 out_data;
725 };
726
727 struct rtw89_mac_dle_dfi_quota {
728 enum rtw89_mac_dle_ctrl_type dle_type;
729 u32 qtaid;
730 u16 rsv_pgnum;
731 u16 use_pgnum;
732 };
733
734 struct rtw89_mac_dle_dfi_qempty {
735 enum rtw89_mac_dle_ctrl_type dle_type;
736 u32 grpsel;
737 u32 qempty;
738 };
739
740 enum rtw89_mac_dle_rsvd_qt_type {
741 DLE_RSVD_QT_MPDU_INFO,
742 DLE_RSVD_QT_B0_CSI,
743 DLE_RSVD_QT_B1_CSI,
744 DLE_RSVD_QT_B0_LMR,
745 DLE_RSVD_QT_B1_LMR,
746 DLE_RSVD_QT_B0_FTM,
747 DLE_RSVD_QT_B1_FTM,
748 };
749
750 struct rtw89_mac_dle_rsvd_qt_cfg {
751 u16 pktid;
752 u16 pg_num;
753 u32 size;
754 };
755
756 enum rtw89_mac_error_scenario {
757 RTW89_RXI300_ERROR = 1,
758 RTW89_WCPU_CPU_EXCEPTION = 2,
759 RTW89_WCPU_ASSERTION = 3,
760 };
761
762 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28)
763
764 /* Define DBG and recovery enum */
765 enum mac_ax_err_info {
766 /* Get error info */
767
768 /* L0 */
769 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,
770 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,
771 MAC_AX_ERR_L0_RESET_DONE = 0x0003,
772 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
773
774 /* L1 */
775 MAC_AX_ERR_L1_PREERR_DMAC = 0x999,
776 MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
777 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
778 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
779 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,
780 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,
781
782 /* L2 */
783 /* address hole (master) */
784 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,
785 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,
786 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,
787 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,
788 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,
789 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,
790 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,
791 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,
792
793 /* AHB bridge timeout (master) */
794 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,
795 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,
796 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,
797 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,
798 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,
799 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,
800 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,
801 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,
802
803 /* APB_SA bridge timeout (master + slave) */
804 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,
805 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,
806 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,
807 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,
808 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,
809 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,
810 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,
811 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,
812 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,
813 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,
814 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,
815 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,
816 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,
817 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,
818 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,
819 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,
820 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,
821 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,
822 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,
823 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,
824 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,
825 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,
826 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,
827 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,
828 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,
829 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,
830 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,
831 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,
832 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,
833 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,
834 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,
835 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,
836 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,
837 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,
838 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,
839 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,
840 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,
841 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,
842 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,
843 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,
844 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,
845 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,
846 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,
847 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,
848 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,
849 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,
850 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,
851 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,
852 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,
853 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,
854 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,
855 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,
856 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,
857 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,
858 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,
859 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,
860 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,
861 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,
862 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,
863 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,
864 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,
865 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,
866 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,
867 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,
868 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,
869 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,
870 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,
871 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,
872 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,
873 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,
874 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,
875 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,
876 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,
877 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,
878 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,
879 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,
880 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,
881 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,
882 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,
883 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,
884 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,
885 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,
886 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,
887 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,
888 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,
889 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,
890 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,
891
892 /* APB_BBRF bridge timeout (master) */
893 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,
894 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,
895 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,
896 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,
897 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,
898 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,
899 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
900 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
901 MAC_AX_ERR_L2_RESET_DONE = 0x2400,
902 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599,
903 MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
904 MAC_AX_ERR_ASSERTION = 0x4000,
905 MAC_AX_ERR_RXI300 = 0x5000,
906 MAC_AX_GET_ERR_MAX,
907 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,
908
909 /* set error info */
910 MAC_AX_ERR_L1_DISABLE_EN = 0x0001,
911 MAC_AX_ERR_L1_RCVY_EN = 0x0002,
912 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
913 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
914 MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A,
915 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
916 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
917 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
918 MAC_AX_ERR_L0_RCVY_EN = 0x0013,
919 MAC_AX_ERR_L0_RESET_FORCE = 0x0020,
920 MAC_AX_ERR_L0_RESET_FORCE_C1 = 0x0021,
921 MAC_AX_ERR_L1_RESET_FORCE = 0x0022,
922 MAC_AX_SET_ERR_MAX,
923 };
924
925 struct rtw89_mac_size_set {
926 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie;
927 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c0;
928 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c2;
929 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c3;
930 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c5;
931 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c6;
932 const struct rtw89_dle_size wde_size0;
933 const struct rtw89_dle_size wde_size1;
934 const struct rtw89_dle_size wde_size0_v1;
935 const struct rtw89_dle_size wde_size3_v1;
936 const struct rtw89_dle_size wde_size4;
937 const struct rtw89_dle_size wde_size4_v1;
938 const struct rtw89_dle_size wde_size5_v1;
939 const struct rtw89_dle_size wde_size6;
940 const struct rtw89_dle_size wde_size7;
941 const struct rtw89_dle_size wde_size7_v1;
942 const struct rtw89_dle_size wde_size8_v1;
943 const struct rtw89_dle_size wde_size9;
944 const struct rtw89_dle_size wde_size16_v1;
945 const struct rtw89_dle_size wde_size17;
946 const struct rtw89_dle_size wde_size18;
947 const struct rtw89_dle_size wde_size18_v1;
948 const struct rtw89_dle_size wde_size19;
949 const struct rtw89_dle_size wde_size22_v1;
950 const struct rtw89_dle_size wde_size23;
951 const struct rtw89_dle_size wde_size30;
952 const struct rtw89_dle_size wde_size31;
953 const struct rtw89_dle_size ple_size0;
954 const struct rtw89_dle_size ple_size1;
955 const struct rtw89_dle_size ple_size0_v1;
956 const struct rtw89_dle_size ple_size3_v1;
957 const struct rtw89_dle_size ple_size4_v1;
958 const struct rtw89_dle_size ple_size4;
959 const struct rtw89_dle_size ple_size6;
960 const struct rtw89_dle_size ple_size6_v1;
961 const struct rtw89_dle_size ple_size7_v1;
962 const struct rtw89_dle_size ple_size8;
963 const struct rtw89_dle_size ple_size9;
964 const struct rtw89_dle_size ple_size17;
965 const struct rtw89_dle_size ple_size18;
966 const struct rtw89_dle_size ple_size19;
967 const struct rtw89_dle_size ple_size20_v1;
968 const struct rtw89_dle_size ple_size22_v1;
969 const struct rtw89_dle_size ple_size27;
970 const struct rtw89_dle_size ple_size29_v1;
971 const struct rtw89_dle_size ple_size31;
972 const struct rtw89_dle_size ple_size34;
973 const struct rtw89_wde_quota wde_qt0;
974 const struct rtw89_wde_quota wde_qt1;
975 const struct rtw89_wde_quota wde_qt0_v1;
976 const struct rtw89_wde_quota wde_qt3;
977 const struct rtw89_wde_quota wde_qt4;
978 const struct rtw89_wde_quota wde_qt4_v1;
979 const struct rtw89_wde_quota wde_qt5_v1;
980 const struct rtw89_wde_quota wde_qt6;
981 const struct rtw89_wde_quota wde_qt7;
982 const struct rtw89_wde_quota wde_qt7_v1;
983 const struct rtw89_wde_quota wde_qt8_v1;
984 const struct rtw89_wde_quota wde_qt16;
985 const struct rtw89_wde_quota wde_qt17;
986 const struct rtw89_wde_quota wde_qt18;
987 const struct rtw89_wde_quota wde_qt19_v1;
988 const struct rtw89_wde_quota wde_qt23;
989 const struct rtw89_wde_quota wde_qt23_v1;
990 const struct rtw89_wde_quota wde_qt30;
991 const struct rtw89_wde_quota wde_qt31;
992 const struct rtw89_ple_quota ple_qt0;
993 const struct rtw89_ple_quota ple_qt1;
994 const struct rtw89_ple_quota ple_qt4;
995 const struct rtw89_ple_quota ple_qt5;
996 const struct rtw89_ple_quota ple_qt5_v2;
997 const struct rtw89_ple_quota ple_qt6_v1;
998 const struct rtw89_ple_quota ple_qt7_v1;
999 const struct rtw89_ple_quota ple_qt8_v1;
1000 const struct rtw89_ple_quota ple_qt9;
1001 const struct rtw89_ple_quota ple_qt9_v1;
1002 const struct rtw89_ple_quota ple_qt12_v1;
1003 const struct rtw89_ple_quota ple_qt13;
1004 const struct rtw89_ple_quota ple_qt13_v1;
1005 const struct rtw89_ple_quota ple_qt14_v1;
1006 const struct rtw89_ple_quota ple_qt15_v1;
1007 const struct rtw89_ple_quota ple_qt18;
1008 const struct rtw89_ple_quota ple_qt25;
1009 const struct rtw89_ple_quota ple_qt26;
1010 const struct rtw89_ple_quota ple_qt27;
1011 const struct rtw89_ple_quota ple_qt28;
1012 const struct rtw89_ple_quota ple_qt42;
1013 const struct rtw89_ple_quota ple_qt43;
1014 const struct rtw89_ple_quota ple_qt44;
1015 const struct rtw89_ple_quota ple_qt44_v2;
1016 const struct rtw89_ple_quota ple_qt45;
1017 const struct rtw89_ple_quota ple_qt45_v2;
1018 const struct rtw89_ple_quota ple_qt46;
1019 const struct rtw89_ple_quota ple_qt47;
1020 const struct rtw89_ple_quota ple_qt47_v2;
1021 const struct rtw89_ple_quota ple_qt57;
1022 const struct rtw89_ple_quota ple_qt58;
1023 const struct rtw89_ple_quota ple_qt59;
1024 const struct rtw89_ple_quota ple_qt61;
1025 const struct rtw89_ple_quota ple_qt62;
1026 const struct rtw89_ple_quota ple_qt64_v2;
1027 const struct rtw89_ple_quota ple_qt65_v2;
1028 const struct rtw89_ple_quota ple_qt78;
1029 const struct rtw89_ple_quota ple_qt79;
1030 const struct rtw89_ple_quota ple_qt_52a_wow;
1031 const struct rtw89_ple_quota ple_qt_52b_wow;
1032 const struct rtw89_ple_quota ple_qt_52bt_wow;
1033 const struct rtw89_ple_quota ple_qt_51b_wow;
1034 const struct rtw89_rsvd_quota ple_rsvd_qt0;
1035 const struct rtw89_rsvd_quota ple_rsvd_qt1;
1036 const struct rtw89_rsvd_quota ple_rsvd_qt1_v1;
1037 const struct rtw89_rsvd_quota ple_rsvd_qt2;
1038 const struct rtw89_rsvd_quota ple_rsvd_qt9;
1039 const struct rtw89_dle_rsvd_size rsvd0_size0;
1040 const struct rtw89_dle_rsvd_size rsvd0_size3;
1041 const struct rtw89_dle_rsvd_size rsvd0_size5;
1042 const struct rtw89_dle_rsvd_size rsvd0_size6;
1043 const struct rtw89_dle_rsvd_size rsvd0_size17;
1044 const struct rtw89_dle_rsvd_size rsvd1_size0;
1045 const struct rtw89_dle_rsvd_size rsvd1_size2;
1046 const struct rtw89_dle_rsvd_size rsvd1_size3;
1047 const struct rtw89_dle_input dle_input3;
1048 const struct rtw89_dle_input dle_input20;
1049 const struct rtw89_dle_input dle_input28;
1050 };
1051
1052 extern const struct rtw89_mac_size_set rtw89_mac_size;
1053
1054 struct rtw89_mac_mu_gid_addr {
1055 u32 position_en[2];
1056 u32 position[4];
1057 };
1058
1059 struct rtw89_mac_gen_def {
1060 u32 band1_offset;
1061 u32 filter_model_addr;
1062 u32 indir_access_addr;
1063 const u32 *mem_base_addrs;
1064 u32 mem_page_size;
1065 u32 rx_fltr;
1066 u32 default_rx_fltr;
1067 const struct rtw89_port_reg *port_base;
1068 u32 agg_len_ht;
1069 u32 ps_status;
1070 const struct rtw89_mac_mu_gid_addr *mu_gid;
1071 u32 boot_dbg;
1072
1073 struct rtw89_reg_def muedca_ctrl;
1074 struct rtw89_reg_def bfee_ctrl;
1075 struct rtw89_reg_def narrow_bw_ru_dis;
1076 struct rtw89_reg_def wow_ctrl;
1077 struct rtw89_reg_def agg_limit;
1078 struct rtw89_reg_def ra_agg_limit;
1079 struct rtw89_reg_def txcnt_limit;
1080
1081 int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band,
1082 enum rtw89_mac_hwmod_sel sel);
1083 int (*sys_init)(struct rtw89_dev *rtwdev);
1084 int (*trx_init)(struct rtw89_dev *rtwdev);
1085 int (*preload_init)(struct rtw89_dev *rtwdev, u8 mac_idx,
1086 enum rtw89_qta_mode mode);
1087 void (*clr_aon_intr)(struct rtw89_dev *rtwdev);
1088 void (*err_imr_ctrl)(struct rtw89_dev *rtwdev, bool en);
1089 int (*mac_func_en)(struct rtw89_dev *rtwdev);
1090 void (*hci_func_en)(struct rtw89_dev *rtwdev);
1091 void (*dmac_func_pre_en)(struct rtw89_dev *rtwdev);
1092 void (*dle_func_en)(struct rtw89_dev *rtwdev, bool enable);
1093 void (*dle_clk_en)(struct rtw89_dev *rtwdev, bool enable);
1094 void (*bf_assoc)(struct rtw89_dev *rtwdev,
1095 struct rtw89_vif_link *rtwvif_link,
1096 struct rtw89_sta_link *rtwsta_link);
1097
1098 int (*typ_fltr_opt)(struct rtw89_dev *rtwdev,
1099 enum rtw89_machdr_frame_type type,
1100 enum rtw89_mac_fwd_target fwd_target,
1101 u8 mac_idx);
1102 int (*cfg_ppdu_status)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
1103 void (*cfg_phy_rpt)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
1104 void (*set_edcca_mode)(struct rtw89_dev *rtwdev, u8 mac_idx, bool normal);
1105 void (*set_vcore_cfg)(struct rtw89_dev *rtwdev, u8 vlv);
1106
1107 int (*dle_mix_cfg)(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg);
1108 int (*chk_dle_rdy)(struct rtw89_dev *rtwdev, bool wde_or_ple);
1109 int (*dle_buf_req)(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id);
1110 void (*hfc_func_en)(struct rtw89_dev *rtwdev, bool en, bool h2c_en);
1111 void (*hfc_h2c_cfg)(struct rtw89_dev *rtwdev);
1112 void (*hfc_mix_cfg)(struct rtw89_dev *rtwdev);
1113 void (*hfc_get_mix_info)(struct rtw89_dev *rtwdev);
1114 void (*wde_quota_cfg)(struct rtw89_dev *rtwdev,
1115 const struct rtw89_wde_quota *min_cfg,
1116 const struct rtw89_wde_quota *max_cfg,
1117 u16 ext_wde_min_qt_wcpu);
1118 void (*ple_quota_cfg)(struct rtw89_dev *rtwdev,
1119 const struct rtw89_ple_quota *min_cfg,
1120 const struct rtw89_ple_quota *max_cfg);
1121 int (*set_cpuio)(struct rtw89_dev *rtwdev,
1122 struct rtw89_cpuio_ctrl *ctrl_para, bool wd);
1123 int (*dle_quota_change)(struct rtw89_dev *rtwdev, bool band1_en);
1124
1125 int (*reset_pwr_state)(struct rtw89_dev *rtwdev);
1126 void (*disable_cpu)(struct rtw89_dev *rtwdev);
1127 void (*fwdl_preconfig)(struct rtw89_dev *rtwdev);
1128 int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason,
1129 bool dlfw, bool include_bb);
1130 u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
1131 int (*fwdl_check_path_ready)(struct rtw89_dev *rtwdev, bool h2c_or_fwdl);
1132 void (*fwdl_secure_idmem_share_mode)(struct rtw89_dev *rtwdev, u8 mode);
1133 int (*parse_efuse_map)(struct rtw89_dev *rtwdev);
1134 int (*parse_phycap_map)(struct rtw89_dev *rtwdev);
1135 int (*cnv_efuse_state)(struct rtw89_dev *rtwdev, bool idle);
1136 int (*efuse_read_fw_secure)(struct rtw89_dev *rtwdev);
1137 int (*efuse_read_ecv)(struct rtw89_dev *rtwdev);
1138 int (*efuse_read_thermal_k)(struct rtw89_dev *rtwdev);
1139 int (*efuse_read_pwr_data)(struct rtw89_dev *rtwdev);
1140
1141 int (*cfg_plt)(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt);
1142 u16 (*get_plt_cnt)(struct rtw89_dev *rtwdev, u8 band);
1143
1144 bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev,
1145 enum rtw89_phy_idx phy_idx,
1146 u32 reg_base, u32 *cr);
1147
1148 int (*write_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask);
1149 int (*read_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 *val);
1150
1151 void (*dump_qta_lost)(struct rtw89_dev *rtwdev);
1152 void (*dump_err_status)(struct rtw89_dev *rtwdev,
1153 enum mac_ax_err_info err);
1154
1155 bool (*is_txq_empty)(struct rtw89_dev *rtwdev);
1156
1157 int (*prep_chan_list)(struct rtw89_dev *rtwdev,
1158 struct rtw89_vif_link *rtwvif_link);
1159 void (*free_chan_list)(struct rtw89_dev *rtwdev);
1160 int (*add_chan_list)(struct rtw89_dev *rtwdev,
1161 struct rtw89_vif_link *rtwvif_link);
1162 int (*add_chan_list_pno)(struct rtw89_dev *rtwdev,
1163 struct rtw89_vif_link *rtwvif_link);
1164 int (*scan_offload)(struct rtw89_dev *rtwdev,
1165 struct rtw89_scan_option *option,
1166 struct rtw89_vif_link *rtwvif_link,
1167 bool wowlan);
1168
1169 int (*wow_config_mac)(struct rtw89_dev *rtwdev, bool enable_wow);
1170 };
1171
1172 extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax;
1173 extern const struct rtw89_mac_gen_def rtw89_mac_gen_be;
1174
1175 static inline
rtw89_mac_mem_base_addrs(struct rtw89_dev * rtwdev,u8 sel)1176 u32 rtw89_mac_mem_base_addrs(struct rtw89_dev *rtwdev, u8 sel)
1177 {
1178 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1179
1180 if (rtwdev->chip->chip_id == RTL8922D &&
1181 sel == RTW89_MAC_MEM_SECURITY_CAM)
1182 return SEC_CAM_BASE_ADDR_BE_8922D;
1183
1184 return mac->mem_base_addrs[sel];
1185 }
1186
1187 static inline
rtw89_mac_reg_by_idx(struct rtw89_dev * rtwdev,u32 reg_base,u8 band)1188 u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band)
1189 {
1190 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1191
1192 return band == 0 ? reg_base : (reg_base + mac->band1_offset);
1193 }
1194
1195 static inline void
rtw89_write16_idx(struct rtw89_dev * rtwdev,u32 addr,u16 data,u8 band)1196 rtw89_write16_idx(struct rtw89_dev *rtwdev, u32 addr, u16 data, u8 band)
1197 {
1198 addr = rtw89_mac_reg_by_idx(rtwdev, addr, band);
1199
1200 rtw89_write16(rtwdev, addr, data);
1201 }
1202
1203 static inline void
rtw89_write32_idx(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data,u8 band)1204 rtw89_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data, u8 band)
1205 {
1206 addr = rtw89_mac_reg_by_idx(rtwdev, addr, band);
1207
1208 rtw89_write32_mask(rtwdev, addr, mask, data);
1209 }
1210
1211 static inline
rtw89_mac_reg_by_port(struct rtw89_dev * rtwdev,u32 base,u8 port,u8 mac_idx)1212 u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx)
1213 {
1214 return rtw89_mac_reg_by_idx(rtwdev, base + port * 0x40, mac_idx);
1215 }
1216
1217 static inline u32
rtw89_read32_port(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base)1218 rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, u32 base)
1219 {
1220 u32 reg;
1221
1222 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1223 rtwvif_link->mac_idx);
1224 return rtw89_read32(rtwdev, reg);
1225 }
1226
1227 static inline u32
rtw89_read32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 mask)1228 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1229 u32 base, u32 mask)
1230 {
1231 u32 reg;
1232
1233 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1234 rtwvif_link->mac_idx);
1235 return rtw89_read32_mask(rtwdev, reg, mask);
1236 }
1237
1238 static inline void
rtw89_write32_port(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 data)1239 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, u32 base,
1240 u32 data)
1241 {
1242 u32 reg;
1243
1244 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1245 rtwvif_link->mac_idx);
1246 rtw89_write32(rtwdev, reg, data);
1247 }
1248
1249 static inline void
rtw89_write32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 mask,u32 data)1250 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1251 u32 base, u32 mask, u32 data)
1252 {
1253 u32 reg;
1254
1255 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1256 rtwvif_link->mac_idx);
1257 rtw89_write32_mask(rtwdev, reg, mask, data);
1258 }
1259
1260 static inline void
rtw89_write16_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 mask,u16 data)1261 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1262 u32 base, u32 mask, u16 data)
1263 {
1264 u32 reg;
1265
1266 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1267 rtwvif_link->mac_idx);
1268 rtw89_write16_mask(rtwdev, reg, mask, data);
1269 }
1270
1271 static inline void
rtw89_write32_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 bit)1272 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1273 u32 base, u32 bit)
1274 {
1275 u32 reg;
1276
1277 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1278 rtwvif_link->mac_idx);
1279 rtw89_write32_clr(rtwdev, reg, bit);
1280 }
1281
1282 static inline void
rtw89_write16_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u16 bit)1283 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1284 u32 base, u16 bit)
1285 {
1286 u32 reg;
1287
1288 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1289 rtwvif_link->mac_idx);
1290 rtw89_write16_clr(rtwdev, reg, bit);
1291 }
1292
1293 static inline void
rtw89_write32_port_set(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 bit)1294 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1295 u32 base, u32 bit)
1296 {
1297 u32 reg;
1298
1299 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1300 rtwvif_link->mac_idx);
1301 rtw89_write32_set(rtwdev, reg, bit);
1302 }
1303
1304 int rtw89_mac_pwr_on(struct rtw89_dev *rtwdev);
1305 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev);
1306 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb,
1307 bool bb_preinit);
1308 int rtw89_mac_preinit(struct rtw89_dev *rtwdev);
1309 int rtw89_mac_init(struct rtw89_dev *rtwdev);
1310 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1311 enum rtw89_qta_mode ext_mode);
1312 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en);
1313 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
1314 enum rtw89_qta_mode mode);
1315 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode);
1316 static inline
rtw89_mac_check_mac_en(struct rtw89_dev * rtwdev,u8 band,enum rtw89_mac_hwmod_sel sel)1317 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band,
1318 enum rtw89_mac_hwmod_sel sel)
1319 {
1320 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1321
1322 return mac->check_mac_en(rtwdev, band, sel);
1323 }
1324
rtw89_mac_clr_aon_intr(struct rtw89_dev * rtwdev)1325 static inline void rtw89_mac_clr_aon_intr(struct rtw89_dev *rtwdev)
1326 {
1327 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1328
1329 if (mac->clr_aon_intr)
1330 mac->clr_aon_intr(rtwdev);
1331 }
1332
1333 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val);
1334 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val);
1335 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl);
1336 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev,
1337 struct rtw89_mac_dle_dfi_quota *quota);
1338 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev);
1339 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev,
1340 struct rtw89_mac_dle_dfi_qempty *qempty);
1341 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev,
1342 enum mac_ax_err_info err);
1343 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif);
1344 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1345 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev,
1346 struct rtw89_vif_link *rtwvif_link,
1347 struct rtw89_vif_link *rtwvif_src,
1348 u16 offset_tu);
1349 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1350 u64 *tsf);
1351 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev,
1352 struct rtw89_vif_link *rtwvif_link, bool en);
1353 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
1354 struct rtw89_vif_link *rtwvif_link);
1355 void rtw89_mac_set_he_tb(struct rtw89_dev *rtwdev,
1356 struct rtw89_vif_link *rtwvif_link);
1357 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1358 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en);
1359 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif);
1360 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
1361 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
1362
rtw89_chip_enable_bb_rf(struct rtw89_dev * rtwdev)1363 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev)
1364 {
1365 const struct rtw89_chip_info *chip = rtwdev->chip;
1366
1367 return chip->ops->enable_bb_rf(rtwdev);
1368 }
1369
rtw89_chip_disable_bb_rf(struct rtw89_dev * rtwdev)1370 static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)
1371 {
1372 const struct rtw89_chip_info *chip = rtwdev->chip;
1373
1374 return chip->ops->disable_bb_rf(rtwdev);
1375 }
1376
rtw89_chip_reset_bb_rf(struct rtw89_dev * rtwdev)1377 static inline int rtw89_chip_reset_bb_rf(struct rtw89_dev *rtwdev)
1378 {
1379 int ret;
1380
1381 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
1382 return 0;
1383
1384 ret = rtw89_chip_disable_bb_rf(rtwdev);
1385 if (ret)
1386 return ret;
1387 ret = rtw89_chip_enable_bb_rf(rtwdev);
1388 if (ret)
1389 return ret;
1390
1391 return 0;
1392 }
1393
1394 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
1395 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err);
1396 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
1397 u8 class, u8 func);
1398 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1399 u32 len, u8 class, u8 func);
1400 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev);
1401 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
1402 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1403 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
1404 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1405 int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx,
1406 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1407 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1408 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1409 int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1410 void rtw89_mac_cfg_phy_rpt_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
1411
1412 static inline
rtw89_mac_cfg_phy_rpt(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)1413 void rtw89_mac_cfg_phy_rpt(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
1414 {
1415 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1416
1417 if (mac->cfg_phy_rpt)
1418 mac->cfg_phy_rpt(rtwdev, mac_idx, enable);
1419 }
1420
1421 static inline
rtw89_mac_cfg_phy_rpt_bands(struct rtw89_dev * rtwdev,bool enable)1422 void rtw89_mac_cfg_phy_rpt_bands(struct rtw89_dev *rtwdev, bool enable)
1423 {
1424 rtw89_mac_cfg_phy_rpt(rtwdev, RTW89_MAC_0, enable);
1425
1426 if (!rtwdev->dbcc_en)
1427 return;
1428
1429 rtw89_mac_cfg_phy_rpt(rtwdev, RTW89_MAC_1, enable);
1430 }
1431
1432 static inline
rtw89_mac_cfg_ppdu_status(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)1433 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
1434 {
1435 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1436
1437 return mac->cfg_ppdu_status(rtwdev, mac_idx, enable);
1438 }
1439
1440 static inline
rtw89_mac_cfg_ppdu_status_bands(struct rtw89_dev * rtwdev,bool enable)1441 int rtw89_mac_cfg_ppdu_status_bands(struct rtw89_dev *rtwdev, bool enable)
1442 {
1443 int ret;
1444
1445 ret = rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, enable);
1446 if (ret)
1447 return ret;
1448
1449 if (!rtwdev->dbcc_en)
1450 return 0;
1451
1452 return rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_1, enable);
1453 }
1454
1455 static inline
rtw89_mac_set_edcca_mode(struct rtw89_dev * rtwdev,u8 mac_idx,bool normal)1456 void rtw89_mac_set_edcca_mode(struct rtw89_dev *rtwdev, u8 mac_idx, bool normal)
1457 {
1458 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1459
1460 if (!mac->set_edcca_mode)
1461 return;
1462
1463 mac->set_edcca_mode(rtwdev, mac_idx, normal);
1464 }
1465
1466 static inline
rtw89_mac_set_vcore_cfg(struct rtw89_dev * rtwdev,u8 vlv)1467 void rtw89_mac_set_vcore_cfg(struct rtw89_dev *rtwdev, u8 vlv)
1468 {
1469 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1470
1471 if (!mac->set_vcore_cfg)
1472 return;
1473
1474 mac->set_vcore_cfg(rtwdev, vlv);
1475 }
1476
1477 static inline
rtw89_mac_set_vcore_reset(struct rtw89_dev * rtwdev)1478 void rtw89_mac_set_vcore_reset(struct rtw89_dev *rtwdev)
1479 {
1480 struct rtw89_hal *hal = &rtwdev->hal;
1481
1482 if (hal->thermal_prot_vlv == 0)
1483 return;
1484
1485 hal->thermal_prot_vlv = 0;
1486 rtw89_mac_set_vcore_cfg(rtwdev, 0);
1487 }
1488
1489 static inline
rtw89_mac_set_edcca_mode_bands(struct rtw89_dev * rtwdev,bool normal)1490 void rtw89_mac_set_edcca_mode_bands(struct rtw89_dev *rtwdev, bool normal)
1491 {
1492 rtw89_mac_set_edcca_mode(rtwdev, RTW89_MAC_0, normal);
1493 rtw89_mac_set_edcca_mode(rtwdev, RTW89_MAC_1, normal);
1494 }
1495
1496 void rtw89_mac_set_rx_fltr(struct rtw89_dev *rtwdev, u8 mac_idx, u32 rx_fltr);
1497 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev);
1498 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
1499 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex);
1500 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
1501 const struct rtw89_mac_ax_coex *coex);
1502 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
1503 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1504 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
1505 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1506 int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev,
1507 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1508 int rtw89_mac_cfg_gnt_v3(struct rtw89_dev *rtwdev,
1509 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1510
1511 static inline
rtw89_mac_cfg_plt(struct rtw89_dev * rtwdev,struct rtw89_mac_ax_plt * plt)1512 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)
1513 {
1514 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1515
1516 return mac->cfg_plt(rtwdev, plt);
1517 }
1518
1519 static inline
rtw89_mac_get_plt_cnt(struct rtw89_dev * rtwdev,u8 band)1520 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band)
1521 {
1522 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1523
1524 return mac->get_plt_cnt(rtwdev, band);
1525 }
1526
1527 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val);
1528 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev);
1529 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev);
1530 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl);
1531 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl);
1532 int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl);
1533 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter);
1534 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev);
1535
1536 static inline
rtw89_mac_bf_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)1537 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev,
1538 struct rtw89_vif_link *rtwvif_link,
1539 struct rtw89_sta_link *rtwsta_link)
1540 {
1541 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1542
1543 if (mac->bf_assoc)
1544 mac->bf_assoc(rtwdev, rtwvif_link, rtwsta_link);
1545 }
1546
1547 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev,
1548 struct rtw89_vif_link *rtwvif_link,
1549 struct rtw89_sta_link *rtwsta_link);
1550 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1551 struct ieee80211_bss_conf *conf);
1552 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
1553 struct rtw89_sta_link *rtwsta_link,
1554 bool disconnect);
1555 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev);
1556 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en);
1557 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1558 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1559 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
1560 struct rtw89_vif_link *rtwvif_link, bool en);
1561 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause);
1562
rtw89_mac_bf_monitor_track(struct rtw89_dev * rtwdev)1563 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
1564 {
1565 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
1566 return;
1567
1568 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags))
1569 return;
1570
1571 _rtw89_mac_bf_monitor_track(rtwdev);
1572 }
1573
rtw89_mac_txpwr_read32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * val)1574 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev,
1575 enum rtw89_phy_idx phy_idx,
1576 u32 reg_base, u32 *val)
1577 {
1578 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1579 u32 cr;
1580
1581 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1582 return -EINVAL;
1583
1584 *val = rtw89_read32(rtwdev, cr);
1585 return 0;
1586 }
1587
rtw89_mac_txpwr_write32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 val)1588 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev,
1589 enum rtw89_phy_idx phy_idx,
1590 u32 reg_base, u32 val)
1591 {
1592 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1593 u32 cr;
1594
1595 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1596 return -EINVAL;
1597
1598 rtw89_write32(rtwdev, cr, val);
1599 return 0;
1600 }
1601
rtw89_mac_txpwr_write32_mask(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 mask,u32 val)1602 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev,
1603 enum rtw89_phy_idx phy_idx,
1604 u32 reg_base, u32 mask, u32 val)
1605 {
1606 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1607 u32 cr;
1608
1609 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1610 return -EINVAL;
1611
1612 rtw89_write32_mask(rtwdev, cr, mask, val);
1613 return 0;
1614 }
1615
rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev * rtwdev,bool enable)1616 static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev,
1617 bool enable)
1618 {
1619 const struct rtw89_chip_info *chip = rtwdev->chip;
1620
1621 if (enable)
1622 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1623 B_AX_HCI_TXDMA_EN);
1624 else
1625 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1626 B_AX_HCI_TXDMA_EN);
1627 }
1628
rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev * rtwdev,bool enable)1629 static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev,
1630 bool enable)
1631 {
1632 const struct rtw89_chip_info *chip = rtwdev->chip;
1633
1634 if (enable)
1635 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1636 B_AX_HCI_RXDMA_EN);
1637 else
1638 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1639 B_AX_HCI_RXDMA_EN);
1640 }
1641
rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev * rtwdev,bool enable)1642 static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev,
1643 bool enable)
1644 {
1645 const struct rtw89_chip_info *chip = rtwdev->chip;
1646
1647 if (enable)
1648 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1649 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
1650 else
1651 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1652 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
1653 }
1654
rtw89_mac_get_power_state(struct rtw89_dev * rtwdev)1655 static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev)
1656 {
1657 u32 val;
1658
1659 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE,
1660 B_AX_WLMAC_PWR_STE_MASK);
1661
1662 return !!val;
1663 }
1664
1665 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link,
1666 bool resume, u32 tx_time);
1667 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link,
1668 u32 *tx_time);
1669 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
1670 struct rtw89_sta_link *rtwsta_link,
1671 bool resume, u8 tx_retry);
1672 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
1673 struct rtw89_sta_link *rtwsta_link, u8 *tx_retry);
1674
1675 enum rtw89_mac_xtal_si_offset {
1676 XTAL0 = 0x0,
1677 XTAL3 = 0x3,
1678 XTAL_SI_XTAL_SC_XI = 0x04,
1679 #define XTAL_SC_XI_MASK GENMASK(7, 0)
1680 XTAL_SI_XTAL_SC_XO = 0x05,
1681 #define XTAL_SC_XO_MASK GENMASK(7, 0)
1682 XTAL_SI_XREF_MODE = 0x0B,
1683 XTAL_SI_PWR_CUT = 0x10,
1684 #define XTAL_SI_SMALL_PWR_CUT BIT(0)
1685 #define XTAL_SI_BIG_PWR_CUT BIT(1)
1686 XTAL_SI_AONLDO_CTRL = 0x10,
1687 XTAL_SI_XTAL_DRV = 0x15,
1688 #define XTAL_SI_DRV_LATCH BIT(4)
1689 XTAL_SI_XTAL_PLL = 0x16,
1690 XTAL_SI_XTAL_XMD_2 = 0x24,
1691 #define XTAL_SI_LDO_LPS GENMASK(6, 4)
1692 XTAL_SI_XTAL_XMD_4 = 0x26,
1693 #define XTAL_SI_LPS_CAP GENMASK(3, 0)
1694 XTAL_SI_XREF_RF1 = 0x2D,
1695 XTAL_SI_XREF_RF2 = 0x2E,
1696 XTAL_SI_CV = 0x41,
1697 #define XTAL_SI_ACV_MASK GENMASK(3, 0)
1698 XTAL_SI_LOW_ADDR = 0x62,
1699 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0)
1700 XTAL_SI_CTRL = 0x63,
1701 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6)
1702 #define XTAL_SI_RDY BIT(5)
1703 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0)
1704 XTAL_SI_READ_VAL = 0x7A,
1705 XTAL_SI_WL_RFC_S0 = 0x80,
1706 #define XTAL_SI_RF00S_EN GENMASK(2, 0)
1707 #define XTAL_SI_RF00 BIT(0)
1708 XTAL_SI_WL_RFC_S1 = 0x81,
1709 #define XTAL_SI_RF10S_EN GENMASK(2, 0)
1710 #define XTAL_SI_RF10 BIT(0)
1711 XTAL_SI_ANAPAR_WL = 0x90,
1712 #define XTAL_SI_SRAM2RFC BIT(7)
1713 #define XTAL_SI_GND_SHDN_WL BIT(6)
1714 #define XTAL_SI_SHDN_WL BIT(5)
1715 #define XTAL_SI_RFC2RF BIT(4)
1716 #define XTAL_SI_OFF_EI BIT(3)
1717 #define XTAL_SI_OFF_WEI BIT(2)
1718 #define XTAL_SI_PON_EI BIT(1)
1719 #define XTAL_SI_PON_WEI BIT(0)
1720 XTAL_SI_SRAM_CTRL = 0xA1,
1721 #define XTAL_SI_SRAM_DIS BIT(1)
1722 #define FULL_BIT_MASK GENMASK(7, 0)
1723 XTAL_SI_APBT = 0xD1,
1724 XTAL_SI_PLL = 0xE0,
1725 XTAL_SI_PLL_1 = 0xE1,
1726 XTAL_SI_CHIP_ID_L = 0xFD,
1727 XTAL_SI_CHIP_ID_H = 0xFE,
1728 };
1729
1730 static inline
rtw89_mac_write_xtal_si(struct rtw89_dev * rtwdev,u8 offset,u8 val,u8 mask)1731 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
1732 {
1733 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1734
1735 return mac->write_xtal_si(rtwdev, offset, val, mask);
1736 }
1737
1738 static inline
rtw89_mac_read_xtal_si(struct rtw89_dev * rtwdev,u8 offset,u8 * val)1739 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
1740 {
1741 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1742
1743 return mac->read_xtal_si(rtwdev, offset, val);
1744 }
1745
1746 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1747 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow);
1748 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
1749 enum rtw89_mac_idx band);
1750 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow);
1751 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1752 bool band1_en);
1753 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev,
1754 enum rtw89_mac_dle_rsvd_qt_type type,
1755 struct rtw89_mac_dle_rsvd_qt_cfg *cfg);
1756 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable);
1757
rtw89_mac_efuse_read_ecv(struct rtw89_dev * rtwdev)1758 static inline int rtw89_mac_efuse_read_ecv(struct rtw89_dev *rtwdev)
1759 {
1760 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1761
1762 if (!mac->efuse_read_ecv)
1763 return -ENOENT;
1764
1765 return mac->efuse_read_ecv(rtwdev);
1766 }
1767
rtw89_mac_efuse_read_thermal_k(struct rtw89_dev * rtwdev)1768 static inline int rtw89_mac_efuse_read_thermal_k(struct rtw89_dev *rtwdev)
1769 {
1770 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1771
1772 if (!mac->efuse_read_thermal_k)
1773 return -ENOENT;
1774
1775 return mac->efuse_read_thermal_k(rtwdev);
1776 }
1777
rtw89_mac_efuse_read_pwr_data(struct rtw89_dev * rtwdev)1778 static inline int rtw89_mac_efuse_read_pwr_data(struct rtw89_dev *rtwdev)
1779 {
1780 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1781
1782 if (!mac->efuse_read_pwr_data)
1783 return -ENOENT;
1784
1785 return mac->efuse_read_pwr_data(rtwdev);
1786 }
1787
1788 static inline
rtw89_mac_fwdl_preconfig(struct rtw89_dev * rtwdev)1789 void rtw89_mac_fwdl_preconfig(struct rtw89_dev *rtwdev)
1790 {
1791 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1792
1793 if (!mac->fwdl_preconfig)
1794 return;
1795
1796 mac->fwdl_preconfig(rtwdev);
1797 }
1798
1799 static inline
rtw89_fwdl_secure_idmem_share_mode(struct rtw89_dev * rtwdev,u8 mode)1800 void rtw89_fwdl_secure_idmem_share_mode(struct rtw89_dev *rtwdev, u8 mode)
1801 {
1802 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1803
1804 if (!mac->fwdl_secure_idmem_share_mode)
1805 return;
1806
1807 mac->fwdl_secure_idmem_share_mode(rtwdev, mode);
1808 }
1809
1810 static inline
rtw89_mac_scan_offload(struct rtw89_dev * rtwdev,struct rtw89_scan_option * option,struct rtw89_vif_link * rtwvif_link,bool wowlan)1811 int rtw89_mac_scan_offload(struct rtw89_dev *rtwdev,
1812 struct rtw89_scan_option *option,
1813 struct rtw89_vif_link *rtwvif_link,
1814 bool wowlan)
1815 {
1816 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1817 int ret;
1818
1819 ret = mac->scan_offload(rtwdev, option, rtwvif_link, wowlan);
1820
1821 if (option->enable) {
1822 /*
1823 * At this point, new scan request is acknowledged by firmware,
1824 * so scan events of previous scan request become obsoleted.
1825 * Purge the queued scan events to prevent interference to
1826 * current new request.
1827 */
1828 rtw89_fw_c2h_purge_obsoleted_scan_events(rtwdev);
1829 }
1830
1831 return ret;
1832 }
1833
1834 static inline
rtw89_tx_rpt_init(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1835 void rtw89_tx_rpt_init(struct rtw89_dev *rtwdev,
1836 struct rtw89_core_tx_request *tx_req)
1837 {
1838 struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt;
1839
1840 if (!rtwdev->hci.tx_rpt_enabled)
1841 return;
1842
1843 tx_req->desc_info.report = true;
1844 /* firmware maintains a 4-bit sequence number */
1845 tx_req->desc_info.sn = atomic_inc_return(&tx_rpt->sn) &
1846 RTW89_MAX_TX_RPTS_MASK;
1847 tx_req->desc_info.tx_cnt_lmt_en = true;
1848 tx_req->desc_info.tx_cnt_lmt = 8;
1849 }
1850
1851 static inline
rtw89_is_tx_rpt_skb(struct rtw89_dev * rtwdev,struct sk_buff * skb)1852 bool rtw89_is_tx_rpt_skb(struct rtw89_dev *rtwdev, struct sk_buff *skb)
1853 {
1854 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
1855 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1856
1857 return rtw89_core_is_tx_wait(rtwdev, skb_data) ||
1858 (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS);
1859 }
1860
1861 static inline
rtw89_tx_rpt_tx_status(struct rtw89_dev * rtwdev,struct sk_buff * skb,u8 tx_status)1862 void rtw89_tx_rpt_tx_status(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1863 u8 tx_status)
1864 {
1865 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
1866 struct ieee80211_tx_info *info;
1867
1868 if (rtw89_core_tx_wait_complete(rtwdev, skb_data, tx_status))
1869 return;
1870
1871 info = IEEE80211_SKB_CB(skb);
1872 ieee80211_tx_info_clear_status(info);
1873
1874 if (tx_status == RTW89_TX_DONE)
1875 info->flags |= IEEE80211_TX_STAT_ACK;
1876 else
1877 info->flags &= ~IEEE80211_TX_STAT_ACK;
1878
1879 ieee80211_tx_status_irqsafe(rtwdev->hw, skb);
1880 }
1881
1882 static inline
rtw89_tx_rpt_skb_add(struct rtw89_dev * rtwdev,struct sk_buff * skb)1883 void rtw89_tx_rpt_skb_add(struct rtw89_dev *rtwdev, struct sk_buff *skb)
1884 {
1885 struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt;
1886 struct rtw89_tx_skb_data *skb_data;
1887 u8 idx;
1888
1889 skb_data = RTW89_TX_SKB_CB(skb);
1890 idx = skb_data->tx_rpt_sn;
1891
1892 scoped_guard(spinlock_irqsave, &tx_rpt->skb_lock) {
1893 /* if skb having the similar seq number is still in the queue,
1894 * this means the queue is overflowed - it isn't normal and
1895 * should indicate firmware doesn't provide TX reports in time;
1896 * report the old skb as dropped, we can't do much more here
1897 */
1898 if (tx_rpt->skbs[idx])
1899 rtw89_tx_rpt_tx_status(rtwdev, tx_rpt->skbs[idx],
1900 RTW89_TX_MACID_DROP);
1901 tx_rpt->skbs[idx] = skb;
1902 }
1903 }
1904
1905 static inline
rtw89_tx_rpt_skbs_purge(struct rtw89_dev * rtwdev)1906 void rtw89_tx_rpt_skbs_purge(struct rtw89_dev *rtwdev)
1907 {
1908 struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt;
1909 struct sk_buff *skbs[RTW89_MAX_TX_RPTS];
1910
1911 scoped_guard(spinlock_irqsave, &tx_rpt->skb_lock) {
1912 memcpy(skbs, tx_rpt->skbs, sizeof(tx_rpt->skbs));
1913 memset(tx_rpt->skbs, 0, sizeof(tx_rpt->skbs));
1914 }
1915
1916 for (int i = 0; i < ARRAY_SIZE(skbs); i++)
1917 if (skbs[i])
1918 rtw89_tx_rpt_tx_status(rtwdev, skbs[i],
1919 RTW89_TX_MACID_DROP);
1920 }
1921
rtw89_mac_chk_preload_allow(struct rtw89_dev * rtwdev)1922 static inline bool rtw89_mac_chk_preload_allow(struct rtw89_dev *rtwdev)
1923 {
1924 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE)
1925 return false;
1926
1927 /* The RTL8922DE will re-enable pre-load function after verification. */
1928
1929 return false;
1930 }
1931
1932 #endif
1933