1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Low-level parallel port routines for built-in port on SGI IP32
3 *
4 * Author: Arnaud Giersch <arnaud.giersch@free.fr>
5 *
6 * Based on parport_pc.c by
7 * Phil Blundell, Tim Waugh, Jose Renau, David Campbell,
8 * Andrea Arcangeli, et al.
9 *
10 * Thanks to Ilya A. Volynets-Evenbakh for his help.
11 *
12 * Copyright (C) 2005, 2006 Arnaud Giersch.
13 */
14
15 /* Current status:
16 *
17 * Basic SPP and PS2 modes are supported.
18 * Support for parallel port IRQ is present.
19 * Hardware SPP (a.k.a. compatibility), EPP, and ECP modes are
20 * supported.
21 * SPP/ECP FIFO can be driven in PIO or DMA mode. PIO mode can work with
22 * or without interrupt support.
23 *
24 * Hardware ECP mode is not fully implemented (ecp_read_data and
25 * ecp_write_addr are actually missing).
26 *
27 * To do:
28 *
29 * Fully implement ECP mode.
30 * EPP and ECP mode need to be tested. I currently do not own any
31 * peripheral supporting these extended mode, and cannot test them.
32 * If DMA mode works well, decide if support for PIO FIFO modes should be
33 * dropped.
34 * Use the io{read,write} family functions when they become available in
35 * the linux-mips.org tree. Note: the MIPS specific functions readsb()
36 * and writesb() are to be translated by ioread8_rep() and iowrite8_rep()
37 * respectively.
38 */
39
40 /* The built-in parallel port on the SGI 02 workstation (a.k.a. IP32) is an
41 * IEEE 1284 parallel port driven by a Texas Instrument TL16PIR552PH chip[1].
42 * This chip supports SPP, bidirectional, EPP and ECP modes. It has a 16 byte
43 * FIFO buffer and supports DMA transfers.
44 *
45 * [1] http://focus.ti.com/docs/prod/folders/print/tl16pir552.html
46 *
47 * Theoretically, we could simply use the parport_pc module. It is however
48 * not so simple. The parport_pc code assumes that the parallel port
49 * registers are port-mapped. On the O2, they are memory-mapped.
50 * Furthermore, each register is replicated on 256 consecutive addresses (as
51 * it is for the built-in serial ports on the same chip).
52 */
53
54 /*--- Some configuration defines ---------------------------------------*/
55
56 /* DEBUG_PARPORT_IP32
57 * 0 disable debug
58 * 1 standard level: pr_debug1 is enabled
59 * 2 parport_ip32_dump_state is enabled
60 * >=3 verbose level: pr_debug is enabled
61 */
62 #if !defined(DEBUG_PARPORT_IP32)
63 # define DEBUG_PARPORT_IP32 0 /* 0 (disabled) for production */
64 #endif
65
66 /*----------------------------------------------------------------------*/
67
68 /* Setup DEBUG macros. This is done before any includes, just in case we
69 * activate pr_debug() with DEBUG_PARPORT_IP32 >= 3.
70 */
71 #if DEBUG_PARPORT_IP32 == 1
72 # warning DEBUG_PARPORT_IP32 == 1
73 #elif DEBUG_PARPORT_IP32 == 2
74 # warning DEBUG_PARPORT_IP32 == 2
75 #elif DEBUG_PARPORT_IP32 >= 3
76 # warning DEBUG_PARPORT_IP32 >= 3
77 # if !defined(DEBUG)
78 # define DEBUG /* enable pr_debug() in kernel.h */
79 # endif
80 #endif
81
82 #include <linux/completion.h>
83 #include <linux/delay.h>
84 #include <linux/dma-mapping.h>
85 #include <linux/err.h>
86 #include <linux/init.h>
87 #include <linux/interrupt.h>
88 #include <linux/jiffies.h>
89 #include <linux/kernel.h>
90 #include <linux/module.h>
91 #include <linux/parport.h>
92 #include <linux/sched/signal.h>
93 #include <linux/slab.h>
94 #include <linux/spinlock.h>
95 #include <linux/stddef.h>
96 #include <linux/types.h>
97 #include <asm/io.h>
98 #include <asm/ip32/ip32_ints.h>
99 #include <asm/ip32/mace.h>
100
101 /*--- Global variables -------------------------------------------------*/
102
103 /* Verbose probing on by default for debugging. */
104 #if DEBUG_PARPORT_IP32 >= 1
105 # define DEFAULT_VERBOSE_PROBING 1
106 #else
107 # define DEFAULT_VERBOSE_PROBING 0
108 #endif
109
110 /* Default prefix for printk */
111 #define PPIP32 "parport_ip32: "
112
113 /*
114 * These are the module parameters:
115 * @features: bit mask of features to enable/disable
116 * (all enabled by default)
117 * @verbose_probing: log chit-chat during initialization
118 */
119 #define PARPORT_IP32_ENABLE_IRQ (1U << 0)
120 #define PARPORT_IP32_ENABLE_DMA (1U << 1)
121 #define PARPORT_IP32_ENABLE_SPP (1U << 2)
122 #define PARPORT_IP32_ENABLE_EPP (1U << 3)
123 #define PARPORT_IP32_ENABLE_ECP (1U << 4)
124 static unsigned int features = ~0U;
125 static bool verbose_probing = DEFAULT_VERBOSE_PROBING;
126
127 /* We do not support more than one port. */
128 static struct parport *this_port;
129
130 /* Timing constants for FIFO modes. */
131 #define FIFO_NFAULT_TIMEOUT 100 /* milliseconds */
132 #define FIFO_POLLING_INTERVAL 50 /* microseconds */
133
134 /*--- I/O register definitions -----------------------------------------*/
135
136 /**
137 * struct parport_ip32_regs - virtual addresses of parallel port registers
138 * @data: Data Register
139 * @dsr: Device Status Register
140 * @dcr: Device Control Register
141 * @eppAddr: EPP Address Register
142 * @eppData0: EPP Data Register 0
143 * @eppData1: EPP Data Register 1
144 * @eppData2: EPP Data Register 2
145 * @eppData3: EPP Data Register 3
146 * @ecpAFifo: ECP Address FIFO
147 * @fifo: General FIFO register. The same address is used for:
148 * - cFifo, the Parallel Port DATA FIFO
149 * - ecpDFifo, the ECP Data FIFO
150 * - tFifo, the ECP Test FIFO
151 * @cnfgA: Configuration Register A
152 * @cnfgB: Configuration Register B
153 * @ecr: Extended Control Register
154 */
155 struct parport_ip32_regs {
156 void __iomem *data;
157 void __iomem *dsr;
158 void __iomem *dcr;
159 void __iomem *eppAddr;
160 void __iomem *eppData0;
161 void __iomem *eppData1;
162 void __iomem *eppData2;
163 void __iomem *eppData3;
164 void __iomem *ecpAFifo;
165 void __iomem *fifo;
166 void __iomem *cnfgA;
167 void __iomem *cnfgB;
168 void __iomem *ecr;
169 };
170
171 /* Device Status Register */
172 #define DSR_nBUSY (1U << 7) /* PARPORT_STATUS_BUSY */
173 #define DSR_nACK (1U << 6) /* PARPORT_STATUS_ACK */
174 #define DSR_PERROR (1U << 5) /* PARPORT_STATUS_PAPEROUT */
175 #define DSR_SELECT (1U << 4) /* PARPORT_STATUS_SELECT */
176 #define DSR_nFAULT (1U << 3) /* PARPORT_STATUS_ERROR */
177 #define DSR_nPRINT (1U << 2) /* specific to TL16PIR552 */
178 /* #define DSR_reserved (1U << 1) */
179 #define DSR_TIMEOUT (1U << 0) /* EPP timeout */
180
181 /* Device Control Register */
182 /* #define DCR_reserved (1U << 7) | (1U << 6) */
183 #define DCR_DIR (1U << 5) /* direction */
184 #define DCR_IRQ (1U << 4) /* interrupt on nAck */
185 #define DCR_SELECT (1U << 3) /* PARPORT_CONTROL_SELECT */
186 #define DCR_nINIT (1U << 2) /* PARPORT_CONTROL_INIT */
187 #define DCR_AUTOFD (1U << 1) /* PARPORT_CONTROL_AUTOFD */
188 #define DCR_STROBE (1U << 0) /* PARPORT_CONTROL_STROBE */
189
190 /* ECP Configuration Register A */
191 #define CNFGA_IRQ (1U << 7)
192 #define CNFGA_ID_MASK ((1U << 6) | (1U << 5) | (1U << 4))
193 #define CNFGA_ID_SHIFT 4
194 #define CNFGA_ID_16 (00U << CNFGA_ID_SHIFT)
195 #define CNFGA_ID_8 (01U << CNFGA_ID_SHIFT)
196 #define CNFGA_ID_32 (02U << CNFGA_ID_SHIFT)
197 /* #define CNFGA_reserved (1U << 3) */
198 #define CNFGA_nBYTEINTRANS (1U << 2)
199 #define CNFGA_PWORDLEFT ((1U << 1) | (1U << 0))
200
201 /* ECP Configuration Register B */
202 #define CNFGB_COMPRESS (1U << 7)
203 #define CNFGB_INTRVAL (1U << 6)
204 #define CNFGB_IRQ_MASK ((1U << 5) | (1U << 4) | (1U << 3))
205 #define CNFGB_IRQ_SHIFT 3
206 #define CNFGB_DMA_MASK ((1U << 2) | (1U << 1) | (1U << 0))
207 #define CNFGB_DMA_SHIFT 0
208
209 /* Extended Control Register */
210 #define ECR_MODE_MASK ((1U << 7) | (1U << 6) | (1U << 5))
211 #define ECR_MODE_SHIFT 5
212 #define ECR_MODE_SPP (00U << ECR_MODE_SHIFT)
213 #define ECR_MODE_PS2 (01U << ECR_MODE_SHIFT)
214 #define ECR_MODE_PPF (02U << ECR_MODE_SHIFT)
215 #define ECR_MODE_ECP (03U << ECR_MODE_SHIFT)
216 #define ECR_MODE_EPP (04U << ECR_MODE_SHIFT)
217 /* #define ECR_MODE_reserved (05U << ECR_MODE_SHIFT) */
218 #define ECR_MODE_TST (06U << ECR_MODE_SHIFT)
219 #define ECR_MODE_CFG (07U << ECR_MODE_SHIFT)
220 #define ECR_nERRINTR (1U << 4)
221 #define ECR_DMAEN (1U << 3)
222 #define ECR_SERVINTR (1U << 2)
223 #define ECR_F_FULL (1U << 1)
224 #define ECR_F_EMPTY (1U << 0)
225
226 /*--- Private data -----------------------------------------------------*/
227
228 /**
229 * enum parport_ip32_irq_mode - operation mode of interrupt handler
230 * @PARPORT_IP32_IRQ_FWD: forward interrupt to the upper parport layer
231 * @PARPORT_IP32_IRQ_HERE: interrupt is handled locally
232 */
233 enum parport_ip32_irq_mode { PARPORT_IP32_IRQ_FWD, PARPORT_IP32_IRQ_HERE };
234
235 /**
236 * struct parport_ip32_private - private stuff for &struct parport
237 * @regs: register addresses
238 * @dcr_cache: cached contents of DCR
239 * @dcr_writable: bit mask of writable DCR bits
240 * @pword: number of bytes per PWord
241 * @fifo_depth: number of PWords that FIFO will hold
242 * @readIntrThreshold: minimum number of PWords we can read
243 * if we get an interrupt
244 * @writeIntrThreshold: minimum number of PWords we can write
245 * if we get an interrupt
246 * @irq_mode: operation mode of interrupt handler for this port
247 * @irq_complete: mutex used to wait for an interrupt to occur
248 */
249 struct parport_ip32_private {
250 struct parport_ip32_regs regs;
251 unsigned int dcr_cache;
252 unsigned int dcr_writable;
253 unsigned int pword;
254 unsigned int fifo_depth;
255 unsigned int readIntrThreshold;
256 unsigned int writeIntrThreshold;
257 enum parport_ip32_irq_mode irq_mode;
258 struct completion irq_complete;
259 };
260
261 /*--- Debug code -------------------------------------------------------*/
262
263 /*
264 * pr_debug1 - print debug messages
265 *
266 * This is like pr_debug(), but is defined for %DEBUG_PARPORT_IP32 >= 1
267 */
268 #if DEBUG_PARPORT_IP32 >= 1
269 # define pr_debug1(...) printk(KERN_DEBUG __VA_ARGS__)
270 #else /* DEBUG_PARPORT_IP32 < 1 */
271 # define pr_debug1(...) do { } while (0)
272 #endif
273
274 /*
275 * pr_trace, pr_trace1 - trace function calls
276 * @p: pointer to &struct parport
277 * @fmt: printk format string
278 * @...: parameters for format string
279 *
280 * Macros used to trace function calls. The given string is formatted after
281 * function name. pr_trace() uses pr_debug(), and pr_trace1() uses
282 * pr_debug1(). __pr_trace() is the low-level macro and is not to be used
283 * directly.
284 */
285 #define __pr_trace(pr, p, fmt, ...) \
286 pr("%s: %s" fmt "\n", \
287 ({ const struct parport *__p = (p); \
288 __p ? __p->name : "parport_ip32"; }), \
289 __func__ , ##__VA_ARGS__)
290 #define pr_trace(p, fmt, ...) __pr_trace(pr_debug, p, fmt , ##__VA_ARGS__)
291 #define pr_trace1(p, fmt, ...) __pr_trace(pr_debug1, p, fmt , ##__VA_ARGS__)
292
293 /*
294 * __pr_probe, pr_probe - print message if @verbose_probing is true
295 * @p: pointer to &struct parport
296 * @fmt: printk format string
297 * @...: parameters for format string
298 *
299 * For new lines, use pr_probe(). Use __pr_probe() for continued lines.
300 */
301 #define __pr_probe(...) \
302 do { if (verbose_probing) printk(__VA_ARGS__); } while (0)
303 #define pr_probe(p, fmt, ...) \
304 __pr_probe(KERN_INFO PPIP32 "0x%lx: " fmt, (p)->base , ##__VA_ARGS__)
305
306 /*
307 * parport_ip32_dump_state - print register status of parport
308 * @p: pointer to &struct parport
309 * @str: string to add in message
310 * @show_ecp_config: shall we dump ECP configuration registers too?
311 *
312 * This function is only here for debugging purpose, and should be used with
313 * care. Reading the parallel port registers may have undesired side effects.
314 * Especially if @show_ecp_config is true, the parallel port is resetted.
315 * This function is only defined if %DEBUG_PARPORT_IP32 >= 2.
316 */
317 #if DEBUG_PARPORT_IP32 >= 2
parport_ip32_dump_state(struct parport * p,char * str,unsigned int show_ecp_config)318 static void parport_ip32_dump_state(struct parport *p, char *str,
319 unsigned int show_ecp_config)
320 {
321 struct parport_ip32_private * const priv = p->physport->private_data;
322 unsigned int i;
323
324 printk(KERN_DEBUG PPIP32 "%s: state (%s):\n", p->name, str);
325 {
326 static const char ecr_modes[8][4] = {"SPP", "PS2", "PPF",
327 "ECP", "EPP", "???",
328 "TST", "CFG"};
329 unsigned int ecr = readb(priv->regs.ecr);
330 printk(KERN_DEBUG PPIP32 " ecr=0x%02x", ecr);
331 pr_cont(" %s",
332 ecr_modes[(ecr & ECR_MODE_MASK) >> ECR_MODE_SHIFT]);
333 if (ecr & ECR_nERRINTR)
334 pr_cont(",nErrIntrEn");
335 if (ecr & ECR_DMAEN)
336 pr_cont(",dmaEn");
337 if (ecr & ECR_SERVINTR)
338 pr_cont(",serviceIntr");
339 if (ecr & ECR_F_FULL)
340 pr_cont(",f_full");
341 if (ecr & ECR_F_EMPTY)
342 pr_cont(",f_empty");
343 pr_cont("\n");
344 }
345 if (show_ecp_config) {
346 unsigned int oecr, cnfgA, cnfgB;
347 oecr = readb(priv->regs.ecr);
348 writeb(ECR_MODE_PS2, priv->regs.ecr);
349 writeb(ECR_MODE_CFG, priv->regs.ecr);
350 cnfgA = readb(priv->regs.cnfgA);
351 cnfgB = readb(priv->regs.cnfgB);
352 writeb(ECR_MODE_PS2, priv->regs.ecr);
353 writeb(oecr, priv->regs.ecr);
354 printk(KERN_DEBUG PPIP32 " cnfgA=0x%02x", cnfgA);
355 pr_cont(" ISA-%s", (cnfgA & CNFGA_IRQ) ? "Level" : "Pulses");
356 switch (cnfgA & CNFGA_ID_MASK) {
357 case CNFGA_ID_8:
358 pr_cont(",8 bits");
359 break;
360 case CNFGA_ID_16:
361 pr_cont(",16 bits");
362 break;
363 case CNFGA_ID_32:
364 pr_cont(",32 bits");
365 break;
366 default:
367 pr_cont(",unknown ID");
368 break;
369 }
370 if (!(cnfgA & CNFGA_nBYTEINTRANS))
371 pr_cont(",ByteInTrans");
372 if ((cnfgA & CNFGA_ID_MASK) != CNFGA_ID_8)
373 pr_cont(",%d byte%s left",
374 cnfgA & CNFGA_PWORDLEFT,
375 ((cnfgA & CNFGA_PWORDLEFT) > 1) ? "s" : "");
376 pr_cont("\n");
377 printk(KERN_DEBUG PPIP32 " cnfgB=0x%02x", cnfgB);
378 pr_cont(" irq=%u,dma=%u",
379 (cnfgB & CNFGB_IRQ_MASK) >> CNFGB_IRQ_SHIFT,
380 (cnfgB & CNFGB_DMA_MASK) >> CNFGB_DMA_SHIFT);
381 pr_cont(",intrValue=%d", !!(cnfgB & CNFGB_INTRVAL));
382 if (cnfgB & CNFGB_COMPRESS)
383 pr_cont(",compress");
384 pr_cont("\n");
385 }
386 for (i = 0; i < 2; i++) {
387 unsigned int dcr = i ? priv->dcr_cache : readb(priv->regs.dcr);
388 printk(KERN_DEBUG PPIP32 " dcr(%s)=0x%02x",
389 i ? "soft" : "hard", dcr);
390 pr_cont(" %s", (dcr & DCR_DIR) ? "rev" : "fwd");
391 if (dcr & DCR_IRQ)
392 pr_cont(",ackIntEn");
393 if (!(dcr & DCR_SELECT))
394 pr_cont(",nSelectIn");
395 if (dcr & DCR_nINIT)
396 pr_cont(",nInit");
397 if (!(dcr & DCR_AUTOFD))
398 pr_cont(",nAutoFD");
399 if (!(dcr & DCR_STROBE))
400 pr_cont(",nStrobe");
401 pr_cont("\n");
402 }
403 #define sep (f++ ? ',' : ' ')
404 {
405 unsigned int f = 0;
406 unsigned int dsr = readb(priv->regs.dsr);
407 printk(KERN_DEBUG PPIP32 " dsr=0x%02x", dsr);
408 if (!(dsr & DSR_nBUSY))
409 pr_cont("%cBusy", sep);
410 if (dsr & DSR_nACK)
411 pr_cont("%cnAck", sep);
412 if (dsr & DSR_PERROR)
413 pr_cont("%cPError", sep);
414 if (dsr & DSR_SELECT)
415 pr_cont("%cSelect", sep);
416 if (dsr & DSR_nFAULT)
417 pr_cont("%cnFault", sep);
418 if (!(dsr & DSR_nPRINT))
419 pr_cont("%c(Print)", sep);
420 if (dsr & DSR_TIMEOUT)
421 pr_cont("%cTimeout", sep);
422 pr_cont("\n");
423 }
424 #undef sep
425 }
426 #else /* DEBUG_PARPORT_IP32 < 2 */
427 #define parport_ip32_dump_state(...) do { } while (0)
428 #endif
429
430 /*
431 * CHECK_EXTRA_BITS - track and log extra bits
432 * @p: pointer to &struct parport
433 * @b: byte to inspect
434 * @m: bit mask of authorized bits
435 *
436 * This is used to track and log extra bits that should not be there in
437 * parport_ip32_write_control() and parport_ip32_frob_control(). It is only
438 * defined if %DEBUG_PARPORT_IP32 >= 1.
439 */
440 #if DEBUG_PARPORT_IP32 >= 1
441 #define CHECK_EXTRA_BITS(p, b, m) \
442 do { \
443 unsigned int __b = (b), __m = (m); \
444 if (__b & ~__m) \
445 pr_debug1(PPIP32 "%s: extra bits in %s(%s): " \
446 "0x%02x/0x%02x\n", \
447 (p)->name, __func__, #b, __b, __m); \
448 } while (0)
449 #else /* DEBUG_PARPORT_IP32 < 1 */
450 #define CHECK_EXTRA_BITS(...) do { } while (0)
451 #endif
452
453 /*--- IP32 parallel port DMA operations --------------------------------*/
454
455 /**
456 * struct parport_ip32_dma_data - private data needed for DMA operation
457 * @dir: DMA direction (from or to device)
458 * @buf: buffer physical address
459 * @len: buffer length
460 * @next: address of next bytes to DMA transfer
461 * @left: number of bytes remaining
462 * @ctx: next context to write (0: context_a; 1: context_b)
463 * @irq_on: are the DMA IRQs currently enabled?
464 * @lock: spinlock to protect access to the structure
465 */
466 struct parport_ip32_dma_data {
467 enum dma_data_direction dir;
468 dma_addr_t buf;
469 dma_addr_t next;
470 size_t len;
471 size_t left;
472 unsigned int ctx;
473 unsigned int irq_on;
474 spinlock_t lock;
475 };
476 static struct parport_ip32_dma_data parport_ip32_dma;
477
478 /**
479 * parport_ip32_dma_setup_context - setup next DMA context
480 * @limit: maximum data size for the context
481 *
482 * The alignment constraints must be verified in caller function, and the
483 * parameter @limit must be set accordingly.
484 */
parport_ip32_dma_setup_context(unsigned int limit)485 static void parport_ip32_dma_setup_context(unsigned int limit)
486 {
487 unsigned long flags;
488
489 spin_lock_irqsave(&parport_ip32_dma.lock, flags);
490 if (parport_ip32_dma.left > 0) {
491 /* Note: ctxreg is "volatile" here only because
492 * mace->perif.ctrl.parport.context_a and context_b are
493 * "volatile". */
494 volatile u64 __iomem *ctxreg = (parport_ip32_dma.ctx == 0) ?
495 &mace->perif.ctrl.parport.context_a :
496 &mace->perif.ctrl.parport.context_b;
497 u64 count;
498 u64 ctxval;
499 if (parport_ip32_dma.left <= limit) {
500 count = parport_ip32_dma.left;
501 ctxval = MACEPAR_CONTEXT_LASTFLAG;
502 } else {
503 count = limit;
504 ctxval = 0;
505 }
506
507 pr_trace(NULL,
508 "(%u): 0x%04x:0x%04x, %u -> %u%s",
509 limit,
510 (unsigned int)parport_ip32_dma.buf,
511 (unsigned int)parport_ip32_dma.next,
512 (unsigned int)count,
513 parport_ip32_dma.ctx, ctxval ? "*" : "");
514
515 ctxval |= parport_ip32_dma.next &
516 MACEPAR_CONTEXT_BASEADDR_MASK;
517 ctxval |= ((count - 1) << MACEPAR_CONTEXT_DATALEN_SHIFT) &
518 MACEPAR_CONTEXT_DATALEN_MASK;
519 writeq(ctxval, ctxreg);
520 parport_ip32_dma.next += count;
521 parport_ip32_dma.left -= count;
522 parport_ip32_dma.ctx ^= 1U;
523 }
524 /* If there is nothing more to send, disable IRQs to avoid to
525 * face an IRQ storm which can lock the machine. Disable them
526 * only once. */
527 if (parport_ip32_dma.left == 0 && parport_ip32_dma.irq_on) {
528 pr_debug(PPIP32 "IRQ off (ctx)\n");
529 disable_irq_nosync(MACEISA_PAR_CTXA_IRQ);
530 disable_irq_nosync(MACEISA_PAR_CTXB_IRQ);
531 parport_ip32_dma.irq_on = 0;
532 }
533 spin_unlock_irqrestore(&parport_ip32_dma.lock, flags);
534 }
535
536 /**
537 * parport_ip32_dma_interrupt - DMA interrupt handler
538 * @irq: interrupt number
539 * @dev_id: unused
540 */
parport_ip32_dma_interrupt(int irq,void * dev_id)541 static irqreturn_t parport_ip32_dma_interrupt(int irq, void *dev_id)
542 {
543 if (parport_ip32_dma.left)
544 pr_trace(NULL, "(%d): ctx=%d", irq, parport_ip32_dma.ctx);
545 parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND);
546 return IRQ_HANDLED;
547 }
548
549 #if DEBUG_PARPORT_IP32
parport_ip32_merr_interrupt(int irq,void * dev_id)550 static irqreturn_t parport_ip32_merr_interrupt(int irq, void *dev_id)
551 {
552 pr_trace1(NULL, "(%d)", irq);
553 return IRQ_HANDLED;
554 }
555 #endif
556
557 /**
558 * parport_ip32_dma_start - begins a DMA transfer
559 * @p: partport to work on
560 * @dir: DMA direction: DMA_TO_DEVICE or DMA_FROM_DEVICE
561 * @addr: pointer to data buffer
562 * @count: buffer size
563 *
564 * Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be
565 * correctly balanced.
566 */
parport_ip32_dma_start(struct parport * p,enum dma_data_direction dir,void * addr,size_t count)567 static int parport_ip32_dma_start(struct parport *p,
568 enum dma_data_direction dir, void *addr, size_t count)
569 {
570 unsigned int limit;
571 u64 ctrl;
572
573 pr_trace(NULL, "(%d, %lu)", dir, (unsigned long)count);
574
575 /* FIXME - add support for DMA_FROM_DEVICE. In this case, buffer must
576 * be 64 bytes aligned. */
577 BUG_ON(dir != DMA_TO_DEVICE);
578
579 /* Reset DMA controller */
580 ctrl = MACEPAR_CTLSTAT_RESET;
581 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
582
583 /* DMA IRQs should normally be enabled */
584 if (!parport_ip32_dma.irq_on) {
585 WARN_ON(1);
586 enable_irq(MACEISA_PAR_CTXA_IRQ);
587 enable_irq(MACEISA_PAR_CTXB_IRQ);
588 parport_ip32_dma.irq_on = 1;
589 }
590
591 /* Prepare DMA pointers */
592 parport_ip32_dma.dir = dir;
593 parport_ip32_dma.buf = dma_map_single(&p->bus_dev, addr, count, dir);
594 parport_ip32_dma.len = count;
595 parport_ip32_dma.next = parport_ip32_dma.buf;
596 parport_ip32_dma.left = parport_ip32_dma.len;
597 parport_ip32_dma.ctx = 0;
598
599 /* Setup DMA direction and first two contexts */
600 ctrl = (dir == DMA_TO_DEVICE) ? 0 : MACEPAR_CTLSTAT_DIRECTION;
601 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
602 /* Single transfer should not cross a 4K page boundary */
603 limit = MACEPAR_CONTEXT_DATA_BOUND -
604 (parport_ip32_dma.next & (MACEPAR_CONTEXT_DATA_BOUND - 1));
605 parport_ip32_dma_setup_context(limit);
606 parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND);
607
608 /* Real start of DMA transfer */
609 ctrl |= MACEPAR_CTLSTAT_ENABLE;
610 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
611
612 return 0;
613 }
614
615 /**
616 * parport_ip32_dma_stop - ends a running DMA transfer
617 * @p: partport to work on
618 *
619 * Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be
620 * correctly balanced.
621 */
parport_ip32_dma_stop(struct parport * p)622 static void parport_ip32_dma_stop(struct parport *p)
623 {
624 u64 ctx_a;
625 u64 ctx_b;
626 u64 ctrl;
627 u64 diag;
628 size_t res[2]; /* {[0] = res_a, [1] = res_b} */
629
630 pr_trace(NULL, "()");
631
632 /* Disable IRQs */
633 spin_lock_irq(&parport_ip32_dma.lock);
634 if (parport_ip32_dma.irq_on) {
635 pr_debug(PPIP32 "IRQ off (stop)\n");
636 disable_irq_nosync(MACEISA_PAR_CTXA_IRQ);
637 disable_irq_nosync(MACEISA_PAR_CTXB_IRQ);
638 parport_ip32_dma.irq_on = 0;
639 }
640 spin_unlock_irq(&parport_ip32_dma.lock);
641 /* Force IRQ synchronization, even if the IRQs were disabled
642 * elsewhere. */
643 synchronize_irq(MACEISA_PAR_CTXA_IRQ);
644 synchronize_irq(MACEISA_PAR_CTXB_IRQ);
645
646 /* Stop DMA transfer */
647 ctrl = readq(&mace->perif.ctrl.parport.cntlstat);
648 ctrl &= ~MACEPAR_CTLSTAT_ENABLE;
649 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
650
651 /* Adjust residue (parport_ip32_dma.left) */
652 ctx_a = readq(&mace->perif.ctrl.parport.context_a);
653 ctx_b = readq(&mace->perif.ctrl.parport.context_b);
654 ctrl = readq(&mace->perif.ctrl.parport.cntlstat);
655 diag = readq(&mace->perif.ctrl.parport.diagnostic);
656 res[0] = (ctrl & MACEPAR_CTLSTAT_CTXA_VALID) ?
657 1 + ((ctx_a & MACEPAR_CONTEXT_DATALEN_MASK) >>
658 MACEPAR_CONTEXT_DATALEN_SHIFT) :
659 0;
660 res[1] = (ctrl & MACEPAR_CTLSTAT_CTXB_VALID) ?
661 1 + ((ctx_b & MACEPAR_CONTEXT_DATALEN_MASK) >>
662 MACEPAR_CONTEXT_DATALEN_SHIFT) :
663 0;
664 if (diag & MACEPAR_DIAG_DMACTIVE)
665 res[(diag & MACEPAR_DIAG_CTXINUSE) != 0] =
666 1 + ((diag & MACEPAR_DIAG_CTRMASK) >>
667 MACEPAR_DIAG_CTRSHIFT);
668 parport_ip32_dma.left += res[0] + res[1];
669
670 /* Reset DMA controller, and re-enable IRQs */
671 ctrl = MACEPAR_CTLSTAT_RESET;
672 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
673 pr_debug(PPIP32 "IRQ on (stop)\n");
674 enable_irq(MACEISA_PAR_CTXA_IRQ);
675 enable_irq(MACEISA_PAR_CTXB_IRQ);
676 parport_ip32_dma.irq_on = 1;
677
678 dma_unmap_single(&p->bus_dev, parport_ip32_dma.buf,
679 parport_ip32_dma.len, parport_ip32_dma.dir);
680 }
681
682 /**
683 * parport_ip32_dma_get_residue - get residue from last DMA transfer
684 *
685 * Returns the number of bytes remaining from last DMA transfer.
686 */
parport_ip32_dma_get_residue(void)687 static inline size_t parport_ip32_dma_get_residue(void)
688 {
689 return parport_ip32_dma.left;
690 }
691
692 /**
693 * parport_ip32_dma_register - initialize DMA engine
694 *
695 * Returns zero for success.
696 */
parport_ip32_dma_register(void)697 static int parport_ip32_dma_register(void)
698 {
699 int err;
700
701 spin_lock_init(&parport_ip32_dma.lock);
702 parport_ip32_dma.irq_on = 1;
703
704 /* Reset DMA controller */
705 writeq(MACEPAR_CTLSTAT_RESET, &mace->perif.ctrl.parport.cntlstat);
706
707 /* Request IRQs */
708 err = request_irq(MACEISA_PAR_CTXA_IRQ, parport_ip32_dma_interrupt,
709 0, "parport_ip32", NULL);
710 if (err)
711 goto fail_a;
712 err = request_irq(MACEISA_PAR_CTXB_IRQ, parport_ip32_dma_interrupt,
713 0, "parport_ip32", NULL);
714 if (err)
715 goto fail_b;
716 #if DEBUG_PARPORT_IP32
717 /* FIXME - what is this IRQ for? */
718 err = request_irq(MACEISA_PAR_MERR_IRQ, parport_ip32_merr_interrupt,
719 0, "parport_ip32", NULL);
720 if (err)
721 goto fail_merr;
722 #endif
723 return 0;
724
725 #if DEBUG_PARPORT_IP32
726 fail_merr:
727 free_irq(MACEISA_PAR_CTXB_IRQ, NULL);
728 #endif
729 fail_b:
730 free_irq(MACEISA_PAR_CTXA_IRQ, NULL);
731 fail_a:
732 return err;
733 }
734
735 /**
736 * parport_ip32_dma_unregister - release and free resources for DMA engine
737 */
parport_ip32_dma_unregister(void)738 static void parport_ip32_dma_unregister(void)
739 {
740 #if DEBUG_PARPORT_IP32
741 free_irq(MACEISA_PAR_MERR_IRQ, NULL);
742 #endif
743 free_irq(MACEISA_PAR_CTXB_IRQ, NULL);
744 free_irq(MACEISA_PAR_CTXA_IRQ, NULL);
745 }
746
747 /*--- Interrupt handlers and associates --------------------------------*/
748
749 /**
750 * parport_ip32_wakeup - wakes up code waiting for an interrupt
751 * @p: pointer to &struct parport
752 */
parport_ip32_wakeup(struct parport * p)753 static inline void parport_ip32_wakeup(struct parport *p)
754 {
755 struct parport_ip32_private * const priv = p->physport->private_data;
756 complete(&priv->irq_complete);
757 }
758
759 /**
760 * parport_ip32_interrupt - interrupt handler
761 * @irq: interrupt number
762 * @dev_id: pointer to &struct parport
763 *
764 * Caught interrupts are forwarded to the upper parport layer if IRQ_mode is
765 * %PARPORT_IP32_IRQ_FWD.
766 */
parport_ip32_interrupt(int irq,void * dev_id)767 static irqreturn_t parport_ip32_interrupt(int irq, void *dev_id)
768 {
769 struct parport * const p = dev_id;
770 struct parport_ip32_private * const priv = p->physport->private_data;
771 enum parport_ip32_irq_mode irq_mode = priv->irq_mode;
772
773 switch (irq_mode) {
774 case PARPORT_IP32_IRQ_FWD:
775 return parport_irq_handler(irq, dev_id);
776
777 case PARPORT_IP32_IRQ_HERE:
778 parport_ip32_wakeup(p);
779 break;
780 }
781
782 return IRQ_HANDLED;
783 }
784
785 /*--- Some utility function to manipulate ECR register -----------------*/
786
787 /**
788 * parport_ip32_read_econtrol - read contents of the ECR register
789 * @p: pointer to &struct parport
790 */
parport_ip32_read_econtrol(struct parport * p)791 static inline unsigned int parport_ip32_read_econtrol(struct parport *p)
792 {
793 struct parport_ip32_private * const priv = p->physport->private_data;
794 return readb(priv->regs.ecr);
795 }
796
797 /**
798 * parport_ip32_write_econtrol - write new contents to the ECR register
799 * @p: pointer to &struct parport
800 * @c: new value to write
801 */
parport_ip32_write_econtrol(struct parport * p,unsigned int c)802 static inline void parport_ip32_write_econtrol(struct parport *p,
803 unsigned int c)
804 {
805 struct parport_ip32_private * const priv = p->physport->private_data;
806 writeb(c, priv->regs.ecr);
807 }
808
809 /**
810 * parport_ip32_frob_econtrol - change bits from the ECR register
811 * @p: pointer to &struct parport
812 * @mask: bit mask of bits to change
813 * @val: new value for changed bits
814 *
815 * Read from the ECR, mask out the bits in @mask, exclusive-or with the bits
816 * in @val, and write the result to the ECR.
817 */
parport_ip32_frob_econtrol(struct parport * p,unsigned int mask,unsigned int val)818 static inline void parport_ip32_frob_econtrol(struct parport *p,
819 unsigned int mask,
820 unsigned int val)
821 {
822 unsigned int c;
823 c = (parport_ip32_read_econtrol(p) & ~mask) ^ val;
824 parport_ip32_write_econtrol(p, c);
825 }
826
827 /**
828 * parport_ip32_set_mode - change mode of ECP port
829 * @p: pointer to &struct parport
830 * @mode: new mode to write in ECR
831 *
832 * ECR is reset in a sane state (interrupts and DMA disabled), and placed in
833 * mode @mode. Go through PS2 mode if needed.
834 */
parport_ip32_set_mode(struct parport * p,unsigned int mode)835 static void parport_ip32_set_mode(struct parport *p, unsigned int mode)
836 {
837 unsigned int omode;
838
839 mode &= ECR_MODE_MASK;
840 omode = parport_ip32_read_econtrol(p) & ECR_MODE_MASK;
841
842 if (!(mode == ECR_MODE_SPP || mode == ECR_MODE_PS2
843 || omode == ECR_MODE_SPP || omode == ECR_MODE_PS2)) {
844 /* We have to go through PS2 mode */
845 unsigned int ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
846 parport_ip32_write_econtrol(p, ecr);
847 }
848 parport_ip32_write_econtrol(p, mode | ECR_nERRINTR | ECR_SERVINTR);
849 }
850
851 /*--- Basic functions needed for parport -------------------------------*/
852
853 /**
854 * parport_ip32_read_data - return current contents of the DATA register
855 * @p: pointer to &struct parport
856 */
parport_ip32_read_data(struct parport * p)857 static inline unsigned char parport_ip32_read_data(struct parport *p)
858 {
859 struct parport_ip32_private * const priv = p->physport->private_data;
860 return readb(priv->regs.data);
861 }
862
863 /**
864 * parport_ip32_write_data - set new contents for the DATA register
865 * @p: pointer to &struct parport
866 * @d: new value to write
867 */
parport_ip32_write_data(struct parport * p,unsigned char d)868 static inline void parport_ip32_write_data(struct parport *p, unsigned char d)
869 {
870 struct parport_ip32_private * const priv = p->physport->private_data;
871 writeb(d, priv->regs.data);
872 }
873
874 /**
875 * parport_ip32_read_status - return current contents of the DSR register
876 * @p: pointer to &struct parport
877 */
parport_ip32_read_status(struct parport * p)878 static inline unsigned char parport_ip32_read_status(struct parport *p)
879 {
880 struct parport_ip32_private * const priv = p->physport->private_data;
881 return readb(priv->regs.dsr);
882 }
883
884 /**
885 * __parport_ip32_read_control - return cached contents of the DCR register
886 * @p: pointer to &struct parport
887 */
__parport_ip32_read_control(struct parport * p)888 static inline unsigned int __parport_ip32_read_control(struct parport *p)
889 {
890 struct parport_ip32_private * const priv = p->physport->private_data;
891 return priv->dcr_cache; /* use soft copy */
892 }
893
894 /**
895 * __parport_ip32_write_control - set new contents for the DCR register
896 * @p: pointer to &struct parport
897 * @c: new value to write
898 */
__parport_ip32_write_control(struct parport * p,unsigned int c)899 static inline void __parport_ip32_write_control(struct parport *p,
900 unsigned int c)
901 {
902 struct parport_ip32_private * const priv = p->physport->private_data;
903 CHECK_EXTRA_BITS(p, c, priv->dcr_writable);
904 c &= priv->dcr_writable; /* only writable bits */
905 writeb(c, priv->regs.dcr);
906 priv->dcr_cache = c; /* update soft copy */
907 }
908
909 /**
910 * __parport_ip32_frob_control - change bits from the DCR register
911 * @p: pointer to &struct parport
912 * @mask: bit mask of bits to change
913 * @val: new value for changed bits
914 *
915 * This is equivalent to read from the DCR, mask out the bits in @mask,
916 * exclusive-or with the bits in @val, and write the result to the DCR.
917 * Actually, the cached contents of the DCR is used.
918 */
__parport_ip32_frob_control(struct parport * p,unsigned int mask,unsigned int val)919 static inline void __parport_ip32_frob_control(struct parport *p,
920 unsigned int mask,
921 unsigned int val)
922 {
923 unsigned int c;
924 c = (__parport_ip32_read_control(p) & ~mask) ^ val;
925 __parport_ip32_write_control(p, c);
926 }
927
928 /**
929 * parport_ip32_read_control - return cached contents of the DCR register
930 * @p: pointer to &struct parport
931 *
932 * The return value is masked so as to only return the value of %DCR_STROBE,
933 * %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT.
934 */
parport_ip32_read_control(struct parport * p)935 static inline unsigned char parport_ip32_read_control(struct parport *p)
936 {
937 const unsigned int rm =
938 DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
939 return __parport_ip32_read_control(p) & rm;
940 }
941
942 /**
943 * parport_ip32_write_control - set new contents for the DCR register
944 * @p: pointer to &struct parport
945 * @c: new value to write
946 *
947 * The value is masked so as to only change the value of %DCR_STROBE,
948 * %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT.
949 */
parport_ip32_write_control(struct parport * p,unsigned char c)950 static inline void parport_ip32_write_control(struct parport *p,
951 unsigned char c)
952 {
953 const unsigned int wm =
954 DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
955 CHECK_EXTRA_BITS(p, c, wm);
956 __parport_ip32_frob_control(p, wm, c & wm);
957 }
958
959 /**
960 * parport_ip32_frob_control - change bits from the DCR register
961 * @p: pointer to &struct parport
962 * @mask: bit mask of bits to change
963 * @val: new value for changed bits
964 *
965 * This differs from __parport_ip32_frob_control() in that it only allows to
966 * change the value of %DCR_STROBE, %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT.
967 */
parport_ip32_frob_control(struct parport * p,unsigned char mask,unsigned char val)968 static inline unsigned char parport_ip32_frob_control(struct parport *p,
969 unsigned char mask,
970 unsigned char val)
971 {
972 const unsigned int wm =
973 DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
974 CHECK_EXTRA_BITS(p, mask, wm);
975 CHECK_EXTRA_BITS(p, val, wm);
976 __parport_ip32_frob_control(p, mask & wm, val & wm);
977 return parport_ip32_read_control(p);
978 }
979
980 /**
981 * parport_ip32_disable_irq - disable interrupts on the rising edge of nACK
982 * @p: pointer to &struct parport
983 */
parport_ip32_disable_irq(struct parport * p)984 static inline void parport_ip32_disable_irq(struct parport *p)
985 {
986 __parport_ip32_frob_control(p, DCR_IRQ, 0);
987 }
988
989 /**
990 * parport_ip32_enable_irq - enable interrupts on the rising edge of nACK
991 * @p: pointer to &struct parport
992 */
parport_ip32_enable_irq(struct parport * p)993 static inline void parport_ip32_enable_irq(struct parport *p)
994 {
995 __parport_ip32_frob_control(p, DCR_IRQ, DCR_IRQ);
996 }
997
998 /**
999 * parport_ip32_data_forward - enable host-to-peripheral communications
1000 * @p: pointer to &struct parport
1001 *
1002 * Enable the data line drivers, for 8-bit host-to-peripheral communications.
1003 */
parport_ip32_data_forward(struct parport * p)1004 static inline void parport_ip32_data_forward(struct parport *p)
1005 {
1006 __parport_ip32_frob_control(p, DCR_DIR, 0);
1007 }
1008
1009 /**
1010 * parport_ip32_data_reverse - enable peripheral-to-host communications
1011 * @p: pointer to &struct parport
1012 *
1013 * Place the data bus in a high impedance state, if @p->modes has the
1014 * PARPORT_MODE_TRISTATE bit set.
1015 */
parport_ip32_data_reverse(struct parport * p)1016 static inline void parport_ip32_data_reverse(struct parport *p)
1017 {
1018 __parport_ip32_frob_control(p, DCR_DIR, DCR_DIR);
1019 }
1020
1021 /**
1022 * parport_ip32_init_state - for core parport code
1023 * @dev: pointer to &struct pardevice
1024 * @s: pointer to &struct parport_state to initialize
1025 */
parport_ip32_init_state(struct pardevice * dev,struct parport_state * s)1026 static void parport_ip32_init_state(struct pardevice *dev,
1027 struct parport_state *s)
1028 {
1029 s->u.ip32.dcr = DCR_SELECT | DCR_nINIT;
1030 s->u.ip32.ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
1031 }
1032
1033 /**
1034 * parport_ip32_save_state - for core parport code
1035 * @p: pointer to &struct parport
1036 * @s: pointer to &struct parport_state to save state to
1037 */
parport_ip32_save_state(struct parport * p,struct parport_state * s)1038 static void parport_ip32_save_state(struct parport *p,
1039 struct parport_state *s)
1040 {
1041 s->u.ip32.dcr = __parport_ip32_read_control(p);
1042 s->u.ip32.ecr = parport_ip32_read_econtrol(p);
1043 }
1044
1045 /**
1046 * parport_ip32_restore_state - for core parport code
1047 * @p: pointer to &struct parport
1048 * @s: pointer to &struct parport_state to restore state from
1049 */
parport_ip32_restore_state(struct parport * p,struct parport_state * s)1050 static void parport_ip32_restore_state(struct parport *p,
1051 struct parport_state *s)
1052 {
1053 parport_ip32_set_mode(p, s->u.ip32.ecr & ECR_MODE_MASK);
1054 parport_ip32_write_econtrol(p, s->u.ip32.ecr);
1055 __parport_ip32_write_control(p, s->u.ip32.dcr);
1056 }
1057
1058 /*--- EPP mode functions -----------------------------------------------*/
1059
1060 /**
1061 * parport_ip32_clear_epp_timeout - clear Timeout bit in EPP mode
1062 * @p: pointer to &struct parport
1063 *
1064 * Returns 1 if the Timeout bit is clear, and 0 otherwise.
1065 */
parport_ip32_clear_epp_timeout(struct parport * p)1066 static unsigned int parport_ip32_clear_epp_timeout(struct parport *p)
1067 {
1068 struct parport_ip32_private * const priv = p->physport->private_data;
1069 unsigned int cleared;
1070
1071 if (!(parport_ip32_read_status(p) & DSR_TIMEOUT))
1072 cleared = 1;
1073 else {
1074 unsigned int r;
1075 /* To clear timeout some chips require double read */
1076 parport_ip32_read_status(p);
1077 r = parport_ip32_read_status(p);
1078 /* Some reset by writing 1 */
1079 writeb(r | DSR_TIMEOUT, priv->regs.dsr);
1080 /* Others by writing 0 */
1081 writeb(r & ~DSR_TIMEOUT, priv->regs.dsr);
1082
1083 r = parport_ip32_read_status(p);
1084 cleared = !(r & DSR_TIMEOUT);
1085 }
1086
1087 pr_trace(p, "(): %s", cleared ? "cleared" : "failed");
1088 return cleared;
1089 }
1090
1091 /**
1092 * parport_ip32_epp_read - generic EPP read function
1093 * @eppreg: I/O register to read from
1094 * @p: pointer to &struct parport
1095 * @buf: buffer to store read data
1096 * @len: length of buffer @buf
1097 * @flags: may be PARPORT_EPP_FAST
1098 */
parport_ip32_epp_read(void __iomem * eppreg,struct parport * p,void * buf,size_t len,int flags)1099 static size_t parport_ip32_epp_read(void __iomem *eppreg,
1100 struct parport *p, void *buf,
1101 size_t len, int flags)
1102 {
1103 struct parport_ip32_private * const priv = p->physport->private_data;
1104 size_t got;
1105 parport_ip32_set_mode(p, ECR_MODE_EPP);
1106 parport_ip32_data_reverse(p);
1107 parport_ip32_write_control(p, DCR_nINIT);
1108 if ((flags & PARPORT_EPP_FAST) && (len > 1)) {
1109 readsb(eppreg, buf, len);
1110 if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
1111 parport_ip32_clear_epp_timeout(p);
1112 return -EIO;
1113 }
1114 got = len;
1115 } else {
1116 u8 *bufp = buf;
1117 for (got = 0; got < len; got++) {
1118 *bufp++ = readb(eppreg);
1119 if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
1120 parport_ip32_clear_epp_timeout(p);
1121 break;
1122 }
1123 }
1124 }
1125 parport_ip32_data_forward(p);
1126 parport_ip32_set_mode(p, ECR_MODE_PS2);
1127 return got;
1128 }
1129
1130 /**
1131 * parport_ip32_epp_write - generic EPP write function
1132 * @eppreg: I/O register to write to
1133 * @p: pointer to &struct parport
1134 * @buf: buffer of data to write
1135 * @len: length of buffer @buf
1136 * @flags: may be PARPORT_EPP_FAST
1137 */
parport_ip32_epp_write(void __iomem * eppreg,struct parport * p,const void * buf,size_t len,int flags)1138 static size_t parport_ip32_epp_write(void __iomem *eppreg,
1139 struct parport *p, const void *buf,
1140 size_t len, int flags)
1141 {
1142 struct parport_ip32_private * const priv = p->physport->private_data;
1143 size_t written;
1144 parport_ip32_set_mode(p, ECR_MODE_EPP);
1145 parport_ip32_data_forward(p);
1146 parport_ip32_write_control(p, DCR_nINIT);
1147 if ((flags & PARPORT_EPP_FAST) && (len > 1)) {
1148 writesb(eppreg, buf, len);
1149 if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
1150 parport_ip32_clear_epp_timeout(p);
1151 return -EIO;
1152 }
1153 written = len;
1154 } else {
1155 const u8 *bufp = buf;
1156 for (written = 0; written < len; written++) {
1157 writeb(*bufp++, eppreg);
1158 if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
1159 parport_ip32_clear_epp_timeout(p);
1160 break;
1161 }
1162 }
1163 }
1164 parport_ip32_set_mode(p, ECR_MODE_PS2);
1165 return written;
1166 }
1167
1168 /**
1169 * parport_ip32_epp_read_data - read a block of data in EPP mode
1170 * @p: pointer to &struct parport
1171 * @buf: buffer to store read data
1172 * @len: length of buffer @buf
1173 * @flags: may be PARPORT_EPP_FAST
1174 */
parport_ip32_epp_read_data(struct parport * p,void * buf,size_t len,int flags)1175 static size_t parport_ip32_epp_read_data(struct parport *p, void *buf,
1176 size_t len, int flags)
1177 {
1178 struct parport_ip32_private * const priv = p->physport->private_data;
1179 return parport_ip32_epp_read(priv->regs.eppData0, p, buf, len, flags);
1180 }
1181
1182 /**
1183 * parport_ip32_epp_write_data - write a block of data in EPP mode
1184 * @p: pointer to &struct parport
1185 * @buf: buffer of data to write
1186 * @len: length of buffer @buf
1187 * @flags: may be PARPORT_EPP_FAST
1188 */
parport_ip32_epp_write_data(struct parport * p,const void * buf,size_t len,int flags)1189 static size_t parport_ip32_epp_write_data(struct parport *p, const void *buf,
1190 size_t len, int flags)
1191 {
1192 struct parport_ip32_private * const priv = p->physport->private_data;
1193 return parport_ip32_epp_write(priv->regs.eppData0, p, buf, len, flags);
1194 }
1195
1196 /**
1197 * parport_ip32_epp_read_addr - read a block of addresses in EPP mode
1198 * @p: pointer to &struct parport
1199 * @buf: buffer to store read data
1200 * @len: length of buffer @buf
1201 * @flags: may be PARPORT_EPP_FAST
1202 */
parport_ip32_epp_read_addr(struct parport * p,void * buf,size_t len,int flags)1203 static size_t parport_ip32_epp_read_addr(struct parport *p, void *buf,
1204 size_t len, int flags)
1205 {
1206 struct parport_ip32_private * const priv = p->physport->private_data;
1207 return parport_ip32_epp_read(priv->regs.eppAddr, p, buf, len, flags);
1208 }
1209
1210 /**
1211 * parport_ip32_epp_write_addr - write a block of addresses in EPP mode
1212 * @p: pointer to &struct parport
1213 * @buf: buffer of data to write
1214 * @len: length of buffer @buf
1215 * @flags: may be PARPORT_EPP_FAST
1216 */
parport_ip32_epp_write_addr(struct parport * p,const void * buf,size_t len,int flags)1217 static size_t parport_ip32_epp_write_addr(struct parport *p, const void *buf,
1218 size_t len, int flags)
1219 {
1220 struct parport_ip32_private * const priv = p->physport->private_data;
1221 return parport_ip32_epp_write(priv->regs.eppAddr, p, buf, len, flags);
1222 }
1223
1224 /*--- ECP mode functions (FIFO) ----------------------------------------*/
1225
1226 /**
1227 * parport_ip32_fifo_wait_break - check if the waiting function should return
1228 * @p: pointer to &struct parport
1229 * @expire: timeout expiring date, in jiffies
1230 *
1231 * parport_ip32_fifo_wait_break() checks if the waiting function should return
1232 * immediately or not. The break conditions are:
1233 * - expired timeout;
1234 * - a pending signal;
1235 * - nFault asserted low.
1236 * This function also calls cond_resched().
1237 */
parport_ip32_fifo_wait_break(struct parport * p,unsigned long expire)1238 static unsigned int parport_ip32_fifo_wait_break(struct parport *p,
1239 unsigned long expire)
1240 {
1241 cond_resched();
1242 if (time_after(jiffies, expire)) {
1243 pr_debug1(PPIP32 "%s: FIFO write timed out\n", p->name);
1244 return 1;
1245 }
1246 if (signal_pending(current)) {
1247 pr_debug1(PPIP32 "%s: Signal pending\n", p->name);
1248 return 1;
1249 }
1250 if (!(parport_ip32_read_status(p) & DSR_nFAULT)) {
1251 pr_debug1(PPIP32 "%s: nFault asserted low\n", p->name);
1252 return 1;
1253 }
1254 return 0;
1255 }
1256
1257 /**
1258 * parport_ip32_fwp_wait_polling - wait for FIFO to empty (polling)
1259 * @p: pointer to &struct parport
1260 *
1261 * Returns the number of bytes that can safely be written in the FIFO. A
1262 * return value of zero means that the calling function should terminate as
1263 * fast as possible.
1264 */
parport_ip32_fwp_wait_polling(struct parport * p)1265 static unsigned int parport_ip32_fwp_wait_polling(struct parport *p)
1266 {
1267 struct parport_ip32_private * const priv = p->physport->private_data;
1268 struct parport * const physport = p->physport;
1269 unsigned long expire;
1270 unsigned int count;
1271 unsigned int ecr;
1272
1273 expire = jiffies + physport->cad->timeout;
1274 count = 0;
1275 while (1) {
1276 if (parport_ip32_fifo_wait_break(p, expire))
1277 break;
1278
1279 /* Check FIFO state. We do nothing when the FIFO is nor full,
1280 * nor empty. It appears that the FIFO full bit is not always
1281 * reliable, the FIFO state is sometimes wrongly reported, and
1282 * the chip gets confused if we give it another byte. */
1283 ecr = parport_ip32_read_econtrol(p);
1284 if (ecr & ECR_F_EMPTY) {
1285 /* FIFO is empty, fill it up */
1286 count = priv->fifo_depth;
1287 break;
1288 }
1289
1290 /* Wait a moment... */
1291 udelay(FIFO_POLLING_INTERVAL);
1292 } /* while (1) */
1293
1294 return count;
1295 }
1296
1297 /**
1298 * parport_ip32_fwp_wait_interrupt - wait for FIFO to empty (interrupt-driven)
1299 * @p: pointer to &struct parport
1300 *
1301 * Returns the number of bytes that can safely be written in the FIFO. A
1302 * return value of zero means that the calling function should terminate as
1303 * fast as possible.
1304 */
parport_ip32_fwp_wait_interrupt(struct parport * p)1305 static unsigned int parport_ip32_fwp_wait_interrupt(struct parport *p)
1306 {
1307 static unsigned int lost_interrupt = 0;
1308 struct parport_ip32_private * const priv = p->physport->private_data;
1309 struct parport * const physport = p->physport;
1310 unsigned long nfault_timeout;
1311 unsigned long expire;
1312 unsigned int count;
1313 unsigned int ecr;
1314
1315 nfault_timeout = min((unsigned long)physport->cad->timeout,
1316 msecs_to_jiffies(FIFO_NFAULT_TIMEOUT));
1317 expire = jiffies + physport->cad->timeout;
1318 count = 0;
1319 while (1) {
1320 if (parport_ip32_fifo_wait_break(p, expire))
1321 break;
1322
1323 /* Initialize mutex used to take interrupts into account */
1324 reinit_completion(&priv->irq_complete);
1325
1326 /* Enable serviceIntr */
1327 parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0);
1328
1329 /* Enabling serviceIntr while the FIFO is empty does not
1330 * always generate an interrupt, so check for emptiness
1331 * now. */
1332 ecr = parport_ip32_read_econtrol(p);
1333 if (!(ecr & ECR_F_EMPTY)) {
1334 /* FIFO is not empty: wait for an interrupt or a
1335 * timeout to occur */
1336 wait_for_completion_interruptible_timeout(
1337 &priv->irq_complete, nfault_timeout);
1338 ecr = parport_ip32_read_econtrol(p);
1339 if ((ecr & ECR_F_EMPTY) && !(ecr & ECR_SERVINTR)
1340 && !lost_interrupt) {
1341 pr_warn(PPIP32 "%s: lost interrupt in %s\n",
1342 p->name, __func__);
1343 lost_interrupt = 1;
1344 }
1345 }
1346
1347 /* Disable serviceIntr */
1348 parport_ip32_frob_econtrol(p, ECR_SERVINTR, ECR_SERVINTR);
1349
1350 /* Check FIFO state */
1351 if (ecr & ECR_F_EMPTY) {
1352 /* FIFO is empty, fill it up */
1353 count = priv->fifo_depth;
1354 break;
1355 } else if (ecr & ECR_SERVINTR) {
1356 /* FIFO is not empty, but we know that can safely push
1357 * writeIntrThreshold bytes into it */
1358 count = priv->writeIntrThreshold;
1359 break;
1360 }
1361 /* FIFO is not empty, and we did not get any interrupt.
1362 * Either it's time to check for nFault, or a signal is
1363 * pending. This is verified in
1364 * parport_ip32_fifo_wait_break(), so we continue the loop. */
1365 } /* while (1) */
1366
1367 return count;
1368 }
1369
1370 /**
1371 * parport_ip32_fifo_write_block_pio - write a block of data (PIO mode)
1372 * @p: pointer to &struct parport
1373 * @buf: buffer of data to write
1374 * @len: length of buffer @buf
1375 *
1376 * Uses PIO to write the contents of the buffer @buf into the parallel port
1377 * FIFO. Returns the number of bytes that were actually written. It can work
1378 * with or without the help of interrupts. The parallel port must be
1379 * correctly initialized before calling parport_ip32_fifo_write_block_pio().
1380 */
parport_ip32_fifo_write_block_pio(struct parport * p,const void * buf,size_t len)1381 static size_t parport_ip32_fifo_write_block_pio(struct parport *p,
1382 const void *buf, size_t len)
1383 {
1384 struct parport_ip32_private * const priv = p->physport->private_data;
1385 const u8 *bufp = buf;
1386 size_t left = len;
1387
1388 priv->irq_mode = PARPORT_IP32_IRQ_HERE;
1389
1390 while (left > 0) {
1391 unsigned int count;
1392
1393 count = (p->irq == PARPORT_IRQ_NONE) ?
1394 parport_ip32_fwp_wait_polling(p) :
1395 parport_ip32_fwp_wait_interrupt(p);
1396 if (count == 0)
1397 break; /* Transmission should be stopped */
1398 if (count > left)
1399 count = left;
1400 if (count == 1) {
1401 writeb(*bufp, priv->regs.fifo);
1402 bufp++, left--;
1403 } else {
1404 writesb(priv->regs.fifo, bufp, count);
1405 bufp += count, left -= count;
1406 }
1407 }
1408
1409 priv->irq_mode = PARPORT_IP32_IRQ_FWD;
1410
1411 return len - left;
1412 }
1413
1414 /**
1415 * parport_ip32_fifo_write_block_dma - write a block of data (DMA mode)
1416 * @p: pointer to &struct parport
1417 * @buf: buffer of data to write
1418 * @len: length of buffer @buf
1419 *
1420 * Uses DMA to write the contents of the buffer @buf into the parallel port
1421 * FIFO. Returns the number of bytes that were actually written. The
1422 * parallel port must be correctly initialized before calling
1423 * parport_ip32_fifo_write_block_dma().
1424 */
parport_ip32_fifo_write_block_dma(struct parport * p,const void * buf,size_t len)1425 static size_t parport_ip32_fifo_write_block_dma(struct parport *p,
1426 const void *buf, size_t len)
1427 {
1428 struct parport_ip32_private * const priv = p->physport->private_data;
1429 struct parport * const physport = p->physport;
1430 unsigned long nfault_timeout;
1431 unsigned long expire;
1432 size_t written;
1433 unsigned int ecr;
1434
1435 priv->irq_mode = PARPORT_IP32_IRQ_HERE;
1436
1437 parport_ip32_dma_start(p, DMA_TO_DEVICE, (void *)buf, len);
1438 reinit_completion(&priv->irq_complete);
1439 parport_ip32_frob_econtrol(p, ECR_DMAEN | ECR_SERVINTR, ECR_DMAEN);
1440
1441 nfault_timeout = min((unsigned long)physport->cad->timeout,
1442 msecs_to_jiffies(FIFO_NFAULT_TIMEOUT));
1443 expire = jiffies + physport->cad->timeout;
1444 while (1) {
1445 if (parport_ip32_fifo_wait_break(p, expire))
1446 break;
1447 wait_for_completion_interruptible_timeout(&priv->irq_complete,
1448 nfault_timeout);
1449 ecr = parport_ip32_read_econtrol(p);
1450 if (ecr & ECR_SERVINTR)
1451 break; /* DMA transfer just finished */
1452 }
1453 parport_ip32_dma_stop(p);
1454 written = len - parport_ip32_dma_get_residue();
1455
1456 priv->irq_mode = PARPORT_IP32_IRQ_FWD;
1457
1458 return written;
1459 }
1460
1461 /**
1462 * parport_ip32_fifo_write_block - write a block of data
1463 * @p: pointer to &struct parport
1464 * @buf: buffer of data to write
1465 * @len: length of buffer @buf
1466 *
1467 * Uses PIO or DMA to write the contents of the buffer @buf into the parallel
1468 * p FIFO. Returns the number of bytes that were actually written.
1469 */
parport_ip32_fifo_write_block(struct parport * p,const void * buf,size_t len)1470 static size_t parport_ip32_fifo_write_block(struct parport *p,
1471 const void *buf, size_t len)
1472 {
1473 size_t written = 0;
1474 if (len)
1475 /* FIXME - Maybe some threshold value should be set for @len
1476 * under which we revert to PIO mode? */
1477 written = (p->modes & PARPORT_MODE_DMA) ?
1478 parport_ip32_fifo_write_block_dma(p, buf, len) :
1479 parport_ip32_fifo_write_block_pio(p, buf, len);
1480 return written;
1481 }
1482
1483 /**
1484 * parport_ip32_drain_fifo - wait for FIFO to empty
1485 * @p: pointer to &struct parport
1486 * @timeout: timeout, in jiffies
1487 *
1488 * This function waits for FIFO to empty. It returns 1 when FIFO is empty, or
1489 * 0 if the timeout @timeout is reached before, or if a signal is pending.
1490 */
parport_ip32_drain_fifo(struct parport * p,unsigned long timeout)1491 static unsigned int parport_ip32_drain_fifo(struct parport *p,
1492 unsigned long timeout)
1493 {
1494 unsigned long expire = jiffies + timeout;
1495 unsigned int polling_interval;
1496 unsigned int counter;
1497
1498 /* Busy wait for approx. 200us */
1499 for (counter = 0; counter < 40; counter++) {
1500 if (parport_ip32_read_econtrol(p) & ECR_F_EMPTY)
1501 break;
1502 if (time_after(jiffies, expire))
1503 break;
1504 if (signal_pending(current))
1505 break;
1506 udelay(5);
1507 }
1508 /* Poll slowly. Polling interval starts with 1 millisecond, and is
1509 * increased exponentially until 128. */
1510 polling_interval = 1; /* msecs */
1511 while (!(parport_ip32_read_econtrol(p) & ECR_F_EMPTY)) {
1512 if (time_after_eq(jiffies, expire))
1513 break;
1514 msleep_interruptible(polling_interval);
1515 if (signal_pending(current))
1516 break;
1517 if (polling_interval < 128)
1518 polling_interval *= 2;
1519 }
1520
1521 return !!(parport_ip32_read_econtrol(p) & ECR_F_EMPTY);
1522 }
1523
1524 /**
1525 * parport_ip32_get_fifo_residue - reset FIFO
1526 * @p: pointer to &struct parport
1527 * @mode: current operation mode (ECR_MODE_PPF or ECR_MODE_ECP)
1528 *
1529 * This function resets FIFO, and returns the number of bytes remaining in it.
1530 */
parport_ip32_get_fifo_residue(struct parport * p,unsigned int mode)1531 static unsigned int parport_ip32_get_fifo_residue(struct parport *p,
1532 unsigned int mode)
1533 {
1534 struct parport_ip32_private * const priv = p->physport->private_data;
1535 unsigned int residue;
1536 unsigned int cnfga;
1537
1538 /* FIXME - We are missing one byte if the printer is off-line. I
1539 * don't know how to detect this. It looks that the full bit is not
1540 * always reliable. For the moment, the problem is avoided in most
1541 * cases by testing for BUSY in parport_ip32_compat_write_data().
1542 */
1543 if (parport_ip32_read_econtrol(p) & ECR_F_EMPTY)
1544 residue = 0;
1545 else {
1546 pr_debug1(PPIP32 "%s: FIFO is stuck\n", p->name);
1547
1548 /* Stop all transfers.
1549 *
1550 * Microsoft's document instructs to drive DCR_STROBE to 0,
1551 * but it doesn't work (at least in Compatibility mode, not
1552 * tested in ECP mode). Switching directly to Test mode (as
1553 * in parport_pc) is not an option: it does confuse the port,
1554 * ECP service interrupts are no more working after that. A
1555 * hard reset is then needed to revert to a sane state.
1556 *
1557 * Let's hope that the FIFO is really stuck and that the
1558 * peripheral doesn't wake up now.
1559 */
1560 parport_ip32_frob_control(p, DCR_STROBE, 0);
1561
1562 /* Fill up FIFO */
1563 for (residue = priv->fifo_depth; residue > 0; residue--) {
1564 if (parport_ip32_read_econtrol(p) & ECR_F_FULL)
1565 break;
1566 writeb(0x00, priv->regs.fifo);
1567 }
1568 }
1569 if (residue)
1570 pr_debug1(PPIP32 "%s: %d PWord%s left in FIFO\n",
1571 p->name, residue,
1572 (residue == 1) ? " was" : "s were");
1573
1574 /* Now reset the FIFO */
1575 parport_ip32_set_mode(p, ECR_MODE_PS2);
1576
1577 /* Host recovery for ECP mode */
1578 if (mode == ECR_MODE_ECP) {
1579 parport_ip32_data_reverse(p);
1580 parport_ip32_frob_control(p, DCR_nINIT, 0);
1581 if (parport_wait_peripheral(p, DSR_PERROR, 0))
1582 pr_debug1(PPIP32 "%s: PEerror timeout 1 in %s\n",
1583 p->name, __func__);
1584 parport_ip32_frob_control(p, DCR_STROBE, DCR_STROBE);
1585 parport_ip32_frob_control(p, DCR_nINIT, DCR_nINIT);
1586 if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR))
1587 pr_debug1(PPIP32 "%s: PEerror timeout 2 in %s\n",
1588 p->name, __func__);
1589 }
1590
1591 /* Adjust residue if needed */
1592 parport_ip32_set_mode(p, ECR_MODE_CFG);
1593 cnfga = readb(priv->regs.cnfgA);
1594 if (!(cnfga & CNFGA_nBYTEINTRANS)) {
1595 pr_debug1(PPIP32 "%s: cnfgA contains 0x%02x\n",
1596 p->name, cnfga);
1597 pr_debug1(PPIP32 "%s: Accounting for extra byte\n",
1598 p->name);
1599 residue++;
1600 }
1601
1602 /* Don't care about partial PWords since we do not support
1603 * PWord != 1 byte. */
1604
1605 /* Back to forward PS2 mode. */
1606 parport_ip32_set_mode(p, ECR_MODE_PS2);
1607 parport_ip32_data_forward(p);
1608
1609 return residue;
1610 }
1611
1612 /**
1613 * parport_ip32_compat_write_data - write a block of data in SPP mode
1614 * @p: pointer to &struct parport
1615 * @buf: buffer of data to write
1616 * @len: length of buffer @buf
1617 * @flags: ignored
1618 */
parport_ip32_compat_write_data(struct parport * p,const void * buf,size_t len,int flags)1619 static size_t parport_ip32_compat_write_data(struct parport *p,
1620 const void *buf, size_t len,
1621 int flags)
1622 {
1623 static unsigned int ready_before = 1;
1624 struct parport_ip32_private * const priv = p->physport->private_data;
1625 struct parport * const physport = p->physport;
1626 size_t written = 0;
1627
1628 /* Special case: a timeout of zero means we cannot call schedule().
1629 * Also if O_NONBLOCK is set then use the default implementation. */
1630 if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
1631 return parport_ieee1284_write_compat(p, buf, len, flags);
1632
1633 /* Reset FIFO, go in forward mode, and disable ackIntEn */
1634 parport_ip32_set_mode(p, ECR_MODE_PS2);
1635 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
1636 parport_ip32_data_forward(p);
1637 parport_ip32_disable_irq(p);
1638 parport_ip32_set_mode(p, ECR_MODE_PPF);
1639 physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
1640
1641 /* Wait for peripheral to become ready */
1642 if (parport_wait_peripheral(p, DSR_nBUSY | DSR_nFAULT,
1643 DSR_nBUSY | DSR_nFAULT)) {
1644 /* Avoid to flood the logs */
1645 if (ready_before)
1646 pr_info(PPIP32 "%s: not ready in %s\n",
1647 p->name, __func__);
1648 ready_before = 0;
1649 goto stop;
1650 }
1651 ready_before = 1;
1652
1653 written = parport_ip32_fifo_write_block(p, buf, len);
1654
1655 /* Wait FIFO to empty. Timeout is proportional to FIFO_depth. */
1656 parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth);
1657
1658 /* Check for a potential residue */
1659 written -= parport_ip32_get_fifo_residue(p, ECR_MODE_PPF);
1660
1661 /* Then, wait for BUSY to get low. */
1662 if (parport_wait_peripheral(p, DSR_nBUSY, DSR_nBUSY))
1663 printk(KERN_DEBUG PPIP32 "%s: BUSY timeout in %s\n",
1664 p->name, __func__);
1665
1666 stop:
1667 /* Reset FIFO */
1668 parport_ip32_set_mode(p, ECR_MODE_PS2);
1669 physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1670
1671 return written;
1672 }
1673
1674 /*
1675 * FIXME - Insert here parport_ip32_ecp_read_data().
1676 */
1677
1678 /**
1679 * parport_ip32_ecp_write_data - write a block of data in ECP mode
1680 * @p: pointer to &struct parport
1681 * @buf: buffer of data to write
1682 * @len: length of buffer @buf
1683 * @flags: ignored
1684 */
parport_ip32_ecp_write_data(struct parport * p,const void * buf,size_t len,int flags)1685 static size_t parport_ip32_ecp_write_data(struct parport *p,
1686 const void *buf, size_t len,
1687 int flags)
1688 {
1689 static unsigned int ready_before = 1;
1690 struct parport_ip32_private * const priv = p->physport->private_data;
1691 struct parport * const physport = p->physport;
1692 size_t written = 0;
1693
1694 /* Special case: a timeout of zero means we cannot call schedule().
1695 * Also if O_NONBLOCK is set then use the default implementation. */
1696 if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
1697 return parport_ieee1284_ecp_write_data(p, buf, len, flags);
1698
1699 /* Negotiate to forward mode if necessary. */
1700 if (physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
1701 /* Event 47: Set nInit high. */
1702 parport_ip32_frob_control(p, DCR_nINIT | DCR_AUTOFD,
1703 DCR_nINIT | DCR_AUTOFD);
1704
1705 /* Event 49: PError goes high. */
1706 if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR)) {
1707 printk(KERN_DEBUG PPIP32 "%s: PError timeout in %s\n",
1708 p->name, __func__);
1709 physport->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN;
1710 return 0;
1711 }
1712 }
1713
1714 /* Reset FIFO, go in forward mode, and disable ackIntEn */
1715 parport_ip32_set_mode(p, ECR_MODE_PS2);
1716 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
1717 parport_ip32_data_forward(p);
1718 parport_ip32_disable_irq(p);
1719 parport_ip32_set_mode(p, ECR_MODE_ECP);
1720 physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
1721
1722 /* Wait for peripheral to become ready */
1723 if (parport_wait_peripheral(p, DSR_nBUSY | DSR_nFAULT,
1724 DSR_nBUSY | DSR_nFAULT)) {
1725 /* Avoid to flood the logs */
1726 if (ready_before)
1727 pr_info(PPIP32 "%s: not ready in %s\n",
1728 p->name, __func__);
1729 ready_before = 0;
1730 goto stop;
1731 }
1732 ready_before = 1;
1733
1734 written = parport_ip32_fifo_write_block(p, buf, len);
1735
1736 /* Wait FIFO to empty. Timeout is proportional to FIFO_depth. */
1737 parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth);
1738
1739 /* Check for a potential residue */
1740 written -= parport_ip32_get_fifo_residue(p, ECR_MODE_ECP);
1741
1742 /* Then, wait for BUSY to get low. */
1743 if (parport_wait_peripheral(p, DSR_nBUSY, DSR_nBUSY))
1744 printk(KERN_DEBUG PPIP32 "%s: BUSY timeout in %s\n",
1745 p->name, __func__);
1746
1747 stop:
1748 /* Reset FIFO */
1749 parport_ip32_set_mode(p, ECR_MODE_PS2);
1750 physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1751
1752 return written;
1753 }
1754
1755 /*
1756 * FIXME - Insert here parport_ip32_ecp_write_addr().
1757 */
1758
1759 /*--- Default parport operations ---------------------------------------*/
1760
1761 static const struct parport_operations parport_ip32_ops __initconst = {
1762 .write_data = parport_ip32_write_data,
1763 .read_data = parport_ip32_read_data,
1764
1765 .write_control = parport_ip32_write_control,
1766 .read_control = parport_ip32_read_control,
1767 .frob_control = parport_ip32_frob_control,
1768
1769 .read_status = parport_ip32_read_status,
1770
1771 .enable_irq = parport_ip32_enable_irq,
1772 .disable_irq = parport_ip32_disable_irq,
1773
1774 .data_forward = parport_ip32_data_forward,
1775 .data_reverse = parport_ip32_data_reverse,
1776
1777 .init_state = parport_ip32_init_state,
1778 .save_state = parport_ip32_save_state,
1779 .restore_state = parport_ip32_restore_state,
1780
1781 .epp_write_data = parport_ieee1284_epp_write_data,
1782 .epp_read_data = parport_ieee1284_epp_read_data,
1783 .epp_write_addr = parport_ieee1284_epp_write_addr,
1784 .epp_read_addr = parport_ieee1284_epp_read_addr,
1785
1786 .ecp_write_data = parport_ieee1284_ecp_write_data,
1787 .ecp_read_data = parport_ieee1284_ecp_read_data,
1788 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
1789
1790 .compat_write_data = parport_ieee1284_write_compat,
1791 .nibble_read_data = parport_ieee1284_read_nibble,
1792 .byte_read_data = parport_ieee1284_read_byte,
1793
1794 .owner = THIS_MODULE,
1795 };
1796
1797 /*--- Device detection -------------------------------------------------*/
1798
1799 /**
1800 * parport_ip32_ecp_supported - check for an ECP port
1801 * @p: pointer to the &parport structure
1802 *
1803 * Returns 1 if an ECP port is found, and 0 otherwise. This function actually
1804 * checks if an Extended Control Register seems to be present. On successful
1805 * return, the port is placed in SPP mode.
1806 */
parport_ip32_ecp_supported(struct parport * p)1807 static __init unsigned int parport_ip32_ecp_supported(struct parport *p)
1808 {
1809 struct parport_ip32_private * const priv = p->physport->private_data;
1810 unsigned int ecr;
1811
1812 ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
1813 writeb(ecr, priv->regs.ecr);
1814 if (readb(priv->regs.ecr) != (ecr | ECR_F_EMPTY))
1815 goto fail;
1816
1817 pr_probe(p, "Found working ECR register\n");
1818 parport_ip32_set_mode(p, ECR_MODE_SPP);
1819 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
1820 return 1;
1821
1822 fail:
1823 pr_probe(p, "ECR register not found\n");
1824 return 0;
1825 }
1826
1827 /**
1828 * parport_ip32_fifo_supported - check for FIFO parameters
1829 * @p: pointer to the &parport structure
1830 *
1831 * Check for FIFO parameters of an Extended Capabilities Port. Returns 1 on
1832 * success, and 0 otherwise. Adjust FIFO parameters in the parport structure.
1833 * On return, the port is placed in SPP mode.
1834 */
parport_ip32_fifo_supported(struct parport * p)1835 static __init unsigned int parport_ip32_fifo_supported(struct parport *p)
1836 {
1837 struct parport_ip32_private * const priv = p->physport->private_data;
1838 unsigned int configa, configb;
1839 unsigned int pword;
1840 unsigned int i;
1841
1842 /* Configuration mode */
1843 parport_ip32_set_mode(p, ECR_MODE_CFG);
1844 configa = readb(priv->regs.cnfgA);
1845 configb = readb(priv->regs.cnfgB);
1846
1847 /* Find out PWord size */
1848 switch (configa & CNFGA_ID_MASK) {
1849 case CNFGA_ID_8:
1850 pword = 1;
1851 break;
1852 case CNFGA_ID_16:
1853 pword = 2;
1854 break;
1855 case CNFGA_ID_32:
1856 pword = 4;
1857 break;
1858 default:
1859 pr_probe(p, "Unknown implementation ID: 0x%0x\n",
1860 (configa & CNFGA_ID_MASK) >> CNFGA_ID_SHIFT);
1861 goto fail;
1862 break;
1863 }
1864 if (pword != 1) {
1865 pr_probe(p, "Unsupported PWord size: %u\n", pword);
1866 goto fail;
1867 }
1868 priv->pword = pword;
1869 pr_probe(p, "PWord is %u bits\n", 8 * priv->pword);
1870
1871 /* Check for compression support */
1872 writeb(configb | CNFGB_COMPRESS, priv->regs.cnfgB);
1873 if (readb(priv->regs.cnfgB) & CNFGB_COMPRESS)
1874 pr_probe(p, "Hardware compression detected (unsupported)\n");
1875 writeb(configb & ~CNFGB_COMPRESS, priv->regs.cnfgB);
1876
1877 /* Reset FIFO and go in test mode (no interrupt, no DMA) */
1878 parport_ip32_set_mode(p, ECR_MODE_TST);
1879
1880 /* FIFO must be empty now */
1881 if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) {
1882 pr_probe(p, "FIFO not reset\n");
1883 goto fail;
1884 }
1885
1886 /* Find out FIFO depth. */
1887 priv->fifo_depth = 0;
1888 for (i = 0; i < 1024; i++) {
1889 if (readb(priv->regs.ecr) & ECR_F_FULL) {
1890 /* FIFO full */
1891 priv->fifo_depth = i;
1892 break;
1893 }
1894 writeb((u8)i, priv->regs.fifo);
1895 }
1896 if (i >= 1024) {
1897 pr_probe(p, "Can't fill FIFO\n");
1898 goto fail;
1899 }
1900 if (!priv->fifo_depth) {
1901 pr_probe(p, "Can't get FIFO depth\n");
1902 goto fail;
1903 }
1904 pr_probe(p, "FIFO is %u PWords deep\n", priv->fifo_depth);
1905
1906 /* Enable interrupts */
1907 parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0);
1908
1909 /* Find out writeIntrThreshold: number of PWords we know we can write
1910 * if we get an interrupt. */
1911 priv->writeIntrThreshold = 0;
1912 for (i = 0; i < priv->fifo_depth; i++) {
1913 if (readb(priv->regs.fifo) != (u8)i) {
1914 pr_probe(p, "Invalid data in FIFO\n");
1915 goto fail;
1916 }
1917 if (!priv->writeIntrThreshold
1918 && readb(priv->regs.ecr) & ECR_SERVINTR)
1919 /* writeIntrThreshold reached */
1920 priv->writeIntrThreshold = i + 1;
1921 if (i + 1 < priv->fifo_depth
1922 && readb(priv->regs.ecr) & ECR_F_EMPTY) {
1923 /* FIFO empty before the last byte? */
1924 pr_probe(p, "Data lost in FIFO\n");
1925 goto fail;
1926 }
1927 }
1928 if (!priv->writeIntrThreshold) {
1929 pr_probe(p, "Can't get writeIntrThreshold\n");
1930 goto fail;
1931 }
1932 pr_probe(p, "writeIntrThreshold is %u\n", priv->writeIntrThreshold);
1933
1934 /* FIFO must be empty now */
1935 if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) {
1936 pr_probe(p, "Can't empty FIFO\n");
1937 goto fail;
1938 }
1939
1940 /* Reset FIFO */
1941 parport_ip32_set_mode(p, ECR_MODE_PS2);
1942 /* Set reverse direction (must be in PS2 mode) */
1943 parport_ip32_data_reverse(p);
1944 /* Test FIFO, no interrupt, no DMA */
1945 parport_ip32_set_mode(p, ECR_MODE_TST);
1946 /* Enable interrupts */
1947 parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0);
1948
1949 /* Find out readIntrThreshold: number of PWords we can read if we get
1950 * an interrupt. */
1951 priv->readIntrThreshold = 0;
1952 for (i = 0; i < priv->fifo_depth; i++) {
1953 writeb(0xaa, priv->regs.fifo);
1954 if (readb(priv->regs.ecr) & ECR_SERVINTR) {
1955 /* readIntrThreshold reached */
1956 priv->readIntrThreshold = i + 1;
1957 break;
1958 }
1959 }
1960 if (!priv->readIntrThreshold) {
1961 pr_probe(p, "Can't get readIntrThreshold\n");
1962 goto fail;
1963 }
1964 pr_probe(p, "readIntrThreshold is %u\n", priv->readIntrThreshold);
1965
1966 /* Reset ECR */
1967 parport_ip32_set_mode(p, ECR_MODE_PS2);
1968 parport_ip32_data_forward(p);
1969 parport_ip32_set_mode(p, ECR_MODE_SPP);
1970 return 1;
1971
1972 fail:
1973 priv->fifo_depth = 0;
1974 parport_ip32_set_mode(p, ECR_MODE_SPP);
1975 return 0;
1976 }
1977
1978 /*--- Initialization code ----------------------------------------------*/
1979
1980 /**
1981 * parport_ip32_make_isa_registers - compute (ISA) register addresses
1982 * @regs: pointer to &struct parport_ip32_regs to fill
1983 * @base: base address of standard and EPP registers
1984 * @base_hi: base address of ECP registers
1985 * @regshift: how much to shift register offset by
1986 *
1987 * Compute register addresses, according to the ISA standard. The addresses
1988 * of the standard and EPP registers are computed from address @base. The
1989 * addresses of the ECP registers are computed from address @base_hi.
1990 */
1991 static void __init
parport_ip32_make_isa_registers(struct parport_ip32_regs * regs,void __iomem * base,void __iomem * base_hi,unsigned int regshift)1992 parport_ip32_make_isa_registers(struct parport_ip32_regs *regs,
1993 void __iomem *base, void __iomem *base_hi,
1994 unsigned int regshift)
1995 {
1996 #define r_base(offset) ((u8 __iomem *)base + ((offset) << regshift))
1997 #define r_base_hi(offset) ((u8 __iomem *)base_hi + ((offset) << regshift))
1998 *regs = (struct parport_ip32_regs){
1999 .data = r_base(0),
2000 .dsr = r_base(1),
2001 .dcr = r_base(2),
2002 .eppAddr = r_base(3),
2003 .eppData0 = r_base(4),
2004 .eppData1 = r_base(5),
2005 .eppData2 = r_base(6),
2006 .eppData3 = r_base(7),
2007 .ecpAFifo = r_base(0),
2008 .fifo = r_base_hi(0),
2009 .cnfgA = r_base_hi(0),
2010 .cnfgB = r_base_hi(1),
2011 .ecr = r_base_hi(2)
2012 };
2013 #undef r_base_hi
2014 #undef r_base
2015 }
2016
2017 /**
2018 * parport_ip32_probe_port - probe and register IP32 built-in parallel port
2019 *
2020 * Returns the new allocated &parport structure. On error, an error code is
2021 * encoded in return value with the ERR_PTR function.
2022 */
parport_ip32_probe_port(void)2023 static __init struct parport *parport_ip32_probe_port(void)
2024 {
2025 struct parport_ip32_regs regs;
2026 struct parport_ip32_private *priv = NULL;
2027 struct parport_operations *ops = NULL;
2028 struct parport *p = NULL;
2029 int err;
2030
2031 parport_ip32_make_isa_registers(®s, &mace->isa.parallel,
2032 &mace->isa.ecp1284, 8 /* regshift */);
2033
2034 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
2035 priv = kmalloc(sizeof(struct parport_ip32_private), GFP_KERNEL);
2036 p = parport_register_port(0, PARPORT_IRQ_NONE, PARPORT_DMA_NONE, ops);
2037 if (ops == NULL || priv == NULL || p == NULL) {
2038 err = -ENOMEM;
2039 goto fail;
2040 }
2041 p->base = MACE_BASE + offsetof(struct sgi_mace, isa.parallel);
2042 p->base_hi = MACE_BASE + offsetof(struct sgi_mace, isa.ecp1284);
2043 p->private_data = priv;
2044
2045 *ops = parport_ip32_ops;
2046 *priv = (struct parport_ip32_private){
2047 .regs = regs,
2048 .dcr_writable = DCR_DIR | DCR_SELECT | DCR_nINIT |
2049 DCR_AUTOFD | DCR_STROBE,
2050 .irq_mode = PARPORT_IP32_IRQ_FWD,
2051 };
2052 init_completion(&priv->irq_complete);
2053
2054 /* Probe port. */
2055 if (!parport_ip32_ecp_supported(p)) {
2056 err = -ENODEV;
2057 goto fail;
2058 }
2059 parport_ip32_dump_state(p, "begin init", 0);
2060
2061 /* We found what looks like a working ECR register. Simply assume
2062 * that all modes are correctly supported. Enable basic modes. */
2063 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2064 p->modes |= PARPORT_MODE_TRISTATE;
2065
2066 if (!parport_ip32_fifo_supported(p)) {
2067 pr_warn(PPIP32 "%s: error: FIFO disabled\n", p->name);
2068 /* Disable hardware modes depending on a working FIFO. */
2069 features &= ~PARPORT_IP32_ENABLE_SPP;
2070 features &= ~PARPORT_IP32_ENABLE_ECP;
2071 /* DMA is not needed if FIFO is not supported. */
2072 features &= ~PARPORT_IP32_ENABLE_DMA;
2073 }
2074
2075 /* Request IRQ */
2076 if (features & PARPORT_IP32_ENABLE_IRQ) {
2077 int irq = MACEISA_PARALLEL_IRQ;
2078 if (request_irq(irq, parport_ip32_interrupt, 0, p->name, p)) {
2079 pr_warn(PPIP32 "%s: error: IRQ disabled\n", p->name);
2080 /* DMA cannot work without interrupts. */
2081 features &= ~PARPORT_IP32_ENABLE_DMA;
2082 } else {
2083 pr_probe(p, "Interrupt support enabled\n");
2084 p->irq = irq;
2085 priv->dcr_writable |= DCR_IRQ;
2086 }
2087 }
2088
2089 /* Allocate DMA resources */
2090 if (features & PARPORT_IP32_ENABLE_DMA) {
2091 if (parport_ip32_dma_register())
2092 pr_warn(PPIP32 "%s: error: DMA disabled\n", p->name);
2093 else {
2094 pr_probe(p, "DMA support enabled\n");
2095 p->dma = 0; /* arbitrary value != PARPORT_DMA_NONE */
2096 p->modes |= PARPORT_MODE_DMA;
2097 }
2098 }
2099
2100 if (features & PARPORT_IP32_ENABLE_SPP) {
2101 /* Enable compatibility FIFO mode */
2102 p->ops->compat_write_data = parport_ip32_compat_write_data;
2103 p->modes |= PARPORT_MODE_COMPAT;
2104 pr_probe(p, "Hardware support for SPP mode enabled\n");
2105 }
2106 if (features & PARPORT_IP32_ENABLE_EPP) {
2107 /* Set up access functions to use EPP hardware. */
2108 p->ops->epp_read_data = parport_ip32_epp_read_data;
2109 p->ops->epp_write_data = parport_ip32_epp_write_data;
2110 p->ops->epp_read_addr = parport_ip32_epp_read_addr;
2111 p->ops->epp_write_addr = parport_ip32_epp_write_addr;
2112 p->modes |= PARPORT_MODE_EPP;
2113 pr_probe(p, "Hardware support for EPP mode enabled\n");
2114 }
2115 if (features & PARPORT_IP32_ENABLE_ECP) {
2116 /* Enable ECP FIFO mode */
2117 p->ops->ecp_write_data = parport_ip32_ecp_write_data;
2118 /* FIXME - not implemented */
2119 /* p->ops->ecp_read_data = parport_ip32_ecp_read_data; */
2120 /* p->ops->ecp_write_addr = parport_ip32_ecp_write_addr; */
2121 p->modes |= PARPORT_MODE_ECP;
2122 pr_probe(p, "Hardware support for ECP mode enabled\n");
2123 }
2124
2125 /* Initialize the port with sensible values */
2126 parport_ip32_set_mode(p, ECR_MODE_PS2);
2127 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
2128 parport_ip32_data_forward(p);
2129 parport_ip32_disable_irq(p);
2130 parport_ip32_write_data(p, 0x00);
2131 parport_ip32_dump_state(p, "end init", 0);
2132
2133 /* Print out what we found */
2134 pr_info("%s: SGI IP32 at 0x%lx (0x%lx)", p->name, p->base, p->base_hi);
2135 if (p->irq != PARPORT_IRQ_NONE)
2136 pr_cont(", irq %d", p->irq);
2137 pr_cont(" [");
2138 #define printmode(x) \
2139 do { \
2140 if (p->modes & PARPORT_MODE_##x) \
2141 pr_cont("%s%s", f++ ? "," : "", #x); \
2142 } while (0)
2143 {
2144 unsigned int f = 0;
2145 printmode(PCSPP);
2146 printmode(TRISTATE);
2147 printmode(COMPAT);
2148 printmode(EPP);
2149 printmode(ECP);
2150 printmode(DMA);
2151 }
2152 #undef printmode
2153 pr_cont("]\n");
2154
2155 parport_announce_port(p);
2156 return p;
2157
2158 fail:
2159 if (p)
2160 parport_put_port(p);
2161 kfree(priv);
2162 kfree(ops);
2163 return ERR_PTR(err);
2164 }
2165
2166 /**
2167 * parport_ip32_unregister_port - unregister a parallel port
2168 * @p: pointer to the &struct parport
2169 *
2170 * Unregisters a parallel port and free previously allocated resources
2171 * (memory, IRQ, ...).
2172 */
parport_ip32_unregister_port(struct parport * p)2173 static __exit void parport_ip32_unregister_port(struct parport *p)
2174 {
2175 struct parport_ip32_private * const priv = p->physport->private_data;
2176 struct parport_operations *ops = p->ops;
2177
2178 parport_remove_port(p);
2179 if (p->modes & PARPORT_MODE_DMA)
2180 parport_ip32_dma_unregister();
2181 if (p->irq != PARPORT_IRQ_NONE)
2182 free_irq(p->irq, p);
2183 parport_put_port(p);
2184 kfree(priv);
2185 kfree(ops);
2186 }
2187
2188 /**
2189 * parport_ip32_init - module initialization function
2190 */
parport_ip32_init(void)2191 static int __init parport_ip32_init(void)
2192 {
2193 pr_info(PPIP32 "SGI IP32 built-in parallel port driver v0.6\n");
2194 this_port = parport_ip32_probe_port();
2195 return PTR_ERR_OR_ZERO(this_port);
2196 }
2197
2198 /**
2199 * parport_ip32_exit - module termination function
2200 */
parport_ip32_exit(void)2201 static void __exit parport_ip32_exit(void)
2202 {
2203 parport_ip32_unregister_port(this_port);
2204 }
2205
2206 /*--- Module stuff -----------------------------------------------------*/
2207
2208 MODULE_AUTHOR("Arnaud Giersch <arnaud.giersch@free.fr>");
2209 MODULE_DESCRIPTION("SGI IP32 built-in parallel port driver");
2210 MODULE_LICENSE("GPL");
2211 MODULE_VERSION("0.6"); /* update in parport_ip32_init() too */
2212
2213 module_init(parport_ip32_init);
2214 module_exit(parport_ip32_exit);
2215
2216 module_param(verbose_probing, bool, S_IRUGO);
2217 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialization");
2218
2219 module_param(features, uint, S_IRUGO);
2220 MODULE_PARM_DESC(features,
2221 "Bit mask of features to enable"
2222 ", bit 0: IRQ support"
2223 ", bit 1: DMA support"
2224 ", bit 2: hardware SPP mode"
2225 ", bit 3: hardware EPP mode"
2226 ", bit 4: hardware ECP mode");
2227