1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm PCIe Endpoint controller driver 4 * 5 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 6 * Author: Siddartha Mohanadoss <smohanad@codeaurora.org 7 * 8 * Copyright (c) 2021, Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/interconnect.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/phy/pcie.h> 19 #include <linux/phy/phy.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_domain.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regmap.h> 24 #include <linux/reset.h> 25 #include <linux/module.h> 26 27 #include "../../pci.h" 28 #include "pcie-designware.h" 29 #include "pcie-qcom-common.h" 30 31 /* PARF registers */ 32 #define PARF_SYS_CTRL 0x00 33 #define PARF_DB_CTRL 0x10 34 #define PARF_PM_CTRL 0x20 35 #define PARF_MHI_CLOCK_RESET_CTRL 0x174 36 #define PARF_MHI_BASE_ADDR_LOWER 0x178 37 #define PARF_MHI_BASE_ADDR_UPPER 0x17c 38 #define PARF_DEBUG_INT_EN 0x190 39 #define PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1a4 40 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x1a8 41 #define PARF_Q2A_FLUSH 0x1ac 42 #define PARF_LTSSM 0x1b0 43 #define PARF_CFG_BITS 0x210 44 #define PARF_INT_ALL_STATUS 0x224 45 #define PARF_INT_ALL_CLEAR 0x228 46 #define PARF_INT_ALL_MASK 0x22c 47 #define PARF_SLV_ADDR_MSB_CTRL 0x2c0 48 #define PARF_DBI_BASE_ADDR 0x350 49 #define PARF_DBI_BASE_ADDR_HI 0x354 50 #define PARF_SLV_ADDR_SPACE_SIZE 0x358 51 #define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c 52 #define PARF_NO_SNOOP_OVERRIDE 0x3d4 53 #define PARF_ATU_BASE_ADDR 0x634 54 #define PARF_ATU_BASE_ADDR_HI 0x638 55 #define PARF_SRIS_MODE 0x644 56 #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 57 #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c 58 #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10 59 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 60 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 61 #define PARF_DEVICE_TYPE 0x1000 62 #define PARF_BDF_TO_SID_CFG 0x2c00 63 #define PARF_INT_ALL_5_MASK 0x2dcc 64 #define PARF_INT_ALL_3_MASK 0x2e18 65 66 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ 67 #define PARF_INT_ALL_LINK_DOWN BIT(1) 68 #define PARF_INT_ALL_BME BIT(2) 69 #define PARF_INT_ALL_PM_TURNOFF BIT(3) 70 #define PARF_INT_ALL_DEBUG BIT(4) 71 #define PARF_INT_ALL_LTR BIT(5) 72 #define PARF_INT_ALL_MHI_Q6 BIT(6) 73 #define PARF_INT_ALL_MHI_A7 BIT(7) 74 #define PARF_INT_ALL_DSTATE_CHANGE BIT(8) 75 #define PARF_INT_ALL_L1SUB_TIMEOUT BIT(9) 76 #define PARF_INT_ALL_MMIO_WRITE BIT(10) 77 #define PARF_INT_ALL_CFG_WRITE BIT(11) 78 #define PARF_INT_ALL_BRIDGE_FLUSH_N BIT(12) 79 #define PARF_INT_ALL_LINK_UP BIT(13) 80 #define PARF_INT_ALL_AER_LEGACY BIT(14) 81 #define PARF_INT_ALL_PLS_ERR BIT(15) 82 #define PARF_INT_ALL_PME_LEGACY BIT(16) 83 #define PARF_INT_ALL_PLS_PME BIT(17) 84 #define PARF_INT_ALL_EDMA BIT(22) 85 86 /* PARF_BDF_TO_SID_CFG register fields */ 87 #define PARF_BDF_TO_SID_BYPASS BIT(0) 88 89 /* PARF_DEBUG_INT_EN register fields */ 90 #define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1) 91 #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2) 92 #define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3) 93 94 /* PARF_NO_SNOOP_OVERRIDE register fields */ 95 #define WR_NO_SNOOP_OVERRIDE_EN BIT(1) 96 #define RD_NO_SNOOP_OVERRIDE_EN BIT(3) 97 98 /* PARF_DEVICE_TYPE register fields */ 99 #define PARF_DEVICE_TYPE_EP 0x0 100 101 /* PARF_PM_CTRL register fields */ 102 #define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1) 103 #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2) 104 #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5) 105 106 /* PARF_MHI_CLOCK_RESET_CTRL fields */ 107 #define PARF_MSTR_AXI_CLK_EN BIT(1) 108 109 /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */ 110 #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0) 111 112 /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ 113 #define PARF_AXI_MSTR_WR_ADDR_HALT_EN BIT(31) 114 115 /* PARF_Q2A_FLUSH register fields */ 116 #define PARF_Q2A_FLUSH_EN BIT(16) 117 118 /* PARF_SYS_CTRL register fields */ 119 #define PARF_SYS_CTRL_AUX_PWR_DET BIT(4) 120 #define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6) 121 #define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS BIT(10) 122 #define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11) 123 124 /* PARF_DB_CTRL register fields */ 125 #define PARF_DB_CTRL_INSR_DBNCR_BLOCK BIT(0) 126 #define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1) 127 #define PARF_DB_CTRL_DBI_WKP_BLOCK BIT(4) 128 #define PARF_DB_CTRL_SLV_WKP_BLOCK BIT(5) 129 #define PARF_DB_CTRL_MST_WKP_BLOCK BIT(6) 130 131 /* PARF_CFG_BITS register fields */ 132 #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1) 133 134 /* PARF_INT_ALL_5_MASK fields */ 135 #define PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR BIT(0) 136 137 /* PARF_INT_ALL_3_MASK fields */ 138 #define PARF_INT_ALL_3_PTM_UPDATING BIT(4) 139 140 /* ELBI registers */ 141 #define ELBI_SYS_STTS 0x08 142 #define ELBI_CS2_ENABLE 0xa4 143 144 /* DBI registers */ 145 #define DBI_CON_STATUS 0x44 146 147 /* DBI register fields */ 148 #define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0) 149 150 #define XMLH_LINK_UP 0x400 151 #define CORE_RESET_TIME_US_MIN 1000 152 #define CORE_RESET_TIME_US_MAX 1005 153 #define WAKE_DELAY_US 2000 /* 2 ms */ 154 155 #define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \ 156 Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_get_link_speed(speed))) 157 158 #define to_pcie_ep(x) dev_get_drvdata((x)->dev) 159 160 enum qcom_pcie_ep_link_status { 161 QCOM_PCIE_EP_LINK_DISABLED, 162 QCOM_PCIE_EP_LINK_ENABLED, 163 QCOM_PCIE_EP_LINK_UP, 164 QCOM_PCIE_EP_LINK_DOWN, 165 }; 166 167 /** 168 * struct qcom_pcie_ep_cfg - Per SoC config struct 169 * @hdma_support: HDMA support on this SoC 170 * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache snooping 171 * @disable_mhi_ram_parity_check: Disable MHI RAM data parity error check 172 * @firmware_managed: Set if the controller is firmware managed 173 */ 174 struct qcom_pcie_ep_cfg { 175 bool hdma_support; 176 bool override_no_snoop; 177 bool disable_mhi_ram_parity_check; 178 bool firmware_managed; 179 }; 180 181 /** 182 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller 183 * @pci: Designware PCIe controller struct 184 * @parf: Qualcomm PCIe specific PARF register base 185 * @mmio: MMIO register base 186 * @perst_map: PERST regmap 187 * @mmio_res: MMIO region resource 188 * @core_reset: PCIe Endpoint core reset 189 * @reset: PERST# GPIO 190 * @wake: WAKE# GPIO 191 * @phy: PHY controller block 192 * @debugfs: PCIe Endpoint Debugfs directory 193 * @icc_mem: Handle to an interconnect path between PCIe and MEM 194 * @clks: PCIe clocks 195 * @num_clks: PCIe clocks count 196 * @perst_en: Flag for PERST enable 197 * @perst_sep_en: Flag for PERST separation enable 198 * @cfg: PCIe EP config struct 199 * @link_status: PCIe Link status 200 * @global_irq: Qualcomm PCIe specific Global IRQ 201 * @perst_irq: PERST# IRQ 202 */ 203 struct qcom_pcie_ep { 204 struct dw_pcie pci; 205 206 void __iomem *parf; 207 void __iomem *mmio; 208 struct regmap *perst_map; 209 struct resource *mmio_res; 210 211 struct reset_control *core_reset; 212 struct gpio_desc *reset; 213 struct gpio_desc *wake; 214 struct phy *phy; 215 struct dentry *debugfs; 216 217 struct icc_path *icc_mem; 218 219 struct clk_bulk_data *clks; 220 int num_clks; 221 222 u32 perst_en; 223 u32 perst_sep_en; 224 225 const struct qcom_pcie_ep_cfg *cfg; 226 enum qcom_pcie_ep_link_status link_status; 227 int global_irq; 228 int perst_irq; 229 }; 230 231 static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep) 232 { 233 struct dw_pcie *pci = &pcie_ep->pci; 234 struct device *dev = pci->dev; 235 int ret; 236 237 ret = reset_control_assert(pcie_ep->core_reset); 238 if (ret) { 239 dev_err(dev, "Cannot assert core reset\n"); 240 return ret; 241 } 242 243 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX); 244 245 ret = reset_control_deassert(pcie_ep->core_reset); 246 if (ret) { 247 dev_err(dev, "Cannot de-assert core reset\n"); 248 return ret; 249 } 250 251 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX); 252 253 return 0; 254 } 255 256 /* 257 * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid 258 * device reset during host reboot and hibernation. The driver is 259 * expected to handle this situation. 260 */ 261 static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep) 262 { 263 if (pcie_ep->perst_map) { 264 regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0); 265 regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0); 266 } 267 } 268 269 static bool qcom_pcie_dw_link_up(struct dw_pcie *pci) 270 { 271 u32 reg; 272 273 reg = readl_relaxed(pci->elbi_base + ELBI_SYS_STTS); 274 275 return reg & XMLH_LINK_UP; 276 } 277 278 static int qcom_pcie_dw_start_link(struct dw_pcie *pci) 279 { 280 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 281 282 enable_irq(pcie_ep->perst_irq); 283 284 return 0; 285 } 286 287 static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) 288 { 289 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 290 291 disable_irq(pcie_ep->perst_irq); 292 } 293 294 static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base, 295 u32 reg, size_t size, u32 val) 296 { 297 int ret; 298 299 writel(1, pci->elbi_base + ELBI_CS2_ENABLE); 300 301 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); 302 if (ret) 303 dev_err(pci->dev, "Failed to write DBI2 register (0x%x): %d\n", reg, ret); 304 305 writel(0, pci->elbi_base + ELBI_CS2_ENABLE); 306 } 307 308 static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) 309 { 310 struct dw_pcie *pci = &pcie_ep->pci; 311 u32 offset, status; 312 int speed, width; 313 int ret; 314 315 if (!pcie_ep->icc_mem) 316 return; 317 318 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 319 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); 320 321 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); 322 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); 323 324 ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); 325 if (ret) 326 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", 327 ret); 328 } 329 330 static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) 331 { 332 struct dw_pcie *pci = &pcie_ep->pci; 333 int ret; 334 335 ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks); 336 if (ret) 337 return ret; 338 339 ret = qcom_pcie_ep_core_reset(pcie_ep); 340 if (ret) 341 goto err_disable_clk; 342 343 ret = phy_init(pcie_ep->phy); 344 if (ret) 345 goto err_disable_clk; 346 347 ret = phy_set_mode_ext(pcie_ep->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_EP); 348 if (ret) 349 goto err_phy_exit; 350 351 ret = phy_power_on(pcie_ep->phy); 352 if (ret) 353 goto err_phy_exit; 354 355 /* 356 * Some Qualcomm platforms require interconnect bandwidth constraints 357 * to be set before enabling interconnect clocks. 358 * 359 * Set an initial peak bandwidth corresponding to single-lane Gen 1 360 * for the pcie-mem path. 361 */ 362 ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); 363 if (ret) { 364 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", 365 ret); 366 goto err_phy_off; 367 } 368 369 return 0; 370 371 err_phy_off: 372 phy_power_off(pcie_ep->phy); 373 err_phy_exit: 374 phy_exit(pcie_ep->phy); 375 err_disable_clk: 376 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); 377 378 return ret; 379 } 380 381 static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) 382 { 383 struct device *dev = pcie_ep->pci.dev; 384 385 pm_runtime_put(dev); 386 387 /* Skip resource disablement if controller is firmware-managed */ 388 if (pcie_ep->cfg && pcie_ep->cfg->firmware_managed) 389 return; 390 391 icc_set_bw(pcie_ep->icc_mem, 0, 0); 392 phy_power_off(pcie_ep->phy); 393 phy_exit(pcie_ep->phy); 394 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); 395 } 396 397 static int qcom_pcie_perst_deassert(struct dw_pcie *pci) 398 { 399 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 400 struct device *dev = pci->dev; 401 u32 val, offset; 402 int ret; 403 404 ret = pm_runtime_resume_and_get(dev); 405 if (ret < 0) { 406 dev_err(dev, "Failed to enable device: %d\n", ret); 407 return ret; 408 } 409 410 /* Skip resource enablement if controller is firmware-managed */ 411 if (pcie_ep->cfg && pcie_ep->cfg->firmware_managed) 412 goto skip_resources_enable; 413 414 ret = qcom_pcie_enable_resources(pcie_ep); 415 if (ret) { 416 dev_err(dev, "Failed to enable resources: %d\n", ret); 417 pm_runtime_put(dev); 418 return ret; 419 } 420 421 skip_resources_enable: 422 /* Perform cleanup that requires refclk */ 423 pci_epc_deinit_notify(pci->ep.epc); 424 dw_pcie_ep_cleanup(&pci->ep); 425 426 /* Assert WAKE# to RC to indicate device is ready */ 427 gpiod_set_value_cansleep(pcie_ep->wake, 1); 428 usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500); 429 gpiod_set_value_cansleep(pcie_ep->wake, 0); 430 431 qcom_pcie_ep_configure_tcsr(pcie_ep); 432 433 /* Disable BDF to SID mapping */ 434 val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG); 435 val |= PARF_BDF_TO_SID_BYPASS; 436 writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG); 437 438 /* Enable debug IRQ */ 439 val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN); 440 val |= PARF_DEBUG_INT_RADM_PM_TURNOFF | 441 PARF_DEBUG_INT_CFG_BUS_MASTER_EN | 442 PARF_DEBUG_INT_PM_DSTATE_CHANGE; 443 writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN); 444 445 /* Configure PCIe to endpoint mode */ 446 writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE); 447 448 /* Allow entering L1 state */ 449 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 450 val &= ~PARF_PM_CTRL_REQ_NOT_ENTR_L1; 451 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 452 453 /* Read halts write */ 454 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES); 455 val &= ~PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN; 456 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES); 457 458 /* Write after write halt */ 459 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 460 val |= PARF_AXI_MSTR_WR_ADDR_HALT_EN; 461 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 462 463 /* Q2A flush disable */ 464 val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH); 465 val &= ~PARF_Q2A_FLUSH_EN; 466 writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH); 467 468 /* 469 * Disable Master AXI clock during idle. Do not allow DBI access 470 * to take the core out of L1. Disable core clock gating that 471 * gates PIPE clock from propagating to core clock. Report to the 472 * host that Vaux is present. 473 */ 474 val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL); 475 val &= ~PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS; 476 val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE | 477 PARF_SYS_CTRL_CORE_CLK_CGC_DIS | 478 PARF_SYS_CTRL_AUX_PWR_DET; 479 writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL); 480 481 /* Disable the debouncers */ 482 val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL); 483 val |= PARF_DB_CTRL_INSR_DBNCR_BLOCK | PARF_DB_CTRL_RMVL_DBNCR_BLOCK | 484 PARF_DB_CTRL_DBI_WKP_BLOCK | PARF_DB_CTRL_SLV_WKP_BLOCK | 485 PARF_DB_CTRL_MST_WKP_BLOCK; 486 writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL); 487 488 /* Request to exit from L1SS for MSI and LTR MSG */ 489 val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS); 490 val |= PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN; 491 writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS); 492 493 dw_pcie_dbi_ro_wr_en(pci); 494 495 /* Set the L0s Exit Latency to 2us-4us = 0x6 */ 496 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 497 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 498 FIELD_MODIFY(PCI_EXP_LNKCAP_L0SEL, &val, 0x6); 499 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); 500 501 /* Set the L1 Exit Latency to be 32us-64 us = 0x6 */ 502 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 503 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 504 FIELD_MODIFY(PCI_EXP_LNKCAP_L1EL, &val, 0x6); 505 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); 506 507 dw_pcie_dbi_ro_wr_dis(pci); 508 509 writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK); 510 val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME | 511 PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE | 512 PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA; 513 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK); 514 515 if (pcie_ep->cfg && pcie_ep->cfg->disable_mhi_ram_parity_check) { 516 val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_5_MASK); 517 val &= ~PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR; 518 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_5_MASK); 519 } 520 521 val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_3_MASK); 522 val &= ~PARF_INT_ALL_3_PTM_UPDATING; 523 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_3_MASK); 524 525 ret = dw_pcie_ep_init_registers(&pcie_ep->pci.ep); 526 if (ret) { 527 dev_err(dev, "Failed to complete initialization: %d\n", ret); 528 goto err_disable_resources; 529 } 530 531 qcom_pcie_common_set_equalization(pci); 532 533 if (pcie_get_link_speed(pci->max_link_speed) == PCIE_SPEED_16_0GT) 534 qcom_pcie_common_set_16gt_lane_margining(pci); 535 536 /* 537 * The physical address of the MMIO region which is exposed as the BAR 538 * should be written to MHI BASE registers. 539 */ 540 writel_relaxed(pcie_ep->mmio_res->start, 541 pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER); 542 writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER); 543 544 /* Gate Master AXI clock to MHI bus during L1SS */ 545 val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); 546 val &= ~PARF_MSTR_AXI_CLK_EN; 547 writel_relaxed(val, pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); 548 549 pci_epc_init_notify(pcie_ep->pci.ep.epc); 550 551 /* Enable LTSSM */ 552 val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); 553 val |= BIT(8); 554 writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); 555 556 if (pcie_ep->cfg && pcie_ep->cfg->override_no_snoop) 557 writel_relaxed(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN, 558 pcie_ep->parf + PARF_NO_SNOOP_OVERRIDE); 559 560 return 0; 561 562 err_disable_resources: 563 qcom_pcie_disable_resources(pcie_ep); 564 565 return ret; 566 } 567 568 static void qcom_pcie_perst_assert(struct dw_pcie *pci) 569 { 570 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); 571 572 qcom_pcie_disable_resources(pcie_ep); 573 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED; 574 } 575 576 /* Common DWC controller ops */ 577 static const struct dw_pcie_ops pci_ops = { 578 .link_up = qcom_pcie_dw_link_up, 579 .start_link = qcom_pcie_dw_start_link, 580 .stop_link = qcom_pcie_dw_stop_link, 581 .write_dbi2 = qcom_pcie_dw_write_dbi2, 582 }; 583 584 static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev, 585 struct qcom_pcie_ep *pcie_ep) 586 { 587 struct device *dev = &pdev->dev; 588 struct dw_pcie *pci = &pcie_ep->pci; 589 struct device_node *syscon; 590 struct resource *res; 591 int ret; 592 593 pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); 594 if (IS_ERR(pcie_ep->parf)) 595 return PTR_ERR(pcie_ep->parf); 596 597 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 598 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); 599 if (IS_ERR(pci->dbi_base)) 600 return PTR_ERR(pci->dbi_base); 601 pci->dbi_base2 = pci->dbi_base; 602 603 pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 604 "mmio"); 605 if (!pcie_ep->mmio_res) { 606 dev_err(dev, "Failed to get mmio resource\n"); 607 return -EINVAL; 608 } 609 610 pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res); 611 if (IS_ERR(pcie_ep->mmio)) 612 return PTR_ERR(pcie_ep->mmio); 613 614 syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0); 615 if (!syscon) { 616 dev_dbg(dev, "PERST separation not available\n"); 617 return 0; 618 } 619 620 pcie_ep->perst_map = syscon_node_to_regmap(syscon); 621 of_node_put(syscon); 622 if (IS_ERR(pcie_ep->perst_map)) 623 return PTR_ERR(pcie_ep->perst_map); 624 625 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs", 626 1, &pcie_ep->perst_en); 627 if (ret < 0) { 628 dev_err(dev, "No Perst Enable offset in syscon\n"); 629 return ret; 630 } 631 632 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs", 633 2, &pcie_ep->perst_sep_en); 634 if (ret < 0) { 635 dev_err(dev, "No Perst Separation Enable offset in syscon\n"); 636 return ret; 637 } 638 639 return 0; 640 } 641 642 static int qcom_pcie_ep_get_resources(struct platform_device *pdev, 643 struct qcom_pcie_ep *pcie_ep) 644 { 645 struct device *dev = &pdev->dev; 646 int ret; 647 648 ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep); 649 if (ret) { 650 dev_err(dev, "Failed to get io resources %d\n", ret); 651 return ret; 652 } 653 654 pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN); 655 if (IS_ERR(pcie_ep->reset)) 656 return PTR_ERR(pcie_ep->reset); 657 658 pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW); 659 if (IS_ERR(pcie_ep->wake)) 660 return PTR_ERR(pcie_ep->wake); 661 662 if (pcie_ep->cfg && pcie_ep->cfg->firmware_managed) 663 return 0; 664 665 pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks); 666 if (pcie_ep->num_clks < 0) { 667 dev_err(dev, "Failed to get clocks\n"); 668 return pcie_ep->num_clks; 669 } 670 671 pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core"); 672 if (IS_ERR(pcie_ep->core_reset)) 673 return PTR_ERR(pcie_ep->core_reset); 674 675 pcie_ep->phy = devm_phy_optional_get(dev, "pciephy"); 676 if (IS_ERR(pcie_ep->phy)) 677 ret = PTR_ERR(pcie_ep->phy); 678 679 pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem"); 680 if (IS_ERR(pcie_ep->icc_mem)) 681 ret = PTR_ERR(pcie_ep->icc_mem); 682 683 return ret; 684 } 685 686 /* TODO: Notify clients about PCIe state change */ 687 static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) 688 { 689 struct qcom_pcie_ep *pcie_ep = data; 690 struct dw_pcie *pci = &pcie_ep->pci; 691 struct device *dev = pci->dev; 692 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS); 693 u32 dstate, val; 694 695 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR); 696 697 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { 698 dev_dbg(dev, "Received Linkdown event\n"); 699 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN; 700 dw_pcie_ep_linkdown(&pci->ep); 701 } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { 702 dev_dbg(dev, "Received Bus Master Enable event\n"); 703 pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED; 704 qcom_pcie_ep_icc_update(pcie_ep); 705 pci_epc_bus_master_enable_notify(pci->ep.epc); 706 } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) { 707 dev_dbg(dev, "Received PM Turn-off event! Entering L23\n"); 708 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 709 val |= PARF_PM_CTRL_READY_ENTR_L23; 710 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 711 } else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) { 712 dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) & 713 DBI_CON_STATUS_POWER_STATE_MASK; 714 dev_dbg(dev, "Received D%d state event\n", dstate); 715 if (dstate == 3) { 716 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); 717 val |= PARF_PM_CTRL_REQ_EXIT_L1; 718 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); 719 } 720 } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { 721 dev_dbg(dev, "Received Linkup event. Enumeration complete!\n"); 722 dw_pcie_ep_linkup(&pci->ep); 723 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP; 724 } else { 725 dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", 726 status); 727 } 728 729 return IRQ_HANDLED; 730 } 731 732 static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data) 733 { 734 struct qcom_pcie_ep *pcie_ep = data; 735 struct dw_pcie *pci = &pcie_ep->pci; 736 struct device *dev = pci->dev; 737 u32 perst; 738 739 perst = gpiod_get_value(pcie_ep->reset); 740 if (perst) { 741 dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link!\n"); 742 qcom_pcie_perst_assert(pci); 743 } else { 744 dev_dbg(dev, "PERST de-asserted by host. Starting link training!\n"); 745 qcom_pcie_perst_deassert(pci); 746 } 747 748 irq_set_irq_type(gpiod_to_irq(pcie_ep->reset), 749 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW)); 750 751 return IRQ_HANDLED; 752 } 753 754 static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, 755 struct qcom_pcie_ep *pcie_ep) 756 { 757 struct device *dev = pcie_ep->pci.dev; 758 char *name; 759 int ret; 760 761 name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_global_irq%d", 762 pcie_ep->pci.ep.epc->domain_nr); 763 if (!name) 764 return -ENOMEM; 765 766 pcie_ep->global_irq = platform_get_irq_byname(pdev, "global"); 767 if (pcie_ep->global_irq < 0) 768 return pcie_ep->global_irq; 769 770 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL, 771 qcom_pcie_ep_global_irq_thread, 772 IRQF_ONESHOT, 773 name, pcie_ep); 774 if (ret) { 775 dev_err(&pdev->dev, "Failed to request Global IRQ\n"); 776 return ret; 777 } 778 779 name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_perst_irq%d", 780 pcie_ep->pci.ep.epc->domain_nr); 781 if (!name) 782 return -ENOMEM; 783 784 pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); 785 irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); 786 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, 787 qcom_pcie_ep_perst_irq_thread, 788 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 789 name, pcie_ep); 790 if (ret) { 791 dev_err(&pdev->dev, "Failed to request PERST IRQ\n"); 792 disable_irq(pcie_ep->global_irq); 793 return ret; 794 } 795 796 return 0; 797 } 798 799 static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 800 unsigned int type, u16 interrupt_num) 801 { 802 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 803 804 switch (type) { 805 case PCI_IRQ_INTX: 806 return dw_pcie_ep_raise_intx_irq(ep, func_no); 807 case PCI_IRQ_MSI: 808 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 809 default: 810 dev_err(pci->dev, "Unknown IRQ type\n"); 811 return -EINVAL; 812 } 813 } 814 815 static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data) 816 { 817 struct qcom_pcie_ep *pcie_ep = (struct qcom_pcie_ep *) 818 dev_get_drvdata(s->private); 819 820 seq_printf(s, "L0s transition count: %u\n", 821 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); 822 823 seq_printf(s, "L1 transition count: %u\n", 824 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); 825 826 seq_printf(s, "L1.1 transition count: %u\n", 827 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); 828 829 seq_printf(s, "L1.2 transition count: %u\n", 830 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); 831 832 seq_printf(s, "L2 transition count: %u\n", 833 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); 834 835 return 0; 836 } 837 838 static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep) 839 { 840 struct dw_pcie *pci = &pcie_ep->pci; 841 842 debugfs_create_devm_seqfile(pci->dev, "link_transition_count", pcie_ep->debugfs, 843 qcom_pcie_ep_link_transition_count); 844 } 845 846 static const struct pci_epc_features qcom_pcie_epc_features = { 847 DWC_EPC_COMMON_FEATURES, 848 .linkup_notifier = true, 849 .msi_capable = true, 850 .align = SZ_4K, 851 .bar[BAR_0] = { .only_64bit = true, }, 852 .bar[BAR_2] = { .only_64bit = true, }, 853 }; 854 855 static const struct pci_epc_features * 856 qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep) 857 { 858 return &qcom_pcie_epc_features; 859 } 860 861 static const struct dw_pcie_ep_ops pci_ep_ops = { 862 .raise_irq = qcom_pcie_ep_raise_irq, 863 .get_features = qcom_pcie_epc_get_features, 864 }; 865 866 static int qcom_pcie_ep_probe(struct platform_device *pdev) 867 { 868 struct device *dev = &pdev->dev; 869 struct qcom_pcie_ep *pcie_ep; 870 char *name; 871 int ret; 872 873 pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL); 874 if (!pcie_ep) 875 return -ENOMEM; 876 877 pcie_ep->pci.dev = dev; 878 pcie_ep->pci.ops = &pci_ops; 879 pcie_ep->pci.ep.ops = &pci_ep_ops; 880 881 pcie_ep->cfg = of_device_get_match_data(dev); 882 if (pcie_ep->cfg && pcie_ep->cfg->hdma_support) { 883 pcie_ep->pci.edma.ll_wr_cnt = 8; 884 pcie_ep->pci.edma.ll_rd_cnt = 8; 885 pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE; 886 } 887 888 platform_set_drvdata(pdev, pcie_ep); 889 890 pm_runtime_get_noresume(dev); 891 pm_runtime_set_active(dev); 892 ret = devm_pm_runtime_enable(dev); 893 if (ret) 894 return ret; 895 896 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); 897 if (ret) 898 return ret; 899 900 ret = dw_pcie_ep_init(&pcie_ep->pci.ep); 901 if (ret) { 902 dev_err(dev, "Failed to initialize endpoint: %d\n", ret); 903 return ret; 904 } 905 906 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep); 907 if (ret) 908 goto err_ep_deinit; 909 910 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); 911 if (!name) { 912 ret = -ENOMEM; 913 goto err_disable_irqs; 914 } 915 916 ret = pm_runtime_put_sync(dev); 917 if (ret < 0) { 918 dev_err(dev, "Failed to suspend device: %d\n", ret); 919 goto err_disable_irqs; 920 } 921 922 pcie_ep->debugfs = debugfs_create_dir(name, NULL); 923 qcom_pcie_ep_init_debugfs(pcie_ep); 924 925 return 0; 926 927 err_disable_irqs: 928 disable_irq(pcie_ep->global_irq); 929 disable_irq(pcie_ep->perst_irq); 930 931 err_ep_deinit: 932 dw_pcie_ep_deinit(&pcie_ep->pci.ep); 933 934 return ret; 935 } 936 937 static void qcom_pcie_ep_remove(struct platform_device *pdev) 938 { 939 struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev); 940 941 disable_irq(pcie_ep->global_irq); 942 disable_irq(pcie_ep->perst_irq); 943 944 debugfs_remove_recursive(pcie_ep->debugfs); 945 946 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) 947 return; 948 pci_epc_deinit_notify(pcie_ep->pci.ep.epc); 949 dw_pcie_ep_deinit(&pcie_ep->pci.ep); 950 951 qcom_pcie_disable_resources(pcie_ep); 952 } 953 954 static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { 955 .hdma_support = true, 956 .override_no_snoop = true, 957 .disable_mhi_ram_parity_check = true, 958 }; 959 960 static const struct qcom_pcie_ep_cfg cfg_1_34_0_fw_managed = { 961 .hdma_support = true, 962 .override_no_snoop = true, 963 .disable_mhi_ram_parity_check = true, 964 .firmware_managed = true, 965 }; 966 967 static const struct of_device_id qcom_pcie_ep_match[] = { 968 { .compatible = "qcom,sa8255p-pcie-ep", .data = &cfg_1_34_0_fw_managed}, 969 { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, 970 { .compatible = "qcom,sdx55-pcie-ep", }, 971 { .compatible = "qcom,sm8450-pcie-ep", }, 972 { .compatible = "qcom,sar2130p-pcie-ep", }, 973 { } 974 }; 975 MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match); 976 977 static struct platform_driver qcom_pcie_ep_driver = { 978 .probe = qcom_pcie_ep_probe, 979 .remove = qcom_pcie_ep_remove, 980 .driver = { 981 .name = "qcom-pcie-ep", 982 .of_match_table = qcom_pcie_ep_match, 983 }, 984 }; 985 builtin_platform_driver(qcom_pcie_ep_driver); 986 987 MODULE_AUTHOR("Siddartha Mohanadoss <smohanad@codeaurora.org>"); 988 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 989 MODULE_DESCRIPTION("Qualcomm PCIe Endpoint controller driver"); 990 MODULE_LICENSE("GPL v2"); 991