xref: /linux/drivers/gpu/drm/msm/adreno/adreno_gpu.c (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  *
6  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
7  */
8 
9 #include <linux/ascii85.h>
10 #include <linux/interconnect.h>
11 #include <linux/firmware/qcom/qcom_scm.h>
12 #include <linux/kernel.h>
13 #include <linux/of_address.h>
14 #include <linux/pm_opp.h>
15 #include <linux/slab.h>
16 #include <linux/soc/qcom/mdt_loader.h>
17 #include <linux/nvmem-consumer.h>
18 #include <soc/qcom/ocmem.h>
19 #include "adreno_gpu.h"
20 #include "a6xx_gpu.h"
21 #include "msm_gem.h"
22 #include "msm_mmu.h"
23 
24 static u64 address_space_size = 0;
25 MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space");
26 module_param(address_space_size, ullong, 0600);
27 
28 static bool zap_available = true;
29 
zap_shader_load_mdt(struct msm_gpu * gpu,const char * fwname,u32 pasid)30 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
31 		u32 pasid)
32 {
33 	struct device *dev = &gpu->pdev->dev;
34 	const struct firmware *fw;
35 	const char *signed_fwname = NULL;
36 	struct device_node *np, *mem_np;
37 	struct resource r;
38 	phys_addr_t mem_phys;
39 	ssize_t mem_size;
40 	void *mem_region = NULL;
41 	int ret;
42 
43 	if (!IS_ENABLED(CONFIG_ARCH_QCOM)) {
44 		zap_available = false;
45 		return -EINVAL;
46 	}
47 
48 	np = of_get_child_by_name(dev->of_node, "zap-shader");
49 	if (!of_device_is_available(np)) {
50 		zap_available = false;
51 		return -ENODEV;
52 	}
53 
54 	mem_np = of_parse_phandle(np, "memory-region", 0);
55 	of_node_put(np);
56 	if (!mem_np) {
57 		zap_available = false;
58 		return -EINVAL;
59 	}
60 
61 	ret = of_address_to_resource(mem_np, 0, &r);
62 	of_node_put(mem_np);
63 	if (ret)
64 		return ret;
65 
66 	mem_phys = r.start;
67 
68 	/*
69 	 * Check for a firmware-name property.  This is the new scheme
70 	 * to handle firmware that may be signed with device specific
71 	 * keys, allowing us to have a different zap fw path for different
72 	 * devices.
73 	 *
74 	 * If the firmware-name property is found, we bypass the
75 	 * adreno_request_fw() mechanism, because we don't need to handle
76 	 * the /lib/firmware/qcom/... vs /lib/firmware/... case.
77 	 *
78 	 * If the firmware-name property is not found, for backwards
79 	 * compatibility we fall back to the fwname from the gpulist
80 	 * table.
81 	 */
82 	of_property_read_string_index(np, "firmware-name", 0, &signed_fwname);
83 	if (signed_fwname) {
84 		fwname = signed_fwname;
85 		ret = request_firmware_direct(&fw, fwname, gpu->dev->dev);
86 		if (ret)
87 			fw = ERR_PTR(ret);
88 	} else if (fwname) {
89 		/* Request the MDT file from the default location: */
90 		fw = adreno_request_fw(to_adreno_gpu(gpu), fwname);
91 	} else {
92 		/*
93 		 * For new targets, we require the firmware-name property,
94 		 * if a zap-shader is required, rather than falling back
95 		 * to a firmware name specified in gpulist.
96 		 *
97 		 * Because the firmware is signed with a (potentially)
98 		 * device specific key, having the name come from gpulist
99 		 * was a bad idea, and is only provided for backwards
100 		 * compatibility for older targets.
101 		 */
102 		return -ENOENT;
103 	}
104 
105 	if (IS_ERR(fw)) {
106 		DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname);
107 		return PTR_ERR(fw);
108 	}
109 
110 	/* Figure out how much memory we need */
111 	mem_size = qcom_mdt_get_size(fw);
112 	if (mem_size < 0) {
113 		ret = mem_size;
114 		goto out;
115 	}
116 
117 	if (mem_size > resource_size(&r)) {
118 		DRM_DEV_ERROR(dev,
119 			"memory region is too small to load the MDT\n");
120 		ret = -E2BIG;
121 		goto out;
122 	}
123 
124 	/* Allocate memory for the firmware image */
125 	mem_region = memremap(mem_phys, mem_size,  MEMREMAP_WC);
126 	if (!mem_region) {
127 		ret = -ENOMEM;
128 		goto out;
129 	}
130 
131 	/*
132 	 * Load the rest of the MDT
133 	 *
134 	 * Note that we could be dealing with two different paths, since
135 	 * with upstream linux-firmware it would be in a qcom/ subdir..
136 	 * adreno_request_fw() handles this, but qcom_mdt_load() does
137 	 * not.  But since we've already gotten through adreno_request_fw()
138 	 * we know which of the two cases it is:
139 	 */
140 	if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) {
141 		ret = qcom_mdt_load(dev, fw, fwname, pasid,
142 				mem_region, mem_phys, mem_size, NULL);
143 	} else {
144 		char *newname;
145 
146 		newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
147 
148 		ret = qcom_mdt_load(dev, fw, newname, pasid,
149 				mem_region, mem_phys, mem_size, NULL);
150 		kfree(newname);
151 	}
152 	if (ret)
153 		goto out;
154 
155 	/* Send the image to the secure world */
156 	ret = qcom_scm_pas_auth_and_reset(pasid);
157 
158 	/*
159 	 * If the scm call returns -EOPNOTSUPP we assume that this target
160 	 * doesn't need/support the zap shader so quietly fail
161 	 */
162 	if (ret == -EOPNOTSUPP)
163 		zap_available = false;
164 	else if (ret)
165 		DRM_DEV_ERROR(dev, "Unable to authorize the image\n");
166 
167 out:
168 	if (mem_region)
169 		memunmap(mem_region);
170 
171 	release_firmware(fw);
172 
173 	return ret;
174 }
175 
adreno_zap_shader_load(struct msm_gpu * gpu,u32 pasid)176 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)
177 {
178 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
179 	struct platform_device *pdev = gpu->pdev;
180 
181 	/* Short cut if we determine the zap shader isn't available/needed */
182 	if (!zap_available)
183 		return -ENODEV;
184 
185 	/* We need SCM to be able to load the firmware */
186 	if (!qcom_scm_is_available()) {
187 		DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n");
188 		return -EPROBE_DEFER;
189 	}
190 
191 	return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);
192 }
193 
194 struct msm_gem_address_space *
adreno_create_address_space(struct msm_gpu * gpu,struct platform_device * pdev)195 adreno_create_address_space(struct msm_gpu *gpu,
196 			    struct platform_device *pdev)
197 {
198 	return adreno_iommu_create_address_space(gpu, pdev, 0);
199 }
200 
201 struct msm_gem_address_space *
adreno_iommu_create_address_space(struct msm_gpu * gpu,struct platform_device * pdev,unsigned long quirks)202 adreno_iommu_create_address_space(struct msm_gpu *gpu,
203 				  struct platform_device *pdev,
204 				  unsigned long quirks)
205 {
206 	struct iommu_domain_geometry *geometry;
207 	struct msm_mmu *mmu;
208 	struct msm_gem_address_space *aspace;
209 	u64 start, size;
210 
211 	mmu = msm_iommu_gpu_new(&pdev->dev, gpu, quirks);
212 	if (IS_ERR_OR_NULL(mmu))
213 		return ERR_CAST(mmu);
214 
215 	geometry = msm_iommu_get_geometry(mmu);
216 	if (IS_ERR(geometry))
217 		return ERR_CAST(geometry);
218 
219 	/*
220 	 * Use the aperture start or SZ_16M, whichever is greater. This will
221 	 * ensure that we align with the allocated pagetable range while still
222 	 * allowing room in the lower 32 bits for GMEM and whatnot
223 	 */
224 	start = max_t(u64, SZ_16M, geometry->aperture_start);
225 	size = geometry->aperture_end - start + 1;
226 
227 	aspace = msm_gem_address_space_create(mmu, "gpu",
228 		start & GENMASK_ULL(48, 0), size);
229 
230 	if (IS_ERR(aspace) && !IS_ERR(mmu))
231 		mmu->funcs->destroy(mmu);
232 
233 	return aspace;
234 }
235 
adreno_private_address_space_size(struct msm_gpu * gpu)236 u64 adreno_private_address_space_size(struct msm_gpu *gpu)
237 {
238 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
239 
240 	if (address_space_size)
241 		return address_space_size;
242 
243 	if (adreno_gpu->info->address_space_size)
244 		return adreno_gpu->info->address_space_size;
245 
246 	return SZ_4G;
247 }
248 
249 #define ARM_SMMU_FSR_TF                 BIT(1)
250 #define ARM_SMMU_FSR_PF			BIT(3)
251 #define ARM_SMMU_FSR_EF			BIT(4)
252 
adreno_fault_handler(struct msm_gpu * gpu,unsigned long iova,int flags,struct adreno_smmu_fault_info * info,const char * block,u32 scratch[4])253 int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
254 			 struct adreno_smmu_fault_info *info, const char *block,
255 			 u32 scratch[4])
256 {
257 	const char *type = "UNKNOWN";
258 	bool do_devcoredump = info && !READ_ONCE(gpu->crashstate);
259 
260 	/*
261 	 * If we aren't going to be resuming later from fault_worker, then do
262 	 * it now.
263 	 */
264 	if (!do_devcoredump) {
265 		gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
266 	}
267 
268 	/*
269 	 * Print a default message if we couldn't get the data from the
270 	 * adreno-smmu-priv
271 	 */
272 	if (!info) {
273 		pr_warn_ratelimited("*** gpu fault: iova=%.16lx flags=%d (%u,%u,%u,%u)\n",
274 			iova, flags,
275 			scratch[0], scratch[1], scratch[2], scratch[3]);
276 
277 		return 0;
278 	}
279 
280 	if (info->fsr & ARM_SMMU_FSR_TF)
281 		type = "TRANSLATION";
282 	else if (info->fsr & ARM_SMMU_FSR_PF)
283 		type = "PERMISSION";
284 	else if (info->fsr & ARM_SMMU_FSR_EF)
285 		type = "EXTERNAL";
286 
287 	pr_warn_ratelimited("*** gpu fault: ttbr0=%.16llx iova=%.16lx dir=%s type=%s source=%s (%u,%u,%u,%u)\n",
288 			info->ttbr0, iova,
289 			flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ",
290 			type, block,
291 			scratch[0], scratch[1], scratch[2], scratch[3]);
292 
293 	if (do_devcoredump) {
294 		/* Turn off the hangcheck timer to keep it from bothering us */
295 		del_timer(&gpu->hangcheck_timer);
296 
297 		gpu->fault_info.ttbr0 = info->ttbr0;
298 		gpu->fault_info.iova  = iova;
299 		gpu->fault_info.flags = flags;
300 		gpu->fault_info.type  = type;
301 		gpu->fault_info.block = block;
302 
303 		kthread_queue_work(gpu->worker, &gpu->fault_work);
304 	}
305 
306 	return 0;
307 }
308 
adreno_get_param(struct msm_gpu * gpu,struct msm_file_private * ctx,uint32_t param,uint64_t * value,uint32_t * len)309 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
310 		     uint32_t param, uint64_t *value, uint32_t *len)
311 {
312 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
313 	struct drm_device *drm = gpu->dev;
314 
315 	/* No pointer params yet */
316 	if (*len != 0)
317 		return UERR(EINVAL, drm, "invalid len");
318 
319 	switch (param) {
320 	case MSM_PARAM_GPU_ID:
321 		*value = adreno_gpu->info->revn;
322 		return 0;
323 	case MSM_PARAM_GMEM_SIZE:
324 		*value = adreno_gpu->info->gmem;
325 		return 0;
326 	case MSM_PARAM_GMEM_BASE:
327 		if (adreno_is_a650_family(adreno_gpu) ||
328 		    adreno_is_a740_family(adreno_gpu))
329 			*value = 0;
330 		else
331 			*value = 0x100000;
332 		return 0;
333 	case MSM_PARAM_CHIP_ID:
334 		*value = adreno_gpu->chip_id;
335 		if (!adreno_gpu->info->revn)
336 			*value |= ((uint64_t) adreno_gpu->speedbin) << 32;
337 		return 0;
338 	case MSM_PARAM_MAX_FREQ:
339 		*value = adreno_gpu->base.fast_rate;
340 		return 0;
341 	case MSM_PARAM_TIMESTAMP:
342 		if (adreno_gpu->funcs->get_timestamp) {
343 			int ret;
344 
345 			pm_runtime_get_sync(&gpu->pdev->dev);
346 			ret = adreno_gpu->funcs->get_timestamp(gpu, value);
347 			pm_runtime_put_autosuspend(&gpu->pdev->dev);
348 
349 			return ret;
350 		}
351 		return -EINVAL;
352 	case MSM_PARAM_PRIORITIES:
353 		*value = gpu->nr_rings * NR_SCHED_PRIORITIES;
354 		return 0;
355 	case MSM_PARAM_PP_PGTABLE:
356 		*value = 0;
357 		return 0;
358 	case MSM_PARAM_FAULTS:
359 		if (ctx->aspace)
360 			*value = gpu->global_faults + ctx->aspace->faults;
361 		else
362 			*value = gpu->global_faults;
363 		return 0;
364 	case MSM_PARAM_SUSPENDS:
365 		*value = gpu->suspend_count;
366 		return 0;
367 	case MSM_PARAM_VA_START:
368 		if (ctx->aspace == gpu->aspace)
369 			return UERR(EINVAL, drm, "requires per-process pgtables");
370 		*value = ctx->aspace->va_start;
371 		return 0;
372 	case MSM_PARAM_VA_SIZE:
373 		if (ctx->aspace == gpu->aspace)
374 			return UERR(EINVAL, drm, "requires per-process pgtables");
375 		*value = ctx->aspace->va_size;
376 		return 0;
377 	case MSM_PARAM_HIGHEST_BANK_BIT:
378 		*value = adreno_gpu->ubwc_config.highest_bank_bit;
379 		return 0;
380 	case MSM_PARAM_RAYTRACING:
381 		*value = adreno_gpu->has_ray_tracing;
382 		return 0;
383 	case MSM_PARAM_UBWC_SWIZZLE:
384 		*value = adreno_gpu->ubwc_config.ubwc_swizzle;
385 		return 0;
386 	case MSM_PARAM_MACROTILE_MODE:
387 		*value = adreno_gpu->ubwc_config.macrotile_mode;
388 		return 0;
389 	case MSM_PARAM_UCHE_TRAP_BASE:
390 		*value = adreno_gpu->uche_trap_base;
391 		return 0;
392 	default:
393 		return UERR(EINVAL, drm, "%s: invalid param: %u", gpu->name, param);
394 	}
395 }
396 
adreno_set_param(struct msm_gpu * gpu,struct msm_file_private * ctx,uint32_t param,uint64_t value,uint32_t len)397 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
398 		     uint32_t param, uint64_t value, uint32_t len)
399 {
400 	struct drm_device *drm = gpu->dev;
401 
402 	switch (param) {
403 	case MSM_PARAM_COMM:
404 	case MSM_PARAM_CMDLINE:
405 		/* kstrdup_quotable_cmdline() limits to PAGE_SIZE, so
406 		 * that should be a reasonable upper bound
407 		 */
408 		if (len > PAGE_SIZE)
409 			return UERR(EINVAL, drm, "invalid len");
410 		break;
411 	default:
412 		if (len != 0)
413 			return UERR(EINVAL, drm, "invalid len");
414 	}
415 
416 	switch (param) {
417 	case MSM_PARAM_COMM:
418 	case MSM_PARAM_CMDLINE: {
419 		char *str, **paramp;
420 
421 		str = memdup_user_nul(u64_to_user_ptr(value), len);
422 		if (IS_ERR(str))
423 			return PTR_ERR(str);
424 
425 		mutex_lock(&gpu->lock);
426 
427 		if (param == MSM_PARAM_COMM) {
428 			paramp = &ctx->comm;
429 		} else {
430 			paramp = &ctx->cmdline;
431 		}
432 
433 		kfree(*paramp);
434 		*paramp = str;
435 
436 		mutex_unlock(&gpu->lock);
437 
438 		return 0;
439 	}
440 	case MSM_PARAM_SYSPROF:
441 		if (!capable(CAP_SYS_ADMIN))
442 			return UERR(EPERM, drm, "invalid permissions");
443 		return msm_file_private_set_sysprof(ctx, gpu, value);
444 	default:
445 		return UERR(EINVAL, drm, "%s: invalid param: %u", gpu->name, param);
446 	}
447 }
448 
449 const struct firmware *
adreno_request_fw(struct adreno_gpu * adreno_gpu,const char * fwname)450 adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname)
451 {
452 	struct drm_device *drm = adreno_gpu->base.dev;
453 	const struct firmware *fw = NULL;
454 	char *newname;
455 	int ret;
456 
457 	newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
458 	if (!newname)
459 		return ERR_PTR(-ENOMEM);
460 
461 	/*
462 	 * Try first to load from qcom/$fwfile using a direct load (to avoid
463 	 * a potential timeout waiting for usermode helper)
464 	 */
465 	if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
466 	    (adreno_gpu->fwloc == FW_LOCATION_NEW)) {
467 
468 		ret = request_firmware_direct(&fw, newname, drm->dev);
469 		if (!ret) {
470 			DRM_DEV_INFO(drm->dev, "loaded %s from new location\n",
471 				newname);
472 			adreno_gpu->fwloc = FW_LOCATION_NEW;
473 			goto out;
474 		} else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
475 			DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
476 				newname, ret);
477 			fw = ERR_PTR(ret);
478 			goto out;
479 		}
480 	}
481 
482 	/*
483 	 * Then try the legacy location without qcom/ prefix
484 	 */
485 	if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
486 	    (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) {
487 
488 		ret = request_firmware_direct(&fw, fwname, drm->dev);
489 		if (!ret) {
490 			DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n",
491 				fwname);
492 			adreno_gpu->fwloc = FW_LOCATION_LEGACY;
493 			goto out;
494 		} else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
495 			DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
496 				fwname, ret);
497 			fw = ERR_PTR(ret);
498 			goto out;
499 		}
500 	}
501 
502 	/*
503 	 * Finally fall back to request_firmware() for cases where the
504 	 * usermode helper is needed (I think mainly android)
505 	 */
506 	if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
507 	    (adreno_gpu->fwloc == FW_LOCATION_HELPER)) {
508 
509 		ret = request_firmware(&fw, newname, drm->dev);
510 		if (!ret) {
511 			DRM_DEV_INFO(drm->dev, "loaded %s with helper\n",
512 				newname);
513 			adreno_gpu->fwloc = FW_LOCATION_HELPER;
514 			goto out;
515 		} else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
516 			DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
517 				newname, ret);
518 			fw = ERR_PTR(ret);
519 			goto out;
520 		}
521 	}
522 
523 	DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname);
524 	fw = ERR_PTR(-ENOENT);
525 out:
526 	kfree(newname);
527 	return fw;
528 }
529 
adreno_load_fw(struct adreno_gpu * adreno_gpu)530 int adreno_load_fw(struct adreno_gpu *adreno_gpu)
531 {
532 	int i;
533 
534 	for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) {
535 		const struct firmware *fw;
536 
537 		if (!adreno_gpu->info->fw[i])
538 			continue;
539 
540 		/* Skip loading GMU firmware with GMU Wrapper */
541 		if (adreno_has_gmu_wrapper(adreno_gpu) && i == ADRENO_FW_GMU)
542 			continue;
543 
544 		/* Skip if the firmware has already been loaded */
545 		if (adreno_gpu->fw[i])
546 			continue;
547 
548 		fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]);
549 		if (IS_ERR(fw))
550 			return PTR_ERR(fw);
551 
552 		adreno_gpu->fw[i] = fw;
553 	}
554 
555 	return 0;
556 }
557 
adreno_fw_create_bo(struct msm_gpu * gpu,const struct firmware * fw,u64 * iova)558 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
559 		const struct firmware *fw, u64 *iova)
560 {
561 	struct drm_gem_object *bo;
562 	void *ptr;
563 
564 	ptr = msm_gem_kernel_new(gpu->dev, fw->size - 4,
565 		MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
566 
567 	if (IS_ERR(ptr))
568 		return ERR_CAST(ptr);
569 
570 	memcpy(ptr, &fw->data[4], fw->size - 4);
571 
572 	msm_gem_put_vaddr(bo);
573 
574 	return bo;
575 }
576 
adreno_hw_init(struct msm_gpu * gpu)577 int adreno_hw_init(struct msm_gpu *gpu)
578 {
579 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
580 	int ret;
581 
582 	VERB("%s", gpu->name);
583 
584 	if (adreno_gpu->info->family >= ADRENO_6XX_GEN1 &&
585 	    qcom_scm_set_gpu_smmu_aperture_is_available()) {
586 		/* We currently always use context bank 0, so hard code this */
587 		ret = qcom_scm_set_gpu_smmu_aperture(0);
588 		if (ret)
589 			DRM_DEV_ERROR(gpu->dev->dev, "unable to set SMMU aperture: %d\n", ret);
590 	}
591 
592 	for (int i = 0; i < gpu->nr_rings; i++) {
593 		struct msm_ringbuffer *ring = gpu->rb[i];
594 
595 		if (!ring)
596 			continue;
597 
598 		ring->cur = ring->start;
599 		ring->next = ring->start;
600 		ring->memptrs->rptr = 0;
601 		ring->memptrs->bv_fence = ring->fctx->completed_fence;
602 
603 		/* Detect and clean up an impossible fence, ie. if GPU managed
604 		 * to scribble something invalid, we don't want that to confuse
605 		 * us into mistakingly believing that submits have completed.
606 		 */
607 		if (fence_before(ring->fctx->last_fence, ring->memptrs->fence)) {
608 			ring->memptrs->fence = ring->fctx->last_fence;
609 		}
610 	}
611 
612 	return 0;
613 }
614 
615 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */
get_rptr(struct adreno_gpu * adreno_gpu,struct msm_ringbuffer * ring)616 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu,
617 		struct msm_ringbuffer *ring)
618 {
619 	struct msm_gpu *gpu = &adreno_gpu->base;
620 
621 	return gpu->funcs->get_rptr(gpu, ring);
622 }
623 
adreno_active_ring(struct msm_gpu * gpu)624 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)
625 {
626 	return gpu->rb[0];
627 }
628 
adreno_recover(struct msm_gpu * gpu)629 void adreno_recover(struct msm_gpu *gpu)
630 {
631 	struct drm_device *dev = gpu->dev;
632 	int ret;
633 
634 	// XXX pm-runtime??  we *need* the device to be off after this
635 	// so maybe continuing to call ->pm_suspend/resume() is better?
636 
637 	gpu->funcs->pm_suspend(gpu);
638 	gpu->funcs->pm_resume(gpu);
639 
640 	ret = msm_gpu_hw_init(gpu);
641 	if (ret) {
642 		DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
643 		/* hmm, oh well? */
644 	}
645 }
646 
adreno_flush(struct msm_gpu * gpu,struct msm_ringbuffer * ring,u32 reg)647 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg)
648 {
649 	uint32_t wptr;
650 
651 	/* Copy the shadow to the actual register */
652 	ring->cur = ring->next;
653 
654 	/*
655 	 * Mask wptr value that we calculate to fit in the HW range. This is
656 	 * to account for the possibility that the last command fit exactly into
657 	 * the ringbuffer and rb->next hasn't wrapped to zero yet
658 	 */
659 	wptr = get_wptr(ring);
660 
661 	/* ensure writes to ringbuffer have hit system memory: */
662 	mb();
663 
664 	gpu_write(gpu, reg, wptr);
665 }
666 
adreno_idle(struct msm_gpu * gpu,struct msm_ringbuffer * ring)667 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
668 {
669 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
670 	uint32_t wptr = get_wptr(ring);
671 
672 	/* wait for CP to drain ringbuffer: */
673 	if (!spin_until(get_rptr(adreno_gpu, ring) == wptr))
674 		return true;
675 
676 	/* TODO maybe we need to reset GPU here to recover from hang? */
677 	DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n",
678 		gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr);
679 
680 	return false;
681 }
682 
adreno_gpu_state_get(struct msm_gpu * gpu,struct msm_gpu_state * state)683 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state)
684 {
685 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
686 	int i, count = 0;
687 
688 	WARN_ON(!mutex_is_locked(&gpu->lock));
689 
690 	kref_init(&state->ref);
691 
692 	ktime_get_real_ts64(&state->time);
693 
694 	for (i = 0; i < gpu->nr_rings; i++) {
695 		int size = 0, j;
696 
697 		state->ring[i].fence = gpu->rb[i]->memptrs->fence;
698 		state->ring[i].iova = gpu->rb[i]->iova;
699 		state->ring[i].seqno = gpu->rb[i]->fctx->last_fence;
700 		state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]);
701 		state->ring[i].wptr = get_wptr(gpu->rb[i]);
702 
703 		/* Copy at least 'wptr' dwords of the data */
704 		size = state->ring[i].wptr;
705 
706 		/* After wptr find the last non zero dword to save space */
707 		for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++)
708 			if (gpu->rb[i]->start[j])
709 				size = j + 1;
710 
711 		if (size) {
712 			state->ring[i].data = kvmemdup(gpu->rb[i]->start, size << 2, GFP_KERNEL);
713 			if (state->ring[i].data)
714 				state->ring[i].data_size = size << 2;
715 		}
716 	}
717 
718 	/* Some targets prefer to collect their own registers */
719 	if (!adreno_gpu->registers)
720 		return 0;
721 
722 	/* Count the number of registers */
723 	for (i = 0; adreno_gpu->registers[i] != ~0; i += 2)
724 		count += adreno_gpu->registers[i + 1] -
725 			adreno_gpu->registers[i] + 1;
726 
727 	state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL);
728 	if (state->registers) {
729 		int pos = 0;
730 
731 		for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
732 			u32 start = adreno_gpu->registers[i];
733 			u32 end   = adreno_gpu->registers[i + 1];
734 			u32 addr;
735 
736 			for (addr = start; addr <= end; addr++) {
737 				state->registers[pos++] = addr;
738 				state->registers[pos++] = gpu_read(gpu, addr);
739 			}
740 		}
741 
742 		state->nr_registers = count;
743 	}
744 
745 	return 0;
746 }
747 
adreno_gpu_state_destroy(struct msm_gpu_state * state)748 void adreno_gpu_state_destroy(struct msm_gpu_state *state)
749 {
750 	int i;
751 
752 	for (i = 0; i < ARRAY_SIZE(state->ring); i++)
753 		kvfree(state->ring[i].data);
754 
755 	for (i = 0; state->bos && i < state->nr_bos; i++)
756 		kvfree(state->bos[i].data);
757 
758 	kfree(state->bos);
759 	kfree(state->comm);
760 	kfree(state->cmd);
761 	kfree(state->registers);
762 }
763 
adreno_gpu_state_kref_destroy(struct kref * kref)764 static void adreno_gpu_state_kref_destroy(struct kref *kref)
765 {
766 	struct msm_gpu_state *state = container_of(kref,
767 		struct msm_gpu_state, ref);
768 
769 	adreno_gpu_state_destroy(state);
770 	kfree(state);
771 }
772 
adreno_gpu_state_put(struct msm_gpu_state * state)773 int adreno_gpu_state_put(struct msm_gpu_state *state)
774 {
775 	if (IS_ERR_OR_NULL(state))
776 		return 1;
777 
778 	return kref_put(&state->ref, adreno_gpu_state_kref_destroy);
779 }
780 
781 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
782 
adreno_gpu_ascii85_encode(u32 * src,size_t len)783 static char *adreno_gpu_ascii85_encode(u32 *src, size_t len)
784 {
785 	void *buf;
786 	size_t buf_itr = 0, buffer_size;
787 	char out[ASCII85_BUFSZ];
788 	long l;
789 	int i;
790 
791 	if (!src || !len)
792 		return NULL;
793 
794 	l = ascii85_encode_len(len);
795 
796 	/*
797 	 * Ascii85 outputs either a 5 byte string or a 1 byte string. So we
798 	 * account for the worst case of 5 bytes per dword plus the 1 for '\0'
799 	 */
800 	buffer_size = (l * 5) + 1;
801 
802 	buf = kvmalloc(buffer_size, GFP_KERNEL);
803 	if (!buf)
804 		return NULL;
805 
806 	for (i = 0; i < l; i++)
807 		buf_itr += scnprintf(buf + buf_itr, buffer_size - buf_itr, "%s",
808 				ascii85_encode(src[i], out));
809 
810 	return buf;
811 }
812 
813 /* len is expected to be in bytes
814  *
815  * WARNING: *ptr should be allocated with kvmalloc or friends.  It can be free'd
816  * with kvfree() and replaced with a newly kvmalloc'd buffer on the first call
817  * when the unencoded raw data is encoded
818  */
adreno_show_object(struct drm_printer * p,void ** ptr,int len,bool * encoded)819 void adreno_show_object(struct drm_printer *p, void **ptr, int len,
820 		bool *encoded)
821 {
822 	if (!*ptr || !len)
823 		return;
824 
825 	if (!*encoded) {
826 		long datalen, i;
827 		u32 *buf = *ptr;
828 
829 		/*
830 		 * Only dump the non-zero part of the buffer - rarely will
831 		 * any data completely fill the entire allocated size of
832 		 * the buffer.
833 		 */
834 		for (datalen = 0, i = 0; i < len >> 2; i++)
835 			if (buf[i])
836 				datalen = ((i + 1) << 2);
837 
838 		/*
839 		 * If we reach here, then the originally captured binary buffer
840 		 * will be replaced with the ascii85 encoded string
841 		 */
842 		*ptr = adreno_gpu_ascii85_encode(buf, datalen);
843 
844 		kvfree(buf);
845 
846 		*encoded = true;
847 	}
848 
849 	if (!*ptr)
850 		return;
851 
852 	drm_puts(p, "    data: !!ascii85 |\n");
853 	drm_puts(p, "     ");
854 
855 	drm_puts(p, *ptr);
856 
857 	drm_puts(p, "\n");
858 }
859 
adreno_show(struct msm_gpu * gpu,struct msm_gpu_state * state,struct drm_printer * p)860 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
861 		struct drm_printer *p)
862 {
863 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
864 	int i;
865 
866 	if (IS_ERR_OR_NULL(state))
867 		return;
868 
869 	drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n",
870 			adreno_gpu->info->revn,
871 			ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
872 	/*
873 	 * If this is state collected due to iova fault, so fault related info
874 	 *
875 	 * TTBR0 would not be zero, so this is a good way to distinguish
876 	 */
877 	if (state->fault_info.ttbr0) {
878 		const struct msm_gpu_fault_info *info = &state->fault_info;
879 
880 		drm_puts(p, "fault-info:\n");
881 		drm_printf(p, "  - ttbr0=%.16llx\n", info->ttbr0);
882 		drm_printf(p, "  - iova=%.16lx\n", info->iova);
883 		drm_printf(p, "  - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ");
884 		drm_printf(p, "  - type=%s\n", info->type);
885 		drm_printf(p, "  - source=%s\n", info->block);
886 	}
887 
888 	drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status);
889 
890 	drm_puts(p, "ringbuffer:\n");
891 
892 	for (i = 0; i < gpu->nr_rings; i++) {
893 		drm_printf(p, "  - id: %d\n", i);
894 		drm_printf(p, "    iova: 0x%016llx\n", state->ring[i].iova);
895 		drm_printf(p, "    last-fence: %u\n", state->ring[i].seqno);
896 		drm_printf(p, "    retired-fence: %u\n", state->ring[i].fence);
897 		drm_printf(p, "    rptr: %u\n", state->ring[i].rptr);
898 		drm_printf(p, "    wptr: %u\n", state->ring[i].wptr);
899 		drm_printf(p, "    size: %u\n", MSM_GPU_RINGBUFFER_SZ);
900 
901 		adreno_show_object(p, &state->ring[i].data,
902 			state->ring[i].data_size, &state->ring[i].encoded);
903 	}
904 
905 	if (state->bos) {
906 		drm_puts(p, "bos:\n");
907 
908 		for (i = 0; i < state->nr_bos; i++) {
909 			drm_printf(p, "  - iova: 0x%016llx\n",
910 				state->bos[i].iova);
911 			drm_printf(p, "    size: %zd\n", state->bos[i].size);
912 			drm_printf(p, "    flags: 0x%x\n", state->bos[i].flags);
913 			drm_printf(p, "    name: %-32s\n", state->bos[i].name);
914 
915 			adreno_show_object(p, &state->bos[i].data,
916 				state->bos[i].size, &state->bos[i].encoded);
917 		}
918 	}
919 
920 	if (state->nr_registers) {
921 		drm_puts(p, "registers:\n");
922 
923 		for (i = 0; i < state->nr_registers; i++) {
924 			drm_printf(p, "  - { offset: 0x%04x, value: 0x%08x }\n",
925 				state->registers[i * 2] << 2,
926 				state->registers[(i * 2) + 1]);
927 		}
928 	}
929 }
930 #endif
931 
932 /* Dump common gpu status and scratch registers on any hang, to make
933  * the hangcheck logs more useful.  The scratch registers seem always
934  * safe to read when GPU has hung (unlike some other regs, depending
935  * on how the GPU hung), and they are useful to match up to cmdstream
936  * dumps when debugging hangs:
937  */
adreno_dump_info(struct msm_gpu * gpu)938 void adreno_dump_info(struct msm_gpu *gpu)
939 {
940 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
941 	int i;
942 
943 	printk("revision: %u (%"ADRENO_CHIPID_FMT")\n",
944 			adreno_gpu->info->revn,
945 			ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
946 
947 	for (i = 0; i < gpu->nr_rings; i++) {
948 		struct msm_ringbuffer *ring = gpu->rb[i];
949 
950 		printk("rb %d: fence:    %d/%d\n", i,
951 			ring->memptrs->fence,
952 			ring->fctx->last_fence);
953 
954 		printk("rptr:     %d\n", get_rptr(adreno_gpu, ring));
955 		printk("rb wptr:  %d\n", get_wptr(ring));
956 	}
957 }
958 
959 /* would be nice to not have to duplicate the _show() stuff with printk(): */
adreno_dump(struct msm_gpu * gpu)960 void adreno_dump(struct msm_gpu *gpu)
961 {
962 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
963 	int i;
964 
965 	if (!adreno_gpu->registers)
966 		return;
967 
968 	/* dump these out in a form that can be parsed by demsm: */
969 	printk("IO:region %s 00000000 00020000\n", gpu->name);
970 	for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
971 		uint32_t start = adreno_gpu->registers[i];
972 		uint32_t end   = adreno_gpu->registers[i+1];
973 		uint32_t addr;
974 
975 		for (addr = start; addr <= end; addr++) {
976 			uint32_t val = gpu_read(gpu, addr);
977 			printk("IO:R %08x %08x\n", addr<<2, val);
978 		}
979 	}
980 }
981 
ring_freewords(struct msm_ringbuffer * ring)982 static uint32_t ring_freewords(struct msm_ringbuffer *ring)
983 {
984 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);
985 	uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2;
986 	/* Use ring->next to calculate free size */
987 	uint32_t wptr = ring->next - ring->start;
988 	uint32_t rptr = get_rptr(adreno_gpu, ring);
989 	return (rptr + (size - 1) - wptr) % size;
990 }
991 
adreno_wait_ring(struct msm_ringbuffer * ring,uint32_t ndwords)992 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords)
993 {
994 	if (spin_until(ring_freewords(ring) >= ndwords))
995 		DRM_DEV_ERROR(ring->gpu->dev->dev,
996 			"timeout waiting for space in ringbuffer %d\n",
997 			ring->id);
998 }
999 
adreno_get_pwrlevels(struct device * dev,struct msm_gpu * gpu)1000 static int adreno_get_pwrlevels(struct device *dev,
1001 		struct msm_gpu *gpu)
1002 {
1003 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1004 	unsigned long freq = ULONG_MAX;
1005 	struct dev_pm_opp *opp;
1006 	int ret;
1007 
1008 	gpu->fast_rate = 0;
1009 
1010 	/* devm_pm_opp_of_add_table may error out but will still create an OPP table */
1011 	ret = devm_pm_opp_of_add_table(dev);
1012 	if (ret == -ENODEV) {
1013 		/* Special cases for ancient hw with ancient DT bindings */
1014 		if (adreno_is_a2xx(adreno_gpu)) {
1015 			dev_warn(dev, "Unable to find the OPP table. Falling back to 200 MHz.\n");
1016 			dev_pm_opp_add(dev, 200000000, 0);
1017 		} else if (adreno_is_a320(adreno_gpu)) {
1018 			dev_warn(dev, "Unable to find the OPP table. Falling back to 450 MHz.\n");
1019 			dev_pm_opp_add(dev, 450000000, 0);
1020 		} else {
1021 			DRM_DEV_ERROR(dev, "Unable to find the OPP table\n");
1022 			return -ENODEV;
1023 		}
1024 	} else if (ret) {
1025 		DRM_DEV_ERROR(dev, "Unable to set the OPP table\n");
1026 		return ret;
1027 	}
1028 
1029 	/* Find the fastest defined rate */
1030 	opp = dev_pm_opp_find_freq_floor(dev, &freq);
1031 	if (IS_ERR(opp))
1032 		return PTR_ERR(opp);
1033 
1034 	gpu->fast_rate = freq;
1035 	dev_pm_opp_put(opp);
1036 
1037 	DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
1038 
1039 	return 0;
1040 }
1041 
adreno_gpu_ocmem_init(struct device * dev,struct adreno_gpu * adreno_gpu,struct adreno_ocmem * adreno_ocmem)1042 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
1043 			  struct adreno_ocmem *adreno_ocmem)
1044 {
1045 	struct ocmem_buf *ocmem_hdl;
1046 	struct ocmem *ocmem;
1047 
1048 	ocmem = of_get_ocmem(dev);
1049 	if (IS_ERR(ocmem)) {
1050 		if (PTR_ERR(ocmem) == -ENODEV) {
1051 			/*
1052 			 * Return success since either the ocmem property was
1053 			 * not specified in device tree, or ocmem support is
1054 			 * not compiled into the kernel.
1055 			 */
1056 			return 0;
1057 		}
1058 
1059 		return PTR_ERR(ocmem);
1060 	}
1061 
1062 	ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->info->gmem);
1063 	if (IS_ERR(ocmem_hdl))
1064 		return PTR_ERR(ocmem_hdl);
1065 
1066 	adreno_ocmem->ocmem = ocmem;
1067 	adreno_ocmem->base = ocmem_hdl->addr;
1068 	adreno_ocmem->hdl = ocmem_hdl;
1069 
1070 	if (WARN_ON(ocmem_hdl->len != adreno_gpu->info->gmem))
1071 		return -ENOMEM;
1072 
1073 	return 0;
1074 }
1075 
adreno_gpu_ocmem_cleanup(struct adreno_ocmem * adreno_ocmem)1076 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
1077 {
1078 	if (adreno_ocmem && adreno_ocmem->base)
1079 		ocmem_free(adreno_ocmem->ocmem, OCMEM_GRAPHICS,
1080 			   adreno_ocmem->hdl);
1081 }
1082 
adreno_read_speedbin(struct device * dev,u32 * speedbin)1083 int adreno_read_speedbin(struct device *dev, u32 *speedbin)
1084 {
1085 	return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
1086 }
1087 
adreno_gpu_init(struct drm_device * drm,struct platform_device * pdev,struct adreno_gpu * adreno_gpu,const struct adreno_gpu_funcs * funcs,int nr_rings)1088 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
1089 		struct adreno_gpu *adreno_gpu,
1090 		const struct adreno_gpu_funcs *funcs, int nr_rings)
1091 {
1092 	struct device *dev = &pdev->dev;
1093 	struct adreno_platform_config *config = dev->platform_data;
1094 	struct msm_gpu_config adreno_gpu_config  = { 0 };
1095 	struct msm_gpu *gpu = &adreno_gpu->base;
1096 	const char *gpu_name;
1097 	u32 speedbin;
1098 	int ret;
1099 
1100 	adreno_gpu->funcs = funcs;
1101 	adreno_gpu->info = config->info;
1102 	adreno_gpu->chip_id = config->chip_id;
1103 
1104 	gpu->allow_relocs = config->info->family < ADRENO_6XX_GEN1;
1105 	gpu->pdev = pdev;
1106 
1107 	/* Only handle the core clock when GMU is not in use (or is absent). */
1108 	if (adreno_has_gmu_wrapper(adreno_gpu) ||
1109 	    adreno_gpu->info->family < ADRENO_6XX_GEN1) {
1110 		/*
1111 		 * This can only be done before devm_pm_opp_of_add_table(), or
1112 		 * dev_pm_opp_set_config() will WARN_ON()
1113 		 */
1114 		if (IS_ERR(devm_clk_get(dev, "core"))) {
1115 			/*
1116 			 * If "core" is absent, go for the legacy clock name.
1117 			 * If we got this far in probing, it's a given one of
1118 			 * them exists.
1119 			 */
1120 			devm_pm_opp_set_clkname(dev, "core_clk");
1121 		} else
1122 			devm_pm_opp_set_clkname(dev, "core");
1123 	}
1124 
1125 	if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
1126 		speedbin = 0xffff;
1127 	adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
1128 
1129 	gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
1130 			ADRENO_CHIPID_ARGS(config->chip_id));
1131 	if (!gpu_name)
1132 		return -ENOMEM;
1133 
1134 	adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
1135 
1136 	adreno_gpu_config.nr_rings = nr_rings;
1137 
1138 	ret = adreno_get_pwrlevels(dev, gpu);
1139 	if (ret)
1140 		return ret;
1141 
1142 	pm_runtime_set_autosuspend_delay(dev,
1143 		adreno_gpu->info->inactive_period);
1144 	pm_runtime_use_autosuspend(dev);
1145 
1146 	return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
1147 			gpu_name, &adreno_gpu_config);
1148 }
1149 
adreno_gpu_cleanup(struct adreno_gpu * adreno_gpu)1150 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
1151 {
1152 	struct msm_gpu *gpu = &adreno_gpu->base;
1153 	struct msm_drm_private *priv = gpu->dev ? gpu->dev->dev_private : NULL;
1154 	unsigned int i;
1155 
1156 	for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
1157 		release_firmware(adreno_gpu->fw[i]);
1158 
1159 	if (priv && pm_runtime_enabled(&priv->gpu_pdev->dev))
1160 		pm_runtime_disable(&priv->gpu_pdev->dev);
1161 
1162 	msm_gpu_cleanup(&adreno_gpu->base);
1163 }
1164