1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_device.h> 30 #include <linux/of_platform.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/regulator/consumer.h> 34 35 #include <video/display_timing.h> 36 #include <video/of_display_timing.h> 37 #include <video/videomode.h> 38 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_device.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_mipi_dsi.h> 43 #include <drm/drm_panel.h> 44 #include <drm/drm_of.h> 45 46 /** 47 * struct panel_desc - Describes a simple panel. 48 */ 49 struct panel_desc { 50 /** 51 * @modes: Pointer to array of fixed modes appropriate for this panel. 52 * 53 * If only one mode then this can just be the address of the mode. 54 * NOTE: cannot be used with "timings" and also if this is specified 55 * then you cannot override the mode in the device tree. 56 */ 57 const struct drm_display_mode *modes; 58 59 /** @num_modes: Number of elements in modes array. */ 60 unsigned int num_modes; 61 62 /** 63 * @timings: Pointer to array of display timings 64 * 65 * NOTE: cannot be used with "modes" and also these will be used to 66 * validate a device tree override if one is present. 67 */ 68 const struct display_timing *timings; 69 70 /** @num_timings: Number of elements in timings array. */ 71 unsigned int num_timings; 72 73 /** @bpc: Bits per color. */ 74 unsigned int bpc; 75 76 /** @size: Structure containing the physical size of this panel. */ 77 struct { 78 /** 79 * @size.width: Width (in mm) of the active display area. 80 */ 81 unsigned int width; 82 83 /** 84 * @size.height: Height (in mm) of the active display area. 85 */ 86 unsigned int height; 87 } size; 88 89 /** @delay: Structure containing various delay values for this panel. */ 90 struct { 91 /** 92 * @delay.prepare: Time for the panel to become ready. 93 * 94 * The time (in milliseconds) that it takes for the panel to 95 * become ready and start receiving video data 96 */ 97 unsigned int prepare; 98 99 /** 100 * @delay.enable: Time for the panel to display a valid frame. 101 * 102 * The time (in milliseconds) that it takes for the panel to 103 * display the first valid frame after starting to receive 104 * video data. 105 */ 106 unsigned int enable; 107 108 /** 109 * @delay.disable: Time for the panel to turn the display off. 110 * 111 * The time (in milliseconds) that it takes for the panel to 112 * turn the display off (no content is visible). 113 */ 114 unsigned int disable; 115 116 /** 117 * @delay.unprepare: Time to power down completely. 118 * 119 * The time (in milliseconds) that it takes for the panel 120 * to power itself down completely. 121 * 122 * This time is used to prevent a future "prepare" from 123 * starting until at least this many milliseconds has passed. 124 * If at prepare time less time has passed since unprepare 125 * finished, the driver waits for the remaining time. 126 */ 127 unsigned int unprepare; 128 } delay; 129 130 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 131 u32 bus_format; 132 133 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 134 u32 bus_flags; 135 136 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 137 int connector_type; 138 }; 139 140 struct panel_desc_dsi { 141 struct panel_desc desc; 142 143 unsigned long flags; 144 enum mipi_dsi_pixel_format format; 145 unsigned int lanes; 146 }; 147 148 struct panel_simple { 149 struct drm_panel base; 150 151 ktime_t unprepared_time; 152 153 const struct panel_desc *desc; 154 155 struct regulator *supply; 156 struct i2c_adapter *ddc; 157 158 struct gpio_desc *enable_gpio; 159 160 const struct drm_edid *drm_edid; 161 162 struct drm_display_mode override_mode; 163 164 enum drm_panel_orientation orientation; 165 }; 166 167 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 168 { 169 return container_of(panel, struct panel_simple, base); 170 } 171 172 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 173 struct drm_connector *connector) 174 { 175 struct drm_display_mode *mode; 176 unsigned int i, num = 0; 177 178 for (i = 0; i < panel->desc->num_timings; i++) { 179 const struct display_timing *dt = &panel->desc->timings[i]; 180 struct videomode vm; 181 182 videomode_from_timing(dt, &vm); 183 mode = drm_mode_create(connector->dev); 184 if (!mode) { 185 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 186 dt->hactive.typ, dt->vactive.typ); 187 continue; 188 } 189 190 drm_display_mode_from_videomode(&vm, mode); 191 192 mode->type |= DRM_MODE_TYPE_DRIVER; 193 194 if (panel->desc->num_timings == 1) 195 mode->type |= DRM_MODE_TYPE_PREFERRED; 196 197 drm_mode_probed_add(connector, mode); 198 num++; 199 } 200 201 return num; 202 } 203 204 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 205 struct drm_connector *connector) 206 { 207 struct drm_display_mode *mode; 208 unsigned int i, num = 0; 209 210 for (i = 0; i < panel->desc->num_modes; i++) { 211 const struct drm_display_mode *m = &panel->desc->modes[i]; 212 213 mode = drm_mode_duplicate(connector->dev, m); 214 if (!mode) { 215 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 216 m->hdisplay, m->vdisplay, 217 drm_mode_vrefresh(m)); 218 continue; 219 } 220 221 mode->type |= DRM_MODE_TYPE_DRIVER; 222 223 if (panel->desc->num_modes == 1) 224 mode->type |= DRM_MODE_TYPE_PREFERRED; 225 226 drm_mode_set_name(mode); 227 228 drm_mode_probed_add(connector, mode); 229 num++; 230 } 231 232 return num; 233 } 234 235 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 236 struct drm_connector *connector) 237 { 238 struct drm_display_mode *mode; 239 bool has_override = panel->override_mode.type; 240 unsigned int num = 0; 241 242 if (!panel->desc) 243 return 0; 244 245 if (has_override) { 246 mode = drm_mode_duplicate(connector->dev, 247 &panel->override_mode); 248 if (mode) { 249 drm_mode_probed_add(connector, mode); 250 num = 1; 251 } else { 252 dev_err(panel->base.dev, "failed to add override mode\n"); 253 } 254 } 255 256 /* Only add timings if override was not there or failed to validate */ 257 if (num == 0 && panel->desc->num_timings) 258 num = panel_simple_get_timings_modes(panel, connector); 259 260 /* 261 * Only add fixed modes if timings/override added no mode. 262 * 263 * We should only ever have either the display timings specified 264 * or a fixed mode. Anything else is rather bogus. 265 */ 266 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 267 if (num == 0) 268 num = panel_simple_get_display_modes(panel, connector); 269 270 connector->display_info.bpc = panel->desc->bpc; 271 connector->display_info.width_mm = panel->desc->size.width; 272 connector->display_info.height_mm = panel->desc->size.height; 273 if (panel->desc->bus_format) 274 drm_display_info_set_bus_formats(&connector->display_info, 275 &panel->desc->bus_format, 1); 276 connector->display_info.bus_flags = panel->desc->bus_flags; 277 278 return num; 279 } 280 281 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 282 { 283 ktime_t now_ktime, min_ktime; 284 285 if (!min_ms) 286 return; 287 288 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 289 now_ktime = ktime_get_boottime(); 290 291 if (ktime_before(now_ktime, min_ktime)) 292 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 293 } 294 295 static int panel_simple_disable(struct drm_panel *panel) 296 { 297 struct panel_simple *p = to_panel_simple(panel); 298 299 if (p->desc->delay.disable) 300 msleep(p->desc->delay.disable); 301 302 return 0; 303 } 304 305 static int panel_simple_suspend(struct device *dev) 306 { 307 struct panel_simple *p = dev_get_drvdata(dev); 308 309 gpiod_set_value_cansleep(p->enable_gpio, 0); 310 regulator_disable(p->supply); 311 p->unprepared_time = ktime_get_boottime(); 312 313 drm_edid_free(p->drm_edid); 314 p->drm_edid = NULL; 315 316 return 0; 317 } 318 319 static int panel_simple_unprepare(struct drm_panel *panel) 320 { 321 int ret; 322 323 pm_runtime_mark_last_busy(panel->dev); 324 ret = pm_runtime_put_autosuspend(panel->dev); 325 if (ret < 0) 326 return ret; 327 328 return 0; 329 } 330 331 static int panel_simple_resume(struct device *dev) 332 { 333 struct panel_simple *p = dev_get_drvdata(dev); 334 int err; 335 336 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 337 338 err = regulator_enable(p->supply); 339 if (err < 0) { 340 dev_err(dev, "failed to enable supply: %d\n", err); 341 return err; 342 } 343 344 gpiod_set_value_cansleep(p->enable_gpio, 1); 345 346 if (p->desc->delay.prepare) 347 msleep(p->desc->delay.prepare); 348 349 return 0; 350 } 351 352 static int panel_simple_prepare(struct drm_panel *panel) 353 { 354 int ret; 355 356 ret = pm_runtime_get_sync(panel->dev); 357 if (ret < 0) { 358 pm_runtime_put_autosuspend(panel->dev); 359 return ret; 360 } 361 362 return 0; 363 } 364 365 static int panel_simple_enable(struct drm_panel *panel) 366 { 367 struct panel_simple *p = to_panel_simple(panel); 368 369 if (p->desc->delay.enable) 370 msleep(p->desc->delay.enable); 371 372 return 0; 373 } 374 375 static int panel_simple_get_modes(struct drm_panel *panel, 376 struct drm_connector *connector) 377 { 378 struct panel_simple *p = to_panel_simple(panel); 379 int num = 0; 380 381 /* probe EDID if a DDC bus is available */ 382 if (p->ddc) { 383 pm_runtime_get_sync(panel->dev); 384 385 if (!p->drm_edid) 386 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 387 388 drm_edid_connector_update(connector, p->drm_edid); 389 390 num += drm_edid_connector_add_modes(connector); 391 392 pm_runtime_mark_last_busy(panel->dev); 393 pm_runtime_put_autosuspend(panel->dev); 394 } 395 396 /* add hard-coded panel modes */ 397 num += panel_simple_get_non_edid_modes(p, connector); 398 399 /* 400 * TODO: Remove once all drm drivers call 401 * drm_connector_set_orientation_from_panel() 402 */ 403 drm_connector_set_panel_orientation(connector, p->orientation); 404 405 return num; 406 } 407 408 static int panel_simple_get_timings(struct drm_panel *panel, 409 unsigned int num_timings, 410 struct display_timing *timings) 411 { 412 struct panel_simple *p = to_panel_simple(panel); 413 unsigned int i; 414 415 if (p->desc->num_timings < num_timings) 416 num_timings = p->desc->num_timings; 417 418 if (timings) 419 for (i = 0; i < num_timings; i++) 420 timings[i] = p->desc->timings[i]; 421 422 return p->desc->num_timings; 423 } 424 425 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 426 { 427 struct panel_simple *p = to_panel_simple(panel); 428 429 return p->orientation; 430 } 431 432 static const struct drm_panel_funcs panel_simple_funcs = { 433 .disable = panel_simple_disable, 434 .unprepare = panel_simple_unprepare, 435 .prepare = panel_simple_prepare, 436 .enable = panel_simple_enable, 437 .get_modes = panel_simple_get_modes, 438 .get_orientation = panel_simple_get_orientation, 439 .get_timings = panel_simple_get_timings, 440 }; 441 442 static struct panel_desc *panel_dpi_probe(struct device *dev) 443 { 444 struct display_timing *timing; 445 const struct device_node *np; 446 struct panel_desc *desc; 447 unsigned int bus_flags; 448 struct videomode vm; 449 int ret; 450 451 np = dev->of_node; 452 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 453 if (!desc) 454 return ERR_PTR(-ENOMEM); 455 456 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 457 if (!timing) 458 return ERR_PTR(-ENOMEM); 459 460 ret = of_get_display_timing(np, "panel-timing", timing); 461 if (ret < 0) { 462 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 463 np); 464 return ERR_PTR(ret); 465 } 466 467 desc->timings = timing; 468 desc->num_timings = 1; 469 470 of_property_read_u32(np, "width-mm", &desc->size.width); 471 of_property_read_u32(np, "height-mm", &desc->size.height); 472 473 /* Extract bus_flags from display_timing */ 474 bus_flags = 0; 475 vm.flags = timing->flags; 476 drm_bus_flags_from_videomode(&vm, &bus_flags); 477 desc->bus_flags = bus_flags; 478 479 /* We do not know the connector for the DT node, so guess it */ 480 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 481 482 return desc; 483 } 484 485 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 486 (to_check->field.typ >= bounds->field.min && \ 487 to_check->field.typ <= bounds->field.max) 488 static void panel_simple_parse_panel_timing_node(struct device *dev, 489 struct panel_simple *panel, 490 const struct display_timing *ot) 491 { 492 const struct panel_desc *desc = panel->desc; 493 struct videomode vm; 494 unsigned int i; 495 496 if (WARN_ON(desc->num_modes)) { 497 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 498 return; 499 } 500 if (WARN_ON(!desc->num_timings)) { 501 dev_err(dev, "Reject override mode: no timings specified\n"); 502 return; 503 } 504 505 for (i = 0; i < panel->desc->num_timings; i++) { 506 const struct display_timing *dt = &panel->desc->timings[i]; 507 508 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 512 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 513 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 514 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 515 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 516 continue; 517 518 if (ot->flags != dt->flags) 519 continue; 520 521 videomode_from_timing(ot, &vm); 522 drm_display_mode_from_videomode(&vm, &panel->override_mode); 523 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 524 DRM_MODE_TYPE_PREFERRED; 525 break; 526 } 527 528 if (WARN_ON(!panel->override_mode.type)) 529 dev_err(dev, "Reject override mode: No display_timing found\n"); 530 } 531 532 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 533 struct panel_simple *panel) 534 { 535 int ret, bpc; 536 537 ret = drm_of_lvds_get_data_mapping(dev->of_node); 538 if (ret < 0) { 539 if (ret == -EINVAL) 540 dev_warn(dev, "Ignore invalid data-mapping property\n"); 541 542 /* 543 * Ignore non-existing or malformatted property, fallback to 544 * default data-mapping, and return 0. 545 */ 546 return 0; 547 } 548 549 switch (ret) { 550 default: 551 WARN_ON(1); 552 fallthrough; 553 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 554 fallthrough; 555 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 556 bpc = 8; 557 break; 558 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 559 bpc = 6; 560 } 561 562 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 563 struct panel_desc *override_desc; 564 565 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 566 if (!override_desc) 567 return -ENOMEM; 568 569 override_desc->bus_format = ret; 570 override_desc->bpc = bpc; 571 panel->desc = override_desc; 572 } 573 574 return 0; 575 } 576 577 static const struct panel_desc *panel_simple_get_desc(struct device *dev) 578 { 579 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI) && 580 dev_is_mipi_dsi(dev)) { 581 const struct panel_desc_dsi *dsi_desc; 582 583 dsi_desc = of_device_get_match_data(dev); 584 if (!dsi_desc) 585 return ERR_PTR(-ENODEV); 586 587 return &dsi_desc->desc; 588 } 589 590 if (dev_is_platform(dev)) { 591 const struct panel_desc *desc; 592 593 desc = of_device_get_match_data(dev); 594 if (!desc) { 595 /* 596 * panel-dpi probes without a descriptor and 597 * panel_dpi_probe() will initialize one for us 598 * based on the device tree. 599 */ 600 if (of_device_is_compatible(dev->of_node, "panel-dpi")) 601 return panel_dpi_probe(dev); 602 else 603 return ERR_PTR(-ENODEV); 604 } 605 606 return desc; 607 } 608 609 return ERR_PTR(-ENODEV); 610 } 611 612 static struct panel_simple *panel_simple_probe(struct device *dev) 613 { 614 const struct panel_desc *desc; 615 struct panel_simple *panel; 616 struct display_timing dt; 617 struct device_node *ddc; 618 int connector_type; 619 u32 bus_flags; 620 int err; 621 622 desc = panel_simple_get_desc(dev); 623 if (IS_ERR(desc)) 624 return ERR_CAST(desc); 625 626 connector_type = desc->connector_type; 627 /* Catch common mistakes for panels. */ 628 switch (connector_type) { 629 case 0: 630 dev_warn(dev, "Specify missing connector_type\n"); 631 connector_type = DRM_MODE_CONNECTOR_DPI; 632 break; 633 case DRM_MODE_CONNECTOR_LVDS: 634 WARN_ON(desc->bus_flags & 635 ~(DRM_BUS_FLAG_DE_LOW | 636 DRM_BUS_FLAG_DE_HIGH | 637 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 638 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 639 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 640 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 641 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 642 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 643 desc->bpc != 6); 644 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 645 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 646 desc->bpc != 8); 647 break; 648 case DRM_MODE_CONNECTOR_eDP: 649 dev_warn(dev, "eDP panels moved to panel-edp\n"); 650 return ERR_PTR(-EINVAL); 651 case DRM_MODE_CONNECTOR_DSI: 652 if (desc->bpc != 6 && desc->bpc != 8) 653 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 654 break; 655 case DRM_MODE_CONNECTOR_DPI: 656 bus_flags = DRM_BUS_FLAG_DE_LOW | 657 DRM_BUS_FLAG_DE_HIGH | 658 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 659 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 660 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 661 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 662 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 663 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 664 if (desc->bus_flags & ~bus_flags) 665 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 666 if (!(desc->bus_flags & bus_flags)) 667 dev_warn(dev, "Specify missing bus_flags\n"); 668 if (desc->bus_format == 0) 669 dev_warn(dev, "Specify missing bus_format\n"); 670 if (desc->bpc != 6 && desc->bpc != 8) 671 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 672 break; 673 default: 674 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 675 connector_type = DRM_MODE_CONNECTOR_DPI; 676 break; 677 } 678 679 panel = devm_drm_panel_alloc(dev, struct panel_simple, base, 680 &panel_simple_funcs, connector_type); 681 if (IS_ERR(panel)) 682 return ERR_CAST(panel); 683 684 panel->desc = desc; 685 686 panel->supply = devm_regulator_get(dev, "power"); 687 if (IS_ERR(panel->supply)) 688 return ERR_CAST(panel->supply); 689 690 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 691 GPIOD_OUT_LOW); 692 if (IS_ERR(panel->enable_gpio)) 693 return dev_err_cast_probe(dev, panel->enable_gpio, 694 "failed to request GPIO\n"); 695 696 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 697 if (err) { 698 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 699 return ERR_PTR(err); 700 } 701 702 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 703 if (ddc) { 704 panel->ddc = of_find_i2c_adapter_by_node(ddc); 705 of_node_put(ddc); 706 707 if (!panel->ddc) 708 return ERR_PTR(-EPROBE_DEFER); 709 } 710 711 if (!of_device_is_compatible(dev->of_node, "panel-dpi") && 712 !of_get_display_timing(dev->of_node, "panel-timing", &dt)) 713 panel_simple_parse_panel_timing_node(dev, panel, &dt); 714 715 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 716 /* Optional data-mapping property for overriding bus format */ 717 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 718 if (err) 719 goto free_ddc; 720 } 721 722 dev_set_drvdata(dev, panel); 723 724 /* 725 * We use runtime PM for prepare / unprepare since those power the panel 726 * on and off and those can be very slow operations. This is important 727 * to optimize powering the panel on briefly to read the EDID before 728 * fully enabling the panel. 729 */ 730 pm_runtime_enable(dev); 731 pm_runtime_set_autosuspend_delay(dev, 1000); 732 pm_runtime_use_autosuspend(dev); 733 734 err = drm_panel_of_backlight(&panel->base); 735 if (err) { 736 dev_err_probe(dev, err, "Could not find backlight\n"); 737 goto disable_pm_runtime; 738 } 739 740 drm_panel_add(&panel->base); 741 742 return panel; 743 744 disable_pm_runtime: 745 pm_runtime_dont_use_autosuspend(dev); 746 pm_runtime_disable(dev); 747 free_ddc: 748 if (panel->ddc) 749 put_device(&panel->ddc->dev); 750 751 return ERR_PTR(err); 752 } 753 754 static void panel_simple_shutdown(struct device *dev) 755 { 756 struct panel_simple *panel = dev_get_drvdata(dev); 757 758 /* 759 * NOTE: the following two calls don't really belong here. It is the 760 * responsibility of a correctly written DRM modeset driver to call 761 * drm_atomic_helper_shutdown() at shutdown time and that should 762 * cause the panel to be disabled / unprepared if needed. For now, 763 * however, we'll keep these calls due to the sheer number of 764 * different DRM modeset drivers used with panel-simple. Once we've 765 * confirmed that all DRM modeset drivers using this panel properly 766 * call drm_atomic_helper_shutdown() we can simply delete the two 767 * calls below. 768 * 769 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW 770 * PANEL DRIVERS. 771 * 772 * FIXME: If we're still haven't figured out if all DRM modeset 773 * drivers properly call drm_atomic_helper_shutdown() but we _have_ 774 * managed to make sure that DRM modeset drivers get their shutdown() 775 * callback before the panel's shutdown() callback (perhaps using 776 * device link), we could add a WARN_ON here to help move forward. 777 */ 778 if (panel->base.enabled) 779 drm_panel_disable(&panel->base); 780 if (panel->base.prepared) 781 drm_panel_unprepare(&panel->base); 782 } 783 784 static void panel_simple_remove(struct device *dev) 785 { 786 struct panel_simple *panel = dev_get_drvdata(dev); 787 788 drm_panel_remove(&panel->base); 789 panel_simple_shutdown(dev); 790 791 pm_runtime_dont_use_autosuspend(dev); 792 pm_runtime_disable(dev); 793 if (panel->ddc) 794 put_device(&panel->ddc->dev); 795 } 796 797 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 798 .clock = 71100, 799 .hdisplay = 1280, 800 .hsync_start = 1280 + 40, 801 .hsync_end = 1280 + 40 + 80, 802 .htotal = 1280 + 40 + 80 + 40, 803 .vdisplay = 800, 804 .vsync_start = 800 + 3, 805 .vsync_end = 800 + 3 + 10, 806 .vtotal = 800 + 3 + 10 + 10, 807 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 808 }; 809 810 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 811 .modes = &ire_am_1280800n3tzqw_t00h_mode, 812 .num_modes = 1, 813 .bpc = 8, 814 .size = { 815 .width = 217, 816 .height = 136, 817 }, 818 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 819 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 820 .connector_type = DRM_MODE_CONNECTOR_LVDS, 821 }; 822 823 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 824 .clock = 9000, 825 .hdisplay = 480, 826 .hsync_start = 480 + 2, 827 .hsync_end = 480 + 2 + 41, 828 .htotal = 480 + 2 + 41 + 2, 829 .vdisplay = 272, 830 .vsync_start = 272 + 2, 831 .vsync_end = 272 + 2 + 10, 832 .vtotal = 272 + 2 + 10 + 2, 833 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 834 }; 835 836 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 837 .modes = &ire_am_480272h3tmqw_t01h_mode, 838 .num_modes = 1, 839 .bpc = 8, 840 .size = { 841 .width = 99, 842 .height = 58, 843 }, 844 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 845 }; 846 847 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 848 .clock = 33333, 849 .hdisplay = 800, 850 .hsync_start = 800 + 0, 851 .hsync_end = 800 + 0 + 255, 852 .htotal = 800 + 0 + 255 + 0, 853 .vdisplay = 480, 854 .vsync_start = 480 + 2, 855 .vsync_end = 480 + 2 + 45, 856 .vtotal = 480 + 2 + 45 + 0, 857 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 858 }; 859 860 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 861 .pixelclock = { 29930000, 33260000, 36590000 }, 862 .hactive = { 800, 800, 800 }, 863 .hfront_porch = { 1, 40, 168 }, 864 .hback_porch = { 88, 88, 88 }, 865 .hsync_len = { 1, 128, 128 }, 866 .vactive = { 480, 480, 480 }, 867 .vfront_porch = { 1, 35, 37 }, 868 .vback_porch = { 8, 8, 8 }, 869 .vsync_len = { 1, 2, 2 }, 870 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 871 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 872 DISPLAY_FLAGS_SYNC_POSEDGE, 873 }; 874 875 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 876 .timings = &ire_am_800480l1tmqw_t00h_timing, 877 .num_timings = 1, 878 .bpc = 8, 879 .size = { 880 .width = 111, 881 .height = 67, 882 }, 883 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 884 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 885 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 886 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 887 .connector_type = DRM_MODE_CONNECTOR_DPI, 888 }; 889 890 static const struct panel_desc ampire_am800480r3tmqwa1h = { 891 .modes = &ire_am800480r3tmqwa1h_mode, 892 .num_modes = 1, 893 .bpc = 6, 894 .size = { 895 .width = 152, 896 .height = 91, 897 }, 898 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 899 }; 900 901 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 902 .pixelclock = { 34500000, 39600000, 50400000 }, 903 .hactive = { 800, 800, 800 }, 904 .hfront_porch = { 12, 112, 312 }, 905 .hback_porch = { 87, 87, 48 }, 906 .hsync_len = { 1, 1, 40 }, 907 .vactive = { 600, 600, 600 }, 908 .vfront_porch = { 1, 21, 61 }, 909 .vback_porch = { 38, 38, 19 }, 910 .vsync_len = { 1, 1, 20 }, 911 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 912 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 913 DISPLAY_FLAGS_SYNC_POSEDGE, 914 }; 915 916 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 917 .timings = &ire_am800600p5tmqw_tb8h_timing, 918 .num_timings = 1, 919 .bpc = 6, 920 .size = { 921 .width = 162, 922 .height = 122, 923 }, 924 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 925 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 926 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 927 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 928 .connector_type = DRM_MODE_CONNECTOR_DPI, 929 }; 930 931 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 932 .pixelclock = { 26400000, 33300000, 46800000 }, 933 .hactive = { 800, 800, 800 }, 934 .hfront_porch = { 16, 210, 354 }, 935 .hback_porch = { 45, 36, 6 }, 936 .hsync_len = { 1, 10, 40 }, 937 .vactive = { 480, 480, 480 }, 938 .vfront_porch = { 7, 22, 147 }, 939 .vback_porch = { 22, 13, 3 }, 940 .vsync_len = { 1, 10, 20 }, 941 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 942 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 943 }; 944 945 static const struct panel_desc armadeus_st0700_adapt = { 946 .timings = &santek_st0700i5y_rbslw_f_timing, 947 .num_timings = 1, 948 .bpc = 6, 949 .size = { 950 .width = 154, 951 .height = 86, 952 }, 953 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 954 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 955 }; 956 957 static const struct drm_display_mode auo_b101aw03_mode = { 958 .clock = 51450, 959 .hdisplay = 1024, 960 .hsync_start = 1024 + 156, 961 .hsync_end = 1024 + 156 + 8, 962 .htotal = 1024 + 156 + 8 + 156, 963 .vdisplay = 600, 964 .vsync_start = 600 + 16, 965 .vsync_end = 600 + 16 + 6, 966 .vtotal = 600 + 16 + 6 + 16, 967 }; 968 969 static const struct panel_desc auo_b101aw03 = { 970 .modes = &auo_b101aw03_mode, 971 .num_modes = 1, 972 .bpc = 6, 973 .size = { 974 .width = 223, 975 .height = 125, 976 }, 977 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 978 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 979 .connector_type = DRM_MODE_CONNECTOR_LVDS, 980 }; 981 982 static const struct drm_display_mode auo_b101xtn01_mode = { 983 .clock = 72000, 984 .hdisplay = 1366, 985 .hsync_start = 1366 + 20, 986 .hsync_end = 1366 + 20 + 70, 987 .htotal = 1366 + 20 + 70, 988 .vdisplay = 768, 989 .vsync_start = 768 + 14, 990 .vsync_end = 768 + 14 + 42, 991 .vtotal = 768 + 14 + 42, 992 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 993 }; 994 995 static const struct panel_desc auo_b101xtn01 = { 996 .modes = &auo_b101xtn01_mode, 997 .num_modes = 1, 998 .bpc = 6, 999 .size = { 1000 .width = 223, 1001 .height = 125, 1002 }, 1003 }; 1004 1005 static const struct drm_display_mode auo_b116xw03_mode = { 1006 .clock = 70589, 1007 .hdisplay = 1366, 1008 .hsync_start = 1366 + 40, 1009 .hsync_end = 1366 + 40 + 40, 1010 .htotal = 1366 + 40 + 40 + 32, 1011 .vdisplay = 768, 1012 .vsync_start = 768 + 10, 1013 .vsync_end = 768 + 10 + 12, 1014 .vtotal = 768 + 10 + 12 + 6, 1015 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1016 }; 1017 1018 static const struct panel_desc auo_b116xw03 = { 1019 .modes = &auo_b116xw03_mode, 1020 .num_modes = 1, 1021 .bpc = 6, 1022 .size = { 1023 .width = 256, 1024 .height = 144, 1025 }, 1026 .delay = { 1027 .prepare = 1, 1028 .enable = 200, 1029 .disable = 200, 1030 .unprepare = 500, 1031 }, 1032 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1033 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1034 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1035 }; 1036 1037 static const struct display_timing auo_g070vvn01_timings = { 1038 .pixelclock = { 33300000, 34209000, 45000000 }, 1039 .hactive = { 800, 800, 800 }, 1040 .hfront_porch = { 20, 40, 200 }, 1041 .hback_porch = { 87, 40, 1 }, 1042 .hsync_len = { 1, 48, 87 }, 1043 .vactive = { 480, 480, 480 }, 1044 .vfront_porch = { 5, 13, 200 }, 1045 .vback_porch = { 31, 31, 29 }, 1046 .vsync_len = { 1, 1, 3 }, 1047 }; 1048 1049 static const struct panel_desc auo_g070vvn01 = { 1050 .timings = &auo_g070vvn01_timings, 1051 .num_timings = 1, 1052 .bpc = 8, 1053 .size = { 1054 .width = 152, 1055 .height = 91, 1056 }, 1057 .delay = { 1058 .prepare = 200, 1059 .enable = 50, 1060 .disable = 50, 1061 .unprepare = 1000, 1062 }, 1063 }; 1064 1065 static const struct display_timing auo_g101evn010_timing = { 1066 .pixelclock = { 64000000, 68930000, 85000000 }, 1067 .hactive = { 1280, 1280, 1280 }, 1068 .hfront_porch = { 8, 64, 256 }, 1069 .hback_porch = { 8, 64, 256 }, 1070 .hsync_len = { 40, 168, 767 }, 1071 .vactive = { 800, 800, 800 }, 1072 .vfront_porch = { 4, 8, 100 }, 1073 .vback_porch = { 4, 8, 100 }, 1074 .vsync_len = { 8, 16, 223 }, 1075 }; 1076 1077 static const struct panel_desc auo_g101evn010 = { 1078 .timings = &auo_g101evn010_timing, 1079 .num_timings = 1, 1080 .bpc = 6, 1081 .size = { 1082 .width = 216, 1083 .height = 135, 1084 }, 1085 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1086 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1087 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1088 }; 1089 1090 static const struct drm_display_mode auo_g104sn02_mode = { 1091 .clock = 40000, 1092 .hdisplay = 800, 1093 .hsync_start = 800 + 40, 1094 .hsync_end = 800 + 40 + 216, 1095 .htotal = 800 + 40 + 216 + 128, 1096 .vdisplay = 600, 1097 .vsync_start = 600 + 10, 1098 .vsync_end = 600 + 10 + 35, 1099 .vtotal = 600 + 10 + 35 + 2, 1100 }; 1101 1102 static const struct panel_desc auo_g104sn02 = { 1103 .modes = &auo_g104sn02_mode, 1104 .num_modes = 1, 1105 .bpc = 8, 1106 .size = { 1107 .width = 211, 1108 .height = 158, 1109 }, 1110 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1111 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1112 }; 1113 1114 static const struct drm_display_mode auo_g104stn01_mode = { 1115 .clock = 40000, 1116 .hdisplay = 800, 1117 .hsync_start = 800 + 40, 1118 .hsync_end = 800 + 40 + 88, 1119 .htotal = 800 + 40 + 88 + 128, 1120 .vdisplay = 600, 1121 .vsync_start = 600 + 1, 1122 .vsync_end = 600 + 1 + 23, 1123 .vtotal = 600 + 1 + 23 + 4, 1124 }; 1125 1126 static const struct panel_desc auo_g104stn01 = { 1127 .modes = &auo_g104stn01_mode, 1128 .num_modes = 1, 1129 .bpc = 8, 1130 .size = { 1131 .width = 211, 1132 .height = 158, 1133 }, 1134 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1135 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1136 }; 1137 1138 static const struct display_timing auo_g121ean01_timing = { 1139 .pixelclock = { 60000000, 74400000, 90000000 }, 1140 .hactive = { 1280, 1280, 1280 }, 1141 .hfront_porch = { 20, 50, 100 }, 1142 .hback_porch = { 20, 50, 100 }, 1143 .hsync_len = { 30, 100, 200 }, 1144 .vactive = { 800, 800, 800 }, 1145 .vfront_porch = { 2, 10, 25 }, 1146 .vback_porch = { 2, 10, 25 }, 1147 .vsync_len = { 4, 18, 50 }, 1148 }; 1149 1150 static const struct panel_desc auo_g121ean01 = { 1151 .timings = &auo_g121ean01_timing, 1152 .num_timings = 1, 1153 .bpc = 8, 1154 .size = { 1155 .width = 261, 1156 .height = 163, 1157 }, 1158 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1159 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1160 }; 1161 1162 static const struct display_timing auo_g133han01_timings = { 1163 .pixelclock = { 134000000, 141200000, 149000000 }, 1164 .hactive = { 1920, 1920, 1920 }, 1165 .hfront_porch = { 39, 58, 77 }, 1166 .hback_porch = { 59, 88, 117 }, 1167 .hsync_len = { 28, 42, 56 }, 1168 .vactive = { 1080, 1080, 1080 }, 1169 .vfront_porch = { 3, 8, 11 }, 1170 .vback_porch = { 5, 14, 19 }, 1171 .vsync_len = { 4, 14, 19 }, 1172 }; 1173 1174 static const struct panel_desc auo_g133han01 = { 1175 .timings = &auo_g133han01_timings, 1176 .num_timings = 1, 1177 .bpc = 8, 1178 .size = { 1179 .width = 293, 1180 .height = 165, 1181 }, 1182 .delay = { 1183 .prepare = 200, 1184 .enable = 50, 1185 .disable = 50, 1186 .unprepare = 1000, 1187 }, 1188 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1189 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1190 }; 1191 1192 static const struct display_timing auo_g156han04_timings = { 1193 .pixelclock = { 137000000, 141000000, 146000000 }, 1194 .hactive = { 1920, 1920, 1920 }, 1195 .hfront_porch = { 60, 60, 60 }, 1196 .hback_porch = { 90, 92, 111 }, 1197 .hsync_len = { 32, 32, 32 }, 1198 .vactive = { 1080, 1080, 1080 }, 1199 .vfront_porch = { 12, 12, 12 }, 1200 .vback_porch = { 24, 36, 56 }, 1201 .vsync_len = { 8, 8, 8 }, 1202 }; 1203 1204 static const struct panel_desc auo_g156han04 = { 1205 .timings = &auo_g156han04_timings, 1206 .num_timings = 1, 1207 .bpc = 8, 1208 .size = { 1209 .width = 344, 1210 .height = 194, 1211 }, 1212 .delay = { 1213 .prepare = 50, /* T2 */ 1214 .enable = 200, /* T3 */ 1215 .disable = 110, /* T10 */ 1216 .unprepare = 1000, /* T13 */ 1217 }, 1218 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1219 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1220 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1221 }; 1222 1223 static const struct drm_display_mode auo_g156xtn01_mode = { 1224 .clock = 76000, 1225 .hdisplay = 1366, 1226 .hsync_start = 1366 + 33, 1227 .hsync_end = 1366 + 33 + 67, 1228 .htotal = 1560, 1229 .vdisplay = 768, 1230 .vsync_start = 768 + 4, 1231 .vsync_end = 768 + 4 + 4, 1232 .vtotal = 806, 1233 }; 1234 1235 static const struct panel_desc auo_g156xtn01 = { 1236 .modes = &auo_g156xtn01_mode, 1237 .num_modes = 1, 1238 .bpc = 8, 1239 .size = { 1240 .width = 344, 1241 .height = 194, 1242 }, 1243 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1244 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1245 }; 1246 1247 static const struct display_timing auo_g185han01_timings = { 1248 .pixelclock = { 120000000, 144000000, 175000000 }, 1249 .hactive = { 1920, 1920, 1920 }, 1250 .hfront_porch = { 36, 120, 148 }, 1251 .hback_porch = { 24, 88, 108 }, 1252 .hsync_len = { 20, 48, 64 }, 1253 .vactive = { 1080, 1080, 1080 }, 1254 .vfront_porch = { 6, 10, 40 }, 1255 .vback_porch = { 2, 5, 20 }, 1256 .vsync_len = { 2, 5, 20 }, 1257 }; 1258 1259 static const struct panel_desc auo_g185han01 = { 1260 .timings = &auo_g185han01_timings, 1261 .num_timings = 1, 1262 .bpc = 8, 1263 .size = { 1264 .width = 409, 1265 .height = 230, 1266 }, 1267 .delay = { 1268 .prepare = 50, 1269 .enable = 200, 1270 .disable = 110, 1271 .unprepare = 1000, 1272 }, 1273 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1274 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1275 }; 1276 1277 static const struct display_timing auo_g190ean01_timings = { 1278 .pixelclock = { 90000000, 108000000, 135000000 }, 1279 .hactive = { 1280, 1280, 1280 }, 1280 .hfront_porch = { 126, 184, 1266 }, 1281 .hback_porch = { 84, 122, 844 }, 1282 .hsync_len = { 70, 102, 704 }, 1283 .vactive = { 1024, 1024, 1024 }, 1284 .vfront_porch = { 4, 26, 76 }, 1285 .vback_porch = { 2, 8, 25 }, 1286 .vsync_len = { 2, 8, 25 }, 1287 }; 1288 1289 static const struct panel_desc auo_g190ean01 = { 1290 .timings = &auo_g190ean01_timings, 1291 .num_timings = 1, 1292 .bpc = 8, 1293 .size = { 1294 .width = 376, 1295 .height = 301, 1296 }, 1297 .delay = { 1298 .prepare = 30, 1299 .enable = 200, 1300 .disable = 110, 1301 .unprepare = 1000, 1302 }, 1303 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1304 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1305 }; 1306 1307 static const struct display_timing auo_p238han01_timings = { 1308 .pixelclock = { 107400000, 142400000, 180000000 }, 1309 .hactive = { 1920, 1920, 1920 }, 1310 .hfront_porch = { 30, 70, 650 }, 1311 .hback_porch = { 30, 70, 650 }, 1312 .hsync_len = { 20, 40, 136 }, 1313 .vactive = { 1080, 1080, 1080 }, 1314 .vfront_porch = { 5, 19, 318 }, 1315 .vback_porch = { 5, 19, 318 }, 1316 .vsync_len = { 4, 12, 120 }, 1317 }; 1318 1319 static const struct panel_desc auo_p238han01 = { 1320 .timings = &auo_p238han01_timings, 1321 .num_timings = 1, 1322 .bpc = 8, 1323 .size = { 1324 .width = 527, 1325 .height = 296, 1326 }, 1327 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1328 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1329 }; 1330 1331 static const struct display_timing auo_p320hvn03_timings = { 1332 .pixelclock = { 106000000, 148500000, 164000000 }, 1333 .hactive = { 1920, 1920, 1920 }, 1334 .hfront_porch = { 25, 50, 130 }, 1335 .hback_porch = { 25, 50, 130 }, 1336 .hsync_len = { 20, 40, 105 }, 1337 .vactive = { 1080, 1080, 1080 }, 1338 .vfront_porch = { 8, 17, 150 }, 1339 .vback_porch = { 8, 17, 150 }, 1340 .vsync_len = { 4, 11, 100 }, 1341 }; 1342 1343 static const struct panel_desc auo_p320hvn03 = { 1344 .timings = &auo_p320hvn03_timings, 1345 .num_timings = 1, 1346 .bpc = 8, 1347 .size = { 1348 .width = 698, 1349 .height = 393, 1350 }, 1351 .delay = { 1352 .prepare = 1, 1353 .enable = 450, 1354 .unprepare = 500, 1355 }, 1356 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1357 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1358 }; 1359 1360 static const struct drm_display_mode auo_t215hvn01_mode = { 1361 .clock = 148800, 1362 .hdisplay = 1920, 1363 .hsync_start = 1920 + 88, 1364 .hsync_end = 1920 + 88 + 44, 1365 .htotal = 1920 + 88 + 44 + 148, 1366 .vdisplay = 1080, 1367 .vsync_start = 1080 + 4, 1368 .vsync_end = 1080 + 4 + 5, 1369 .vtotal = 1080 + 4 + 5 + 36, 1370 }; 1371 1372 static const struct panel_desc auo_t215hvn01 = { 1373 .modes = &auo_t215hvn01_mode, 1374 .num_modes = 1, 1375 .bpc = 8, 1376 .size = { 1377 .width = 430, 1378 .height = 270, 1379 }, 1380 .delay = { 1381 .disable = 5, 1382 .unprepare = 1000, 1383 }, 1384 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1385 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1386 }; 1387 1388 static const struct drm_display_mode avic_tm070ddh03_mode = { 1389 .clock = 51200, 1390 .hdisplay = 1024, 1391 .hsync_start = 1024 + 160, 1392 .hsync_end = 1024 + 160 + 4, 1393 .htotal = 1024 + 160 + 4 + 156, 1394 .vdisplay = 600, 1395 .vsync_start = 600 + 17, 1396 .vsync_end = 600 + 17 + 1, 1397 .vtotal = 600 + 17 + 1 + 17, 1398 }; 1399 1400 static const struct panel_desc avic_tm070ddh03 = { 1401 .modes = &avic_tm070ddh03_mode, 1402 .num_modes = 1, 1403 .bpc = 8, 1404 .size = { 1405 .width = 154, 1406 .height = 90, 1407 }, 1408 .delay = { 1409 .prepare = 20, 1410 .enable = 200, 1411 .disable = 200, 1412 }, 1413 }; 1414 1415 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1416 .clock = 30000, 1417 .hdisplay = 800, 1418 .hsync_start = 800 + 40, 1419 .hsync_end = 800 + 40 + 48, 1420 .htotal = 800 + 40 + 48 + 40, 1421 .vdisplay = 480, 1422 .vsync_start = 480 + 13, 1423 .vsync_end = 480 + 13 + 3, 1424 .vtotal = 480 + 13 + 3 + 29, 1425 }; 1426 1427 static const struct panel_desc bananapi_s070wv20_ct16 = { 1428 .modes = &bananapi_s070wv20_ct16_mode, 1429 .num_modes = 1, 1430 .bpc = 6, 1431 .size = { 1432 .width = 154, 1433 .height = 86, 1434 }, 1435 }; 1436 1437 static const struct display_timing boe_av101hdt_a10_timing = { 1438 .pixelclock = { 74210000, 75330000, 76780000, }, 1439 .hactive = { 1280, 1280, 1280, }, 1440 .hfront_porch = { 10, 42, 33, }, 1441 .hback_porch = { 10, 18, 33, }, 1442 .hsync_len = { 30, 10, 30, }, 1443 .vactive = { 720, 720, 720, }, 1444 .vfront_porch = { 200, 183, 200, }, 1445 .vback_porch = { 8, 8, 8, }, 1446 .vsync_len = { 2, 19, 2, }, 1447 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1448 }; 1449 1450 static const struct panel_desc boe_av101hdt_a10 = { 1451 .timings = &boe_av101hdt_a10_timing, 1452 .num_timings = 1, 1453 .bpc = 8, 1454 .size = { 1455 .width = 224, 1456 .height = 126, 1457 }, 1458 .delay = { 1459 .enable = 50, 1460 .disable = 50, 1461 }, 1462 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1463 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1464 }; 1465 1466 static const struct display_timing boe_av123z7m_n17_timing = { 1467 .pixelclock = { 86600000, 88000000, 90800000, }, 1468 .hactive = { 1920, 1920, 1920, }, 1469 .hfront_porch = { 10, 10, 10, }, 1470 .hback_porch = { 10, 10, 10, }, 1471 .hsync_len = { 9, 12, 25, }, 1472 .vactive = { 720, 720, 720, }, 1473 .vfront_porch = { 7, 10, 13, }, 1474 .vback_porch = { 7, 10, 13, }, 1475 .vsync_len = { 7, 11, 14, }, 1476 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1477 }; 1478 1479 static const struct panel_desc boe_av123z7m_n17 = { 1480 .timings = &boe_av123z7m_n17_timing, 1481 .bpc = 8, 1482 .num_timings = 1, 1483 .size = { 1484 .width = 292, 1485 .height = 110, 1486 }, 1487 .delay = { 1488 .prepare = 50, 1489 .disable = 50, 1490 }, 1491 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1492 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1493 }; 1494 1495 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1496 .clock = 78945, 1497 .hdisplay = 1280, 1498 .hsync_start = 1280 + 0, 1499 .hsync_end = 1280 + 0 + 2, 1500 .htotal = 1280 + 62 + 0 + 2, 1501 .vdisplay = 800, 1502 .vsync_start = 800 + 8, 1503 .vsync_end = 800 + 8 + 2, 1504 .vtotal = 800 + 6 + 8 + 2, 1505 }; 1506 1507 static const struct panel_desc boe_bp082wx1_100 = { 1508 .modes = &boe_bp101wx1_100_mode, 1509 .num_modes = 1, 1510 .bpc = 8, 1511 .size = { 1512 .width = 177, 1513 .height = 110, 1514 }, 1515 .delay = { 1516 .enable = 50, 1517 .disable = 50, 1518 }, 1519 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1520 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1521 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1522 }; 1523 1524 static const struct panel_desc boe_bp101wx1_100 = { 1525 .modes = &boe_bp101wx1_100_mode, 1526 .num_modes = 1, 1527 .bpc = 8, 1528 .size = { 1529 .width = 217, 1530 .height = 136, 1531 }, 1532 .delay = { 1533 .enable = 50, 1534 .disable = 50, 1535 }, 1536 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1537 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1538 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1539 }; 1540 1541 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1542 .pixelclock = { 69922000, 71000000, 72293000 }, 1543 .hactive = { 1280, 1280, 1280 }, 1544 .hfront_porch = { 48, 48, 48 }, 1545 .hback_porch = { 80, 80, 80 }, 1546 .hsync_len = { 32, 32, 32 }, 1547 .vactive = { 800, 800, 800 }, 1548 .vfront_porch = { 3, 3, 3 }, 1549 .vback_porch = { 14, 14, 14 }, 1550 .vsync_len = { 6, 6, 6 }, 1551 }; 1552 1553 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1554 .timings = &boe_ev121wxm_n10_1850_timing, 1555 .num_timings = 1, 1556 .bpc = 8, 1557 .size = { 1558 .width = 261, 1559 .height = 163, 1560 }, 1561 .delay = { 1562 .prepare = 9, 1563 .enable = 300, 1564 .unprepare = 300, 1565 .disable = 560, 1566 }, 1567 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1568 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1569 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1570 }; 1571 1572 static const struct drm_display_mode boe_hv070wsa_mode = { 1573 .clock = 42105, 1574 .hdisplay = 1024, 1575 .hsync_start = 1024 + 30, 1576 .hsync_end = 1024 + 30 + 30, 1577 .htotal = 1024 + 30 + 30 + 30, 1578 .vdisplay = 600, 1579 .vsync_start = 600 + 10, 1580 .vsync_end = 600 + 10 + 10, 1581 .vtotal = 600 + 10 + 10 + 10, 1582 }; 1583 1584 static const struct panel_desc boe_hv070wsa = { 1585 .modes = &boe_hv070wsa_mode, 1586 .num_modes = 1, 1587 .bpc = 8, 1588 .size = { 1589 .width = 154, 1590 .height = 90, 1591 }, 1592 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1593 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1594 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1595 }; 1596 1597 static const struct display_timing cct_cmt430b19n00_timing = { 1598 .pixelclock = { 8000000, 9000000, 12000000 }, 1599 .hactive = { 480, 480, 480 }, 1600 .hfront_porch = { 2, 8, 75 }, 1601 .hback_porch = { 3, 43, 43 }, 1602 .hsync_len = { 2, 4, 75 }, 1603 .vactive = { 272, 272, 272 }, 1604 .vfront_porch = { 2, 8, 37 }, 1605 .vback_porch = { 2, 12, 12 }, 1606 .vsync_len = { 2, 4, 37 }, 1607 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1608 }; 1609 1610 static const struct panel_desc cct_cmt430b19n00 = { 1611 .timings = &cct_cmt430b19n00_timing, 1612 .num_timings = 1, 1613 .bpc = 8, 1614 .size = { 1615 .width = 95, 1616 .height = 53, 1617 }, 1618 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1619 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1620 .connector_type = DRM_MODE_CONNECTOR_DPI, 1621 }; 1622 1623 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1624 .clock = 9000, 1625 .hdisplay = 480, 1626 .hsync_start = 480 + 5, 1627 .hsync_end = 480 + 5 + 5, 1628 .htotal = 480 + 5 + 5 + 40, 1629 .vdisplay = 272, 1630 .vsync_start = 272 + 8, 1631 .vsync_end = 272 + 8 + 8, 1632 .vtotal = 272 + 8 + 8 + 8, 1633 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1634 }; 1635 1636 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1637 .modes = &cdtech_s043wq26h_ct7_mode, 1638 .num_modes = 1, 1639 .bpc = 8, 1640 .size = { 1641 .width = 95, 1642 .height = 54, 1643 }, 1644 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1645 }; 1646 1647 /* S070PWS19HP-FC21 2017/04/22 */ 1648 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1649 .clock = 51200, 1650 .hdisplay = 1024, 1651 .hsync_start = 1024 + 160, 1652 .hsync_end = 1024 + 160 + 20, 1653 .htotal = 1024 + 160 + 20 + 140, 1654 .vdisplay = 600, 1655 .vsync_start = 600 + 12, 1656 .vsync_end = 600 + 12 + 3, 1657 .vtotal = 600 + 12 + 3 + 20, 1658 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1659 }; 1660 1661 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1662 .modes = &cdtech_s070pws19hp_fc21_mode, 1663 .num_modes = 1, 1664 .bpc = 6, 1665 .size = { 1666 .width = 154, 1667 .height = 86, 1668 }, 1669 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1670 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1671 .connector_type = DRM_MODE_CONNECTOR_DPI, 1672 }; 1673 1674 /* S070SWV29HG-DC44 2017/09/21 */ 1675 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1676 .clock = 33300, 1677 .hdisplay = 800, 1678 .hsync_start = 800 + 210, 1679 .hsync_end = 800 + 210 + 2, 1680 .htotal = 800 + 210 + 2 + 44, 1681 .vdisplay = 480, 1682 .vsync_start = 480 + 22, 1683 .vsync_end = 480 + 22 + 2, 1684 .vtotal = 480 + 22 + 2 + 21, 1685 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1686 }; 1687 1688 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1689 .modes = &cdtech_s070swv29hg_dc44_mode, 1690 .num_modes = 1, 1691 .bpc = 6, 1692 .size = { 1693 .width = 154, 1694 .height = 86, 1695 }, 1696 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1697 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1698 .connector_type = DRM_MODE_CONNECTOR_DPI, 1699 }; 1700 1701 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1702 .clock = 35000, 1703 .hdisplay = 800, 1704 .hsync_start = 800 + 40, 1705 .hsync_end = 800 + 40 + 40, 1706 .htotal = 800 + 40 + 40 + 48, 1707 .vdisplay = 480, 1708 .vsync_start = 480 + 29, 1709 .vsync_end = 480 + 29 + 13, 1710 .vtotal = 480 + 29 + 13 + 3, 1711 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1712 }; 1713 1714 static const struct panel_desc cdtech_s070wv95_ct16 = { 1715 .modes = &cdtech_s070wv95_ct16_mode, 1716 .num_modes = 1, 1717 .bpc = 8, 1718 .size = { 1719 .width = 154, 1720 .height = 85, 1721 }, 1722 }; 1723 1724 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1725 .pixelclock = { 68900000, 71100000, 73400000 }, 1726 .hactive = { 1280, 1280, 1280 }, 1727 .hfront_porch = { 65, 80, 95 }, 1728 .hback_porch = { 64, 79, 94 }, 1729 .hsync_len = { 1, 1, 1 }, 1730 .vactive = { 800, 800, 800 }, 1731 .vfront_porch = { 7, 11, 14 }, 1732 .vback_porch = { 7, 11, 14 }, 1733 .vsync_len = { 1, 1, 1 }, 1734 .flags = DISPLAY_FLAGS_DE_HIGH, 1735 }; 1736 1737 static const struct panel_desc chefree_ch101olhlwh_002 = { 1738 .timings = &chefree_ch101olhlwh_002_timing, 1739 .num_timings = 1, 1740 .bpc = 8, 1741 .size = { 1742 .width = 217, 1743 .height = 135, 1744 }, 1745 .delay = { 1746 .enable = 200, 1747 .disable = 200, 1748 }, 1749 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1750 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1751 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1752 }; 1753 1754 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1755 .clock = 66770, 1756 .hdisplay = 800, 1757 .hsync_start = 800 + 49, 1758 .hsync_end = 800 + 49 + 33, 1759 .htotal = 800 + 49 + 33 + 17, 1760 .vdisplay = 1280, 1761 .vsync_start = 1280 + 1, 1762 .vsync_end = 1280 + 1 + 7, 1763 .vtotal = 1280 + 1 + 7 + 15, 1764 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1765 }; 1766 1767 static const struct panel_desc chunghwa_claa070wp03xg = { 1768 .modes = &chunghwa_claa070wp03xg_mode, 1769 .num_modes = 1, 1770 .bpc = 6, 1771 .size = { 1772 .width = 94, 1773 .height = 150, 1774 }, 1775 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1776 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1777 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1778 }; 1779 1780 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1781 .clock = 72070, 1782 .hdisplay = 1366, 1783 .hsync_start = 1366 + 58, 1784 .hsync_end = 1366 + 58 + 58, 1785 .htotal = 1366 + 58 + 58 + 58, 1786 .vdisplay = 768, 1787 .vsync_start = 768 + 4, 1788 .vsync_end = 768 + 4 + 4, 1789 .vtotal = 768 + 4 + 4 + 4, 1790 }; 1791 1792 static const struct panel_desc chunghwa_claa101wa01a = { 1793 .modes = &chunghwa_claa101wa01a_mode, 1794 .num_modes = 1, 1795 .bpc = 6, 1796 .size = { 1797 .width = 220, 1798 .height = 120, 1799 }, 1800 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1801 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1802 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1803 }; 1804 1805 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1806 .clock = 69300, 1807 .hdisplay = 1366, 1808 .hsync_start = 1366 + 48, 1809 .hsync_end = 1366 + 48 + 32, 1810 .htotal = 1366 + 48 + 32 + 20, 1811 .vdisplay = 768, 1812 .vsync_start = 768 + 16, 1813 .vsync_end = 768 + 16 + 8, 1814 .vtotal = 768 + 16 + 8 + 16, 1815 }; 1816 1817 static const struct panel_desc chunghwa_claa101wb01 = { 1818 .modes = &chunghwa_claa101wb01_mode, 1819 .num_modes = 1, 1820 .bpc = 6, 1821 .size = { 1822 .width = 223, 1823 .height = 125, 1824 }, 1825 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1826 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1827 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1828 }; 1829 1830 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1831 .pixelclock = { 5000000, 9000000, 12000000 }, 1832 .hactive = { 480, 480, 480 }, 1833 .hfront_porch = { 12, 12, 12 }, 1834 .hback_porch = { 12, 12, 12 }, 1835 .hsync_len = { 21, 21, 21 }, 1836 .vactive = { 272, 272, 272 }, 1837 .vfront_porch = { 4, 4, 4 }, 1838 .vback_porch = { 4, 4, 4 }, 1839 .vsync_len = { 8, 8, 8 }, 1840 }; 1841 1842 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1843 .timings = &dataimage_fg040346dsswbg04_timing, 1844 .num_timings = 1, 1845 .bpc = 8, 1846 .size = { 1847 .width = 95, 1848 .height = 54, 1849 }, 1850 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1851 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1852 .connector_type = DRM_MODE_CONNECTOR_DPI, 1853 }; 1854 1855 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1856 .pixelclock = { 68900000, 71110000, 73400000 }, 1857 .hactive = { 1280, 1280, 1280 }, 1858 .vactive = { 800, 800, 800 }, 1859 .hback_porch = { 100, 100, 100 }, 1860 .hfront_porch = { 100, 100, 100 }, 1861 .vback_porch = { 5, 5, 5 }, 1862 .vfront_porch = { 5, 5, 5 }, 1863 .hsync_len = { 24, 24, 24 }, 1864 .vsync_len = { 3, 3, 3 }, 1865 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1866 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1867 }; 1868 1869 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1870 .timings = &dataimage_fg1001l0dsswmg01_timing, 1871 .num_timings = 1, 1872 .bpc = 8, 1873 .size = { 1874 .width = 217, 1875 .height = 136, 1876 }, 1877 }; 1878 1879 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1880 .clock = 33260, 1881 .hdisplay = 800, 1882 .hsync_start = 800 + 40, 1883 .hsync_end = 800 + 40 + 128, 1884 .htotal = 800 + 40 + 128 + 88, 1885 .vdisplay = 480, 1886 .vsync_start = 480 + 10, 1887 .vsync_end = 480 + 10 + 2, 1888 .vtotal = 480 + 10 + 2 + 33, 1889 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1890 }; 1891 1892 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1893 .modes = &dataimage_scf0700c48ggu18_mode, 1894 .num_modes = 1, 1895 .bpc = 8, 1896 .size = { 1897 .width = 152, 1898 .height = 91, 1899 }, 1900 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1901 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1902 .connector_type = DRM_MODE_CONNECTOR_DPI, 1903 }; 1904 1905 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1906 .pixelclock = { 45000000, 51200000, 57000000 }, 1907 .hactive = { 1024, 1024, 1024 }, 1908 .hfront_porch = { 100, 106, 113 }, 1909 .hback_porch = { 100, 106, 113 }, 1910 .hsync_len = { 100, 108, 114 }, 1911 .vactive = { 600, 600, 600 }, 1912 .vfront_porch = { 8, 11, 15 }, 1913 .vback_porch = { 8, 11, 15 }, 1914 .vsync_len = { 9, 13, 15 }, 1915 .flags = DISPLAY_FLAGS_DE_HIGH, 1916 }; 1917 1918 static const struct panel_desc dlc_dlc0700yzg_1 = { 1919 .timings = &dlc_dlc0700yzg_1_timing, 1920 .num_timings = 1, 1921 .bpc = 6, 1922 .size = { 1923 .width = 154, 1924 .height = 86, 1925 }, 1926 .delay = { 1927 .prepare = 30, 1928 .enable = 200, 1929 .disable = 200, 1930 }, 1931 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1932 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1933 }; 1934 1935 static const struct display_timing dlc_dlc1010gig_timing = { 1936 .pixelclock = { 68900000, 71100000, 73400000 }, 1937 .hactive = { 1280, 1280, 1280 }, 1938 .hfront_porch = { 43, 53, 63 }, 1939 .hback_porch = { 43, 53, 63 }, 1940 .hsync_len = { 44, 54, 64 }, 1941 .vactive = { 800, 800, 800 }, 1942 .vfront_porch = { 5, 8, 11 }, 1943 .vback_porch = { 5, 8, 11 }, 1944 .vsync_len = { 5, 7, 11 }, 1945 .flags = DISPLAY_FLAGS_DE_HIGH, 1946 }; 1947 1948 static const struct panel_desc dlc_dlc1010gig = { 1949 .timings = &dlc_dlc1010gig_timing, 1950 .num_timings = 1, 1951 .bpc = 8, 1952 .size = { 1953 .width = 216, 1954 .height = 135, 1955 }, 1956 .delay = { 1957 .prepare = 60, 1958 .enable = 150, 1959 .disable = 100, 1960 .unprepare = 60, 1961 }, 1962 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1963 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1964 }; 1965 1966 static const struct drm_display_mode edt_et035012dm6_mode = { 1967 .clock = 6500, 1968 .hdisplay = 320, 1969 .hsync_start = 320 + 20, 1970 .hsync_end = 320 + 20 + 30, 1971 .htotal = 320 + 20 + 68, 1972 .vdisplay = 240, 1973 .vsync_start = 240 + 4, 1974 .vsync_end = 240 + 4 + 4, 1975 .vtotal = 240 + 4 + 4 + 14, 1976 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1977 }; 1978 1979 static const struct panel_desc edt_et035012dm6 = { 1980 .modes = &edt_et035012dm6_mode, 1981 .num_modes = 1, 1982 .bpc = 8, 1983 .size = { 1984 .width = 70, 1985 .height = 52, 1986 }, 1987 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1988 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1989 }; 1990 1991 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1992 .clock = 6520, 1993 .hdisplay = 320, 1994 .hsync_start = 320 + 20, 1995 .hsync_end = 320 + 20 + 68, 1996 .htotal = 320 + 20 + 68, 1997 .vdisplay = 240, 1998 .vsync_start = 240 + 4, 1999 .vsync_end = 240 + 4 + 18, 2000 .vtotal = 240 + 4 + 18, 2001 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2002 }; 2003 2004 static const struct panel_desc edt_etm0350g0dh6 = { 2005 .modes = &edt_etm0350g0dh6_mode, 2006 .num_modes = 1, 2007 .bpc = 6, 2008 .size = { 2009 .width = 70, 2010 .height = 53, 2011 }, 2012 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2013 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2014 .connector_type = DRM_MODE_CONNECTOR_DPI, 2015 }; 2016 2017 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 2018 .clock = 10870, 2019 .hdisplay = 480, 2020 .hsync_start = 480 + 8, 2021 .hsync_end = 480 + 8 + 4, 2022 .htotal = 480 + 8 + 4 + 41, 2023 2024 /* 2025 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 2026 * fb_align 2027 */ 2028 2029 .vdisplay = 288, 2030 .vsync_start = 288 + 2, 2031 .vsync_end = 288 + 2 + 4, 2032 .vtotal = 288 + 2 + 4 + 10, 2033 }; 2034 2035 static const struct panel_desc edt_etm043080dh6gp = { 2036 .modes = &edt_etm043080dh6gp_mode, 2037 .num_modes = 1, 2038 .bpc = 8, 2039 .size = { 2040 .width = 100, 2041 .height = 65, 2042 }, 2043 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2044 .connector_type = DRM_MODE_CONNECTOR_DPI, 2045 }; 2046 2047 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 2048 .clock = 9000, 2049 .hdisplay = 480, 2050 .hsync_start = 480 + 2, 2051 .hsync_end = 480 + 2 + 41, 2052 .htotal = 480 + 2 + 41 + 2, 2053 .vdisplay = 272, 2054 .vsync_start = 272 + 2, 2055 .vsync_end = 272 + 2 + 10, 2056 .vtotal = 272 + 2 + 10 + 2, 2057 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2058 }; 2059 2060 static const struct panel_desc edt_etm0430g0dh6 = { 2061 .modes = &edt_etm0430g0dh6_mode, 2062 .num_modes = 1, 2063 .bpc = 6, 2064 .size = { 2065 .width = 95, 2066 .height = 54, 2067 }, 2068 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2069 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2070 .connector_type = DRM_MODE_CONNECTOR_DPI, 2071 }; 2072 2073 static const struct drm_display_mode edt_et057090dhu_mode = { 2074 .clock = 25175, 2075 .hdisplay = 640, 2076 .hsync_start = 640 + 16, 2077 .hsync_end = 640 + 16 + 30, 2078 .htotal = 640 + 16 + 30 + 114, 2079 .vdisplay = 480, 2080 .vsync_start = 480 + 10, 2081 .vsync_end = 480 + 10 + 3, 2082 .vtotal = 480 + 10 + 3 + 32, 2083 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2084 }; 2085 2086 static const struct panel_desc edt_et057090dhu = { 2087 .modes = &edt_et057090dhu_mode, 2088 .num_modes = 1, 2089 .bpc = 6, 2090 .size = { 2091 .width = 115, 2092 .height = 86, 2093 }, 2094 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2095 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2096 .connector_type = DRM_MODE_CONNECTOR_DPI, 2097 }; 2098 2099 static const struct display_timing edt_et057023udba_timing = { 2100 .pixelclock = { 23200000, 24190000, 39640000 }, 2101 .hactive = { 640, 640, 640 }, 2102 .hfront_porch = { 20, 40, 200 }, 2103 .hback_porch = { 87, 40, 1 }, 2104 .hsync_len = { 1, 48, 87 }, 2105 .vactive = { 480, 480, 480 }, 2106 .vfront_porch = { 5, 13, 200 }, 2107 .vback_porch = { 31, 31, 29 }, 2108 .vsync_len = { 1, 1, 3 }, 2109 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2110 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2111 DISPLAY_FLAGS_SYNC_POSEDGE, 2112 }; 2113 2114 static const struct panel_desc edt_et057023udba = { 2115 .timings = &edt_et057023udba_timing, 2116 .num_timings = 1, 2117 .bpc = 8, 2118 .size = { 2119 .width = 115, 2120 .height = 86, 2121 }, 2122 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2123 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2124 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2125 .connector_type = DRM_MODE_CONNECTOR_DPI, 2126 }; 2127 2128 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2129 .clock = 33260, 2130 .hdisplay = 800, 2131 .hsync_start = 800 + 40, 2132 .hsync_end = 800 + 40 + 128, 2133 .htotal = 800 + 40 + 128 + 88, 2134 .vdisplay = 480, 2135 .vsync_start = 480 + 10, 2136 .vsync_end = 480 + 10 + 2, 2137 .vtotal = 480 + 10 + 2 + 33, 2138 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2139 }; 2140 2141 static const struct panel_desc edt_etm0700g0dh6 = { 2142 .modes = &edt_etm0700g0dh6_mode, 2143 .num_modes = 1, 2144 .bpc = 6, 2145 .size = { 2146 .width = 152, 2147 .height = 91, 2148 }, 2149 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2150 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2151 .connector_type = DRM_MODE_CONNECTOR_DPI, 2152 }; 2153 2154 static const struct panel_desc edt_etm0700g0bdh6 = { 2155 .modes = &edt_etm0700g0dh6_mode, 2156 .num_modes = 1, 2157 .bpc = 6, 2158 .size = { 2159 .width = 152, 2160 .height = 91, 2161 }, 2162 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2163 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2164 .connector_type = DRM_MODE_CONNECTOR_DPI, 2165 }; 2166 2167 static const struct display_timing edt_etml0700y5dha_timing = { 2168 .pixelclock = { 40800000, 51200000, 67200000 }, 2169 .hactive = { 1024, 1024, 1024 }, 2170 .hfront_porch = { 30, 106, 125 }, 2171 .hback_porch = { 30, 106, 125 }, 2172 .hsync_len = { 30, 108, 126 }, 2173 .vactive = { 600, 600, 600 }, 2174 .vfront_porch = { 3, 12, 67}, 2175 .vback_porch = { 3, 12, 67 }, 2176 .vsync_len = { 4, 11, 66 }, 2177 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2178 DISPLAY_FLAGS_DE_HIGH, 2179 }; 2180 2181 static const struct panel_desc edt_etml0700y5dha = { 2182 .timings = &edt_etml0700y5dha_timing, 2183 .num_timings = 1, 2184 .bpc = 8, 2185 .size = { 2186 .width = 155, 2187 .height = 86, 2188 }, 2189 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2190 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2191 }; 2192 2193 static const struct display_timing edt_etml1010g3dra_timing = { 2194 .pixelclock = { 66300000, 72400000, 78900000 }, 2195 .hactive = { 1280, 1280, 1280 }, 2196 .hfront_porch = { 12, 72, 132 }, 2197 .hback_porch = { 86, 86, 86 }, 2198 .hsync_len = { 2, 2, 2 }, 2199 .vactive = { 800, 800, 800 }, 2200 .vfront_porch = { 1, 15, 49 }, 2201 .vback_porch = { 21, 21, 21 }, 2202 .vsync_len = { 2, 2, 2 }, 2203 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2204 DISPLAY_FLAGS_DE_HIGH, 2205 }; 2206 2207 static const struct panel_desc edt_etml1010g3dra = { 2208 .timings = &edt_etml1010g3dra_timing, 2209 .num_timings = 1, 2210 .bpc = 8, 2211 .size = { 2212 .width = 216, 2213 .height = 135, 2214 }, 2215 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2216 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2217 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2218 }; 2219 2220 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2221 .clock = 25175, 2222 .hdisplay = 640, 2223 .hsync_start = 640, 2224 .hsync_end = 640 + 16, 2225 .htotal = 640 + 16 + 30 + 114, 2226 .vdisplay = 480, 2227 .vsync_start = 480 + 10, 2228 .vsync_end = 480 + 10 + 3, 2229 .vtotal = 480 + 10 + 3 + 35, 2230 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2231 }; 2232 2233 static const struct panel_desc edt_etmv570g2dhu = { 2234 .modes = &edt_etmv570g2dhu_mode, 2235 .num_modes = 1, 2236 .bpc = 6, 2237 .size = { 2238 .width = 115, 2239 .height = 86, 2240 }, 2241 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2242 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2243 .connector_type = DRM_MODE_CONNECTOR_DPI, 2244 }; 2245 2246 static const struct display_timing eink_vb3300_kca_timing = { 2247 .pixelclock = { 40000000, 40000000, 40000000 }, 2248 .hactive = { 334, 334, 334 }, 2249 .hfront_porch = { 1, 1, 1 }, 2250 .hback_porch = { 1, 1, 1 }, 2251 .hsync_len = { 1, 1, 1 }, 2252 .vactive = { 1405, 1405, 1405 }, 2253 .vfront_porch = { 1, 1, 1 }, 2254 .vback_porch = { 1, 1, 1 }, 2255 .vsync_len = { 1, 1, 1 }, 2256 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2257 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2258 }; 2259 2260 static const struct panel_desc eink_vb3300_kca = { 2261 .timings = &eink_vb3300_kca_timing, 2262 .num_timings = 1, 2263 .bpc = 6, 2264 .size = { 2265 .width = 157, 2266 .height = 209, 2267 }, 2268 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2269 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2270 .connector_type = DRM_MODE_CONNECTOR_DPI, 2271 }; 2272 2273 static const struct display_timing evervision_vgg644804_timing = { 2274 .pixelclock = { 25175000, 25175000, 25175000 }, 2275 .hactive = { 640, 640, 640 }, 2276 .hfront_porch = { 16, 16, 16 }, 2277 .hback_porch = { 82, 114, 170 }, 2278 .hsync_len = { 5, 30, 30 }, 2279 .vactive = { 480, 480, 480 }, 2280 .vfront_porch = { 10, 10, 10 }, 2281 .vback_porch = { 30, 32, 34 }, 2282 .vsync_len = { 1, 3, 5 }, 2283 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2284 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2285 DISPLAY_FLAGS_SYNC_POSEDGE, 2286 }; 2287 2288 static const struct panel_desc evervision_vgg644804 = { 2289 .timings = &evervision_vgg644804_timing, 2290 .num_timings = 1, 2291 .bpc = 6, 2292 .size = { 2293 .width = 115, 2294 .height = 86, 2295 }, 2296 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2297 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2298 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2299 }; 2300 2301 static const struct display_timing evervision_vgg804821_timing = { 2302 .pixelclock = { 27600000, 33300000, 50000000 }, 2303 .hactive = { 800, 800, 800 }, 2304 .hfront_porch = { 40, 66, 70 }, 2305 .hback_porch = { 40, 67, 70 }, 2306 .hsync_len = { 40, 67, 70 }, 2307 .vactive = { 480, 480, 480 }, 2308 .vfront_porch = { 6, 10, 10 }, 2309 .vback_porch = { 7, 11, 11 }, 2310 .vsync_len = { 7, 11, 11 }, 2311 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2312 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2313 DISPLAY_FLAGS_SYNC_NEGEDGE, 2314 }; 2315 2316 static const struct panel_desc evervision_vgg804821 = { 2317 .timings = &evervision_vgg804821_timing, 2318 .num_timings = 1, 2319 .bpc = 8, 2320 .size = { 2321 .width = 108, 2322 .height = 64, 2323 }, 2324 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2325 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2326 }; 2327 2328 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2329 .clock = 32260, 2330 .hdisplay = 800, 2331 .hsync_start = 800 + 168, 2332 .hsync_end = 800 + 168 + 64, 2333 .htotal = 800 + 168 + 64 + 88, 2334 .vdisplay = 480, 2335 .vsync_start = 480 + 37, 2336 .vsync_end = 480 + 37 + 2, 2337 .vtotal = 480 + 37 + 2 + 8, 2338 }; 2339 2340 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2341 .modes = &foxlink_fl500wvr00_a0t_mode, 2342 .num_modes = 1, 2343 .bpc = 8, 2344 .size = { 2345 .width = 108, 2346 .height = 65, 2347 }, 2348 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2349 }; 2350 2351 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2352 { /* 60 Hz */ 2353 .clock = 6000, 2354 .hdisplay = 320, 2355 .hsync_start = 320 + 44, 2356 .hsync_end = 320 + 44 + 16, 2357 .htotal = 320 + 44 + 16 + 20, 2358 .vdisplay = 240, 2359 .vsync_start = 240 + 2, 2360 .vsync_end = 240 + 2 + 6, 2361 .vtotal = 240 + 2 + 6 + 2, 2362 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2363 }, 2364 { /* 50 Hz */ 2365 .clock = 5400, 2366 .hdisplay = 320, 2367 .hsync_start = 320 + 56, 2368 .hsync_end = 320 + 56 + 16, 2369 .htotal = 320 + 56 + 16 + 40, 2370 .vdisplay = 240, 2371 .vsync_start = 240 + 2, 2372 .vsync_end = 240 + 2 + 6, 2373 .vtotal = 240 + 2 + 6 + 2, 2374 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2375 }, 2376 }; 2377 2378 static const struct panel_desc frida_frd350h54004 = { 2379 .modes = frida_frd350h54004_modes, 2380 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2381 .bpc = 8, 2382 .size = { 2383 .width = 77, 2384 .height = 64, 2385 }, 2386 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2387 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2388 .connector_type = DRM_MODE_CONNECTOR_DPI, 2389 }; 2390 2391 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2392 .clock = 9000, 2393 .hdisplay = 480, 2394 .hsync_start = 480 + 5, 2395 .hsync_end = 480 + 5 + 1, 2396 .htotal = 480 + 5 + 1 + 40, 2397 .vdisplay = 272, 2398 .vsync_start = 272 + 8, 2399 .vsync_end = 272 + 8 + 1, 2400 .vtotal = 272 + 8 + 1 + 8, 2401 }; 2402 2403 static const struct panel_desc giantplus_gpg482739qs5 = { 2404 .modes = &giantplus_gpg482739qs5_mode, 2405 .num_modes = 1, 2406 .bpc = 8, 2407 .size = { 2408 .width = 95, 2409 .height = 54, 2410 }, 2411 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2412 }; 2413 2414 static const struct display_timing giantplus_gpm940b0_timing = { 2415 .pixelclock = { 13500000, 27000000, 27500000 }, 2416 .hactive = { 320, 320, 320 }, 2417 .hfront_porch = { 14, 686, 718 }, 2418 .hback_porch = { 50, 70, 255 }, 2419 .hsync_len = { 1, 1, 1 }, 2420 .vactive = { 240, 240, 240 }, 2421 .vfront_porch = { 1, 1, 179 }, 2422 .vback_porch = { 1, 21, 31 }, 2423 .vsync_len = { 1, 1, 6 }, 2424 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2425 }; 2426 2427 static const struct panel_desc giantplus_gpm940b0 = { 2428 .timings = &giantplus_gpm940b0_timing, 2429 .num_timings = 1, 2430 .bpc = 8, 2431 .size = { 2432 .width = 60, 2433 .height = 45, 2434 }, 2435 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2436 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2437 }; 2438 2439 static const struct display_timing hannstar_hsd070pww1_timing = { 2440 .pixelclock = { 64300000, 71100000, 82000000 }, 2441 .hactive = { 1280, 1280, 1280 }, 2442 .hfront_porch = { 1, 1, 10 }, 2443 .hback_porch = { 1, 1, 10 }, 2444 /* 2445 * According to the data sheet, the minimum horizontal blanking interval 2446 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2447 * minimum working horizontal blanking interval to be 60 clocks. 2448 */ 2449 .hsync_len = { 58, 158, 661 }, 2450 .vactive = { 800, 800, 800 }, 2451 .vfront_porch = { 1, 1, 10 }, 2452 .vback_porch = { 1, 1, 10 }, 2453 .vsync_len = { 1, 21, 203 }, 2454 .flags = DISPLAY_FLAGS_DE_HIGH, 2455 }; 2456 2457 static const struct panel_desc hannstar_hsd070pww1 = { 2458 .timings = &hannstar_hsd070pww1_timing, 2459 .num_timings = 1, 2460 .bpc = 6, 2461 .size = { 2462 .width = 151, 2463 .height = 94, 2464 }, 2465 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2466 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2467 }; 2468 2469 static const struct display_timing hannstar_hsd100pxn1_timing = { 2470 .pixelclock = { 55000000, 65000000, 75000000 }, 2471 .hactive = { 1024, 1024, 1024 }, 2472 .hfront_porch = { 40, 40, 40 }, 2473 .hback_porch = { 220, 220, 220 }, 2474 .hsync_len = { 20, 60, 100 }, 2475 .vactive = { 768, 768, 768 }, 2476 .vfront_porch = { 7, 7, 7 }, 2477 .vback_porch = { 21, 21, 21 }, 2478 .vsync_len = { 10, 10, 10 }, 2479 .flags = DISPLAY_FLAGS_DE_HIGH, 2480 }; 2481 2482 static const struct panel_desc hannstar_hsd100pxn1 = { 2483 .timings = &hannstar_hsd100pxn1_timing, 2484 .num_timings = 1, 2485 .bpc = 6, 2486 .size = { 2487 .width = 203, 2488 .height = 152, 2489 }, 2490 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2491 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2492 }; 2493 2494 static const struct display_timing hannstar_hsd101pww2_timing = { 2495 .pixelclock = { 64300000, 71100000, 82000000 }, 2496 .hactive = { 1280, 1280, 1280 }, 2497 .hfront_porch = { 1, 1, 10 }, 2498 .hback_porch = { 1, 1, 10 }, 2499 .hsync_len = { 58, 158, 661 }, 2500 .vactive = { 800, 800, 800 }, 2501 .vfront_porch = { 1, 1, 10 }, 2502 .vback_porch = { 1, 1, 10 }, 2503 .vsync_len = { 1, 21, 203 }, 2504 .flags = DISPLAY_FLAGS_DE_HIGH, 2505 }; 2506 2507 static const struct panel_desc hannstar_hsd101pww2 = { 2508 .timings = &hannstar_hsd101pww2_timing, 2509 .num_timings = 1, 2510 .bpc = 8, 2511 .size = { 2512 .width = 217, 2513 .height = 136, 2514 }, 2515 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2516 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2517 }; 2518 2519 static const struct display_timing hannstar_hsd156juw2_timing = { 2520 .pixelclock = { 66000000, 72800000, 80500000 }, 2521 .hactive = { 1920, 1920, 1920 }, 2522 .hfront_porch = { 20, 30, 30 }, 2523 .hback_porch = { 20, 30, 30 }, 2524 .hsync_len = { 50, 60, 90 }, 2525 .vactive = { 1080, 1080, 1080 }, 2526 .vfront_porch = { 1, 2, 4 }, 2527 .vback_porch = { 1, 2, 4 }, 2528 .vsync_len = { 3, 40, 80 }, 2529 .flags = DISPLAY_FLAGS_DE_HIGH, 2530 }; 2531 2532 static const struct panel_desc hannstar_hsd156juw2 = { 2533 .timings = &hannstar_hsd156juw2_timing, 2534 .num_timings = 1, 2535 .bpc = 8, 2536 .size = { 2537 .width = 344, 2538 .height = 194, 2539 }, 2540 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2541 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2542 }; 2543 2544 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2545 .clock = 33333, 2546 .hdisplay = 800, 2547 .hsync_start = 800 + 85, 2548 .hsync_end = 800 + 85 + 86, 2549 .htotal = 800 + 85 + 86 + 85, 2550 .vdisplay = 480, 2551 .vsync_start = 480 + 16, 2552 .vsync_end = 480 + 16 + 13, 2553 .vtotal = 480 + 16 + 13 + 16, 2554 }; 2555 2556 static const struct panel_desc hitachi_tx23d38vm0caa = { 2557 .modes = &hitachi_tx23d38vm0caa_mode, 2558 .num_modes = 1, 2559 .bpc = 6, 2560 .size = { 2561 .width = 195, 2562 .height = 117, 2563 }, 2564 .delay = { 2565 .enable = 160, 2566 .disable = 160, 2567 }, 2568 }; 2569 2570 static const struct drm_display_mode innolux_at043tn24_mode = { 2571 .clock = 9000, 2572 .hdisplay = 480, 2573 .hsync_start = 480 + 2, 2574 .hsync_end = 480 + 2 + 41, 2575 .htotal = 480 + 2 + 41 + 2, 2576 .vdisplay = 272, 2577 .vsync_start = 272 + 2, 2578 .vsync_end = 272 + 2 + 10, 2579 .vtotal = 272 + 2 + 10 + 2, 2580 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2581 }; 2582 2583 static const struct panel_desc innolux_at043tn24 = { 2584 .modes = &innolux_at043tn24_mode, 2585 .num_modes = 1, 2586 .bpc = 8, 2587 .size = { 2588 .width = 95, 2589 .height = 54, 2590 }, 2591 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2592 .connector_type = DRM_MODE_CONNECTOR_DPI, 2593 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2594 }; 2595 2596 static const struct drm_display_mode innolux_at070tn92_mode = { 2597 .clock = 33333, 2598 .hdisplay = 800, 2599 .hsync_start = 800 + 210, 2600 .hsync_end = 800 + 210 + 20, 2601 .htotal = 800 + 210 + 20 + 46, 2602 .vdisplay = 480, 2603 .vsync_start = 480 + 22, 2604 .vsync_end = 480 + 22 + 10, 2605 .vtotal = 480 + 22 + 23 + 10, 2606 }; 2607 2608 static const struct panel_desc innolux_at070tn92 = { 2609 .modes = &innolux_at070tn92_mode, 2610 .num_modes = 1, 2611 .size = { 2612 .width = 154, 2613 .height = 86, 2614 }, 2615 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2616 }; 2617 2618 static const struct display_timing innolux_g070ace_l01_timing = { 2619 .pixelclock = { 25200000, 35000000, 35700000 }, 2620 .hactive = { 800, 800, 800 }, 2621 .hfront_porch = { 30, 32, 87 }, 2622 .hback_porch = { 30, 32, 87 }, 2623 .hsync_len = { 1, 1, 1 }, 2624 .vactive = { 480, 480, 480 }, 2625 .vfront_porch = { 3, 3, 3 }, 2626 .vback_porch = { 13, 13, 13 }, 2627 .vsync_len = { 1, 1, 4 }, 2628 .flags = DISPLAY_FLAGS_DE_HIGH, 2629 }; 2630 2631 static const struct panel_desc innolux_g070ace_l01 = { 2632 .timings = &innolux_g070ace_l01_timing, 2633 .num_timings = 1, 2634 .bpc = 8, 2635 .size = { 2636 .width = 152, 2637 .height = 91, 2638 }, 2639 .delay = { 2640 .prepare = 10, 2641 .enable = 50, 2642 .disable = 50, 2643 .unprepare = 500, 2644 }, 2645 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2646 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2647 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2648 }; 2649 2650 static const struct display_timing innolux_g070y2_l01_timing = { 2651 .pixelclock = { 28000000, 29500000, 32000000 }, 2652 .hactive = { 800, 800, 800 }, 2653 .hfront_porch = { 61, 91, 141 }, 2654 .hback_porch = { 60, 90, 140 }, 2655 .hsync_len = { 12, 12, 12 }, 2656 .vactive = { 480, 480, 480 }, 2657 .vfront_porch = { 4, 9, 30 }, 2658 .vback_porch = { 4, 8, 28 }, 2659 .vsync_len = { 2, 2, 2 }, 2660 .flags = DISPLAY_FLAGS_DE_HIGH, 2661 }; 2662 2663 static const struct panel_desc innolux_g070y2_l01 = { 2664 .timings = &innolux_g070y2_l01_timing, 2665 .num_timings = 1, 2666 .bpc = 8, 2667 .size = { 2668 .width = 152, 2669 .height = 91, 2670 }, 2671 .delay = { 2672 .prepare = 10, 2673 .enable = 100, 2674 .disable = 100, 2675 .unprepare = 800, 2676 }, 2677 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2678 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2679 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2680 }; 2681 2682 static const struct display_timing innolux_g070ace_lh3_timing = { 2683 .pixelclock = { 25200000, 25400000, 35700000 }, 2684 .hactive = { 800, 800, 800 }, 2685 .hfront_porch = { 30, 32, 87 }, 2686 .hback_porch = { 29, 31, 86 }, 2687 .hsync_len = { 1, 1, 1 }, 2688 .vactive = { 480, 480, 480 }, 2689 .vfront_porch = { 4, 5, 65 }, 2690 .vback_porch = { 3, 4, 65 }, 2691 .vsync_len = { 1, 1, 1 }, 2692 .flags = DISPLAY_FLAGS_DE_HIGH, 2693 }; 2694 2695 static const struct panel_desc innolux_g070ace_lh3 = { 2696 .timings = &innolux_g070ace_lh3_timing, 2697 .num_timings = 1, 2698 .bpc = 8, 2699 .size = { 2700 .width = 152, 2701 .height = 91, 2702 }, 2703 .delay = { 2704 .prepare = 10, 2705 .enable = 450, 2706 .disable = 200, 2707 .unprepare = 510, 2708 }, 2709 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2710 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2711 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2712 }; 2713 2714 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2715 .clock = 33333, 2716 .hdisplay = 800, 2717 .hsync_start = 800 + 210, 2718 .hsync_end = 800 + 210 + 20, 2719 .htotal = 800 + 210 + 20 + 46, 2720 .vdisplay = 480, 2721 .vsync_start = 480 + 22, 2722 .vsync_end = 480 + 22 + 10, 2723 .vtotal = 480 + 22 + 23 + 10, 2724 }; 2725 2726 static const struct panel_desc innolux_g070y2_t02 = { 2727 .modes = &innolux_g070y2_t02_mode, 2728 .num_modes = 1, 2729 .bpc = 8, 2730 .size = { 2731 .width = 152, 2732 .height = 92, 2733 }, 2734 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2735 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2736 .connector_type = DRM_MODE_CONNECTOR_DPI, 2737 }; 2738 2739 static const struct display_timing innolux_g101ice_l01_timing = { 2740 .pixelclock = { 60400000, 71100000, 74700000 }, 2741 .hactive = { 1280, 1280, 1280 }, 2742 .hfront_porch = { 30, 60, 70 }, 2743 .hback_porch = { 30, 60, 70 }, 2744 .hsync_len = { 22, 40, 60 }, 2745 .vactive = { 800, 800, 800 }, 2746 .vfront_porch = { 3, 8, 14 }, 2747 .vback_porch = { 3, 8, 14 }, 2748 .vsync_len = { 4, 7, 12 }, 2749 .flags = DISPLAY_FLAGS_DE_HIGH, 2750 }; 2751 2752 static const struct panel_desc innolux_g101ice_l01 = { 2753 .timings = &innolux_g101ice_l01_timing, 2754 .num_timings = 1, 2755 .bpc = 8, 2756 .size = { 2757 .width = 217, 2758 .height = 135, 2759 }, 2760 .delay = { 2761 .enable = 200, 2762 .disable = 200, 2763 }, 2764 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2765 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2766 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2767 }; 2768 2769 static const struct display_timing innolux_g121i1_l01_timing = { 2770 .pixelclock = { 67450000, 71000000, 74550000 }, 2771 .hactive = { 1280, 1280, 1280 }, 2772 .hfront_porch = { 40, 80, 160 }, 2773 .hback_porch = { 39, 79, 159 }, 2774 .hsync_len = { 1, 1, 1 }, 2775 .vactive = { 800, 800, 800 }, 2776 .vfront_porch = { 5, 11, 100 }, 2777 .vback_porch = { 4, 11, 99 }, 2778 .vsync_len = { 1, 1, 1 }, 2779 }; 2780 2781 static const struct panel_desc innolux_g121i1_l01 = { 2782 .timings = &innolux_g121i1_l01_timing, 2783 .num_timings = 1, 2784 .bpc = 6, 2785 .size = { 2786 .width = 261, 2787 .height = 163, 2788 }, 2789 .delay = { 2790 .enable = 200, 2791 .disable = 20, 2792 }, 2793 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2794 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2795 }; 2796 2797 static const struct display_timing innolux_g121x1_l03_timings = { 2798 .pixelclock = { 57500000, 64900000, 74400000 }, 2799 .hactive = { 1024, 1024, 1024 }, 2800 .hfront_porch = { 90, 140, 190 }, 2801 .hback_porch = { 90, 140, 190 }, 2802 .hsync_len = { 36, 40, 60 }, 2803 .vactive = { 768, 768, 768 }, 2804 .vfront_porch = { 2, 15, 30 }, 2805 .vback_porch = { 2, 15, 30 }, 2806 .vsync_len = { 2, 8, 20 }, 2807 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2808 }; 2809 2810 static const struct panel_desc innolux_g121x1_l03 = { 2811 .timings = &innolux_g121x1_l03_timings, 2812 .num_timings = 1, 2813 .bpc = 6, 2814 .size = { 2815 .width = 246, 2816 .height = 185, 2817 }, 2818 .delay = { 2819 .enable = 200, 2820 .unprepare = 200, 2821 .disable = 400, 2822 }, 2823 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2824 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2825 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2826 }; 2827 2828 static const struct panel_desc innolux_g121xce_l01 = { 2829 .timings = &innolux_g121x1_l03_timings, 2830 .num_timings = 1, 2831 .bpc = 8, 2832 .size = { 2833 .width = 246, 2834 .height = 185, 2835 }, 2836 .delay = { 2837 .enable = 200, 2838 .unprepare = 200, 2839 .disable = 400, 2840 }, 2841 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2842 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2843 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2844 }; 2845 2846 static const struct display_timing innolux_g150xge_l05_timing = { 2847 .pixelclock = { 53350000, 65000000, 80000000 }, 2848 .hactive = { 1024, 1024, 1024 }, 2849 .hfront_porch = { 58, 160, 288 }, 2850 .hback_porch = { 58, 160, 288 }, 2851 .hsync_len = { 1, 1, 1 }, 2852 .vactive = { 768, 768, 768 }, 2853 .vfront_porch = { 6, 19, 216 }, 2854 .vback_porch = { 6, 19, 216 }, 2855 .vsync_len = { 1, 1, 1 }, 2856 .flags = DISPLAY_FLAGS_DE_HIGH, 2857 }; 2858 2859 static const struct panel_desc innolux_g150xge_l05 = { 2860 .timings = &innolux_g150xge_l05_timing, 2861 .num_timings = 1, 2862 .bpc = 8, 2863 .size = { 2864 .width = 304, 2865 .height = 228, 2866 }, 2867 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2868 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2869 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2870 }; 2871 2872 static const struct display_timing innolux_g156hce_l01_timings = { 2873 .pixelclock = { 120000000, 141860000, 150000000 }, 2874 .hactive = { 1920, 1920, 1920 }, 2875 .hfront_porch = { 80, 90, 100 }, 2876 .hback_porch = { 80, 90, 100 }, 2877 .hsync_len = { 20, 30, 30 }, 2878 .vactive = { 1080, 1080, 1080 }, 2879 .vfront_porch = { 3, 10, 20 }, 2880 .vback_porch = { 3, 10, 20 }, 2881 .vsync_len = { 4, 10, 10 }, 2882 }; 2883 2884 static const struct panel_desc innolux_g156hce_l01 = { 2885 .timings = &innolux_g156hce_l01_timings, 2886 .num_timings = 1, 2887 .bpc = 8, 2888 .size = { 2889 .width = 344, 2890 .height = 194, 2891 }, 2892 .delay = { 2893 .prepare = 1, /* T1+T2 */ 2894 .enable = 450, /* T5 */ 2895 .disable = 200, /* T6 */ 2896 .unprepare = 10, /* T3+T7 */ 2897 }, 2898 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2899 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2900 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2901 }; 2902 2903 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2904 .clock = 69300, 2905 .hdisplay = 1366, 2906 .hsync_start = 1366 + 16, 2907 .hsync_end = 1366 + 16 + 34, 2908 .htotal = 1366 + 16 + 34 + 50, 2909 .vdisplay = 768, 2910 .vsync_start = 768 + 2, 2911 .vsync_end = 768 + 2 + 6, 2912 .vtotal = 768 + 2 + 6 + 12, 2913 }; 2914 2915 static const struct panel_desc innolux_n156bge_l21 = { 2916 .modes = &innolux_n156bge_l21_mode, 2917 .num_modes = 1, 2918 .bpc = 6, 2919 .size = { 2920 .width = 344, 2921 .height = 193, 2922 }, 2923 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2924 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2925 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2926 }; 2927 2928 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2929 .clock = 51501, 2930 .hdisplay = 1024, 2931 .hsync_start = 1024 + 128, 2932 .hsync_end = 1024 + 128 + 64, 2933 .htotal = 1024 + 128 + 64 + 128, 2934 .vdisplay = 600, 2935 .vsync_start = 600 + 16, 2936 .vsync_end = 600 + 16 + 4, 2937 .vtotal = 600 + 16 + 4 + 16, 2938 }; 2939 2940 static const struct panel_desc innolux_zj070na_01p = { 2941 .modes = &innolux_zj070na_01p_mode, 2942 .num_modes = 1, 2943 .bpc = 6, 2944 .size = { 2945 .width = 154, 2946 .height = 90, 2947 }, 2948 }; 2949 2950 static const struct display_timing jutouch_jt070tm041_timing = { 2951 .pixelclock = { 40800000, 51200000, 67200000 }, 2952 .hactive = { 1024, 1024, 1024 }, 2953 .hfront_porch = { 16, 160, 216 }, 2954 .hback_porch = { 160, 160, 160 }, 2955 .hsync_len = { 1, 1, 140 }, 2956 .vactive = { 600, 600, 600 }, 2957 .vfront_porch = { 1, 12, 127 }, 2958 .vback_porch = { 23, 23, 23 }, 2959 .vsync_len = { 1, 1, 20 }, 2960 }; 2961 2962 static const struct panel_desc jutouch_jt070tm041 = { 2963 .timings = &jutouch_jt070tm041_timing, 2964 .num_timings = 1, 2965 .bpc = 8, 2966 .size = { 2967 .width = 154, 2968 .height = 86, 2969 }, 2970 .delay = { 2971 .enable = 50, 2972 .disable = 50, 2973 }, 2974 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2975 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2976 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2977 }; 2978 2979 static const struct display_timing jutouch_jt101tm023_timing = { 2980 .pixelclock = { 66300000, 72400000, 78900000 }, 2981 .hactive = { 1280, 1280, 1280 }, 2982 .hfront_porch = { 12, 72, 132 }, 2983 .hback_porch = { 88, 88, 88 }, 2984 .hsync_len = { 10, 10, 48 }, 2985 .vactive = { 800, 800, 800 }, 2986 .vfront_porch = { 1, 15, 49 }, 2987 .vback_porch = { 23, 23, 23 }, 2988 .vsync_len = { 5, 6, 13 }, 2989 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2990 DISPLAY_FLAGS_DE_HIGH, 2991 }; 2992 2993 static const struct panel_desc jutouch_jt101tm023 = { 2994 .timings = &jutouch_jt101tm023_timing, 2995 .num_timings = 1, 2996 .bpc = 8, 2997 .size = { 2998 .width = 217, 2999 .height = 136, 3000 }, 3001 .delay = { 3002 .enable = 50, 3003 .disable = 50, 3004 }, 3005 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3006 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3007 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3008 }; 3009 3010 3011 static const struct display_timing koe_tx14d24vm1bpa_timing = { 3012 .pixelclock = { 5580000, 5850000, 6200000 }, 3013 .hactive = { 320, 320, 320 }, 3014 .hfront_porch = { 30, 30, 30 }, 3015 .hback_porch = { 30, 30, 30 }, 3016 .hsync_len = { 1, 5, 17 }, 3017 .vactive = { 240, 240, 240 }, 3018 .vfront_porch = { 6, 6, 6 }, 3019 .vback_porch = { 5, 5, 5 }, 3020 .vsync_len = { 1, 2, 11 }, 3021 .flags = DISPLAY_FLAGS_DE_HIGH, 3022 }; 3023 3024 static const struct panel_desc koe_tx14d24vm1bpa = { 3025 .timings = &koe_tx14d24vm1bpa_timing, 3026 .num_timings = 1, 3027 .bpc = 6, 3028 .size = { 3029 .width = 115, 3030 .height = 86, 3031 }, 3032 }; 3033 3034 static const struct display_timing koe_tx26d202vm0bwa_timing = { 3035 .pixelclock = { 151820000, 156720000, 159780000 }, 3036 .hactive = { 1920, 1920, 1920 }, 3037 .hfront_porch = { 105, 130, 142 }, 3038 .hback_porch = { 45, 70, 82 }, 3039 .hsync_len = { 30, 30, 30 }, 3040 .vactive = { 1200, 1200, 1200}, 3041 .vfront_porch = { 3, 5, 10 }, 3042 .vback_porch = { 2, 5, 10 }, 3043 .vsync_len = { 5, 5, 5 }, 3044 .flags = DISPLAY_FLAGS_DE_HIGH, 3045 }; 3046 3047 static const struct panel_desc koe_tx26d202vm0bwa = { 3048 .timings = &koe_tx26d202vm0bwa_timing, 3049 .num_timings = 1, 3050 .bpc = 8, 3051 .size = { 3052 .width = 217, 3053 .height = 136, 3054 }, 3055 .delay = { 3056 .prepare = 1000, 3057 .enable = 1000, 3058 .unprepare = 1000, 3059 .disable = 1000, 3060 }, 3061 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3062 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3063 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3064 }; 3065 3066 static const struct display_timing koe_tx31d200vm0baa_timing = { 3067 .pixelclock = { 39600000, 43200000, 48000000 }, 3068 .hactive = { 1280, 1280, 1280 }, 3069 .hfront_porch = { 16, 36, 56 }, 3070 .hback_porch = { 16, 36, 56 }, 3071 .hsync_len = { 8, 8, 8 }, 3072 .vactive = { 480, 480, 480 }, 3073 .vfront_porch = { 6, 21, 33 }, 3074 .vback_porch = { 6, 21, 33 }, 3075 .vsync_len = { 8, 8, 8 }, 3076 .flags = DISPLAY_FLAGS_DE_HIGH, 3077 }; 3078 3079 static const struct panel_desc koe_tx31d200vm0baa = { 3080 .timings = &koe_tx31d200vm0baa_timing, 3081 .num_timings = 1, 3082 .bpc = 6, 3083 .size = { 3084 .width = 292, 3085 .height = 109, 3086 }, 3087 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3088 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3089 }; 3090 3091 static const struct display_timing kyo_tcg121xglp_timing = { 3092 .pixelclock = { 52000000, 65000000, 71000000 }, 3093 .hactive = { 1024, 1024, 1024 }, 3094 .hfront_porch = { 2, 2, 2 }, 3095 .hback_porch = { 2, 2, 2 }, 3096 .hsync_len = { 86, 124, 244 }, 3097 .vactive = { 768, 768, 768 }, 3098 .vfront_porch = { 2, 2, 2 }, 3099 .vback_porch = { 2, 2, 2 }, 3100 .vsync_len = { 6, 34, 73 }, 3101 .flags = DISPLAY_FLAGS_DE_HIGH, 3102 }; 3103 3104 static const struct panel_desc kyo_tcg121xglp = { 3105 .timings = &kyo_tcg121xglp_timing, 3106 .num_timings = 1, 3107 .bpc = 8, 3108 .size = { 3109 .width = 246, 3110 .height = 184, 3111 }, 3112 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3113 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3114 }; 3115 3116 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 3117 .clock = 7000, 3118 .hdisplay = 320, 3119 .hsync_start = 320 + 20, 3120 .hsync_end = 320 + 20 + 30, 3121 .htotal = 320 + 20 + 30 + 38, 3122 .vdisplay = 240, 3123 .vsync_start = 240 + 4, 3124 .vsync_end = 240 + 4 + 3, 3125 .vtotal = 240 + 4 + 3 + 15, 3126 }; 3127 3128 static const struct panel_desc lemaker_bl035_rgb_002 = { 3129 .modes = &lemaker_bl035_rgb_002_mode, 3130 .num_modes = 1, 3131 .size = { 3132 .width = 70, 3133 .height = 52, 3134 }, 3135 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3136 .bus_flags = DRM_BUS_FLAG_DE_LOW, 3137 }; 3138 3139 static const struct display_timing lg_lb070wv8_timing = { 3140 .pixelclock = { 31950000, 33260000, 34600000 }, 3141 .hactive = { 800, 800, 800 }, 3142 .hfront_porch = { 88, 88, 88 }, 3143 .hback_porch = { 88, 88, 88 }, 3144 .hsync_len = { 80, 80, 80 }, 3145 .vactive = { 480, 480, 480 }, 3146 .vfront_porch = { 10, 10, 10 }, 3147 .vback_porch = { 10, 10, 10 }, 3148 .vsync_len = { 25, 25, 25 }, 3149 }; 3150 3151 static const struct panel_desc lg_lb070wv8 = { 3152 .timings = &lg_lb070wv8_timing, 3153 .num_timings = 1, 3154 .bpc = 8, 3155 .size = { 3156 .width = 151, 3157 .height = 91, 3158 }, 3159 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3160 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3161 }; 3162 3163 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 3164 .clock = 155127, 3165 .hdisplay = 1920, 3166 .hsync_start = 1920 + 128, 3167 .hsync_end = 1920 + 128 + 20, 3168 .htotal = 1920 + 128 + 20 + 12, 3169 .vdisplay = 1200, 3170 .vsync_start = 1200 + 19, 3171 .vsync_end = 1200 + 19 + 4, 3172 .vtotal = 1200 + 19 + 4 + 20, 3173 }; 3174 3175 static const struct panel_desc lincolntech_lcd185_101ct = { 3176 .modes = &lincolntech_lcd185_101ct_mode, 3177 .bpc = 8, 3178 .num_modes = 1, 3179 .size = { 3180 .width = 217, 3181 .height = 136, 3182 }, 3183 .delay = { 3184 .prepare = 50, 3185 .disable = 50, 3186 }, 3187 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3188 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3189 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3190 }; 3191 3192 static const struct display_timing logictechno_lt161010_2nh_timing = { 3193 .pixelclock = { 26400000, 33300000, 46800000 }, 3194 .hactive = { 800, 800, 800 }, 3195 .hfront_porch = { 16, 210, 354 }, 3196 .hback_porch = { 46, 46, 46 }, 3197 .hsync_len = { 1, 20, 40 }, 3198 .vactive = { 480, 480, 480 }, 3199 .vfront_porch = { 7, 22, 147 }, 3200 .vback_porch = { 23, 23, 23 }, 3201 .vsync_len = { 1, 10, 20 }, 3202 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3203 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3204 DISPLAY_FLAGS_SYNC_POSEDGE, 3205 }; 3206 3207 static const struct panel_desc logictechno_lt161010_2nh = { 3208 .timings = &logictechno_lt161010_2nh_timing, 3209 .num_timings = 1, 3210 .bpc = 6, 3211 .size = { 3212 .width = 154, 3213 .height = 86, 3214 }, 3215 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3216 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3217 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3218 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3219 .connector_type = DRM_MODE_CONNECTOR_DPI, 3220 }; 3221 3222 static const struct display_timing logictechno_lt170410_2whc_timing = { 3223 .pixelclock = { 68900000, 71100000, 73400000 }, 3224 .hactive = { 1280, 1280, 1280 }, 3225 .hfront_porch = { 23, 60, 71 }, 3226 .hback_porch = { 23, 60, 71 }, 3227 .hsync_len = { 15, 40, 47 }, 3228 .vactive = { 800, 800, 800 }, 3229 .vfront_porch = { 5, 7, 10 }, 3230 .vback_porch = { 5, 7, 10 }, 3231 .vsync_len = { 6, 9, 12 }, 3232 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3233 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3234 DISPLAY_FLAGS_SYNC_POSEDGE, 3235 }; 3236 3237 static const struct panel_desc logictechno_lt170410_2whc = { 3238 .timings = &logictechno_lt170410_2whc_timing, 3239 .num_timings = 1, 3240 .bpc = 8, 3241 .size = { 3242 .width = 217, 3243 .height = 136, 3244 }, 3245 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3246 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3247 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3248 }; 3249 3250 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 3251 .clock = 33000, 3252 .hdisplay = 800, 3253 .hsync_start = 800 + 112, 3254 .hsync_end = 800 + 112 + 3, 3255 .htotal = 800 + 112 + 3 + 85, 3256 .vdisplay = 480, 3257 .vsync_start = 480 + 38, 3258 .vsync_end = 480 + 38 + 3, 3259 .vtotal = 480 + 38 + 3 + 29, 3260 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3261 }; 3262 3263 static const struct panel_desc logictechno_lttd800480070_l2rt = { 3264 .modes = &logictechno_lttd800480070_l2rt_mode, 3265 .num_modes = 1, 3266 .bpc = 8, 3267 .size = { 3268 .width = 154, 3269 .height = 86, 3270 }, 3271 .delay = { 3272 .prepare = 45, 3273 .enable = 100, 3274 .disable = 100, 3275 .unprepare = 45 3276 }, 3277 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3278 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3279 .connector_type = DRM_MODE_CONNECTOR_DPI, 3280 }; 3281 3282 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3283 .clock = 33000, 3284 .hdisplay = 800, 3285 .hsync_start = 800 + 154, 3286 .hsync_end = 800 + 154 + 3, 3287 .htotal = 800 + 154 + 3 + 43, 3288 .vdisplay = 480, 3289 .vsync_start = 480 + 47, 3290 .vsync_end = 480 + 47 + 3, 3291 .vtotal = 480 + 47 + 3 + 20, 3292 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3293 }; 3294 3295 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3296 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3297 .num_modes = 1, 3298 .bpc = 8, 3299 .size = { 3300 .width = 154, 3301 .height = 86, 3302 }, 3303 .delay = { 3304 .prepare = 45, 3305 .enable = 100, 3306 .disable = 100, 3307 .unprepare = 45 3308 }, 3309 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3310 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3311 .connector_type = DRM_MODE_CONNECTOR_DPI, 3312 }; 3313 3314 static const struct drm_display_mode logicpd_type_28_mode = { 3315 .clock = 9107, 3316 .hdisplay = 480, 3317 .hsync_start = 480 + 3, 3318 .hsync_end = 480 + 3 + 42, 3319 .htotal = 480 + 3 + 42 + 2, 3320 3321 .vdisplay = 272, 3322 .vsync_start = 272 + 2, 3323 .vsync_end = 272 + 2 + 11, 3324 .vtotal = 272 + 2 + 11 + 3, 3325 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3326 }; 3327 3328 static const struct panel_desc logicpd_type_28 = { 3329 .modes = &logicpd_type_28_mode, 3330 .num_modes = 1, 3331 .bpc = 8, 3332 .size = { 3333 .width = 105, 3334 .height = 67, 3335 }, 3336 .delay = { 3337 .prepare = 200, 3338 .enable = 200, 3339 .unprepare = 200, 3340 .disable = 200, 3341 }, 3342 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3343 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3344 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3345 .connector_type = DRM_MODE_CONNECTOR_DPI, 3346 }; 3347 3348 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3349 .clock = 150275, 3350 .hdisplay = 1920, 3351 .hsync_start = 1920 + 32, 3352 .hsync_end = 1920 + 32 + 52, 3353 .htotal = 1920 + 32 + 52 + 24, 3354 .vdisplay = 1200, 3355 .vsync_start = 1200 + 24, 3356 .vsync_end = 1200 + 24 + 8, 3357 .vtotal = 1200 + 24 + 8 + 3, 3358 }; 3359 3360 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3361 .modes = µtips_mf_101hiebcaf0_c_mode, 3362 .bpc = 8, 3363 .num_modes = 1, 3364 .size = { 3365 .width = 217, 3366 .height = 136, 3367 }, 3368 .delay = { 3369 .prepare = 50, 3370 .disable = 50, 3371 }, 3372 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3373 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3374 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3375 }; 3376 3377 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3378 .clock = 93301, 3379 .hdisplay = 1920, 3380 .hsync_start = 1920 + 72, 3381 .hsync_end = 1920 + 72 + 72, 3382 .htotal = 1920 + 72 + 72 + 72, 3383 .vdisplay = 720, 3384 .vsync_start = 720 + 3, 3385 .vsync_end = 720 + 3 + 3, 3386 .vtotal = 720 + 3 + 3 + 2, 3387 }; 3388 3389 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3390 .modes = µtips_mf_103hieb0ga0_mode, 3391 .bpc = 8, 3392 .num_modes = 1, 3393 .size = { 3394 .width = 244, 3395 .height = 92, 3396 }, 3397 .delay = { 3398 .prepare = 50, 3399 .disable = 50, 3400 }, 3401 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3402 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3403 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3404 }; 3405 3406 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3407 .clock = 30400, 3408 .hdisplay = 800, 3409 .hsync_start = 800 + 0, 3410 .hsync_end = 800 + 1, 3411 .htotal = 800 + 0 + 1 + 160, 3412 .vdisplay = 480, 3413 .vsync_start = 480 + 0, 3414 .vsync_end = 480 + 48 + 1, 3415 .vtotal = 480 + 48 + 1 + 0, 3416 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3417 }; 3418 3419 static const struct panel_desc mitsubishi_aa070mc01 = { 3420 .modes = &mitsubishi_aa070mc01_mode, 3421 .num_modes = 1, 3422 .bpc = 8, 3423 .size = { 3424 .width = 152, 3425 .height = 91, 3426 }, 3427 3428 .delay = { 3429 .enable = 200, 3430 .unprepare = 200, 3431 .disable = 400, 3432 }, 3433 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3434 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3435 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3436 }; 3437 3438 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3439 .clock = 56234, 3440 .hdisplay = 1024, 3441 .hsync_start = 1024 + 24, 3442 .hsync_end = 1024 + 24 + 63, 3443 .htotal = 1024 + 24 + 63 + 1, 3444 .vdisplay = 768, 3445 .vsync_start = 768 + 3, 3446 .vsync_end = 768 + 3 + 6, 3447 .vtotal = 768 + 3 + 6 + 1, 3448 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3449 }; 3450 3451 static const struct panel_desc mitsubishi_aa084xe01 = { 3452 .modes = &mitsubishi_aa084xe01_mode, 3453 .num_modes = 1, 3454 .bpc = 8, 3455 .size = { 3456 .width = 1024, 3457 .height = 768, 3458 }, 3459 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3460 .connector_type = DRM_MODE_CONNECTOR_DPI, 3461 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3462 }; 3463 3464 static const struct display_timing multi_inno_mi0700a2t_30_timing = { 3465 .pixelclock = { 26400000, 33000000, 46800000 }, 3466 .hactive = { 800, 800, 800 }, 3467 .hfront_porch = { 16, 204, 354 }, 3468 .hback_porch = { 46, 46, 46 }, 3469 .hsync_len = { 1, 6, 40 }, 3470 .vactive = { 480, 480, 480 }, 3471 .vfront_porch = { 7, 22, 147 }, 3472 .vback_porch = { 23, 23, 23 }, 3473 .vsync_len = { 1, 3, 20 }, 3474 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3475 DISPLAY_FLAGS_DE_HIGH, 3476 }; 3477 3478 static const struct panel_desc multi_inno_mi0700a2t_30 = { 3479 .timings = &multi_inno_mi0700a2t_30_timing, 3480 .num_timings = 1, 3481 .bpc = 6, 3482 .size = { 3483 .width = 153, 3484 .height = 92, 3485 }, 3486 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3487 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3488 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3489 }; 3490 3491 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3492 .pixelclock = { 29000000, 33000000, 38000000 }, 3493 .hactive = { 800, 800, 800 }, 3494 .hfront_porch = { 180, 210, 240 }, 3495 .hback_porch = { 16, 16, 16 }, 3496 .hsync_len = { 30, 30, 30 }, 3497 .vactive = { 480, 480, 480 }, 3498 .vfront_porch = { 12, 22, 32 }, 3499 .vback_porch = { 10, 10, 10 }, 3500 .vsync_len = { 13, 13, 13 }, 3501 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3502 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3503 DISPLAY_FLAGS_SYNC_POSEDGE, 3504 }; 3505 3506 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3507 .timings = &multi_inno_mi0700s4t_6_timing, 3508 .num_timings = 1, 3509 .bpc = 8, 3510 .size = { 3511 .width = 154, 3512 .height = 86, 3513 }, 3514 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3515 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3516 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3517 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3518 .connector_type = DRM_MODE_CONNECTOR_DPI, 3519 }; 3520 3521 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3522 .pixelclock = { 32000000, 40000000, 50000000 }, 3523 .hactive = { 800, 800, 800 }, 3524 .hfront_porch = { 16, 210, 354 }, 3525 .hback_porch = { 6, 26, 45 }, 3526 .hsync_len = { 1, 20, 40 }, 3527 .vactive = { 600, 600, 600 }, 3528 .vfront_porch = { 1, 12, 77 }, 3529 .vback_porch = { 3, 13, 22 }, 3530 .vsync_len = { 1, 10, 20 }, 3531 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3532 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3533 DISPLAY_FLAGS_SYNC_POSEDGE, 3534 }; 3535 3536 static const struct panel_desc multi_inno_mi0800ft_9 = { 3537 .timings = &multi_inno_mi0800ft_9_timing, 3538 .num_timings = 1, 3539 .bpc = 8, 3540 .size = { 3541 .width = 162, 3542 .height = 122, 3543 }, 3544 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3545 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3546 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3547 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3548 .connector_type = DRM_MODE_CONNECTOR_DPI, 3549 }; 3550 3551 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3552 .pixelclock = { 68900000, 70000000, 73400000 }, 3553 .hactive = { 1280, 1280, 1280 }, 3554 .hfront_porch = { 30, 60, 71 }, 3555 .hback_porch = { 30, 60, 71 }, 3556 .hsync_len = { 10, 10, 48 }, 3557 .vactive = { 800, 800, 800 }, 3558 .vfront_porch = { 5, 10, 10 }, 3559 .vback_porch = { 5, 10, 10 }, 3560 .vsync_len = { 5, 6, 13 }, 3561 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3562 DISPLAY_FLAGS_DE_HIGH, 3563 }; 3564 3565 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3566 .timings = &multi_inno_mi1010ait_1cp_timing, 3567 .num_timings = 1, 3568 .bpc = 8, 3569 .size = { 3570 .width = 217, 3571 .height = 136, 3572 }, 3573 .delay = { 3574 .enable = 50, 3575 .disable = 50, 3576 }, 3577 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3578 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3579 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3580 }; 3581 3582 static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = { 3583 .pixelclock = { 40800000, 51200000, 67200000 }, 3584 .hactive = { 1024, 1024, 1024 }, 3585 .hfront_porch = { 30, 110, 130 }, 3586 .hback_porch = { 30, 110, 130 }, 3587 .hsync_len = { 30, 100, 116 }, 3588 .vactive = { 600, 600, 600 }, 3589 .vfront_porch = { 4, 13, 80 }, 3590 .vback_porch = { 4, 13, 80 }, 3591 .vsync_len = { 2, 9, 40 }, 3592 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3593 DISPLAY_FLAGS_DE_HIGH, 3594 }; 3595 3596 static const struct panel_desc multi_inno_mi1010z1t_1cp11 = { 3597 .timings = &multi_inno_mi1010z1t_1cp11_timing, 3598 .num_timings = 1, 3599 .bpc = 6, 3600 .size = { 3601 .width = 260, 3602 .height = 162, 3603 }, 3604 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3605 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3606 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3607 }; 3608 3609 static const struct display_timing nec_nl12880bc20_05_timing = { 3610 .pixelclock = { 67000000, 71000000, 75000000 }, 3611 .hactive = { 1280, 1280, 1280 }, 3612 .hfront_porch = { 2, 30, 30 }, 3613 .hback_porch = { 6, 100, 100 }, 3614 .hsync_len = { 2, 30, 30 }, 3615 .vactive = { 800, 800, 800 }, 3616 .vfront_porch = { 5, 5, 5 }, 3617 .vback_porch = { 11, 11, 11 }, 3618 .vsync_len = { 7, 7, 7 }, 3619 }; 3620 3621 static const struct panel_desc nec_nl12880bc20_05 = { 3622 .timings = &nec_nl12880bc20_05_timing, 3623 .num_timings = 1, 3624 .bpc = 8, 3625 .size = { 3626 .width = 261, 3627 .height = 163, 3628 }, 3629 .delay = { 3630 .enable = 50, 3631 .disable = 50, 3632 }, 3633 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3634 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3635 }; 3636 3637 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3638 .clock = 10870, 3639 .hdisplay = 480, 3640 .hsync_start = 480 + 2, 3641 .hsync_end = 480 + 2 + 41, 3642 .htotal = 480 + 2 + 41 + 2, 3643 .vdisplay = 272, 3644 .vsync_start = 272 + 2, 3645 .vsync_end = 272 + 2 + 4, 3646 .vtotal = 272 + 2 + 4 + 2, 3647 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3648 }; 3649 3650 static const struct panel_desc nec_nl4827hc19_05b = { 3651 .modes = &nec_nl4827hc19_05b_mode, 3652 .num_modes = 1, 3653 .bpc = 8, 3654 .size = { 3655 .width = 95, 3656 .height = 54, 3657 }, 3658 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3659 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3660 }; 3661 3662 static const struct drm_display_mode netron_dy_e231732_mode = { 3663 .clock = 66000, 3664 .hdisplay = 1024, 3665 .hsync_start = 1024 + 160, 3666 .hsync_end = 1024 + 160 + 70, 3667 .htotal = 1024 + 160 + 70 + 90, 3668 .vdisplay = 600, 3669 .vsync_start = 600 + 127, 3670 .vsync_end = 600 + 127 + 20, 3671 .vtotal = 600 + 127 + 20 + 3, 3672 }; 3673 3674 static const struct panel_desc netron_dy_e231732 = { 3675 .modes = &netron_dy_e231732_mode, 3676 .num_modes = 1, 3677 .size = { 3678 .width = 154, 3679 .height = 87, 3680 }, 3681 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3682 }; 3683 3684 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3685 .clock = 9000, 3686 .hdisplay = 480, 3687 .hsync_start = 480 + 2, 3688 .hsync_end = 480 + 2 + 41, 3689 .htotal = 480 + 2 + 41 + 2, 3690 .vdisplay = 272, 3691 .vsync_start = 272 + 2, 3692 .vsync_end = 272 + 2 + 10, 3693 .vtotal = 272 + 2 + 10 + 2, 3694 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3695 }; 3696 3697 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3698 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3699 .num_modes = 1, 3700 .bpc = 8, 3701 .size = { 3702 .width = 95, 3703 .height = 54, 3704 }, 3705 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3706 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3707 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3708 .connector_type = DRM_MODE_CONNECTOR_DPI, 3709 }; 3710 3711 static const struct drm_display_mode nlt_nl13676bc25_03f_mode = { 3712 .clock = 75400, 3713 .hdisplay = 1366, 3714 .hsync_start = 1366 + 14, 3715 .hsync_end = 1366 + 14 + 56, 3716 .htotal = 1366 + 14 + 56 + 64, 3717 .vdisplay = 768, 3718 .vsync_start = 768 + 1, 3719 .vsync_end = 768 + 1 + 3, 3720 .vtotal = 768 + 1 + 3 + 22, 3721 }; 3722 3723 static const struct panel_desc nlt_nl13676bc25_03f = { 3724 .modes = &nlt_nl13676bc25_03f_mode, 3725 .num_modes = 1, 3726 .bpc = 8, 3727 .size = { 3728 .width = 363, 3729 .height = 215, 3730 }, 3731 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3732 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3733 }; 3734 3735 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3736 .pixelclock = { 130000000, 148350000, 163000000 }, 3737 .hactive = { 1920, 1920, 1920 }, 3738 .hfront_porch = { 80, 100, 100 }, 3739 .hback_porch = { 100, 120, 120 }, 3740 .hsync_len = { 50, 60, 60 }, 3741 .vactive = { 1080, 1080, 1080 }, 3742 .vfront_porch = { 12, 30, 30 }, 3743 .vback_porch = { 4, 10, 10 }, 3744 .vsync_len = { 4, 5, 5 }, 3745 }; 3746 3747 static const struct panel_desc nlt_nl192108ac18_02d = { 3748 .timings = &nlt_nl192108ac18_02d_timing, 3749 .num_timings = 1, 3750 .bpc = 8, 3751 .size = { 3752 .width = 344, 3753 .height = 194, 3754 }, 3755 .delay = { 3756 .unprepare = 500, 3757 }, 3758 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3759 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3760 }; 3761 3762 static const struct drm_display_mode nvd_9128_mode = { 3763 .clock = 29500, 3764 .hdisplay = 800, 3765 .hsync_start = 800 + 130, 3766 .hsync_end = 800 + 130 + 98, 3767 .htotal = 800 + 0 + 130 + 98, 3768 .vdisplay = 480, 3769 .vsync_start = 480 + 10, 3770 .vsync_end = 480 + 10 + 50, 3771 .vtotal = 480 + 0 + 10 + 50, 3772 }; 3773 3774 static const struct panel_desc nvd_9128 = { 3775 .modes = &nvd_9128_mode, 3776 .num_modes = 1, 3777 .bpc = 8, 3778 .size = { 3779 .width = 156, 3780 .height = 88, 3781 }, 3782 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3783 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3784 }; 3785 3786 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3787 .pixelclock = { 30000000, 30000000, 40000000 }, 3788 .hactive = { 800, 800, 800 }, 3789 .hfront_porch = { 40, 40, 40 }, 3790 .hback_porch = { 40, 40, 40 }, 3791 .hsync_len = { 1, 48, 48 }, 3792 .vactive = { 480, 480, 480 }, 3793 .vfront_porch = { 13, 13, 13 }, 3794 .vback_porch = { 29, 29, 29 }, 3795 .vsync_len = { 3, 3, 3 }, 3796 .flags = DISPLAY_FLAGS_DE_HIGH, 3797 }; 3798 3799 static const struct panel_desc okaya_rs800480t_7x0gp = { 3800 .timings = &okaya_rs800480t_7x0gp_timing, 3801 .num_timings = 1, 3802 .bpc = 6, 3803 .size = { 3804 .width = 154, 3805 .height = 87, 3806 }, 3807 .delay = { 3808 .prepare = 41, 3809 .enable = 50, 3810 .unprepare = 41, 3811 .disable = 50, 3812 }, 3813 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3814 }; 3815 3816 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3817 .clock = 9000, 3818 .hdisplay = 480, 3819 .hsync_start = 480 + 5, 3820 .hsync_end = 480 + 5 + 30, 3821 .htotal = 480 + 5 + 30 + 10, 3822 .vdisplay = 272, 3823 .vsync_start = 272 + 8, 3824 .vsync_end = 272 + 8 + 5, 3825 .vtotal = 272 + 8 + 5 + 3, 3826 }; 3827 3828 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3829 .modes = &olimex_lcd_olinuxino_43ts_mode, 3830 .num_modes = 1, 3831 .size = { 3832 .width = 95, 3833 .height = 54, 3834 }, 3835 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3836 }; 3837 3838 static const struct drm_display_mode olimex_lcd_olinuxino_5cts_mode = { 3839 .clock = 33300, 3840 .hdisplay = 800, 3841 .hsync_start = 800 + 210, 3842 .hsync_end = 800 + 210 + 20, 3843 .htotal = 800 + 210 + 20 + 26, 3844 .vdisplay = 480, 3845 .vsync_start = 480 + 22, 3846 .vsync_end = 480 + 22 + 10, 3847 .vtotal = 480 + 22 + 10 + 13, 3848 }; 3849 3850 static const struct panel_desc olimex_lcd_olinuxino_5cts = { 3851 .modes = &olimex_lcd_olinuxino_5cts_mode, 3852 .num_modes = 1, 3853 .size = { 3854 .width = 154, 3855 .height = 86, 3856 }, 3857 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3858 }; 3859 3860 3861 static const struct display_timing ontat_kd50g21_40nt_a1_timing = { 3862 .pixelclock = { 30000000, 30000000, 50000000 }, 3863 .hactive = { 800, 800, 800 }, 3864 .hfront_porch = { 1, 40, 255 }, 3865 .hback_porch = { 1, 40, 87 }, 3866 .hsync_len = { 1, 48, 87 }, 3867 .vactive = { 480, 480, 480 }, 3868 .vfront_porch = { 1, 13, 255 }, 3869 .vback_porch = { 1, 29, 29 }, 3870 .vsync_len = { 3, 3, 31 }, 3871 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3872 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3873 }; 3874 3875 static const struct panel_desc ontat_kd50g21_40nt_a1 = { 3876 .timings = &ontat_kd50g21_40nt_a1_timing, 3877 .num_timings = 1, 3878 .bpc = 8, 3879 .size = { 3880 .width = 108, 3881 .height = 65, 3882 }, 3883 .delay = { 3884 .prepare = 147, /* 5 VSDs */ 3885 .enable = 147, /* 5 VSDs */ 3886 .disable = 88, /* 3 VSDs */ 3887 .unprepare = 117, /* 4 VSDs */ 3888 }, 3889 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3890 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3891 .connector_type = DRM_MODE_CONNECTOR_DPI, 3892 }; 3893 3894 /* 3895 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3896 * pixel clocks, but this is the timing that was being used in the Adafruit 3897 * installation instructions. 3898 */ 3899 static const struct drm_display_mode ontat_yx700wv03_mode = { 3900 .clock = 29500, 3901 .hdisplay = 800, 3902 .hsync_start = 824, 3903 .hsync_end = 896, 3904 .htotal = 992, 3905 .vdisplay = 480, 3906 .vsync_start = 483, 3907 .vsync_end = 493, 3908 .vtotal = 500, 3909 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3910 }; 3911 3912 /* 3913 * Specification at: 3914 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3915 */ 3916 static const struct panel_desc ontat_yx700wv03 = { 3917 .modes = &ontat_yx700wv03_mode, 3918 .num_modes = 1, 3919 .bpc = 8, 3920 .size = { 3921 .width = 154, 3922 .height = 83, 3923 }, 3924 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3925 }; 3926 3927 static const struct drm_display_mode ortustech_com37h3m_mode = { 3928 .clock = 22230, 3929 .hdisplay = 480, 3930 .hsync_start = 480 + 40, 3931 .hsync_end = 480 + 40 + 10, 3932 .htotal = 480 + 40 + 10 + 40, 3933 .vdisplay = 640, 3934 .vsync_start = 640 + 4, 3935 .vsync_end = 640 + 4 + 2, 3936 .vtotal = 640 + 4 + 2 + 4, 3937 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3938 }; 3939 3940 static const struct panel_desc ortustech_com37h3m = { 3941 .modes = &ortustech_com37h3m_mode, 3942 .num_modes = 1, 3943 .bpc = 8, 3944 .size = { 3945 .width = 56, /* 56.16mm */ 3946 .height = 75, /* 74.88mm */ 3947 }, 3948 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3949 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3950 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3951 }; 3952 3953 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3954 .clock = 25000, 3955 .hdisplay = 480, 3956 .hsync_start = 480 + 10, 3957 .hsync_end = 480 + 10 + 10, 3958 .htotal = 480 + 10 + 10 + 15, 3959 .vdisplay = 800, 3960 .vsync_start = 800 + 3, 3961 .vsync_end = 800 + 3 + 3, 3962 .vtotal = 800 + 3 + 3 + 3, 3963 }; 3964 3965 static const struct panel_desc ortustech_com43h4m85ulc = { 3966 .modes = &ortustech_com43h4m85ulc_mode, 3967 .num_modes = 1, 3968 .bpc = 6, 3969 .size = { 3970 .width = 56, 3971 .height = 93, 3972 }, 3973 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3974 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3975 .connector_type = DRM_MODE_CONNECTOR_DPI, 3976 }; 3977 3978 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3979 .clock = 33000, 3980 .hdisplay = 800, 3981 .hsync_start = 800 + 210, 3982 .hsync_end = 800 + 210 + 30, 3983 .htotal = 800 + 210 + 30 + 16, 3984 .vdisplay = 480, 3985 .vsync_start = 480 + 22, 3986 .vsync_end = 480 + 22 + 13, 3987 .vtotal = 480 + 22 + 13 + 10, 3988 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3989 }; 3990 3991 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3992 .modes = &osddisplays_osd070t1718_19ts_mode, 3993 .num_modes = 1, 3994 .bpc = 8, 3995 .size = { 3996 .width = 152, 3997 .height = 91, 3998 }, 3999 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4000 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 4001 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4002 .connector_type = DRM_MODE_CONNECTOR_DPI, 4003 }; 4004 4005 static const struct drm_display_mode pda_91_00156_a0_mode = { 4006 .clock = 33300, 4007 .hdisplay = 800, 4008 .hsync_start = 800 + 1, 4009 .hsync_end = 800 + 1 + 64, 4010 .htotal = 800 + 1 + 64 + 64, 4011 .vdisplay = 480, 4012 .vsync_start = 480 + 1, 4013 .vsync_end = 480 + 1 + 23, 4014 .vtotal = 480 + 1 + 23 + 22, 4015 }; 4016 4017 static const struct panel_desc pda_91_00156_a0 = { 4018 .modes = &pda_91_00156_a0_mode, 4019 .num_modes = 1, 4020 .size = { 4021 .width = 152, 4022 .height = 91, 4023 }, 4024 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4025 }; 4026 4027 static const struct drm_display_mode powertip_ph128800t004_zza01_mode = { 4028 .clock = 71150, 4029 .hdisplay = 1280, 4030 .hsync_start = 1280 + 48, 4031 .hsync_end = 1280 + 48 + 32, 4032 .htotal = 1280 + 48 + 32 + 80, 4033 .vdisplay = 800, 4034 .vsync_start = 800 + 9, 4035 .vsync_end = 800 + 9 + 8, 4036 .vtotal = 800 + 9 + 8 + 6, 4037 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4038 }; 4039 4040 static const struct panel_desc powertip_ph128800t004_zza01 = { 4041 .modes = &powertip_ph128800t004_zza01_mode, 4042 .num_modes = 1, 4043 .bpc = 8, 4044 .size = { 4045 .width = 216, 4046 .height = 135, 4047 }, 4048 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4049 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4050 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4051 }; 4052 4053 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 4054 .clock = 66500, 4055 .hdisplay = 1280, 4056 .hsync_start = 1280 + 12, 4057 .hsync_end = 1280 + 12 + 20, 4058 .htotal = 1280 + 12 + 20 + 56, 4059 .vdisplay = 800, 4060 .vsync_start = 800 + 1, 4061 .vsync_end = 800 + 1 + 3, 4062 .vtotal = 800 + 1 + 3 + 20, 4063 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4064 }; 4065 4066 static const struct panel_desc powertip_ph128800t006_zhc01 = { 4067 .modes = &powertip_ph128800t006_zhc01_mode, 4068 .num_modes = 1, 4069 .bpc = 8, 4070 .size = { 4071 .width = 216, 4072 .height = 135, 4073 }, 4074 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4075 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4076 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4077 }; 4078 4079 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 4080 .clock = 24750, 4081 .hdisplay = 800, 4082 .hsync_start = 800 + 54, 4083 .hsync_end = 800 + 54 + 2, 4084 .htotal = 800 + 54 + 2 + 44, 4085 .vdisplay = 480, 4086 .vsync_start = 480 + 49, 4087 .vsync_end = 480 + 49 + 2, 4088 .vtotal = 480 + 49 + 2 + 22, 4089 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4090 }; 4091 4092 static const struct panel_desc powertip_ph800480t013_idf02 = { 4093 .modes = &powertip_ph800480t013_idf02_mode, 4094 .num_modes = 1, 4095 .bpc = 8, 4096 .size = { 4097 .width = 152, 4098 .height = 91, 4099 }, 4100 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4101 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4102 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4103 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4104 .connector_type = DRM_MODE_CONNECTOR_DPI, 4105 }; 4106 4107 static const struct drm_display_mode powertip_ph800480t032_zhc19_mode = { 4108 .clock = 27200, 4109 .hdisplay = 800, 4110 .hsync_start = 800 + 52, 4111 .hsync_end = 800 + 52 + 2, 4112 .htotal = 800 + 52 + 2 + 44, 4113 .vdisplay = 480, 4114 .vsync_start = 480 + 7, 4115 .vsync_end = 480 + 7 + 2, 4116 .vtotal = 480 + 7 + 2 + 2, 4117 }; 4118 4119 static const struct panel_desc powertip_ph800480t032_zhc19 = { 4120 .modes = &powertip_ph800480t032_zhc19_mode, 4121 .num_modes = 1, 4122 .bpc = 8, 4123 .size = { 4124 .width = 152, 4125 .height = 91, 4126 }, 4127 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4128 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4129 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4130 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4131 .connector_type = DRM_MODE_CONNECTOR_DPI, 4132 }; 4133 4134 static const struct drm_display_mode primeview_pm070wl4_mode = { 4135 .clock = 32000, 4136 .hdisplay = 800, 4137 .hsync_start = 800 + 42, 4138 .hsync_end = 800 + 42 + 128, 4139 .htotal = 800 + 42 + 128 + 86, 4140 .vdisplay = 480, 4141 .vsync_start = 480 + 10, 4142 .vsync_end = 480 + 10 + 2, 4143 .vtotal = 480 + 10 + 2 + 33, 4144 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4145 }; 4146 4147 static const struct panel_desc primeview_pm070wl4 = { 4148 .modes = &primeview_pm070wl4_mode, 4149 .num_modes = 1, 4150 .bpc = 6, 4151 .size = { 4152 .width = 152, 4153 .height = 91, 4154 }, 4155 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4156 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4157 .connector_type = DRM_MODE_CONNECTOR_DPI, 4158 }; 4159 4160 static const struct drm_display_mode qd43003c0_40_mode = { 4161 .clock = 9000, 4162 .hdisplay = 480, 4163 .hsync_start = 480 + 8, 4164 .hsync_end = 480 + 8 + 4, 4165 .htotal = 480 + 8 + 4 + 39, 4166 .vdisplay = 272, 4167 .vsync_start = 272 + 4, 4168 .vsync_end = 272 + 4 + 10, 4169 .vtotal = 272 + 4 + 10 + 2, 4170 }; 4171 4172 static const struct panel_desc qd43003c0_40 = { 4173 .modes = &qd43003c0_40_mode, 4174 .num_modes = 1, 4175 .bpc = 8, 4176 .size = { 4177 .width = 95, 4178 .height = 53, 4179 }, 4180 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4181 }; 4182 4183 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 4184 { /* 60 Hz */ 4185 .clock = 10800, 4186 .hdisplay = 480, 4187 .hsync_start = 480 + 77, 4188 .hsync_end = 480 + 77 + 41, 4189 .htotal = 480 + 77 + 41 + 2, 4190 .vdisplay = 272, 4191 .vsync_start = 272 + 16, 4192 .vsync_end = 272 + 16 + 10, 4193 .vtotal = 272 + 16 + 10 + 2, 4194 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4195 }, 4196 { /* 50 Hz */ 4197 .clock = 10800, 4198 .hdisplay = 480, 4199 .hsync_start = 480 + 17, 4200 .hsync_end = 480 + 17 + 41, 4201 .htotal = 480 + 17 + 41 + 2, 4202 .vdisplay = 272, 4203 .vsync_start = 272 + 116, 4204 .vsync_end = 272 + 116 + 10, 4205 .vtotal = 272 + 116 + 10 + 2, 4206 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4207 }, 4208 }; 4209 4210 static const struct panel_desc qishenglong_gopher2b_lcd = { 4211 .modes = qishenglong_gopher2b_lcd_modes, 4212 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 4213 .bpc = 8, 4214 .size = { 4215 .width = 95, 4216 .height = 54, 4217 }, 4218 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4219 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4220 .connector_type = DRM_MODE_CONNECTOR_DPI, 4221 }; 4222 4223 static const struct display_timing raystar_rff500f_awh_dnn_timing = { 4224 .pixelclock = { 23000000, 25000000, 27000000 }, 4225 .hactive = { 800, 800, 800 }, 4226 .hback_porch = { 4, 8, 48 }, 4227 .hfront_porch = { 4, 8, 48 }, 4228 .hsync_len = { 2, 4, 8 }, 4229 .vactive = { 480, 480, 480 }, 4230 .vback_porch = { 4, 8, 12 }, 4231 .vfront_porch = { 4, 8, 12 }, 4232 .vsync_len = { 2, 4, 8 }, 4233 }; 4234 4235 static const struct panel_desc raystar_rff500f_awh_dnn = { 4236 .timings = &raystar_rff500f_awh_dnn_timing, 4237 .num_timings = 1, 4238 .bpc = 8, 4239 .size = { 4240 .width = 108, 4241 .height = 65, 4242 }, 4243 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4244 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4245 }; 4246 4247 static const struct display_timing rocktech_rk043fn48h_timing = { 4248 .pixelclock = { 6000000, 9000000, 12000000 }, 4249 .hactive = { 480, 480, 480 }, 4250 .hback_porch = { 8, 43, 43 }, 4251 .hfront_porch = { 2, 8, 10 }, 4252 .hsync_len = { 1, 1, 1 }, 4253 .vactive = { 272, 272, 272 }, 4254 .vback_porch = { 2, 12, 26 }, 4255 .vfront_porch = { 1, 4, 4 }, 4256 .vsync_len = { 1, 10, 10 }, 4257 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 4258 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4259 DISPLAY_FLAGS_SYNC_POSEDGE, 4260 }; 4261 4262 static const struct panel_desc rocktech_rk043fn48h = { 4263 .timings = &rocktech_rk043fn48h_timing, 4264 .num_timings = 1, 4265 .bpc = 8, 4266 .size = { 4267 .width = 95, 4268 .height = 54, 4269 }, 4270 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4271 .connector_type = DRM_MODE_CONNECTOR_DPI, 4272 }; 4273 4274 static const struct display_timing rocktech_rk070er9427_timing = { 4275 .pixelclock = { 26400000, 33300000, 46800000 }, 4276 .hactive = { 800, 800, 800 }, 4277 .hfront_porch = { 16, 210, 354 }, 4278 .hback_porch = { 46, 46, 46 }, 4279 .hsync_len = { 1, 1, 1 }, 4280 .vactive = { 480, 480, 480 }, 4281 .vfront_porch = { 7, 22, 147 }, 4282 .vback_porch = { 23, 23, 23 }, 4283 .vsync_len = { 1, 1, 1 }, 4284 .flags = DISPLAY_FLAGS_DE_HIGH, 4285 }; 4286 4287 static const struct panel_desc rocktech_rk070er9427 = { 4288 .timings = &rocktech_rk070er9427_timing, 4289 .num_timings = 1, 4290 .bpc = 6, 4291 .size = { 4292 .width = 154, 4293 .height = 86, 4294 }, 4295 .delay = { 4296 .prepare = 41, 4297 .enable = 50, 4298 .unprepare = 41, 4299 .disable = 50, 4300 }, 4301 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4302 }; 4303 4304 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 4305 .clock = 71100, 4306 .hdisplay = 1280, 4307 .hsync_start = 1280 + 48, 4308 .hsync_end = 1280 + 48 + 32, 4309 .htotal = 1280 + 48 + 32 + 80, 4310 .vdisplay = 800, 4311 .vsync_start = 800 + 2, 4312 .vsync_end = 800 + 2 + 5, 4313 .vtotal = 800 + 2 + 5 + 16, 4314 }; 4315 4316 static const struct panel_desc rocktech_rk101ii01d_ct = { 4317 .modes = &rocktech_rk101ii01d_ct_mode, 4318 .bpc = 8, 4319 .num_modes = 1, 4320 .size = { 4321 .width = 217, 4322 .height = 136, 4323 }, 4324 .delay = { 4325 .prepare = 50, 4326 .disable = 50, 4327 }, 4328 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4329 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4330 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4331 }; 4332 4333 static const struct display_timing samsung_ltl101al01_timing = { 4334 .pixelclock = { 66663000, 66663000, 66663000 }, 4335 .hactive = { 1280, 1280, 1280 }, 4336 .hfront_porch = { 18, 18, 18 }, 4337 .hback_porch = { 36, 36, 36 }, 4338 .hsync_len = { 16, 16, 16 }, 4339 .vactive = { 800, 800, 800 }, 4340 .vfront_porch = { 4, 4, 4 }, 4341 .vback_porch = { 16, 16, 16 }, 4342 .vsync_len = { 3, 3, 3 }, 4343 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4344 }; 4345 4346 static const struct panel_desc samsung_ltl101al01 = { 4347 .timings = &samsung_ltl101al01_timing, 4348 .num_timings = 1, 4349 .bpc = 8, 4350 .size = { 4351 .width = 217, 4352 .height = 135, 4353 }, 4354 .delay = { 4355 .prepare = 40, 4356 .enable = 300, 4357 .disable = 200, 4358 .unprepare = 600, 4359 }, 4360 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4361 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4362 }; 4363 4364 static const struct display_timing samsung_ltl106al01_timing = { 4365 .pixelclock = { 71980000, 71980000, 71980000 }, 4366 .hactive = { 1366, 1366, 1366 }, 4367 .hfront_porch = { 56, 56, 56 }, 4368 .hback_porch = { 106, 106, 106 }, 4369 .hsync_len = { 14, 14, 14 }, 4370 .vactive = { 768, 768, 768 }, 4371 .vfront_porch = { 3, 3, 3 }, 4372 .vback_porch = { 6, 6, 6 }, 4373 .vsync_len = { 1, 1, 1 }, 4374 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4375 }; 4376 4377 static const struct panel_desc samsung_ltl106al01 = { 4378 .timings = &samsung_ltl106al01_timing, 4379 .num_timings = 1, 4380 .bpc = 8, 4381 .size = { 4382 .width = 235, 4383 .height = 132, 4384 }, 4385 .delay = { 4386 .prepare = 5, 4387 .enable = 10, 4388 .disable = 10, 4389 .unprepare = 5, 4390 }, 4391 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4392 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4393 }; 4394 4395 static const struct drm_display_mode samsung_ltn101nt05_mode = { 4396 .clock = 54030, 4397 .hdisplay = 1024, 4398 .hsync_start = 1024 + 24, 4399 .hsync_end = 1024 + 24 + 136, 4400 .htotal = 1024 + 24 + 136 + 160, 4401 .vdisplay = 600, 4402 .vsync_start = 600 + 3, 4403 .vsync_end = 600 + 3 + 6, 4404 .vtotal = 600 + 3 + 6 + 61, 4405 }; 4406 4407 static const struct panel_desc samsung_ltn101nt05 = { 4408 .modes = &samsung_ltn101nt05_mode, 4409 .num_modes = 1, 4410 .bpc = 6, 4411 .size = { 4412 .width = 223, 4413 .height = 125, 4414 }, 4415 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4416 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4417 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4418 }; 4419 4420 static const struct display_timing satoz_sat050at40h12r2_timing = { 4421 .pixelclock = {33300000, 33300000, 50000000}, 4422 .hactive = {800, 800, 800}, 4423 .hfront_porch = {16, 210, 354}, 4424 .hback_porch = {46, 46, 46}, 4425 .hsync_len = {1, 1, 40}, 4426 .vactive = {480, 480, 480}, 4427 .vfront_porch = {7, 22, 147}, 4428 .vback_porch = {23, 23, 23}, 4429 .vsync_len = {1, 1, 20}, 4430 }; 4431 4432 static const struct panel_desc satoz_sat050at40h12r2 = { 4433 .timings = &satoz_sat050at40h12r2_timing, 4434 .num_timings = 1, 4435 .bpc = 8, 4436 .size = { 4437 .width = 108, 4438 .height = 65, 4439 }, 4440 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4441 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4442 }; 4443 4444 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 4445 .clock = 33260, 4446 .hdisplay = 800, 4447 .hsync_start = 800 + 64, 4448 .hsync_end = 800 + 64 + 128, 4449 .htotal = 800 + 64 + 128 + 64, 4450 .vdisplay = 480, 4451 .vsync_start = 480 + 8, 4452 .vsync_end = 480 + 8 + 2, 4453 .vtotal = 480 + 8 + 2 + 35, 4454 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4455 }; 4456 4457 static const struct panel_desc sharp_lq070y3dg3b = { 4458 .modes = &sharp_lq070y3dg3b_mode, 4459 .num_modes = 1, 4460 .bpc = 8, 4461 .size = { 4462 .width = 152, /* 152.4mm */ 4463 .height = 91, /* 91.4mm */ 4464 }, 4465 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4466 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4467 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4468 }; 4469 4470 static const struct drm_display_mode sharp_lq035q7db03_mode = { 4471 .clock = 5500, 4472 .hdisplay = 240, 4473 .hsync_start = 240 + 16, 4474 .hsync_end = 240 + 16 + 7, 4475 .htotal = 240 + 16 + 7 + 5, 4476 .vdisplay = 320, 4477 .vsync_start = 320 + 9, 4478 .vsync_end = 320 + 9 + 1, 4479 .vtotal = 320 + 9 + 1 + 7, 4480 }; 4481 4482 static const struct panel_desc sharp_lq035q7db03 = { 4483 .modes = &sharp_lq035q7db03_mode, 4484 .num_modes = 1, 4485 .bpc = 6, 4486 .size = { 4487 .width = 54, 4488 .height = 72, 4489 }, 4490 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4491 }; 4492 4493 static const struct display_timing sharp_lq101k1ly04_timing = { 4494 .pixelclock = { 60000000, 65000000, 80000000 }, 4495 .hactive = { 1280, 1280, 1280 }, 4496 .hfront_porch = { 20, 20, 20 }, 4497 .hback_porch = { 20, 20, 20 }, 4498 .hsync_len = { 10, 10, 10 }, 4499 .vactive = { 800, 800, 800 }, 4500 .vfront_porch = { 4, 4, 4 }, 4501 .vback_porch = { 4, 4, 4 }, 4502 .vsync_len = { 4, 4, 4 }, 4503 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4504 }; 4505 4506 static const struct panel_desc sharp_lq101k1ly04 = { 4507 .timings = &sharp_lq101k1ly04_timing, 4508 .num_timings = 1, 4509 .bpc = 8, 4510 .size = { 4511 .width = 217, 4512 .height = 136, 4513 }, 4514 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4515 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4516 }; 4517 4518 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4519 { /* 50 Hz */ 4520 .clock = 3000, 4521 .hdisplay = 240, 4522 .hsync_start = 240 + 58, 4523 .hsync_end = 240 + 58 + 1, 4524 .htotal = 240 + 58 + 1 + 1, 4525 .vdisplay = 160, 4526 .vsync_start = 160 + 24, 4527 .vsync_end = 160 + 24 + 10, 4528 .vtotal = 160 + 24 + 10 + 6, 4529 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4530 }, 4531 { /* 60 Hz */ 4532 .clock = 3000, 4533 .hdisplay = 240, 4534 .hsync_start = 240 + 8, 4535 .hsync_end = 240 + 8 + 1, 4536 .htotal = 240 + 8 + 1 + 1, 4537 .vdisplay = 160, 4538 .vsync_start = 160 + 24, 4539 .vsync_end = 160 + 24 + 10, 4540 .vtotal = 160 + 24 + 10 + 6, 4541 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4542 }, 4543 }; 4544 4545 static const struct panel_desc sharp_ls020b1dd01d = { 4546 .modes = sharp_ls020b1dd01d_modes, 4547 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4548 .bpc = 6, 4549 .size = { 4550 .width = 42, 4551 .height = 28, 4552 }, 4553 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4554 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4555 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4556 | DRM_BUS_FLAG_SHARP_SIGNALS, 4557 }; 4558 4559 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4560 .clock = 33300, 4561 .hdisplay = 800, 4562 .hsync_start = 800 + 1, 4563 .hsync_end = 800 + 1 + 64, 4564 .htotal = 800 + 1 + 64 + 64, 4565 .vdisplay = 480, 4566 .vsync_start = 480 + 1, 4567 .vsync_end = 480 + 1 + 23, 4568 .vtotal = 480 + 1 + 23 + 22, 4569 }; 4570 4571 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4572 .modes = &shelly_sca07010_bfn_lnn_mode, 4573 .num_modes = 1, 4574 .size = { 4575 .width = 152, 4576 .height = 91, 4577 }, 4578 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4579 }; 4580 4581 static const struct drm_display_mode starry_kr070pe2t_mode = { 4582 .clock = 33000, 4583 .hdisplay = 800, 4584 .hsync_start = 800 + 209, 4585 .hsync_end = 800 + 209 + 1, 4586 .htotal = 800 + 209 + 1 + 45, 4587 .vdisplay = 480, 4588 .vsync_start = 480 + 22, 4589 .vsync_end = 480 + 22 + 1, 4590 .vtotal = 480 + 22 + 1 + 22, 4591 }; 4592 4593 static const struct panel_desc starry_kr070pe2t = { 4594 .modes = &starry_kr070pe2t_mode, 4595 .num_modes = 1, 4596 .bpc = 8, 4597 .size = { 4598 .width = 152, 4599 .height = 86, 4600 }, 4601 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4602 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4603 .connector_type = DRM_MODE_CONNECTOR_DPI, 4604 }; 4605 4606 static const struct display_timing startek_kd070wvfpa_mode = { 4607 .pixelclock = { 25200000, 27200000, 30500000 }, 4608 .hactive = { 800, 800, 800 }, 4609 .hfront_porch = { 19, 44, 115 }, 4610 .hback_porch = { 5, 16, 101 }, 4611 .hsync_len = { 1, 2, 100 }, 4612 .vactive = { 480, 480, 480 }, 4613 .vfront_porch = { 5, 43, 67 }, 4614 .vback_porch = { 5, 5, 67 }, 4615 .vsync_len = { 1, 2, 66 }, 4616 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4617 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4618 DISPLAY_FLAGS_SYNC_POSEDGE, 4619 }; 4620 4621 static const struct panel_desc startek_kd070wvfpa = { 4622 .timings = &startek_kd070wvfpa_mode, 4623 .num_timings = 1, 4624 .bpc = 8, 4625 .size = { 4626 .width = 152, 4627 .height = 91, 4628 }, 4629 .delay = { 4630 .prepare = 20, 4631 .enable = 200, 4632 .disable = 200, 4633 }, 4634 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4635 .connector_type = DRM_MODE_CONNECTOR_DPI, 4636 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4637 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4638 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4639 }; 4640 4641 static const struct display_timing tsd_tst043015cmhx_timing = { 4642 .pixelclock = { 5000000, 9000000, 12000000 }, 4643 .hactive = { 480, 480, 480 }, 4644 .hfront_porch = { 4, 5, 65 }, 4645 .hback_porch = { 36, 40, 255 }, 4646 .hsync_len = { 1, 1, 1 }, 4647 .vactive = { 272, 272, 272 }, 4648 .vfront_porch = { 2, 8, 97 }, 4649 .vback_porch = { 3, 8, 31 }, 4650 .vsync_len = { 1, 1, 1 }, 4651 4652 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4653 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4654 }; 4655 4656 static const struct panel_desc tsd_tst043015cmhx = { 4657 .timings = &tsd_tst043015cmhx_timing, 4658 .num_timings = 1, 4659 .bpc = 8, 4660 .size = { 4661 .width = 105, 4662 .height = 67, 4663 }, 4664 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4665 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4666 }; 4667 4668 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4669 .clock = 30000, 4670 .hdisplay = 800, 4671 .hsync_start = 800 + 39, 4672 .hsync_end = 800 + 39 + 47, 4673 .htotal = 800 + 39 + 47 + 39, 4674 .vdisplay = 480, 4675 .vsync_start = 480 + 13, 4676 .vsync_end = 480 + 13 + 2, 4677 .vtotal = 480 + 13 + 2 + 29, 4678 }; 4679 4680 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4681 .modes = &tfc_s9700rtwv43tr_01b_mode, 4682 .num_modes = 1, 4683 .bpc = 8, 4684 .size = { 4685 .width = 155, 4686 .height = 90, 4687 }, 4688 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4689 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4690 }; 4691 4692 static const struct display_timing tianma_tm070jdhg30_timing = { 4693 .pixelclock = { 62600000, 68200000, 78100000 }, 4694 .hactive = { 1280, 1280, 1280 }, 4695 .hfront_porch = { 15, 64, 159 }, 4696 .hback_porch = { 5, 5, 5 }, 4697 .hsync_len = { 1, 1, 256 }, 4698 .vactive = { 800, 800, 800 }, 4699 .vfront_porch = { 3, 40, 99 }, 4700 .vback_porch = { 2, 2, 2 }, 4701 .vsync_len = { 1, 1, 128 }, 4702 .flags = DISPLAY_FLAGS_DE_HIGH, 4703 }; 4704 4705 static const struct panel_desc tianma_tm070jdhg30 = { 4706 .timings = &tianma_tm070jdhg30_timing, 4707 .num_timings = 1, 4708 .bpc = 8, 4709 .size = { 4710 .width = 151, 4711 .height = 95, 4712 }, 4713 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4714 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4715 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4716 }; 4717 4718 static const struct panel_desc tianma_tm070jvhg33 = { 4719 .timings = &tianma_tm070jdhg30_timing, 4720 .num_timings = 1, 4721 .bpc = 8, 4722 .size = { 4723 .width = 150, 4724 .height = 94, 4725 }, 4726 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4727 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4728 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4729 }; 4730 4731 /* 4732 * The TM070JDHG34-00 datasheet computes total blanking as back porch + 4733 * front porch, not including sync pulse width. This is for both H and 4734 * V. To make the total blanking and period correct, subtract the pulse 4735 * width from the front porch. 4736 * 4737 * This works well for the Min and Typ values, but for Max values the sync 4738 * pulse width is higher than back porch + front porch, so work around that 4739 * by reducing the Max sync length value to 1 and then treating the Max 4740 * porches as in the Min and Typ cases. 4741 * 4742 * Exact datasheet values are added as a comment where they differ from the 4743 * ones implemented for the above reason. 4744 * 4745 * The P0700WXF1MBAA datasheet is even less detailed, only listing period 4746 * and total blanking time, however the resulting values are the same as 4747 * the TM070JDHG34-00. 4748 */ 4749 static const struct display_timing tianma_tm070jdhg34_00_timing = { 4750 .pixelclock = { 68400000, 71900000, 78100000 }, 4751 .hactive = { 1280, 1280, 1280 }, 4752 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ 4753 .hback_porch = { 5, 5, 5 }, 4754 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ 4755 .vactive = { 800, 800, 800 }, 4756 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ 4757 .vback_porch = { 2, 2, 2 }, 4758 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ 4759 .flags = DISPLAY_FLAGS_DE_HIGH, 4760 }; 4761 4762 static const struct panel_desc tianma_tm070jdhg34_00 = { 4763 .timings = &tianma_tm070jdhg34_00_timing, 4764 .num_timings = 1, 4765 .bpc = 8, 4766 .size = { 4767 .width = 150, /* 149.76 */ 4768 .height = 94, /* 93.60 */ 4769 }, 4770 .delay = { 4771 .prepare = 15, /* Tp1 */ 4772 .enable = 150, /* Tp2 */ 4773 .disable = 150, /* Tp4 */ 4774 .unprepare = 120, /* Tp3 */ 4775 }, 4776 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4777 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4778 }; 4779 4780 static const struct panel_desc tianma_p0700wxf1mbaa = { 4781 .timings = &tianma_tm070jdhg34_00_timing, 4782 .num_timings = 1, 4783 .bpc = 8, 4784 .size = { 4785 .width = 150, /* 149.76 */ 4786 .height = 94, /* 93.60 */ 4787 }, 4788 .delay = { 4789 .prepare = 18, /* Tr + Tp1 */ 4790 .enable = 152, /* Tp2 + Tp5 */ 4791 .disable = 152, /* Tp6 + Tp4 */ 4792 .unprepare = 120, /* Tp3 */ 4793 }, 4794 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4795 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4796 }; 4797 4798 static const struct display_timing tianma_tm070rvhg71_timing = { 4799 .pixelclock = { 27700000, 29200000, 39600000 }, 4800 .hactive = { 800, 800, 800 }, 4801 .hfront_porch = { 12, 40, 212 }, 4802 .hback_porch = { 88, 88, 88 }, 4803 .hsync_len = { 1, 1, 40 }, 4804 .vactive = { 480, 480, 480 }, 4805 .vfront_porch = { 1, 13, 88 }, 4806 .vback_porch = { 32, 32, 32 }, 4807 .vsync_len = { 1, 1, 3 }, 4808 .flags = DISPLAY_FLAGS_DE_HIGH, 4809 }; 4810 4811 static const struct panel_desc tianma_tm070rvhg71 = { 4812 .timings = &tianma_tm070rvhg71_timing, 4813 .num_timings = 1, 4814 .bpc = 8, 4815 .size = { 4816 .width = 154, 4817 .height = 86, 4818 }, 4819 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4820 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4821 }; 4822 4823 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4824 { 4825 .clock = 10000, 4826 .hdisplay = 320, 4827 .hsync_start = 320 + 50, 4828 .hsync_end = 320 + 50 + 6, 4829 .htotal = 320 + 50 + 6 + 38, 4830 .vdisplay = 240, 4831 .vsync_start = 240 + 3, 4832 .vsync_end = 240 + 3 + 1, 4833 .vtotal = 240 + 3 + 1 + 17, 4834 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4835 }, 4836 }; 4837 4838 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4839 .modes = ti_nspire_cx_lcd_mode, 4840 .num_modes = 1, 4841 .bpc = 8, 4842 .size = { 4843 .width = 65, 4844 .height = 49, 4845 }, 4846 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4847 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4848 }; 4849 4850 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4851 { 4852 .clock = 10000, 4853 .hdisplay = 320, 4854 .hsync_start = 320 + 6, 4855 .hsync_end = 320 + 6 + 6, 4856 .htotal = 320 + 6 + 6 + 6, 4857 .vdisplay = 240, 4858 .vsync_start = 240 + 0, 4859 .vsync_end = 240 + 0 + 1, 4860 .vtotal = 240 + 0 + 1 + 0, 4861 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4862 }, 4863 }; 4864 4865 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4866 .modes = ti_nspire_classic_lcd_mode, 4867 .num_modes = 1, 4868 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4869 .bpc = 8, 4870 .size = { 4871 .width = 71, 4872 .height = 53, 4873 }, 4874 /* This is the grayscale bus format */ 4875 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4876 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4877 }; 4878 4879 static const struct display_timing topland_tian_g07017_01_timing = { 4880 .pixelclock = { 44900000, 51200000, 63000000 }, 4881 .hactive = { 1024, 1024, 1024 }, 4882 .hfront_porch = { 16, 160, 216 }, 4883 .hback_porch = { 160, 160, 160 }, 4884 .hsync_len = { 1, 1, 140 }, 4885 .vactive = { 600, 600, 600 }, 4886 .vfront_porch = { 1, 12, 127 }, 4887 .vback_porch = { 23, 23, 23 }, 4888 .vsync_len = { 1, 1, 20 }, 4889 }; 4890 4891 static const struct panel_desc topland_tian_g07017_01 = { 4892 .timings = &topland_tian_g07017_01_timing, 4893 .num_timings = 1, 4894 .bpc = 8, 4895 .size = { 4896 .width = 154, 4897 .height = 86, 4898 }, 4899 .delay = { 4900 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */ 4901 .enable = 100, /* 6.4 - Power on: 6 VSyncs */ 4902 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */ 4903 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */ 4904 }, 4905 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4906 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4907 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4908 }; 4909 4910 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4911 .clock = 79500, 4912 .hdisplay = 1280, 4913 .hsync_start = 1280 + 192, 4914 .hsync_end = 1280 + 192 + 128, 4915 .htotal = 1280 + 192 + 128 + 64, 4916 .vdisplay = 768, 4917 .vsync_start = 768 + 20, 4918 .vsync_end = 768 + 20 + 7, 4919 .vtotal = 768 + 20 + 7 + 3, 4920 }; 4921 4922 static const struct panel_desc toshiba_lt089ac29000 = { 4923 .modes = &toshiba_lt089ac29000_mode, 4924 .num_modes = 1, 4925 .size = { 4926 .width = 194, 4927 .height = 116, 4928 }, 4929 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4930 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4931 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4932 }; 4933 4934 static const struct drm_display_mode tpk_f07a_0102_mode = { 4935 .clock = 33260, 4936 .hdisplay = 800, 4937 .hsync_start = 800 + 40, 4938 .hsync_end = 800 + 40 + 128, 4939 .htotal = 800 + 40 + 128 + 88, 4940 .vdisplay = 480, 4941 .vsync_start = 480 + 10, 4942 .vsync_end = 480 + 10 + 2, 4943 .vtotal = 480 + 10 + 2 + 33, 4944 }; 4945 4946 static const struct panel_desc tpk_f07a_0102 = { 4947 .modes = &tpk_f07a_0102_mode, 4948 .num_modes = 1, 4949 .size = { 4950 .width = 152, 4951 .height = 91, 4952 }, 4953 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4954 }; 4955 4956 static const struct drm_display_mode tpk_f10a_0102_mode = { 4957 .clock = 45000, 4958 .hdisplay = 1024, 4959 .hsync_start = 1024 + 176, 4960 .hsync_end = 1024 + 176 + 5, 4961 .htotal = 1024 + 176 + 5 + 88, 4962 .vdisplay = 600, 4963 .vsync_start = 600 + 20, 4964 .vsync_end = 600 + 20 + 5, 4965 .vtotal = 600 + 20 + 5 + 25, 4966 }; 4967 4968 static const struct panel_desc tpk_f10a_0102 = { 4969 .modes = &tpk_f10a_0102_mode, 4970 .num_modes = 1, 4971 .size = { 4972 .width = 223, 4973 .height = 125, 4974 }, 4975 }; 4976 4977 static const struct display_timing urt_umsh_8596md_timing = { 4978 .pixelclock = { 33260000, 33260000, 33260000 }, 4979 .hactive = { 800, 800, 800 }, 4980 .hfront_porch = { 41, 41, 41 }, 4981 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4982 .hsync_len = { 71, 128, 128 }, 4983 .vactive = { 480, 480, 480 }, 4984 .vfront_porch = { 10, 10, 10 }, 4985 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4986 .vsync_len = { 2, 2, 2 }, 4987 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4988 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4989 }; 4990 4991 static const struct panel_desc urt_umsh_8596md_lvds = { 4992 .timings = &urt_umsh_8596md_timing, 4993 .num_timings = 1, 4994 .bpc = 6, 4995 .size = { 4996 .width = 152, 4997 .height = 91, 4998 }, 4999 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 5000 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5001 }; 5002 5003 static const struct panel_desc urt_umsh_8596md_parallel = { 5004 .timings = &urt_umsh_8596md_timing, 5005 .num_timings = 1, 5006 .bpc = 6, 5007 .size = { 5008 .width = 152, 5009 .height = 91, 5010 }, 5011 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 5012 }; 5013 5014 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 5015 .clock = 60000, 5016 .hdisplay = 1024, 5017 .hsync_start = 1024 + 160, 5018 .hsync_end = 1024 + 160 + 100, 5019 .htotal = 1024 + 160 + 100 + 60, 5020 .vdisplay = 600, 5021 .vsync_start = 600 + 12, 5022 .vsync_end = 600 + 12 + 10, 5023 .vtotal = 600 + 12 + 10 + 13, 5024 }; 5025 5026 static const struct panel_desc vivax_tpc9150_panel = { 5027 .modes = &vivax_tpc9150_panel_mode, 5028 .num_modes = 1, 5029 .bpc = 6, 5030 .size = { 5031 .width = 200, 5032 .height = 115, 5033 }, 5034 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 5035 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5036 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5037 }; 5038 5039 static const struct drm_display_mode vl050_8048nt_c01_mode = { 5040 .clock = 33333, 5041 .hdisplay = 800, 5042 .hsync_start = 800 + 210, 5043 .hsync_end = 800 + 210 + 20, 5044 .htotal = 800 + 210 + 20 + 46, 5045 .vdisplay = 480, 5046 .vsync_start = 480 + 22, 5047 .vsync_end = 480 + 22 + 10, 5048 .vtotal = 480 + 22 + 10 + 23, 5049 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5050 }; 5051 5052 static const struct panel_desc vl050_8048nt_c01 = { 5053 .modes = &vl050_8048nt_c01_mode, 5054 .num_modes = 1, 5055 .bpc = 8, 5056 .size = { 5057 .width = 120, 5058 .height = 76, 5059 }, 5060 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5061 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 5062 }; 5063 5064 static const struct drm_display_mode waveshare_133inch_mode = { 5065 .clock = 148500, 5066 .hdisplay = 1920, 5067 .hsync_start = 1920 + 88, 5068 .hsync_end = 1920 + 88 + 44, 5069 .htotal = 1920 + 88 + 44 + 148, 5070 .vdisplay = 1080, 5071 .vsync_start = 1080 + 4, 5072 .vsync_end = 1080 + 4 + 5, 5073 .vtotal = 1080 + 4 + 5 + 36, 5074 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5075 }; 5076 5077 static const struct panel_desc waveshare_133inch = { 5078 .modes = &waveshare_133inch_mode, 5079 .num_modes = 1, 5080 .bpc = 8, 5081 .size = { 5082 .width = 293, 5083 .height = 163, 5084 }, 5085 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5086 .connector_type = DRM_MODE_CONNECTOR_DPI, 5087 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5088 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5089 }; 5090 5091 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 5092 .clock = 6410, 5093 .hdisplay = 320, 5094 .hsync_start = 320 + 20, 5095 .hsync_end = 320 + 20 + 30, 5096 .htotal = 320 + 20 + 30 + 38, 5097 .vdisplay = 240, 5098 .vsync_start = 240 + 4, 5099 .vsync_end = 240 + 4 + 3, 5100 .vtotal = 240 + 4 + 3 + 15, 5101 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5102 }; 5103 5104 static const struct panel_desc winstar_wf35ltiacd = { 5105 .modes = &winstar_wf35ltiacd_mode, 5106 .num_modes = 1, 5107 .bpc = 8, 5108 .size = { 5109 .width = 70, 5110 .height = 53, 5111 }, 5112 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5113 }; 5114 5115 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 5116 .clock = 51200, 5117 .hdisplay = 1024, 5118 .hsync_start = 1024 + 100, 5119 .hsync_end = 1024 + 100 + 100, 5120 .htotal = 1024 + 100 + 100 + 120, 5121 .vdisplay = 600, 5122 .vsync_start = 600 + 10, 5123 .vsync_end = 600 + 10 + 10, 5124 .vtotal = 600 + 10 + 10 + 15, 5125 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 5126 }; 5127 5128 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 5129 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 5130 .num_modes = 1, 5131 .bpc = 8, 5132 .size = { 5133 .width = 154, 5134 .height = 90, 5135 }, 5136 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5137 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5138 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5139 }; 5140 5141 static const struct drm_display_mode mchp_ac69t88a_mode = { 5142 .clock = 25000, 5143 .hdisplay = 800, 5144 .hsync_start = 800 + 88, 5145 .hsync_end = 800 + 88 + 5, 5146 .htotal = 800 + 88 + 5 + 40, 5147 .vdisplay = 480, 5148 .vsync_start = 480 + 23, 5149 .vsync_end = 480 + 23 + 5, 5150 .vtotal = 480 + 23 + 5 + 1, 5151 }; 5152 5153 static const struct panel_desc mchp_ac69t88a = { 5154 .modes = &mchp_ac69t88a_mode, 5155 .num_modes = 1, 5156 .bpc = 8, 5157 .size = { 5158 .width = 108, 5159 .height = 65, 5160 }, 5161 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5162 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 5163 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5164 }; 5165 5166 static const struct drm_display_mode arm_rtsm_mode[] = { 5167 { 5168 .clock = 65000, 5169 .hdisplay = 1024, 5170 .hsync_start = 1024 + 24, 5171 .hsync_end = 1024 + 24 + 136, 5172 .htotal = 1024 + 24 + 136 + 160, 5173 .vdisplay = 768, 5174 .vsync_start = 768 + 3, 5175 .vsync_end = 768 + 3 + 6, 5176 .vtotal = 768 + 3 + 6 + 29, 5177 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5178 }, 5179 }; 5180 5181 static const struct panel_desc arm_rtsm = { 5182 .modes = arm_rtsm_mode, 5183 .num_modes = 1, 5184 .bpc = 8, 5185 .size = { 5186 .width = 400, 5187 .height = 300, 5188 }, 5189 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5190 }; 5191 5192 static const struct of_device_id platform_of_match[] = { 5193 { 5194 .compatible = "ampire,am-1280800n3tzqw-t00h", 5195 .data = &ire_am_1280800n3tzqw_t00h, 5196 }, { 5197 .compatible = "ampire,am-480272h3tmqw-t01h", 5198 .data = &ire_am_480272h3tmqw_t01h, 5199 }, { 5200 .compatible = "ampire,am-800480l1tmqw-t00h", 5201 .data = &ire_am_800480l1tmqw_t00h, 5202 }, { 5203 .compatible = "ampire,am800480r3tmqwa1h", 5204 .data = &ire_am800480r3tmqwa1h, 5205 }, { 5206 .compatible = "ampire,am800600p5tmqw-tb8h", 5207 .data = &ire_am800600p5tmqwtb8h, 5208 }, { 5209 .compatible = "arm,rtsm-display", 5210 .data = &arm_rtsm, 5211 }, { 5212 .compatible = "armadeus,st0700-adapt", 5213 .data = &armadeus_st0700_adapt, 5214 }, { 5215 .compatible = "auo,b101aw03", 5216 .data = &auo_b101aw03, 5217 }, { 5218 .compatible = "auo,b101xtn01", 5219 .data = &auo_b101xtn01, 5220 }, { 5221 .compatible = "auo,b116xw03", 5222 .data = &auo_b116xw03, 5223 }, { 5224 .compatible = "auo,g070vvn01", 5225 .data = &auo_g070vvn01, 5226 }, { 5227 .compatible = "auo,g101evn010", 5228 .data = &auo_g101evn010, 5229 }, { 5230 .compatible = "auo,g104sn02", 5231 .data = &auo_g104sn02, 5232 }, { 5233 .compatible = "auo,g104stn01", 5234 .data = &auo_g104stn01, 5235 }, { 5236 .compatible = "auo,g121ean01", 5237 .data = &auo_g121ean01, 5238 }, { 5239 .compatible = "auo,g133han01", 5240 .data = &auo_g133han01, 5241 }, { 5242 .compatible = "auo,g156han04", 5243 .data = &auo_g156han04, 5244 }, { 5245 .compatible = "auo,g156xtn01", 5246 .data = &auo_g156xtn01, 5247 }, { 5248 .compatible = "auo,g185han01", 5249 .data = &auo_g185han01, 5250 }, { 5251 .compatible = "auo,g190ean01", 5252 .data = &auo_g190ean01, 5253 }, { 5254 .compatible = "auo,p238han01", 5255 .data = &auo_p238han01, 5256 }, { 5257 .compatible = "auo,p320hvn03", 5258 .data = &auo_p320hvn03, 5259 }, { 5260 .compatible = "auo,t215hvn01", 5261 .data = &auo_t215hvn01, 5262 }, { 5263 .compatible = "avic,tm070ddh03", 5264 .data = &avic_tm070ddh03, 5265 }, { 5266 .compatible = "bananapi,s070wv20-ct16", 5267 .data = &bananapi_s070wv20_ct16, 5268 }, { 5269 .compatible = "boe,av101hdt-a10", 5270 .data = &boe_av101hdt_a10, 5271 }, { 5272 .compatible = "boe,av123z7m-n17", 5273 .data = &boe_av123z7m_n17, 5274 }, { 5275 .compatible = "boe,bp082wx1-100", 5276 .data = &boe_bp082wx1_100, 5277 }, { 5278 .compatible = "boe,bp101wx1-100", 5279 .data = &boe_bp101wx1_100, 5280 }, { 5281 .compatible = "boe,ev121wxm-n10-1850", 5282 .data = &boe_ev121wxm_n10_1850, 5283 }, { 5284 .compatible = "boe,hv070wsa-100", 5285 .data = &boe_hv070wsa 5286 }, { 5287 .compatible = "cct,cmt430b19n00", 5288 .data = &cct_cmt430b19n00, 5289 }, { 5290 .compatible = "cdtech,s043wq26h-ct7", 5291 .data = &cdtech_s043wq26h_ct7, 5292 }, { 5293 .compatible = "cdtech,s070pws19hp-fc21", 5294 .data = &cdtech_s070pws19hp_fc21, 5295 }, { 5296 .compatible = "cdtech,s070swv29hg-dc44", 5297 .data = &cdtech_s070swv29hg_dc44, 5298 }, { 5299 .compatible = "cdtech,s070wv95-ct16", 5300 .data = &cdtech_s070wv95_ct16, 5301 }, { 5302 .compatible = "chefree,ch101olhlwh-002", 5303 .data = &chefree_ch101olhlwh_002, 5304 }, { 5305 .compatible = "chunghwa,claa070wp03xg", 5306 .data = &chunghwa_claa070wp03xg, 5307 }, { 5308 .compatible = "chunghwa,claa101wa01a", 5309 .data = &chunghwa_claa101wa01a 5310 }, { 5311 .compatible = "chunghwa,claa101wb01", 5312 .data = &chunghwa_claa101wb01 5313 }, { 5314 .compatible = "dataimage,fg040346dsswbg04", 5315 .data = &dataimage_fg040346dsswbg04, 5316 }, { 5317 .compatible = "dataimage,fg1001l0dsswmg01", 5318 .data = &dataimage_fg1001l0dsswmg01, 5319 }, { 5320 .compatible = "dataimage,scf0700c48ggu18", 5321 .data = &dataimage_scf0700c48ggu18, 5322 }, { 5323 .compatible = "dlc,dlc0700yzg-1", 5324 .data = &dlc_dlc0700yzg_1, 5325 }, { 5326 .compatible = "dlc,dlc1010gig", 5327 .data = &dlc_dlc1010gig, 5328 }, { 5329 .compatible = "edt,et035012dm6", 5330 .data = &edt_et035012dm6, 5331 }, { 5332 .compatible = "edt,etm0350g0dh6", 5333 .data = &edt_etm0350g0dh6, 5334 }, { 5335 .compatible = "edt,etm043080dh6gp", 5336 .data = &edt_etm043080dh6gp, 5337 }, { 5338 .compatible = "edt,etm0430g0dh6", 5339 .data = &edt_etm0430g0dh6, 5340 }, { 5341 .compatible = "edt,et057023udba", 5342 .data = &edt_et057023udba, 5343 }, { 5344 .compatible = "edt,et057090dhu", 5345 .data = &edt_et057090dhu, 5346 }, { 5347 .compatible = "edt,et070080dh6", 5348 .data = &edt_etm0700g0dh6, 5349 }, { 5350 .compatible = "edt,etm0700g0dh6", 5351 .data = &edt_etm0700g0dh6, 5352 }, { 5353 .compatible = "edt,etm0700g0bdh6", 5354 .data = &edt_etm0700g0bdh6, 5355 }, { 5356 .compatible = "edt,etm0700g0edh6", 5357 .data = &edt_etm0700g0bdh6, 5358 }, { 5359 .compatible = "edt,etml0700y5dha", 5360 .data = &edt_etml0700y5dha, 5361 }, { 5362 .compatible = "edt,etml1010g3dra", 5363 .data = &edt_etml1010g3dra, 5364 }, { 5365 .compatible = "edt,etmv570g2dhu", 5366 .data = &edt_etmv570g2dhu, 5367 }, { 5368 .compatible = "eink,vb3300-kca", 5369 .data = &eink_vb3300_kca, 5370 }, { 5371 .compatible = "evervision,vgg644804", 5372 .data = &evervision_vgg644804, 5373 }, { 5374 .compatible = "evervision,vgg804821", 5375 .data = &evervision_vgg804821, 5376 }, { 5377 .compatible = "foxlink,fl500wvr00-a0t", 5378 .data = &foxlink_fl500wvr00_a0t, 5379 }, { 5380 .compatible = "frida,frd350h54004", 5381 .data = &frida_frd350h54004, 5382 }, { 5383 .compatible = "giantplus,gpg482739qs5", 5384 .data = &giantplus_gpg482739qs5 5385 }, { 5386 .compatible = "giantplus,gpm940b0", 5387 .data = &giantplus_gpm940b0, 5388 }, { 5389 .compatible = "hannstar,hsd070pww1", 5390 .data = &hannstar_hsd070pww1, 5391 }, { 5392 .compatible = "hannstar,hsd100pxn1", 5393 .data = &hannstar_hsd100pxn1, 5394 }, { 5395 .compatible = "hannstar,hsd101pww2", 5396 .data = &hannstar_hsd101pww2, 5397 }, { 5398 .compatible = "hannstar,hsd156juw2", 5399 .data = &hannstar_hsd156juw2, 5400 }, { 5401 .compatible = "hit,tx23d38vm0caa", 5402 .data = &hitachi_tx23d38vm0caa 5403 }, { 5404 .compatible = "innolux,at043tn24", 5405 .data = &innolux_at043tn24, 5406 }, { 5407 .compatible = "innolux,at070tn92", 5408 .data = &innolux_at070tn92, 5409 }, { 5410 .compatible = "innolux,g070ace-l01", 5411 .data = &innolux_g070ace_l01, 5412 }, { 5413 .compatible = "innolux,g070ace-lh3", 5414 .data = &innolux_g070ace_lh3, 5415 }, { 5416 .compatible = "innolux,g070y2-l01", 5417 .data = &innolux_g070y2_l01, 5418 }, { 5419 .compatible = "innolux,g070y2-t02", 5420 .data = &innolux_g070y2_t02, 5421 }, { 5422 .compatible = "innolux,g101ice-l01", 5423 .data = &innolux_g101ice_l01 5424 }, { 5425 .compatible = "innolux,g121i1-l01", 5426 .data = &innolux_g121i1_l01 5427 }, { 5428 .compatible = "innolux,g121x1-l03", 5429 .data = &innolux_g121x1_l03, 5430 }, { 5431 .compatible = "innolux,g121xce-l01", 5432 .data = &innolux_g121xce_l01, 5433 }, { 5434 .compatible = "innolux,g150xge-l05", 5435 .data = &innolux_g150xge_l05, 5436 }, { 5437 .compatible = "innolux,g156hce-l01", 5438 .data = &innolux_g156hce_l01, 5439 }, { 5440 .compatible = "innolux,n156bge-l21", 5441 .data = &innolux_n156bge_l21, 5442 }, { 5443 .compatible = "innolux,zj070na-01p", 5444 .data = &innolux_zj070na_01p, 5445 }, { 5446 .compatible = "jutouch,jt070tm041", 5447 .data = &jutouch_jt070tm041, 5448 }, { 5449 .compatible = "jutouch,jt101tm023", 5450 .data = &jutouch_jt101tm023, 5451 }, { 5452 .compatible = "koe,tx14d24vm1bpa", 5453 .data = &koe_tx14d24vm1bpa, 5454 }, { 5455 .compatible = "koe,tx26d202vm0bwa", 5456 .data = &koe_tx26d202vm0bwa, 5457 }, { 5458 .compatible = "koe,tx31d200vm0baa", 5459 .data = &koe_tx31d200vm0baa, 5460 }, { 5461 .compatible = "kyo,tcg121xglp", 5462 .data = &kyo_tcg121xglp, 5463 }, { 5464 .compatible = "lemaker,bl035-rgb-002", 5465 .data = &lemaker_bl035_rgb_002, 5466 }, { 5467 .compatible = "lg,lb070wv8", 5468 .data = &lg_lb070wv8, 5469 }, { 5470 .compatible = "lincolntech,lcd185-101ct", 5471 .data = &lincolntech_lcd185_101ct, 5472 }, { 5473 .compatible = "logicpd,type28", 5474 .data = &logicpd_type_28, 5475 }, { 5476 .compatible = "logictechno,lt161010-2nhc", 5477 .data = &logictechno_lt161010_2nh, 5478 }, { 5479 .compatible = "logictechno,lt161010-2nhr", 5480 .data = &logictechno_lt161010_2nh, 5481 }, { 5482 .compatible = "logictechno,lt170410-2whc", 5483 .data = &logictechno_lt170410_2whc, 5484 }, { 5485 .compatible = "logictechno,lttd800480070-l2rt", 5486 .data = &logictechno_lttd800480070_l2rt, 5487 }, { 5488 .compatible = "logictechno,lttd800480070-l6wh-rt", 5489 .data = &logictechno_lttd800480070_l6wh_rt, 5490 }, { 5491 .compatible = "microtips,mf-101hiebcaf0", 5492 .data = µtips_mf_101hiebcaf0_c, 5493 }, { 5494 .compatible = "microtips,mf-103hieb0ga0", 5495 .data = µtips_mf_103hieb0ga0, 5496 }, { 5497 .compatible = "mitsubishi,aa070mc01-ca1", 5498 .data = &mitsubishi_aa070mc01, 5499 }, { 5500 .compatible = "mitsubishi,aa084xe01", 5501 .data = &mitsubishi_aa084xe01, 5502 }, { 5503 .compatible = "multi-inno,mi0700a2t-30", 5504 .data = &multi_inno_mi0700a2t_30, 5505 }, { 5506 .compatible = "multi-inno,mi0700s4t-6", 5507 .data = &multi_inno_mi0700s4t_6, 5508 }, { 5509 .compatible = "multi-inno,mi0800ft-9", 5510 .data = &multi_inno_mi0800ft_9, 5511 }, { 5512 .compatible = "multi-inno,mi1010ait-1cp", 5513 .data = &multi_inno_mi1010ait_1cp, 5514 }, { 5515 .compatible = "multi-inno,mi1010z1t-1cp11", 5516 .data = &multi_inno_mi1010z1t_1cp11, 5517 }, { 5518 .compatible = "nec,nl12880bc20-05", 5519 .data = &nec_nl12880bc20_05, 5520 }, { 5521 .compatible = "nec,nl4827hc19-05b", 5522 .data = &nec_nl4827hc19_05b, 5523 }, { 5524 .compatible = "netron-dy,e231732", 5525 .data = &netron_dy_e231732, 5526 }, { 5527 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 5528 .data = &newhaven_nhd_43_480272ef_atxl, 5529 }, { 5530 .compatible = "nlt,nl13676bc25-03f", 5531 .data = &nlt_nl13676bc25_03f, 5532 }, { 5533 .compatible = "nlt,nl192108ac18-02d", 5534 .data = &nlt_nl192108ac18_02d, 5535 }, { 5536 .compatible = "nvd,9128", 5537 .data = &nvd_9128, 5538 }, { 5539 .compatible = "okaya,rs800480t-7x0gp", 5540 .data = &okaya_rs800480t_7x0gp, 5541 }, { 5542 .compatible = "olimex,lcd-olinuxino-43-ts", 5543 .data = &olimex_lcd_olinuxino_43ts, 5544 }, { 5545 .compatible = "olimex,lcd-olinuxino-5-cts", 5546 .data = &olimex_lcd_olinuxino_5cts, 5547 }, { 5548 .compatible = "ontat,kd50g21-40nt-a1", 5549 .data = &ontat_kd50g21_40nt_a1, 5550 }, { 5551 .compatible = "ontat,yx700wv03", 5552 .data = &ontat_yx700wv03, 5553 }, { 5554 .compatible = "ortustech,com37h3m05dtc", 5555 .data = &ortustech_com37h3m, 5556 }, { 5557 .compatible = "ortustech,com37h3m99dtc", 5558 .data = &ortustech_com37h3m, 5559 }, { 5560 .compatible = "ortustech,com43h4m85ulc", 5561 .data = &ortustech_com43h4m85ulc, 5562 }, { 5563 .compatible = "osddisplays,osd070t1718-19ts", 5564 .data = &osddisplays_osd070t1718_19ts, 5565 }, { 5566 .compatible = "pda,91-00156-a0", 5567 .data = &pda_91_00156_a0, 5568 }, { 5569 .compatible = "powertip,ph128800t004-zza01", 5570 .data = &powertip_ph128800t004_zza01, 5571 }, { 5572 .compatible = "powertip,ph128800t006-zhc01", 5573 .data = &powertip_ph128800t006_zhc01, 5574 }, { 5575 .compatible = "powertip,ph800480t013-idf02", 5576 .data = &powertip_ph800480t013_idf02, 5577 }, { 5578 .compatible = "powertip,ph800480t032-zhc19", 5579 .data = &powertip_ph800480t032_zhc19, 5580 }, { 5581 .compatible = "primeview,pm070wl4", 5582 .data = &primeview_pm070wl4, 5583 }, { 5584 .compatible = "qiaodian,qd43003c0-40", 5585 .data = &qd43003c0_40, 5586 }, { 5587 .compatible = "qishenglong,gopher2b-lcd", 5588 .data = &qishenglong_gopher2b_lcd, 5589 }, { 5590 .compatible = "raystar,rff500f-awh-dnn", 5591 .data = &raystar_rff500f_awh_dnn, 5592 }, { 5593 .compatible = "rocktech,rk043fn48h", 5594 .data = &rocktech_rk043fn48h, 5595 }, { 5596 .compatible = "rocktech,rk070er9427", 5597 .data = &rocktech_rk070er9427, 5598 }, { 5599 .compatible = "rocktech,rk101ii01d-ct", 5600 .data = &rocktech_rk101ii01d_ct, 5601 }, { 5602 .compatible = "samsung,ltl101al01", 5603 .data = &samsung_ltl101al01, 5604 }, { 5605 .compatible = "samsung,ltl106al01", 5606 .data = &samsung_ltl106al01, 5607 }, { 5608 .compatible = "samsung,ltn101nt05", 5609 .data = &samsung_ltn101nt05, 5610 }, { 5611 .compatible = "satoz,sat050at40h12r2", 5612 .data = &satoz_sat050at40h12r2, 5613 }, { 5614 .compatible = "sharp,lq035q7db03", 5615 .data = &sharp_lq035q7db03, 5616 }, { 5617 .compatible = "sharp,lq070y3dg3b", 5618 .data = &sharp_lq070y3dg3b, 5619 }, { 5620 .compatible = "sharp,lq101k1ly04", 5621 .data = &sharp_lq101k1ly04, 5622 }, { 5623 .compatible = "sharp,ls020b1dd01d", 5624 .data = &sharp_ls020b1dd01d, 5625 }, { 5626 .compatible = "shelly,sca07010-bfn-lnn", 5627 .data = &shelly_sca07010_bfn_lnn, 5628 }, { 5629 .compatible = "starry,kr070pe2t", 5630 .data = &starry_kr070pe2t, 5631 }, { 5632 .compatible = "startek,kd070wvfpa", 5633 .data = &startek_kd070wvfpa, 5634 }, { 5635 .compatible = "team-source-display,tst043015cmhx", 5636 .data = &tsd_tst043015cmhx, 5637 }, { 5638 .compatible = "tfc,s9700rtwv43tr-01b", 5639 .data = &tfc_s9700rtwv43tr_01b, 5640 }, { 5641 .compatible = "tianma,p0700wxf1mbaa", 5642 .data = &tianma_p0700wxf1mbaa, 5643 }, { 5644 .compatible = "tianma,tm050rdh03", 5645 .data = &ontat_kd50g21_40nt_a1, 5646 }, { 5647 .compatible = "tianma,tm070jdhg30", 5648 .data = &tianma_tm070jdhg30, 5649 }, { 5650 .compatible = "tianma,tm070jdhg34-00", 5651 .data = &tianma_tm070jdhg34_00, 5652 }, { 5653 .compatible = "tianma,tm070jvhg33", 5654 .data = &tianma_tm070jvhg33, 5655 }, { 5656 .compatible = "tianma,tm070rvhg71", 5657 .data = &tianma_tm070rvhg71, 5658 }, { 5659 .compatible = "ti,nspire-cx-lcd-panel", 5660 .data = &ti_nspire_cx_lcd_panel, 5661 }, { 5662 .compatible = "ti,nspire-classic-lcd-panel", 5663 .data = &ti_nspire_classic_lcd_panel, 5664 }, { 5665 .compatible = "toshiba,lt089ac29000", 5666 .data = &toshiba_lt089ac29000, 5667 }, { 5668 .compatible = "topland,tian-g07017-01", 5669 .data = &topland_tian_g07017_01, 5670 }, { 5671 .compatible = "tpk,f07a-0102", 5672 .data = &tpk_f07a_0102, 5673 }, { 5674 .compatible = "tpk,f10a-0102", 5675 .data = &tpk_f10a_0102, 5676 }, { 5677 .compatible = "urt,umsh-8596md-t", 5678 .data = &urt_umsh_8596md_parallel, 5679 }, { 5680 .compatible = "urt,umsh-8596md-1t", 5681 .data = &urt_umsh_8596md_parallel, 5682 }, { 5683 .compatible = "urt,umsh-8596md-7t", 5684 .data = &urt_umsh_8596md_parallel, 5685 }, { 5686 .compatible = "urt,umsh-8596md-11t", 5687 .data = &urt_umsh_8596md_lvds, 5688 }, { 5689 .compatible = "urt,umsh-8596md-19t", 5690 .data = &urt_umsh_8596md_lvds, 5691 }, { 5692 .compatible = "urt,umsh-8596md-20t", 5693 .data = &urt_umsh_8596md_parallel, 5694 }, { 5695 .compatible = "vivax,tpc9150-panel", 5696 .data = &vivax_tpc9150_panel, 5697 }, { 5698 .compatible = "vxt,vl050-8048nt-c01", 5699 .data = &vl050_8048nt_c01, 5700 }, { 5701 .compatible = "waveshare,13.3inch-panel", 5702 .data = &waveshare_133inch, 5703 }, { 5704 .compatible = "winstar,wf35ltiacd", 5705 .data = &winstar_wf35ltiacd, 5706 }, { 5707 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 5708 .data = &yes_optoelectronics_ytc700tlag_05_201c, 5709 }, { 5710 .compatible = "microchip,ac69t88a", 5711 .data = &mchp_ac69t88a, 5712 }, { 5713 /* Must be the last entry */ 5714 .compatible = "panel-dpi", 5715 5716 /* 5717 * Explicitly NULL, the panel_desc structure will be 5718 * allocated by panel_dpi_probe(). 5719 */ 5720 .data = NULL, 5721 }, { 5722 /* sentinel */ 5723 } 5724 }; 5725 MODULE_DEVICE_TABLE(of, platform_of_match); 5726 5727 static int panel_simple_platform_probe(struct platform_device *pdev) 5728 { 5729 struct panel_simple *panel; 5730 5731 panel = panel_simple_probe(&pdev->dev); 5732 if (IS_ERR(panel)) 5733 return PTR_ERR(panel); 5734 5735 return 0; 5736 } 5737 5738 static void panel_simple_platform_remove(struct platform_device *pdev) 5739 { 5740 panel_simple_remove(&pdev->dev); 5741 } 5742 5743 static void panel_simple_platform_shutdown(struct platform_device *pdev) 5744 { 5745 panel_simple_shutdown(&pdev->dev); 5746 } 5747 5748 static const struct dev_pm_ops panel_simple_pm_ops = { 5749 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 5750 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5751 pm_runtime_force_resume) 5752 }; 5753 5754 static struct platform_driver panel_simple_platform_driver = { 5755 .driver = { 5756 .name = "panel-simple", 5757 .of_match_table = platform_of_match, 5758 .pm = &panel_simple_pm_ops, 5759 }, 5760 .probe = panel_simple_platform_probe, 5761 .remove = panel_simple_platform_remove, 5762 .shutdown = panel_simple_platform_shutdown, 5763 }; 5764 5765 static const struct drm_display_mode auo_b080uan01_mode = { 5766 .clock = 154500, 5767 .hdisplay = 1200, 5768 .hsync_start = 1200 + 62, 5769 .hsync_end = 1200 + 62 + 4, 5770 .htotal = 1200 + 62 + 4 + 62, 5771 .vdisplay = 1920, 5772 .vsync_start = 1920 + 9, 5773 .vsync_end = 1920 + 9 + 2, 5774 .vtotal = 1920 + 9 + 2 + 8, 5775 }; 5776 5777 static const struct panel_desc_dsi auo_b080uan01 = { 5778 .desc = { 5779 .modes = &auo_b080uan01_mode, 5780 .num_modes = 1, 5781 .bpc = 8, 5782 .size = { 5783 .width = 108, 5784 .height = 272, 5785 }, 5786 .connector_type = DRM_MODE_CONNECTOR_DSI, 5787 }, 5788 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5789 .format = MIPI_DSI_FMT_RGB888, 5790 .lanes = 4, 5791 }; 5792 5793 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 5794 .clock = 160000, 5795 .hdisplay = 1200, 5796 .hsync_start = 1200 + 120, 5797 .hsync_end = 1200 + 120 + 20, 5798 .htotal = 1200 + 120 + 20 + 21, 5799 .vdisplay = 1920, 5800 .vsync_start = 1920 + 21, 5801 .vsync_end = 1920 + 21 + 3, 5802 .vtotal = 1920 + 21 + 3 + 18, 5803 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5804 }; 5805 5806 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 5807 .desc = { 5808 .modes = &boe_tv080wum_nl0_mode, 5809 .num_modes = 1, 5810 .size = { 5811 .width = 107, 5812 .height = 172, 5813 }, 5814 .connector_type = DRM_MODE_CONNECTOR_DSI, 5815 }, 5816 .flags = MIPI_DSI_MODE_VIDEO | 5817 MIPI_DSI_MODE_VIDEO_BURST | 5818 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 5819 .format = MIPI_DSI_FMT_RGB888, 5820 .lanes = 4, 5821 }; 5822 5823 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 5824 .clock = 67000, 5825 .hdisplay = 720, 5826 .hsync_start = 720 + 12, 5827 .hsync_end = 720 + 12 + 4, 5828 .htotal = 720 + 12 + 4 + 112, 5829 .vdisplay = 1280, 5830 .vsync_start = 1280 + 8, 5831 .vsync_end = 1280 + 8 + 4, 5832 .vtotal = 1280 + 8 + 4 + 12, 5833 }; 5834 5835 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 5836 .desc = { 5837 .modes = &lg_lh500wx1_sd03_mode, 5838 .num_modes = 1, 5839 .bpc = 8, 5840 .size = { 5841 .width = 62, 5842 .height = 110, 5843 }, 5844 .connector_type = DRM_MODE_CONNECTOR_DSI, 5845 }, 5846 .flags = MIPI_DSI_MODE_VIDEO, 5847 .format = MIPI_DSI_FMT_RGB888, 5848 .lanes = 4, 5849 }; 5850 5851 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5852 .clock = 157200, 5853 .hdisplay = 1920, 5854 .hsync_start = 1920 + 154, 5855 .hsync_end = 1920 + 154 + 16, 5856 .htotal = 1920 + 154 + 16 + 32, 5857 .vdisplay = 1200, 5858 .vsync_start = 1200 + 17, 5859 .vsync_end = 1200 + 17 + 2, 5860 .vtotal = 1200 + 17 + 2 + 16, 5861 }; 5862 5863 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5864 .desc = { 5865 .modes = &panasonic_vvx10f004b00_mode, 5866 .num_modes = 1, 5867 .bpc = 8, 5868 .size = { 5869 .width = 217, 5870 .height = 136, 5871 }, 5872 .connector_type = DRM_MODE_CONNECTOR_DSI, 5873 }, 5874 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5875 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5876 .format = MIPI_DSI_FMT_RGB888, 5877 .lanes = 4, 5878 }; 5879 5880 static const struct drm_display_mode lg_acx467akm_7_mode = { 5881 .clock = 150000, 5882 .hdisplay = 1080, 5883 .hsync_start = 1080 + 2, 5884 .hsync_end = 1080 + 2 + 2, 5885 .htotal = 1080 + 2 + 2 + 2, 5886 .vdisplay = 1920, 5887 .vsync_start = 1920 + 2, 5888 .vsync_end = 1920 + 2 + 2, 5889 .vtotal = 1920 + 2 + 2 + 2, 5890 }; 5891 5892 static const struct panel_desc_dsi lg_acx467akm_7 = { 5893 .desc = { 5894 .modes = &lg_acx467akm_7_mode, 5895 .num_modes = 1, 5896 .bpc = 8, 5897 .size = { 5898 .width = 62, 5899 .height = 110, 5900 }, 5901 .connector_type = DRM_MODE_CONNECTOR_DSI, 5902 }, 5903 .flags = 0, 5904 .format = MIPI_DSI_FMT_RGB888, 5905 .lanes = 4, 5906 }; 5907 5908 static const struct drm_display_mode osd101t2045_53ts_mode = { 5909 .clock = 154500, 5910 .hdisplay = 1920, 5911 .hsync_start = 1920 + 112, 5912 .hsync_end = 1920 + 112 + 16, 5913 .htotal = 1920 + 112 + 16 + 32, 5914 .vdisplay = 1200, 5915 .vsync_start = 1200 + 16, 5916 .vsync_end = 1200 + 16 + 2, 5917 .vtotal = 1200 + 16 + 2 + 16, 5918 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5919 }; 5920 5921 static const struct panel_desc_dsi osd101t2045_53ts = { 5922 .desc = { 5923 .modes = &osd101t2045_53ts_mode, 5924 .num_modes = 1, 5925 .bpc = 8, 5926 .size = { 5927 .width = 217, 5928 .height = 136, 5929 }, 5930 .connector_type = DRM_MODE_CONNECTOR_DSI, 5931 }, 5932 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5933 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5934 MIPI_DSI_MODE_NO_EOT_PACKET, 5935 .format = MIPI_DSI_FMT_RGB888, 5936 .lanes = 4, 5937 }; 5938 5939 static const struct of_device_id dsi_of_match[] = { 5940 { 5941 .compatible = "auo,b080uan01", 5942 .data = &auo_b080uan01 5943 }, { 5944 .compatible = "boe,tv080wum-nl0", 5945 .data = &boe_tv080wum_nl0 5946 }, { 5947 .compatible = "lg,lh500wx1-sd03", 5948 .data = &lg_lh500wx1_sd03 5949 }, { 5950 .compatible = "panasonic,vvx10f004b00", 5951 .data = &panasonic_vvx10f004b00 5952 }, { 5953 .compatible = "lg,acx467akm-7", 5954 .data = &lg_acx467akm_7 5955 }, { 5956 .compatible = "osddisplays,osd101t2045-53ts", 5957 .data = &osd101t2045_53ts 5958 }, { 5959 /* sentinel */ 5960 } 5961 }; 5962 MODULE_DEVICE_TABLE(of, dsi_of_match); 5963 5964 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5965 { 5966 const struct panel_desc_dsi *desc; 5967 struct panel_simple *panel; 5968 int err; 5969 5970 panel = panel_simple_probe(&dsi->dev); 5971 if (IS_ERR(panel)) 5972 return PTR_ERR(panel); 5973 5974 desc = container_of(panel->desc, struct panel_desc_dsi, desc); 5975 dsi->mode_flags = desc->flags; 5976 dsi->format = desc->format; 5977 dsi->lanes = desc->lanes; 5978 5979 err = mipi_dsi_attach(dsi); 5980 if (err) { 5981 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5982 5983 drm_panel_remove(&panel->base); 5984 } 5985 5986 return err; 5987 } 5988 5989 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5990 { 5991 int err; 5992 5993 err = mipi_dsi_detach(dsi); 5994 if (err < 0) 5995 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5996 5997 panel_simple_remove(&dsi->dev); 5998 } 5999 6000 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 6001 { 6002 panel_simple_shutdown(&dsi->dev); 6003 } 6004 6005 static struct mipi_dsi_driver panel_simple_dsi_driver = { 6006 .driver = { 6007 .name = "panel-simple-dsi", 6008 .of_match_table = dsi_of_match, 6009 .pm = &panel_simple_pm_ops, 6010 }, 6011 .probe = panel_simple_dsi_probe, 6012 .remove = panel_simple_dsi_remove, 6013 .shutdown = panel_simple_dsi_shutdown, 6014 }; 6015 6016 static int __init panel_simple_init(void) 6017 { 6018 int err; 6019 6020 err = platform_driver_register(&panel_simple_platform_driver); 6021 if (err < 0) 6022 return err; 6023 6024 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 6025 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 6026 if (err < 0) 6027 goto err_did_platform_register; 6028 } 6029 6030 return 0; 6031 6032 err_did_platform_register: 6033 platform_driver_unregister(&panel_simple_platform_driver); 6034 6035 return err; 6036 } 6037 module_init(panel_simple_init); 6038 6039 static void __exit panel_simple_exit(void) 6040 { 6041 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 6042 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 6043 6044 platform_driver_unregister(&panel_simple_platform_driver); 6045 } 6046 module_exit(panel_simple_exit); 6047 6048 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 6049 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 6050 MODULE_LICENSE("GPL and additional rights"); 6051