xref: /linux/drivers/mfd/palmas.c (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * TI Palmas MFD Driver
4  *
5  * Copyright 2011-2012 Texas Instruments Inc.
6  *
7  * Author: Graeme Gregory <gg@slimlogic.co.uk>
8  */
9 
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/i2c.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/regmap.h>
18 #include <linux/err.h>
19 #include <linux/mfd/core.h>
20 #include <linux/mfd/palmas.h>
21 #include <linux/of.h>
22 #include <linux/of_platform.h>
23 
24 static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
25 	{
26 		.reg_bits = 8,
27 		.val_bits = 8,
28 		.max_register = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
29 					PALMAS_PRIMARY_SECONDARY_PAD3),
30 	},
31 	{
32 		.reg_bits = 8,
33 		.val_bits = 8,
34 		.max_register = PALMAS_BASE_TO_REG(PALMAS_GPADC_BASE,
35 					PALMAS_GPADC_SMPS_VSEL_MONITORING),
36 	},
37 	{
38 		.reg_bits = 8,
39 		.val_bits = 8,
40 		.max_register = PALMAS_BASE_TO_REG(PALMAS_TRIM_GPADC_BASE,
41 					PALMAS_GPADC_TRIM16),
42 	},
43 };
44 
45 static const struct regmap_irq tps65917_irqs[] = {
46 	/* INT1 IRQs */
47 	[TPS65917_RESERVED1] = {
48 		.mask = TPS65917_RESERVED,
49 	},
50 	[TPS65917_PWRON_IRQ] = {
51 		.mask = TPS65917_INT1_STATUS_PWRON,
52 	},
53 	[TPS65917_LONG_PRESS_KEY_IRQ] = {
54 		.mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
55 	},
56 	[TPS65917_RESERVED2] = {
57 		.mask = TPS65917_RESERVED,
58 	},
59 	[TPS65917_PWRDOWN_IRQ] = {
60 		.mask = TPS65917_INT1_STATUS_PWRDOWN,
61 	},
62 	[TPS65917_HOTDIE_IRQ] = {
63 		.mask = TPS65917_INT1_STATUS_HOTDIE,
64 	},
65 	[TPS65917_VSYS_MON_IRQ] = {
66 		.mask = TPS65917_INT1_STATUS_VSYS_MON,
67 	},
68 	[TPS65917_RESERVED3] = {
69 		.mask = TPS65917_RESERVED,
70 	},
71 	/* INT2 IRQs*/
72 	[TPS65917_RESERVED4] = {
73 		.mask = TPS65917_RESERVED,
74 		.reg_offset = 1,
75 	},
76 	[TPS65917_OTP_ERROR_IRQ] = {
77 		.mask = TPS65917_INT2_STATUS_OTP_ERROR,
78 		.reg_offset = 1,
79 	},
80 	[TPS65917_WDT_IRQ] = {
81 		.mask = TPS65917_INT2_STATUS_WDT,
82 		.reg_offset = 1,
83 	},
84 	[TPS65917_RESERVED5] = {
85 		.mask = TPS65917_RESERVED,
86 		.reg_offset = 1,
87 	},
88 	[TPS65917_RESET_IN_IRQ] = {
89 		.mask = TPS65917_INT2_STATUS_RESET_IN,
90 		.reg_offset = 1,
91 	},
92 	[TPS65917_FSD_IRQ] = {
93 		.mask = TPS65917_INT2_STATUS_FSD,
94 		.reg_offset = 1,
95 	},
96 	[TPS65917_SHORT_IRQ] = {
97 		.mask = TPS65917_INT2_STATUS_SHORT,
98 		.reg_offset = 1,
99 	},
100 	[TPS65917_RESERVED6] = {
101 		.mask = TPS65917_RESERVED,
102 		.reg_offset = 1,
103 	},
104 	/* INT3 IRQs */
105 	[TPS65917_GPADC_AUTO_0_IRQ] = {
106 		.mask = TPS65917_INT3_STATUS_GPADC_AUTO_0,
107 		.reg_offset = 2,
108 	},
109 	[TPS65917_GPADC_AUTO_1_IRQ] = {
110 		.mask = TPS65917_INT3_STATUS_GPADC_AUTO_1,
111 		.reg_offset = 2,
112 	},
113 	[TPS65917_GPADC_EOC_SW_IRQ] = {
114 		.mask = TPS65917_INT3_STATUS_GPADC_EOC_SW,
115 		.reg_offset = 2,
116 	},
117 	[TPS65917_RESREVED6] = {
118 		.mask = TPS65917_RESERVED6,
119 		.reg_offset = 2,
120 	},
121 	[TPS65917_RESERVED7] = {
122 		.mask = TPS65917_RESERVED,
123 		.reg_offset = 2,
124 	},
125 	[TPS65917_RESERVED8] = {
126 		.mask = TPS65917_RESERVED,
127 		.reg_offset = 2,
128 	},
129 	[TPS65917_RESERVED9] = {
130 		.mask = TPS65917_RESERVED,
131 		.reg_offset = 2,
132 	},
133 	[TPS65917_VBUS_IRQ] = {
134 		.mask = TPS65917_INT3_STATUS_VBUS,
135 		.reg_offset = 2,
136 	},
137 	/* INT4 IRQs */
138 	[TPS65917_GPIO_0_IRQ] = {
139 		.mask = TPS65917_INT4_STATUS_GPIO_0,
140 		.reg_offset = 3,
141 	},
142 	[TPS65917_GPIO_1_IRQ] = {
143 		.mask = TPS65917_INT4_STATUS_GPIO_1,
144 		.reg_offset = 3,
145 	},
146 	[TPS65917_GPIO_2_IRQ] = {
147 		.mask = TPS65917_INT4_STATUS_GPIO_2,
148 		.reg_offset = 3,
149 	},
150 	[TPS65917_GPIO_3_IRQ] = {
151 		.mask = TPS65917_INT4_STATUS_GPIO_3,
152 		.reg_offset = 3,
153 	},
154 	[TPS65917_GPIO_4_IRQ] = {
155 		.mask = TPS65917_INT4_STATUS_GPIO_4,
156 		.reg_offset = 3,
157 	},
158 	[TPS65917_GPIO_5_IRQ] = {
159 		.mask = TPS65917_INT4_STATUS_GPIO_5,
160 		.reg_offset = 3,
161 	},
162 	[TPS65917_GPIO_6_IRQ] = {
163 		.mask = TPS65917_INT4_STATUS_GPIO_6,
164 		.reg_offset = 3,
165 	},
166 	[TPS65917_RESERVED10] = {
167 		.mask = TPS65917_RESERVED10,
168 		.reg_offset = 3,
169 	},
170 };
171 
172 static const struct regmap_irq palmas_irqs[] = {
173 	/* INT1 IRQs */
174 	[PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = {
175 		.mask = PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV,
176 	},
177 	[PALMAS_PWRON_IRQ] = {
178 		.mask = PALMAS_INT1_STATUS_PWRON,
179 	},
180 	[PALMAS_LONG_PRESS_KEY_IRQ] = {
181 		.mask = PALMAS_INT1_STATUS_LONG_PRESS_KEY,
182 	},
183 	[PALMAS_RPWRON_IRQ] = {
184 		.mask = PALMAS_INT1_STATUS_RPWRON,
185 	},
186 	[PALMAS_PWRDOWN_IRQ] = {
187 		.mask = PALMAS_INT1_STATUS_PWRDOWN,
188 	},
189 	[PALMAS_HOTDIE_IRQ] = {
190 		.mask = PALMAS_INT1_STATUS_HOTDIE,
191 	},
192 	[PALMAS_VSYS_MON_IRQ] = {
193 		.mask = PALMAS_INT1_STATUS_VSYS_MON,
194 	},
195 	[PALMAS_VBAT_MON_IRQ] = {
196 		.mask = PALMAS_INT1_STATUS_VBAT_MON,
197 	},
198 	/* INT2 IRQs*/
199 	[PALMAS_RTC_ALARM_IRQ] = {
200 		.mask = PALMAS_INT2_STATUS_RTC_ALARM,
201 		.reg_offset = 1,
202 	},
203 	[PALMAS_RTC_TIMER_IRQ] = {
204 		.mask = PALMAS_INT2_STATUS_RTC_TIMER,
205 		.reg_offset = 1,
206 	},
207 	[PALMAS_WDT_IRQ] = {
208 		.mask = PALMAS_INT2_STATUS_WDT,
209 		.reg_offset = 1,
210 	},
211 	[PALMAS_BATREMOVAL_IRQ] = {
212 		.mask = PALMAS_INT2_STATUS_BATREMOVAL,
213 		.reg_offset = 1,
214 	},
215 	[PALMAS_RESET_IN_IRQ] = {
216 		.mask = PALMAS_INT2_STATUS_RESET_IN,
217 		.reg_offset = 1,
218 	},
219 	[PALMAS_FBI_BB_IRQ] = {
220 		.mask = PALMAS_INT2_STATUS_FBI_BB,
221 		.reg_offset = 1,
222 	},
223 	[PALMAS_SHORT_IRQ] = {
224 		.mask = PALMAS_INT2_STATUS_SHORT,
225 		.reg_offset = 1,
226 	},
227 	[PALMAS_VAC_ACOK_IRQ] = {
228 		.mask = PALMAS_INT2_STATUS_VAC_ACOK,
229 		.reg_offset = 1,
230 	},
231 	/* INT3 IRQs */
232 	[PALMAS_GPADC_AUTO_0_IRQ] = {
233 		.mask = PALMAS_INT3_STATUS_GPADC_AUTO_0,
234 		.reg_offset = 2,
235 	},
236 	[PALMAS_GPADC_AUTO_1_IRQ] = {
237 		.mask = PALMAS_INT3_STATUS_GPADC_AUTO_1,
238 		.reg_offset = 2,
239 	},
240 	[PALMAS_GPADC_EOC_SW_IRQ] = {
241 		.mask = PALMAS_INT3_STATUS_GPADC_EOC_SW,
242 		.reg_offset = 2,
243 	},
244 	[PALMAS_GPADC_EOC_RT_IRQ] = {
245 		.mask = PALMAS_INT3_STATUS_GPADC_EOC_RT,
246 		.reg_offset = 2,
247 	},
248 	[PALMAS_ID_OTG_IRQ] = {
249 		.mask = PALMAS_INT3_STATUS_ID_OTG,
250 		.reg_offset = 2,
251 	},
252 	[PALMAS_ID_IRQ] = {
253 		.mask = PALMAS_INT3_STATUS_ID,
254 		.reg_offset = 2,
255 	},
256 	[PALMAS_VBUS_OTG_IRQ] = {
257 		.mask = PALMAS_INT3_STATUS_VBUS_OTG,
258 		.reg_offset = 2,
259 	},
260 	[PALMAS_VBUS_IRQ] = {
261 		.mask = PALMAS_INT3_STATUS_VBUS,
262 		.reg_offset = 2,
263 	},
264 	/* INT4 IRQs */
265 	[PALMAS_GPIO_0_IRQ] = {
266 		.mask = PALMAS_INT4_STATUS_GPIO_0,
267 		.reg_offset = 3,
268 	},
269 	[PALMAS_GPIO_1_IRQ] = {
270 		.mask = PALMAS_INT4_STATUS_GPIO_1,
271 		.reg_offset = 3,
272 	},
273 	[PALMAS_GPIO_2_IRQ] = {
274 		.mask = PALMAS_INT4_STATUS_GPIO_2,
275 		.reg_offset = 3,
276 	},
277 	[PALMAS_GPIO_3_IRQ] = {
278 		.mask = PALMAS_INT4_STATUS_GPIO_3,
279 		.reg_offset = 3,
280 	},
281 	[PALMAS_GPIO_4_IRQ] = {
282 		.mask = PALMAS_INT4_STATUS_GPIO_4,
283 		.reg_offset = 3,
284 	},
285 	[PALMAS_GPIO_5_IRQ] = {
286 		.mask = PALMAS_INT4_STATUS_GPIO_5,
287 		.reg_offset = 3,
288 	},
289 	[PALMAS_GPIO_6_IRQ] = {
290 		.mask = PALMAS_INT4_STATUS_GPIO_6,
291 		.reg_offset = 3,
292 	},
293 	[PALMAS_GPIO_7_IRQ] = {
294 		.mask = PALMAS_INT4_STATUS_GPIO_7,
295 		.reg_offset = 3,
296 	},
297 };
298 
299 static const struct regmap_irq_chip palmas_irq_chip = {
300 	.name = "palmas",
301 	.irqs = palmas_irqs,
302 	.num_irqs = ARRAY_SIZE(palmas_irqs),
303 
304 	.num_regs = 4,
305 	.irq_reg_stride = 5,
306 	.status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
307 			PALMAS_INT1_STATUS),
308 	.mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
309 			PALMAS_INT1_MASK),
310 };
311 
312 static const struct regmap_irq_chip tps65917_irq_chip = {
313 	.name = "tps65917",
314 	.irqs = tps65917_irqs,
315 	.num_irqs = ARRAY_SIZE(tps65917_irqs),
316 
317 	.num_regs = 4,
318 	.irq_reg_stride = 5,
319 	.status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
320 			PALMAS_INT1_STATUS),
321 	.mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
322 			PALMAS_INT1_MASK),
323 };
324 
palmas_ext_control_req_config(struct palmas * palmas,enum palmas_external_requestor_id id,int ext_ctrl,bool enable)325 int palmas_ext_control_req_config(struct palmas *palmas,
326 	enum palmas_external_requestor_id id,  int ext_ctrl, bool enable)
327 {
328 	struct palmas_pmic_driver_data *pmic_ddata = palmas->pmic_ddata;
329 	int preq_mask_bit = 0;
330 	int reg_add = 0;
331 	int bit_pos, ret;
332 
333 	if (!(ext_ctrl & PALMAS_EXT_REQ))
334 		return 0;
335 
336 	if (id >= PALMAS_EXTERNAL_REQSTR_ID_MAX)
337 		return 0;
338 
339 	if (ext_ctrl & PALMAS_EXT_CONTROL_NSLEEP) {
340 		reg_add = PALMAS_NSLEEP_RES_ASSIGN;
341 		preq_mask_bit = 0;
342 	} else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE1) {
343 		reg_add = PALMAS_ENABLE1_RES_ASSIGN;
344 		preq_mask_bit = 1;
345 	} else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE2) {
346 		reg_add = PALMAS_ENABLE2_RES_ASSIGN;
347 		preq_mask_bit = 2;
348 	}
349 
350 	bit_pos = pmic_ddata->sleep_req_info[id].bit_pos;
351 	reg_add += pmic_ddata->sleep_req_info[id].reg_offset;
352 	if (enable)
353 		ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
354 				reg_add, BIT(bit_pos), BIT(bit_pos));
355 	else
356 		ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
357 				reg_add, BIT(bit_pos), 0);
358 	if (ret < 0) {
359 		dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
360 			reg_add, ret);
361 		return ret;
362 	}
363 
364 	/* Unmask the PREQ */
365 	ret = palmas_update_bits(palmas, PALMAS_PMU_CONTROL_BASE,
366 			PALMAS_POWER_CTRL, BIT(preq_mask_bit), 0);
367 	if (ret < 0) {
368 		dev_err(palmas->dev, "POWER_CTRL register update failed %d\n",
369 			ret);
370 		return ret;
371 	}
372 	return ret;
373 }
374 EXPORT_SYMBOL_GPL(palmas_ext_control_req_config);
375 
palmas_set_pdata_irq_flag(struct i2c_client * i2c,struct palmas_platform_data * pdata)376 static int palmas_set_pdata_irq_flag(struct i2c_client *i2c,
377 		struct palmas_platform_data *pdata)
378 {
379 	struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
380 	if (!irq_data) {
381 		dev_err(&i2c->dev, "Invalid IRQ: %d\n", i2c->irq);
382 		return -EINVAL;
383 	}
384 
385 	pdata->irq_flags = irqd_get_trigger_type(irq_data);
386 	dev_info(&i2c->dev, "Irq flag is 0x%08x\n", pdata->irq_flags);
387 	return 0;
388 }
389 
palmas_dt_to_pdata(struct i2c_client * i2c,struct palmas_platform_data * pdata)390 static void palmas_dt_to_pdata(struct i2c_client *i2c,
391 		struct palmas_platform_data *pdata)
392 {
393 	struct device_node *node = i2c->dev.of_node;
394 	int ret;
395 	u32 prop;
396 
397 	ret = of_property_read_u32(node, "ti,mux-pad1", &prop);
398 	if (!ret) {
399 		pdata->mux_from_pdata = 1;
400 		pdata->pad1 = prop;
401 	}
402 
403 	ret = of_property_read_u32(node, "ti,mux-pad2", &prop);
404 	if (!ret) {
405 		pdata->mux_from_pdata = 1;
406 		pdata->pad2 = prop;
407 	}
408 
409 	/* The default for this register is all masked */
410 	ret = of_property_read_u32(node, "ti,power-ctrl", &prop);
411 	if (!ret)
412 		pdata->power_ctrl = prop;
413 	else
414 		pdata->power_ctrl = PALMAS_POWER_CTRL_NSLEEP_MASK |
415 					PALMAS_POWER_CTRL_ENABLE1_MASK |
416 					PALMAS_POWER_CTRL_ENABLE2_MASK;
417 	if (i2c->irq)
418 		palmas_set_pdata_irq_flag(i2c, pdata);
419 
420 	pdata->pm_off = of_property_read_bool(node,
421 			"ti,system-power-controller");
422 }
423 
424 static struct palmas *palmas_dev;
palmas_power_off(void)425 static void palmas_power_off(void)
426 {
427 	unsigned int addr;
428 	int ret, slave;
429 	u8 powerhold_mask;
430 	struct device_node *np = palmas_dev->dev->of_node;
431 
432 	if (of_property_read_bool(np, "ti,palmas-override-powerhold")) {
433 		addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
434 					  PALMAS_PRIMARY_SECONDARY_PAD2);
435 		slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
436 
437 		if (of_device_is_compatible(np, "ti,tps65917"))
438 			powerhold_mask =
439 				TPS65917_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK;
440 		else
441 			powerhold_mask =
442 				PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK;
443 
444 		ret = regmap_update_bits(palmas_dev->regmap[slave], addr,
445 					 powerhold_mask, 0);
446 		if (ret)
447 			dev_err(palmas_dev->dev,
448 				"Unable to write PRIMARY_SECONDARY_PAD2 %d\n",
449 				ret);
450 	}
451 
452 	slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
453 	addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_DEV_CTRL);
454 
455 	ret = regmap_update_bits(
456 			palmas_dev->regmap[slave],
457 			addr,
458 			PALMAS_DEV_CTRL_DEV_ON,
459 			0);
460 
461 	if (ret)
462 		pr_err("%s: Unable to write to DEV_CTRL_DEV_ON: %d\n",
463 				__func__, ret);
464 }
465 
466 struct palmas_driver_data {
467 	unsigned int features;
468 	const struct regmap_irq_chip *irq_chip;
469 };
470 
471 static const struct palmas_driver_data palmas_data = {
472 	.features = PALMAS_PMIC_FEATURE_SMPS10_BOOST,
473 	.irq_chip = &palmas_irq_chip,
474 };
475 
476 static const struct palmas_driver_data tps659038_data = {
477 	.irq_chip = &palmas_irq_chip,
478 };
479 
480 static const struct palmas_driver_data tps65917_data = {
481 	.irq_chip = &tps65917_irq_chip,
482 };
483 
palmas_i2c_probe(struct i2c_client * i2c)484 static int palmas_i2c_probe(struct i2c_client *i2c)
485 {
486 	struct palmas *palmas;
487 	struct palmas_platform_data *pdata;
488 	const struct palmas_driver_data *driver_data;
489 	struct device_node *node = i2c->dev.of_node;
490 	int ret = 0, i;
491 	unsigned int reg, addr;
492 	int slave;
493 
494 	pdata = dev_get_platdata(&i2c->dev);
495 
496 	if (node && !pdata) {
497 		pdata = devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL);
498 
499 		if (!pdata)
500 			return -ENOMEM;
501 
502 		palmas_dt_to_pdata(i2c, pdata);
503 	}
504 
505 	if (!pdata)
506 		return -EINVAL;
507 
508 	palmas = devm_kzalloc(&i2c->dev, sizeof(struct palmas), GFP_KERNEL);
509 	if (palmas == NULL)
510 		return -ENOMEM;
511 
512 	i2c_set_clientdata(i2c, palmas);
513 	palmas->dev = &i2c->dev;
514 	palmas->irq = i2c->irq;
515 
516 	driver_data = i2c_get_match_data(i2c);
517 	palmas->features = driver_data->features;
518 
519 	for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
520 		if (i == 0)
521 			palmas->i2c_clients[i] = i2c;
522 		else {
523 			palmas->i2c_clients[i] =
524 					i2c_new_dummy_device(i2c->adapter,
525 							i2c->addr + i);
526 			if (IS_ERR(palmas->i2c_clients[i])) {
527 				dev_err(palmas->dev,
528 					"can't attach client %d\n", i);
529 				ret = PTR_ERR(palmas->i2c_clients[i]);
530 				goto err_i2c;
531 			}
532 			palmas->i2c_clients[i]->dev.of_node = of_node_get(node);
533 		}
534 		palmas->regmap[i] = devm_regmap_init_i2c(palmas->i2c_clients[i],
535 				&palmas_regmap_config[i]);
536 		if (IS_ERR(palmas->regmap[i])) {
537 			ret = PTR_ERR(palmas->regmap[i]);
538 			dev_err(palmas->dev,
539 				"Failed to allocate regmap %d, err: %d\n",
540 				i, ret);
541 			goto err_i2c;
542 		}
543 	}
544 
545 	if (!palmas->irq) {
546 		dev_warn(palmas->dev, "IRQ missing: skipping irq request\n");
547 		goto no_irq;
548 	}
549 
550 	/* Change interrupt line output polarity */
551 	if (pdata->irq_flags & IRQ_TYPE_LEVEL_HIGH)
552 		reg = PALMAS_POLARITY_CTRL_INT_POLARITY;
553 	else
554 		reg = 0;
555 	ret = palmas_update_bits(palmas, PALMAS_PU_PD_OD_BASE,
556 			PALMAS_POLARITY_CTRL, PALMAS_POLARITY_CTRL_INT_POLARITY,
557 			reg);
558 	if (ret < 0) {
559 		dev_err(palmas->dev, "POLARITY_CTRL update failed: %d\n", ret);
560 		goto err_i2c;
561 	}
562 
563 	/* Change IRQ into clear on read mode for efficiency */
564 	slave = PALMAS_BASE_TO_SLAVE(PALMAS_INTERRUPT_BASE);
565 	addr = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, PALMAS_INT_CTRL);
566 	reg = PALMAS_INT_CTRL_INT_CLEAR;
567 
568 	regmap_write(palmas->regmap[slave], addr, reg);
569 
570 	ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq,
571 				  IRQF_ONESHOT | pdata->irq_flags, 0,
572 				  driver_data->irq_chip, &palmas->irq_data);
573 	if (ret < 0)
574 		goto err_i2c;
575 
576 no_irq:
577 	slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
578 	addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
579 			PALMAS_PRIMARY_SECONDARY_PAD1);
580 
581 	if (pdata->mux_from_pdata) {
582 		reg = pdata->pad1;
583 		ret = regmap_write(palmas->regmap[slave], addr, reg);
584 		if (ret)
585 			goto err_irq;
586 	} else {
587 		ret = regmap_read(palmas->regmap[slave], addr, &reg);
588 		if (ret)
589 			goto err_irq;
590 	}
591 
592 	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0))
593 		palmas->gpio_muxed |= PALMAS_GPIO_0_MUXED;
594 	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK))
595 		palmas->gpio_muxed |= PALMAS_GPIO_1_MUXED;
596 	else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
597 			(2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
598 		palmas->led_muxed |= PALMAS_LED1_MUXED;
599 	else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
600 			(3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
601 		palmas->pwm_muxed |= PALMAS_PWM1_MUXED;
602 	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK))
603 		palmas->gpio_muxed |= PALMAS_GPIO_2_MUXED;
604 	else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
605 			(2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
606 		palmas->led_muxed |= PALMAS_LED2_MUXED;
607 	else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
608 			(3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
609 		palmas->pwm_muxed |= PALMAS_PWM2_MUXED;
610 	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3))
611 		palmas->gpio_muxed |= PALMAS_GPIO_3_MUXED;
612 
613 	addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
614 			PALMAS_PRIMARY_SECONDARY_PAD2);
615 
616 	if (pdata->mux_from_pdata) {
617 		reg = pdata->pad2;
618 		ret = regmap_write(palmas->regmap[slave], addr, reg);
619 		if (ret)
620 			goto err_irq;
621 	} else {
622 		ret = regmap_read(palmas->regmap[slave], addr, &reg);
623 		if (ret)
624 			goto err_irq;
625 	}
626 
627 	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4))
628 		palmas->gpio_muxed |= PALMAS_GPIO_4_MUXED;
629 	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK))
630 		palmas->gpio_muxed |= PALMAS_GPIO_5_MUXED;
631 	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6))
632 		palmas->gpio_muxed |= PALMAS_GPIO_6_MUXED;
633 	if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK))
634 		palmas->gpio_muxed |= PALMAS_GPIO_7_MUXED;
635 
636 	dev_info(palmas->dev, "Muxing GPIO %x, PWM %x, LED %x\n",
637 			palmas->gpio_muxed, palmas->pwm_muxed,
638 			palmas->led_muxed);
639 
640 	reg = pdata->power_ctrl;
641 
642 	slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
643 	addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_POWER_CTRL);
644 
645 	ret = regmap_write(palmas->regmap[slave], addr, reg);
646 	if (ret)
647 		goto err_irq;
648 
649 	/*
650 	 * If we are probing with DT do this the DT way and return here
651 	 * otherwise continue and add devices using mfd helpers.
652 	 */
653 	if (node) {
654 		ret = devm_of_platform_populate(&i2c->dev);
655 		if (ret < 0) {
656 			goto err_irq;
657 		} else if (pdata->pm_off && !pm_power_off) {
658 			palmas_dev = palmas;
659 			pm_power_off = palmas_power_off;
660 		}
661 	}
662 
663 	return ret;
664 
665 err_irq:
666 	regmap_del_irq_chip(palmas->irq, palmas->irq_data);
667 err_i2c:
668 	for (i = 1; i < PALMAS_NUM_CLIENTS; i++) {
669 		if (palmas->i2c_clients[i])
670 			i2c_unregister_device(palmas->i2c_clients[i]);
671 	}
672 	return ret;
673 }
674 
palmas_i2c_remove(struct i2c_client * i2c)675 static void palmas_i2c_remove(struct i2c_client *i2c)
676 {
677 	struct palmas *palmas = i2c_get_clientdata(i2c);
678 	int i;
679 
680 	regmap_del_irq_chip(palmas->irq, palmas->irq_data);
681 
682 	for (i = 1; i < PALMAS_NUM_CLIENTS; i++) {
683 		if (palmas->i2c_clients[i])
684 			i2c_unregister_device(palmas->i2c_clients[i]);
685 	}
686 
687 	if (palmas == palmas_dev) {
688 		pm_power_off = NULL;
689 		palmas_dev = NULL;
690 	}
691 }
692 
693 static const struct of_device_id of_palmas_match_tbl[] = {
694 	{ .compatible = "ti,palmas", .data = &palmas_data },
695 	{ .compatible = "ti,tps659038", .data = &tps659038_data },
696 	{ .compatible = "ti,tps65917", .data = &tps65917_data },
697 	{ }
698 };
699 MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
700 
701 static const struct i2c_device_id palmas_i2c_id[] = {
702 	{ "palmas", (kernel_ulong_t)&palmas_data },
703 	{ "twl6035", (kernel_ulong_t)&palmas_data },
704 	{ "twl6037", (kernel_ulong_t)&palmas_data },
705 	{ "tps65913", (kernel_ulong_t)&palmas_data },
706 	{ /* end */ }
707 };
708 MODULE_DEVICE_TABLE(i2c, palmas_i2c_id);
709 
710 static struct i2c_driver palmas_i2c_driver = {
711 	.driver = {
712 		   .name = "palmas",
713 		   .of_match_table = of_palmas_match_tbl,
714 	},
715 	.probe = palmas_i2c_probe,
716 	.remove = palmas_i2c_remove,
717 	.id_table = palmas_i2c_id,
718 };
719 
palmas_i2c_init(void)720 static int __init palmas_i2c_init(void)
721 {
722 	return i2c_add_driver(&palmas_i2c_driver);
723 }
724 /* init early so consumer devices can complete system boot */
725 subsys_initcall(palmas_i2c_init);
726 
palmas_i2c_exit(void)727 static void __exit palmas_i2c_exit(void)
728 {
729 	i2c_del_driver(&palmas_i2c_driver);
730 }
731 module_exit(palmas_i2c_exit);
732 
733 MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
734 MODULE_DESCRIPTION("Palmas chip family multi-function driver");
735 MODULE_LICENSE("GPL");
736