1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2014 Freescale Semiconductor, Inc. 6 // 7 // Author: Nicolin Chen <nicoleotsuka@gmail.com> 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/module.h> 13 #include <linux/of_platform.h> 14 #include <linux/dma/imx-dma.h> 15 #include <linux/pm_runtime.h> 16 #include <sound/dmaengine_pcm.h> 17 #include <sound/pcm_params.h> 18 19 #include "fsl_asrc.h" 20 21 #define IDEAL_RATIO_DECIMAL_DEPTH 26 22 #define DIVIDER_NUM 64 23 #define INIT_RETRY_NUM 50 24 25 #define pair_err(fmt, ...) \ 26 dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 27 28 #define pair_dbg(fmt, ...) \ 29 dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 30 31 #define pair_warn(fmt, ...) \ 32 dev_warn(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 33 34 /* Corresponding to process_option */ 35 static unsigned int supported_asrc_rate[] = { 36 5512, 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, 37 64000, 88200, 96000, 128000, 176400, 192000, 38 }; 39 40 static struct snd_pcm_hw_constraint_list fsl_asrc_rate_constraints = { 41 .count = ARRAY_SIZE(supported_asrc_rate), 42 .list = supported_asrc_rate, 43 }; 44 45 /* 46 * The following tables map the relationship between asrc_inclk/asrc_outclk in 47 * fsl_asrc.h and the registers of ASRCSR 48 */ 49 static unsigned char input_clk_map_imx35[ASRC_CLK_MAP_LEN] = { 50 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 51 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 52 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 53 }; 54 55 static unsigned char output_clk_map_imx35[ASRC_CLK_MAP_LEN] = { 56 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 57 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 58 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 59 }; 60 61 /* i.MX53 uses the same map for input and output */ 62 static unsigned char input_clk_map_imx53[ASRC_CLK_MAP_LEN] = { 63 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 64 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd, 65 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 66 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 67 }; 68 69 static unsigned char output_clk_map_imx53[ASRC_CLK_MAP_LEN] = { 70 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 71 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd, 72 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 73 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 74 }; 75 76 /* 77 * i.MX8QM/i.MX8QXP uses the same map for input and output. 78 * clk_map_imx8qm[0] is for i.MX8QM asrc0 79 * clk_map_imx8qm[1] is for i.MX8QM asrc1 80 * clk_map_imx8qxp[0] is for i.MX8QXP asrc0 81 * clk_map_imx8qxp[1] is for i.MX8QXP asrc1 82 */ 83 static unsigned char clk_map_imx8qm[2][ASRC_CLK_MAP_LEN] = { 84 { 85 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 86 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 87 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 88 }, 89 { 90 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 91 0x0, 0x1, 0x2, 0x3, 0xb, 0xc, 0xf, 0xf, 0xd, 0xe, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 92 0x4, 0x5, 0x6, 0xf, 0x8, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 93 }, 94 }; 95 96 static unsigned char clk_map_imx8qxp[2][ASRC_CLK_MAP_LEN] = { 97 { 98 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 99 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0xf, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xf, 100 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 101 }, 102 { 103 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 104 0x0, 0x1, 0x2, 0x3, 0x7, 0x8, 0xf, 0xf, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 105 0xf, 0xf, 0x6, 0xf, 0xf, 0xf, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 106 }, 107 }; 108 109 static unsigned char clk_map_imx952[ASRC_CLK_MAP_LEN] = { 110 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 111 0x0, 0x1, 0x2, 0x3, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x4, 0x5, 0x6, 0x8, 0xf, 0xf, 112 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0x9, 0xa, 0xb, 0xc, 0xd, 0xf, 0xf, 0xf, 0xf, 113 }; 114 115 /* 116 * According to RM, the divider range is 1 ~ 8, 117 * prescaler is power of 2 from 1 ~ 128. 118 */ 119 static int asrc_clk_divider[DIVIDER_NUM] = { 120 1, 2, 4, 8, 16, 32, 64, 128, /* divider = 1 */ 121 2, 4, 8, 16, 32, 64, 128, 256, /* divider = 2 */ 122 3, 6, 12, 24, 48, 96, 192, 384, /* divider = 3 */ 123 4, 8, 16, 32, 64, 128, 256, 512, /* divider = 4 */ 124 5, 10, 20, 40, 80, 160, 320, 640, /* divider = 5 */ 125 6, 12, 24, 48, 96, 192, 384, 768, /* divider = 6 */ 126 7, 14, 28, 56, 112, 224, 448, 896, /* divider = 7 */ 127 8, 16, 32, 64, 128, 256, 512, 1024, /* divider = 8 */ 128 }; 129 130 /* 131 * Check if the divider is available for internal ratio mode 132 */ 133 static bool fsl_asrc_divider_avail(int clk_rate, int rate, int *div) 134 { 135 u32 rem, i; 136 u64 n; 137 138 if (div) 139 *div = 0; 140 141 if (clk_rate == 0 || rate == 0) 142 return false; 143 144 n = clk_rate; 145 rem = do_div(n, rate); 146 147 if (div) 148 *div = n; 149 150 if (rem != 0) 151 return false; 152 153 for (i = 0; i < DIVIDER_NUM; i++) { 154 if (n == asrc_clk_divider[i]) 155 break; 156 } 157 158 if (i == DIVIDER_NUM) 159 return false; 160 161 return true; 162 } 163 164 /** 165 * fsl_asrc_sel_proc - Select the pre-processing and post-processing options 166 * @inrate: input sample rate 167 * @outrate: output sample rate 168 * @pre_proc: return value for pre-processing option 169 * @post_proc: return value for post-processing option 170 * 171 * Make sure to exclude following unsupported cases before 172 * calling this function: 173 * 1) inrate > 8.125 * outrate 174 * 2) inrate > 16.125 * outrate 175 * 176 */ 177 static void fsl_asrc_sel_proc(int inrate, int outrate, 178 int *pre_proc, int *post_proc) 179 { 180 bool post_proc_cond2; 181 bool post_proc_cond0; 182 183 /* select pre_proc between [0, 2] */ 184 if (inrate * 8 > 33 * outrate) 185 *pre_proc = 2; 186 else if (inrate * 8 > 15 * outrate) { 187 if (inrate > 152000) 188 *pre_proc = 2; 189 else 190 *pre_proc = 1; 191 } else if (inrate < 76000) 192 *pre_proc = 0; 193 else if (inrate > 152000) 194 *pre_proc = 2; 195 else 196 *pre_proc = 1; 197 198 /* Condition for selection of post-processing */ 199 post_proc_cond2 = (inrate * 15 > outrate * 16 && outrate < 56000) || 200 (inrate > 56000 && outrate < 56000); 201 post_proc_cond0 = inrate * 23 < outrate * 8; 202 203 if (post_proc_cond2) 204 *post_proc = 2; 205 else if (post_proc_cond0) 206 *post_proc = 0; 207 else 208 *post_proc = 1; 209 } 210 211 /** 212 * fsl_asrc_request_pair - Request ASRC pair 213 * @channels: number of channels 214 * @pair: pointer to pair 215 * 216 * It assigns pair by the order of A->C->B because allocation of pair B, 217 * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A 218 * while pair A and pair C are comparatively independent. 219 */ 220 static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair) 221 { 222 enum asrc_pair_index index = ASRC_INVALID_PAIR; 223 struct fsl_asrc *asrc = pair->asrc; 224 struct device *dev = &asrc->pdev->dev; 225 unsigned long lock_flags; 226 int i, ret = 0; 227 228 spin_lock_irqsave(&asrc->lock, lock_flags); 229 230 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) { 231 if (asrc->pair[i] != NULL) 232 continue; 233 234 index = i; 235 236 if (i != ASRC_PAIR_B) 237 break; 238 } 239 240 if (index == ASRC_INVALID_PAIR) { 241 dev_err(dev, "all pairs are busy now\n"); 242 ret = -EBUSY; 243 } else if (asrc->channel_avail < channels) { 244 dev_err(dev, "can't afford required channels: %d\n", channels); 245 ret = -EINVAL; 246 } else { 247 asrc->channel_avail -= channels; 248 asrc->pair[index] = pair; 249 pair->channels = channels; 250 pair->index = index; 251 } 252 253 spin_unlock_irqrestore(&asrc->lock, lock_flags); 254 255 return ret; 256 } 257 258 /** 259 * fsl_asrc_release_pair - Release ASRC pair 260 * @pair: pair to release 261 * 262 * It clears the resource from asrc and releases the occupied channels. 263 */ 264 static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair) 265 { 266 struct fsl_asrc *asrc = pair->asrc; 267 enum asrc_pair_index index = pair->index; 268 unsigned long lock_flags; 269 270 /* Make sure the pair is disabled */ 271 regmap_update_bits(asrc->regmap, REG_ASRCTR, 272 ASRCTR_ASRCEi_MASK(index), 0); 273 274 spin_lock_irqsave(&asrc->lock, lock_flags); 275 276 asrc->channel_avail += pair->channels; 277 asrc->pair[index] = NULL; 278 pair->error = 0; 279 280 spin_unlock_irqrestore(&asrc->lock, lock_flags); 281 } 282 283 /** 284 * fsl_asrc_set_watermarks- configure input and output thresholds 285 * @pair: pointer to pair 286 * @in: input threshold 287 * @out: output threshold 288 */ 289 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out) 290 { 291 struct fsl_asrc *asrc = pair->asrc; 292 enum asrc_pair_index index = pair->index; 293 294 regmap_update_bits(asrc->regmap, REG_ASRMCR(index), 295 ASRMCRi_EXTTHRSHi_MASK | 296 ASRMCRi_INFIFO_THRESHOLD_MASK | 297 ASRMCRi_OUTFIFO_THRESHOLD_MASK, 298 ASRMCRi_EXTTHRSHi | 299 ASRMCRi_INFIFO_THRESHOLD(in) | 300 ASRMCRi_OUTFIFO_THRESHOLD(out)); 301 } 302 303 /** 304 * fsl_asrc_cal_asrck_divisor - Calculate the total divisor between asrck clock rate and sample rate 305 * @pair: pointer to pair 306 * @div: divider 307 * 308 * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider 309 */ 310 static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div) 311 { 312 u32 ps; 313 314 /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */ 315 for (ps = 0; div > 8; ps++) 316 div >>= 1; 317 318 return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps; 319 } 320 321 /** 322 * fsl_asrc_set_ideal_ratio - Calculate and set the ratio for Ideal Ratio mode only 323 * @pair: pointer to pair 324 * @inrate: input rate 325 * @outrate: output rate 326 * 327 * The ratio is a 32-bit fixed point value with 26 fractional bits. 328 */ 329 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair, 330 int inrate, int outrate) 331 { 332 struct fsl_asrc *asrc = pair->asrc; 333 enum asrc_pair_index index = pair->index; 334 unsigned long ratio; 335 int i; 336 337 if (!outrate) { 338 pair_err("output rate should not be zero\n"); 339 return -EINVAL; 340 } 341 342 /* Calculate the intergal part of the ratio */ 343 ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH; 344 345 /* ... and then the 26 depth decimal part */ 346 inrate %= outrate; 347 348 for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) { 349 inrate <<= 1; 350 351 if (inrate < outrate) 352 continue; 353 354 ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i); 355 inrate -= outrate; 356 357 if (!inrate) 358 break; 359 } 360 361 regmap_write(asrc->regmap, REG_ASRIDRL(index), ratio); 362 regmap_write(asrc->regmap, REG_ASRIDRH(index), ratio >> 24); 363 364 return 0; 365 } 366 367 /** 368 * fsl_asrc_config_pair - Configure the assigned ASRC pair 369 * @pair: pointer to pair 370 * @use_ideal_rate: boolean configuration 371 * 372 * It configures those ASRC registers according to a configuration instance 373 * of struct asrc_config which includes in/output sample rate, width, channel 374 * and clock settings. 375 * 376 * Note: 377 * The ideal ratio configuration can work with a flexible clock rate setting. 378 * Using IDEAL_RATIO_RATE gives a faster converting speed but overloads ASRC. 379 * For a regular audio playback, the clock rate should not be slower than an 380 * clock rate aligning with the output sample rate; For a use case requiring 381 * faster conversion, set use_ideal_rate to have the faster speed. 382 */ 383 static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate) 384 { 385 struct fsl_asrc_pair_priv *pair_priv = pair->private; 386 struct asrc_config *config = pair_priv->config; 387 struct fsl_asrc *asrc = pair->asrc; 388 struct fsl_asrc_priv *asrc_priv = asrc->private; 389 enum asrc_pair_index index = pair->index; 390 enum asrc_word_width input_word_width; 391 enum asrc_word_width output_word_width; 392 u32 inrate, outrate, indiv, outdiv; 393 u32 clk_index[2], div[2]; 394 u64 clk_rate; 395 int in, out, channels; 396 int pre_proc, post_proc; 397 struct clk *clk; 398 bool ideal, div_avail; 399 400 if (!config) { 401 pair_err("invalid pair config\n"); 402 return -EINVAL; 403 } 404 405 /* Validate channels */ 406 if (config->channel_num < 1 || config->channel_num > 10) { 407 pair_err("does not support %d channels\n", config->channel_num); 408 return -EINVAL; 409 } 410 411 switch (snd_pcm_format_width(config->input_format)) { 412 case 8: 413 input_word_width = ASRC_WIDTH_8_BIT; 414 break; 415 case 16: 416 input_word_width = ASRC_WIDTH_16_BIT; 417 break; 418 case 24: 419 input_word_width = ASRC_WIDTH_24_BIT; 420 break; 421 default: 422 pair_err("does not support this input format, %d\n", 423 config->input_format); 424 return -EINVAL; 425 } 426 427 switch (snd_pcm_format_width(config->output_format)) { 428 case 16: 429 output_word_width = ASRC_WIDTH_16_BIT; 430 break; 431 case 24: 432 output_word_width = ASRC_WIDTH_24_BIT; 433 break; 434 default: 435 pair_err("does not support this output format, %d\n", 436 config->output_format); 437 return -EINVAL; 438 } 439 440 inrate = config->input_sample_rate; 441 outrate = config->output_sample_rate; 442 ideal = config->inclk == INCLK_NONE; 443 444 /* Validate input and output sample rates */ 445 for (in = 0; in < ARRAY_SIZE(supported_asrc_rate); in++) 446 if (inrate == supported_asrc_rate[in]) 447 break; 448 449 if (in == ARRAY_SIZE(supported_asrc_rate)) { 450 pair_err("unsupported input sample rate: %dHz\n", inrate); 451 return -EINVAL; 452 } 453 454 for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++) 455 if (outrate == supported_asrc_rate[out]) 456 break; 457 458 if (out == ARRAY_SIZE(supported_asrc_rate)) { 459 pair_err("unsupported output sample rate: %dHz\n", outrate); 460 return -EINVAL; 461 } 462 463 if ((outrate >= 5512 && outrate <= 30000) && 464 (outrate > 24 * inrate || inrate > 8 * outrate)) { 465 pair_err("exceed supported ratio range [1/24, 8] for \ 466 inrate/outrate: %d/%d\n", inrate, outrate); 467 return -EINVAL; 468 } 469 470 /* Validate input and output clock sources */ 471 clk_index[IN] = asrc_priv->clk_map[IN][config->inclk]; 472 clk_index[OUT] = asrc_priv->clk_map[OUT][config->outclk]; 473 474 /* We only have output clock for ideal ratio mode */ 475 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]]; 476 477 clk_rate = clk_get_rate(clk); 478 div_avail = fsl_asrc_divider_avail(clk_rate, inrate, &div[IN]); 479 480 /* 481 * The divider range is [1, 1024], defined by the hardware. For non- 482 * ideal ratio configuration, clock rate has to be strictly aligned 483 * with the sample rate. For ideal ratio configuration, clock rates 484 * only result in different converting speeds. So remainder does not 485 * matter, as long as we keep the divider within its valid range. 486 */ 487 if (div[IN] == 0 || (!ideal && !div_avail)) { 488 pair_err("failed to support input sample rate %dHz by asrck_%x\n", 489 inrate, clk_index[ideal ? OUT : IN]); 490 return -EINVAL; 491 } 492 493 div[IN] = min_t(u32, 1024, div[IN]); 494 495 clk = asrc_priv->asrck_clk[clk_index[OUT]]; 496 clk_rate = clk_get_rate(clk); 497 if (ideal && use_ideal_rate) 498 div_avail = fsl_asrc_divider_avail(clk_rate, IDEAL_RATIO_RATE, &div[OUT]); 499 else 500 div_avail = fsl_asrc_divider_avail(clk_rate, outrate, &div[OUT]); 501 502 /* Output divider has the same limitation as the input one */ 503 if (div[OUT] == 0 || (!ideal && !div_avail)) { 504 pair_err("failed to support output sample rate %dHz by asrck_%x\n", 505 outrate, clk_index[OUT]); 506 return -EINVAL; 507 } 508 509 div[OUT] = min_t(u32, 1024, div[OUT]); 510 511 /* Set the channel number */ 512 channels = config->channel_num; 513 514 if (asrc_priv->soc->channel_bits < 4) 515 channels /= 2; 516 517 /* Update channels for current pair */ 518 regmap_update_bits(asrc->regmap, REG_ASRCNCR, 519 ASRCNCR_ANCi_MASK(index, asrc_priv->soc->channel_bits), 520 ASRCNCR_ANCi(index, channels, asrc_priv->soc->channel_bits)); 521 522 /* Default setting: Automatic selection for processing mode */ 523 regmap_update_bits(asrc->regmap, REG_ASRCTR, 524 ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index)); 525 regmap_update_bits(asrc->regmap, REG_ASRCTR, 526 ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index), 527 ASRCTR_USR(index)); 528 529 /* Set the input and output clock sources */ 530 regmap_update_bits(asrc->regmap, REG_ASRCSR, 531 ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index), 532 ASRCSR_AICS(index, clk_index[IN]) | 533 ASRCSR_AOCS(index, clk_index[OUT])); 534 535 /* Calculate the input clock divisors */ 536 indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]); 537 outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]); 538 539 /* Suppose indiv and outdiv includes prescaler, so add its MASK too */ 540 regmap_update_bits(asrc->regmap, REG_ASRCDR(index), 541 ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) | 542 ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index), 543 ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv)); 544 545 /* Implement word_width configurations */ 546 regmap_update_bits(asrc->regmap, REG_ASRMCR1(index), 547 ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK, 548 ASRMCR1i_OW16(output_word_width) | 549 ASRMCR1i_IWD(input_word_width)); 550 551 /* Enable BUFFER STALL */ 552 regmap_update_bits(asrc->regmap, REG_ASRMCR(index), 553 ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi); 554 555 /* Set default thresholds for input and output FIFO */ 556 fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD, 557 ASRC_INPUTFIFO_THRESHOLD); 558 559 /* Configure the following only for Ideal Ratio mode */ 560 if (!ideal) 561 return 0; 562 563 /* Clear ASTSx bit to use Ideal Ratio mode */ 564 regmap_update_bits(asrc->regmap, REG_ASRCTR, 565 ASRCTR_ATSi_MASK(index), 0); 566 567 /* Enable Ideal Ratio mode */ 568 regmap_update_bits(asrc->regmap, REG_ASRCTR, 569 ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index), 570 ASRCTR_IDR(index) | ASRCTR_USR(index)); 571 572 fsl_asrc_sel_proc(inrate, outrate, &pre_proc, &post_proc); 573 574 /* Apply configurations for pre- and post-processing */ 575 regmap_update_bits(asrc->regmap, REG_ASRCFG, 576 ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index), 577 ASRCFG_PREMOD(index, pre_proc) | 578 ASRCFG_POSTMOD(index, post_proc)); 579 580 return fsl_asrc_set_ideal_ratio(pair, inrate, outrate); 581 } 582 583 /** 584 * fsl_asrc_start_pair - Start the assigned ASRC pair 585 * @pair: pointer to pair 586 * 587 * It enables the assigned pair and makes it stopped at the stall level. 588 */ 589 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair) 590 { 591 struct fsl_asrc *asrc = pair->asrc; 592 enum asrc_pair_index index = pair->index; 593 int reg, retry = INIT_RETRY_NUM, i; 594 595 /* Enable the current pair */ 596 regmap_update_bits(asrc->regmap, REG_ASRCTR, 597 ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index)); 598 599 /* Wait for status of initialization */ 600 do { 601 udelay(5); 602 regmap_read(asrc->regmap, REG_ASRCFG, ®); 603 reg &= ASRCFG_INIRQi_MASK(index); 604 } while (!reg && --retry); 605 606 /* NOTE: Doesn't treat initialization timeout as an error */ 607 if (!retry) 608 pair_warn("initialization isn't finished\n"); 609 610 /* Make the input fifo to ASRC STALL level */ 611 regmap_read(asrc->regmap, REG_ASRCNCR, ®); 612 for (i = 0; i < pair->channels * 4; i++) 613 regmap_write(asrc->regmap, REG_ASRDI(index), 0); 614 615 /* Enable overload interrupt */ 616 regmap_write(asrc->regmap, REG_ASRIER, ASRIER_AOLIE); 617 } 618 619 /** 620 * fsl_asrc_stop_pair - Stop the assigned ASRC pair 621 * @pair: pointer to pair 622 */ 623 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair) 624 { 625 struct fsl_asrc *asrc = pair->asrc; 626 enum asrc_pair_index index = pair->index; 627 628 /* Stop the current pair */ 629 regmap_update_bits(asrc->regmap, REG_ASRCTR, 630 ASRCTR_ASRCEi_MASK(index), 0); 631 } 632 633 /** 634 * fsl_asrc_get_dma_channel- Get DMA channel according to the pair and direction. 635 * @pair: pointer to pair 636 * @dir: DMA direction 637 */ 638 static struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, 639 bool dir) 640 { 641 struct fsl_asrc *asrc = pair->asrc; 642 enum asrc_pair_index index = pair->index; 643 char name[4]; 644 645 sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a'); 646 647 return dma_request_slave_channel(&asrc->pdev->dev, name); 648 } 649 650 static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream, 651 struct snd_soc_dai *dai) 652 { 653 struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai); 654 struct fsl_asrc_priv *asrc_priv = asrc->private; 655 656 /* Odd channel number is not valid for older ASRC (channel_bits==3) */ 657 if (asrc_priv->soc->channel_bits == 3) 658 snd_pcm_hw_constraint_step(substream->runtime, 0, 659 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 660 661 662 return snd_pcm_hw_constraint_list(substream->runtime, 0, 663 SNDRV_PCM_HW_PARAM_RATE, &fsl_asrc_rate_constraints); 664 } 665 666 /* Select proper clock source for internal ratio mode */ 667 static void fsl_asrc_select_clk(struct fsl_asrc_priv *asrc_priv, 668 struct fsl_asrc_pair *pair, 669 int in_rate, 670 int out_rate) 671 { 672 struct fsl_asrc_pair_priv *pair_priv = pair->private; 673 struct asrc_config *config = pair_priv->config; 674 int rate[2], select_clk[2]; /* Array size 2 means IN and OUT */ 675 int clk_rate, clk_index; 676 int i, j; 677 678 rate[IN] = in_rate; 679 rate[OUT] = out_rate; 680 681 /* Select proper clock source for internal ratio mode */ 682 for (j = 0; j < 2; j++) { 683 for (i = 0; i < ASRC_CLK_MAP_LEN; i++) { 684 clk_index = asrc_priv->clk_map[j][i]; 685 clk_rate = clk_get_rate(asrc_priv->asrck_clk[clk_index]); 686 /* Only match a perfect clock source with no remainder */ 687 if (fsl_asrc_divider_avail(clk_rate, rate[j], NULL)) 688 break; 689 } 690 691 select_clk[j] = i; 692 } 693 694 /* Switch to ideal ratio mode if there is no proper clock source */ 695 if (select_clk[IN] == ASRC_CLK_MAP_LEN || select_clk[OUT] == ASRC_CLK_MAP_LEN) { 696 select_clk[IN] = INCLK_NONE; 697 select_clk[OUT] = OUTCLK_ASRCK1_CLK; 698 } 699 700 config->inclk = select_clk[IN]; 701 config->outclk = select_clk[OUT]; 702 } 703 704 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream, 705 struct snd_pcm_hw_params *params, 706 struct snd_soc_dai *dai) 707 { 708 struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai); 709 struct fsl_asrc_priv *asrc_priv = asrc->private; 710 struct snd_pcm_runtime *runtime = substream->runtime; 711 struct fsl_asrc_pair *pair = runtime->private_data; 712 struct fsl_asrc_pair_priv *pair_priv = pair->private; 713 unsigned int channels = params_channels(params); 714 unsigned int rate = params_rate(params); 715 struct asrc_config config; 716 int ret; 717 718 ret = fsl_asrc_request_pair(channels, pair); 719 if (ret) { 720 dev_err(dai->dev, "fail to request asrc pair\n"); 721 return ret; 722 } 723 724 pair_priv->config = &config; 725 726 config.pair = pair->index; 727 config.channel_num = channels; 728 729 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 730 config.input_format = params_format(params); 731 config.output_format = asrc->asrc_format; 732 config.input_sample_rate = rate; 733 config.output_sample_rate = asrc->asrc_rate; 734 } else { 735 config.input_format = asrc->asrc_format; 736 config.output_format = params_format(params); 737 config.input_sample_rate = asrc->asrc_rate; 738 config.output_sample_rate = rate; 739 } 740 741 fsl_asrc_select_clk(asrc_priv, pair, 742 config.input_sample_rate, 743 config.output_sample_rate); 744 745 ret = fsl_asrc_config_pair(pair, false); 746 if (ret) { 747 dev_err(dai->dev, "fail to config asrc pair\n"); 748 return ret; 749 } 750 751 return 0; 752 } 753 754 static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream, 755 struct snd_soc_dai *dai) 756 { 757 struct snd_pcm_runtime *runtime = substream->runtime; 758 struct fsl_asrc_pair *pair = runtime->private_data; 759 760 if (pair) 761 fsl_asrc_release_pair(pair); 762 763 return 0; 764 } 765 766 static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd, 767 struct snd_soc_dai *dai) 768 { 769 struct snd_pcm_runtime *runtime = substream->runtime; 770 struct fsl_asrc_pair *pair = runtime->private_data; 771 772 switch (cmd) { 773 case SNDRV_PCM_TRIGGER_START: 774 case SNDRV_PCM_TRIGGER_RESUME: 775 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 776 fsl_asrc_start_pair(pair); 777 break; 778 case SNDRV_PCM_TRIGGER_STOP: 779 case SNDRV_PCM_TRIGGER_SUSPEND: 780 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 781 fsl_asrc_stop_pair(pair); 782 break; 783 default: 784 return -EINVAL; 785 } 786 787 return 0; 788 } 789 790 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai) 791 { 792 struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai); 793 794 snd_soc_dai_init_dma_data(dai, &asrc->dma_params_tx, 795 &asrc->dma_params_rx); 796 797 return 0; 798 } 799 800 static const struct snd_soc_dai_ops fsl_asrc_dai_ops = { 801 .probe = fsl_asrc_dai_probe, 802 .startup = fsl_asrc_dai_startup, 803 .hw_params = fsl_asrc_dai_hw_params, 804 .hw_free = fsl_asrc_dai_hw_free, 805 .trigger = fsl_asrc_dai_trigger, 806 }; 807 808 #define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \ 809 SNDRV_PCM_FMTBIT_S16_LE | \ 810 SNDRV_PCM_FMTBIT_S24_3LE) 811 812 static struct snd_soc_dai_driver fsl_asrc_dai = { 813 .playback = { 814 .stream_name = "ASRC-Playback", 815 .channels_min = 1, 816 .channels_max = 10, 817 .rate_min = 5512, 818 .rate_max = 192000, 819 .rates = SNDRV_PCM_RATE_KNOT, 820 .formats = FSL_ASRC_FORMATS | 821 SNDRV_PCM_FMTBIT_S8, 822 }, 823 .capture = { 824 .stream_name = "ASRC-Capture", 825 .channels_min = 1, 826 .channels_max = 10, 827 .rate_min = 5512, 828 .rate_max = 192000, 829 .rates = SNDRV_PCM_RATE_KNOT, 830 .formats = FSL_ASRC_FORMATS, 831 }, 832 .ops = &fsl_asrc_dai_ops, 833 }; 834 835 static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg) 836 { 837 switch (reg) { 838 case REG_ASRCTR: 839 case REG_ASRIER: 840 case REG_ASRCNCR: 841 case REG_ASRCFG: 842 case REG_ASRCSR: 843 case REG_ASRCDR1: 844 case REG_ASRCDR2: 845 case REG_ASRSTR: 846 case REG_ASRPM1: 847 case REG_ASRPM2: 848 case REG_ASRPM3: 849 case REG_ASRPM4: 850 case REG_ASRPM5: 851 case REG_ASRTFR1: 852 case REG_ASRCCR: 853 case REG_ASRDOA: 854 case REG_ASRDOB: 855 case REG_ASRDOC: 856 case REG_ASRIDRHA: 857 case REG_ASRIDRLA: 858 case REG_ASRIDRHB: 859 case REG_ASRIDRLB: 860 case REG_ASRIDRHC: 861 case REG_ASRIDRLC: 862 case REG_ASR76K: 863 case REG_ASR56K: 864 case REG_ASRMCRA: 865 case REG_ASRFSTA: 866 case REG_ASRMCRB: 867 case REG_ASRFSTB: 868 case REG_ASRMCRC: 869 case REG_ASRFSTC: 870 case REG_ASRMCR1A: 871 case REG_ASRMCR1B: 872 case REG_ASRMCR1C: 873 return true; 874 default: 875 return false; 876 } 877 } 878 879 static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg) 880 { 881 switch (reg) { 882 case REG_ASRSTR: 883 case REG_ASRDIA: 884 case REG_ASRDIB: 885 case REG_ASRDIC: 886 case REG_ASRDOA: 887 case REG_ASRDOB: 888 case REG_ASRDOC: 889 case REG_ASRFSTA: 890 case REG_ASRFSTB: 891 case REG_ASRFSTC: 892 case REG_ASRCFG: 893 return true; 894 default: 895 return false; 896 } 897 } 898 899 static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg) 900 { 901 switch (reg) { 902 case REG_ASRCTR: 903 case REG_ASRIER: 904 case REG_ASRCNCR: 905 case REG_ASRCFG: 906 case REG_ASRCSR: 907 case REG_ASRCDR1: 908 case REG_ASRCDR2: 909 case REG_ASRSTR: 910 case REG_ASRPM1: 911 case REG_ASRPM2: 912 case REG_ASRPM3: 913 case REG_ASRPM4: 914 case REG_ASRPM5: 915 case REG_ASRTFR1: 916 case REG_ASRCCR: 917 case REG_ASRDIA: 918 case REG_ASRDIB: 919 case REG_ASRDIC: 920 case REG_ASRIDRHA: 921 case REG_ASRIDRLA: 922 case REG_ASRIDRHB: 923 case REG_ASRIDRLB: 924 case REG_ASRIDRHC: 925 case REG_ASRIDRLC: 926 case REG_ASR76K: 927 case REG_ASR56K: 928 case REG_ASRMCRA: 929 case REG_ASRMCRB: 930 case REG_ASRMCRC: 931 case REG_ASRMCR1A: 932 case REG_ASRMCR1B: 933 case REG_ASRMCR1C: 934 return true; 935 default: 936 return false; 937 } 938 } 939 940 static const struct reg_default fsl_asrc_reg[] = { 941 { REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 }, 942 { REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 }, 943 { REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 }, 944 { REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 }, 945 { REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 }, 946 { REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 }, 947 { REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 }, 948 { REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 }, 949 { REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 }, 950 { REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 }, 951 { REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 }, 952 { REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 }, 953 { REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 }, 954 { REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 }, 955 { REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 }, 956 { REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 }, 957 { REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 }, 958 { REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 }, 959 { REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 }, 960 { REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 }, 961 { REG_ASRMCR1C, 0x0000 }, 962 }; 963 964 static const struct regmap_config fsl_asrc_regmap_config = { 965 .reg_bits = 32, 966 .reg_stride = 4, 967 .val_bits = 32, 968 969 .max_register = REG_ASRMCR1C, 970 .reg_defaults = fsl_asrc_reg, 971 .num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg), 972 .readable_reg = fsl_asrc_readable_reg, 973 .volatile_reg = fsl_asrc_volatile_reg, 974 .writeable_reg = fsl_asrc_writeable_reg, 975 .cache_type = REGCACHE_FLAT, 976 }; 977 978 /** 979 * fsl_asrc_init - Initialize ASRC registers with a default configuration 980 * @asrc: ASRC context 981 */ 982 static int fsl_asrc_init(struct fsl_asrc *asrc) 983 { 984 unsigned long ipg_rate; 985 986 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */ 987 regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN); 988 989 /* Disable interrupt by default */ 990 regmap_write(asrc->regmap, REG_ASRIER, 0x0); 991 992 /* Apply recommended settings for parameters from Reference Manual */ 993 regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff); 994 regmap_write(asrc->regmap, REG_ASRPM2, 0x255555); 995 regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280); 996 regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280); 997 regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280); 998 999 /* Base address for task queue FIFO. Set to 0x7C */ 1000 regmap_update_bits(asrc->regmap, REG_ASRTFR1, 1001 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc)); 1002 1003 /* 1004 * Set the period of the 76KHz and 56KHz sampling clocks based on 1005 * the ASRC processing clock. 1006 * On iMX6, ipg_clk = 133MHz, REG_ASR76K = 0x06D6, REG_ASR56K = 0x0947 1007 */ 1008 ipg_rate = clk_get_rate(asrc->ipg_clk); 1009 regmap_write(asrc->regmap, REG_ASR76K, ipg_rate / 76000); 1010 return regmap_write(asrc->regmap, REG_ASR56K, ipg_rate / 56000); 1011 } 1012 1013 /** 1014 * fsl_asrc_isr- Interrupt handler for ASRC 1015 * @irq: irq number 1016 * @dev_id: ASRC context 1017 */ 1018 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id) 1019 { 1020 struct fsl_asrc *asrc = (struct fsl_asrc *)dev_id; 1021 struct device *dev = &asrc->pdev->dev; 1022 enum asrc_pair_index index; 1023 u32 status; 1024 1025 regmap_read(asrc->regmap, REG_ASRSTR, &status); 1026 1027 /* Clean overload error */ 1028 regmap_write(asrc->regmap, REG_ASRSTR, ASRSTR_AOLE); 1029 1030 /* 1031 * We here use dev_dbg() for all exceptions because ASRC itself does 1032 * not care if FIFO overflowed or underrun while a warning in the 1033 * interrupt would result a ridged conversion. 1034 */ 1035 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) { 1036 if (!asrc->pair[index]) 1037 continue; 1038 1039 if (status & ASRSTR_ATQOL) { 1040 asrc->pair[index]->error |= ASRC_TASK_Q_OVERLOAD; 1041 dev_dbg(dev, "ASRC Task Queue FIFO overload\n"); 1042 } 1043 1044 if (status & ASRSTR_AOOL(index)) { 1045 asrc->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD; 1046 pair_dbg("Output Task Overload\n"); 1047 } 1048 1049 if (status & ASRSTR_AIOL(index)) { 1050 asrc->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD; 1051 pair_dbg("Input Task Overload\n"); 1052 } 1053 1054 if (status & ASRSTR_AODO(index)) { 1055 asrc->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW; 1056 pair_dbg("Output Data Buffer has overflowed\n"); 1057 } 1058 1059 if (status & ASRSTR_AIDU(index)) { 1060 asrc->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN; 1061 pair_dbg("Input Data Buffer has underflowed\n"); 1062 } 1063 } 1064 1065 return IRQ_HANDLED; 1066 } 1067 1068 static int fsl_asrc_get_fifo_addr(u8 dir, enum asrc_pair_index index) 1069 { 1070 return REG_ASRDx(dir, index); 1071 } 1072 1073 /* Get sample numbers in FIFO */ 1074 static unsigned int fsl_asrc_get_output_fifo_size(struct fsl_asrc_pair *pair) 1075 { 1076 struct fsl_asrc *asrc = pair->asrc; 1077 enum asrc_pair_index index = pair->index; 1078 u32 val; 1079 1080 regmap_read(asrc->regmap, REG_ASRFST(index), &val); 1081 1082 val &= ASRFSTi_OUTPUT_FIFO_MASK; 1083 1084 return val >> ASRFSTi_OUTPUT_FIFO_SHIFT; 1085 } 1086 1087 static bool fsl_asrc_m2m_output_ready(struct fsl_asrc_pair *pair) 1088 { 1089 struct fsl_asrc *asrc = pair->asrc; 1090 enum asrc_pair_index index = pair->index; 1091 u32 val; 1092 int ret; 1093 1094 /* Check output fifo status if it exceeds the watermark. */ 1095 ret = regmap_read_poll_timeout(asrc->regmap, REG_ASRFST(index), val, 1096 (ASRFSTi_OUTPUT_FIFO_FILL(val) >= ASRC_M2M_OUTPUTFIFO_WML), 1097 1, 1000); 1098 1099 if (ret) { 1100 pair_warn("output is not ready\n"); 1101 return false; 1102 } 1103 1104 return true; 1105 } 1106 1107 static int fsl_asrc_m2m_prepare(struct fsl_asrc_pair *pair) 1108 { 1109 struct fsl_asrc_pair_priv *pair_priv = pair->private; 1110 struct fsl_asrc *asrc = pair->asrc; 1111 struct device *dev = &asrc->pdev->dev; 1112 struct asrc_config config; 1113 int ret; 1114 1115 /* fill config */ 1116 config.pair = pair->index; 1117 config.channel_num = pair->channels; 1118 config.input_sample_rate = pair->rate[IN]; 1119 config.output_sample_rate = pair->rate[OUT]; 1120 config.input_format = pair->sample_format[IN]; 1121 config.output_format = pair->sample_format[OUT]; 1122 config.inclk = INCLK_NONE; 1123 config.outclk = OUTCLK_ASRCK1_CLK; 1124 1125 pair_priv->config = &config; 1126 ret = fsl_asrc_config_pair(pair, true); 1127 if (ret) { 1128 dev_err(dev, "failed to config pair: %d\n", ret); 1129 return ret; 1130 } 1131 1132 pair->first_convert = 1; 1133 1134 return 0; 1135 } 1136 1137 static int fsl_asrc_m2m_start(struct fsl_asrc_pair *pair) 1138 { 1139 if (pair->first_convert) { 1140 fsl_asrc_start_pair(pair); 1141 pair->first_convert = 0; 1142 } 1143 /* 1144 * Clear DMA request during the stall state of ASRC: 1145 * During STALL state, the remaining in input fifo would never be 1146 * smaller than the input threshold while the output fifo would not 1147 * be bigger than output one. Thus the DMA request would be cleared. 1148 */ 1149 fsl_asrc_set_watermarks(pair, ASRC_FIFO_THRESHOLD_MIN, 1150 ASRC_FIFO_THRESHOLD_MAX); 1151 1152 /* Update the real input threshold to raise DMA request */ 1153 fsl_asrc_set_watermarks(pair, ASRC_M2M_INPUTFIFO_WML, 1154 ASRC_M2M_OUTPUTFIFO_WML); 1155 1156 return 0; 1157 } 1158 1159 static int fsl_asrc_m2m_stop(struct fsl_asrc_pair *pair) 1160 { 1161 if (!pair->first_convert) { 1162 fsl_asrc_stop_pair(pair); 1163 pair->first_convert = 1; 1164 } 1165 1166 return 0; 1167 } 1168 1169 /* calculate capture data length according to output data length and sample rate */ 1170 static int fsl_asrc_m2m_calc_out_len(struct fsl_asrc_pair *pair, int input_buffer_length) 1171 { 1172 unsigned int in_width, out_width; 1173 unsigned int channels = pair->channels; 1174 unsigned int in_samples, out_samples; 1175 unsigned int out_length; 1176 1177 in_width = snd_pcm_format_physical_width(pair->sample_format[IN]) / 8; 1178 out_width = snd_pcm_format_physical_width(pair->sample_format[OUT]) / 8; 1179 1180 in_samples = input_buffer_length / in_width / channels; 1181 out_samples = pair->rate[OUT] * in_samples / pair->rate[IN]; 1182 out_length = (out_samples - ASRC_OUTPUT_LAST_SAMPLE) * out_width * channels; 1183 1184 return out_length; 1185 } 1186 1187 static int fsl_asrc_m2m_get_maxburst(u8 dir, struct fsl_asrc_pair *pair) 1188 { 1189 struct fsl_asrc *asrc = pair->asrc; 1190 struct fsl_asrc_priv *asrc_priv = asrc->private; 1191 int wml = (dir == IN) ? ASRC_M2M_INPUTFIFO_WML : ASRC_M2M_OUTPUTFIFO_WML; 1192 1193 if (!asrc_priv->soc->use_edma) 1194 return wml * pair->channels; 1195 else 1196 return 1; 1197 } 1198 1199 static int fsl_asrc_m2m_get_cap(struct fsl_asrc_m2m_cap *cap) 1200 { 1201 cap->fmt_in = FSL_ASRC_FORMATS; 1202 cap->fmt_out = FSL_ASRC_FORMATS | SNDRV_PCM_FMTBIT_S8; 1203 1204 cap->rate_in = supported_asrc_rate; 1205 cap->rate_in_count = ARRAY_SIZE(supported_asrc_rate); 1206 cap->rate_out = supported_asrc_rate; 1207 cap->rate_out_count = ARRAY_SIZE(supported_asrc_rate); 1208 cap->chan_min = 1; 1209 cap->chan_max = 10; 1210 1211 return 0; 1212 } 1213 1214 static int fsl_asrc_m2m_pair_resume(struct fsl_asrc_pair *pair) 1215 { 1216 struct fsl_asrc *asrc = pair->asrc; 1217 int i; 1218 1219 for (i = 0; i < pair->channels * 4; i++) 1220 regmap_write(asrc->regmap, REG_ASRDI(pair->index), 0); 1221 1222 pair->first_convert = 1; 1223 return 0; 1224 } 1225 1226 static int fsl_asrc_runtime_resume(struct device *dev); 1227 static int fsl_asrc_runtime_suspend(struct device *dev); 1228 1229 static int fsl_asrc_probe(struct platform_device *pdev) 1230 { 1231 struct device_node *np = pdev->dev.of_node; 1232 struct fsl_asrc_priv *asrc_priv; 1233 struct fsl_asrc *asrc; 1234 struct resource *res; 1235 void __iomem *regs; 1236 int irq, ret, i; 1237 u32 asrc_fmt = 0; 1238 u32 map_idx; 1239 char tmp[16]; 1240 u32 width; 1241 1242 asrc = devm_kzalloc(&pdev->dev, sizeof(*asrc), GFP_KERNEL); 1243 if (!asrc) 1244 return -ENOMEM; 1245 1246 asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL); 1247 if (!asrc_priv) 1248 return -ENOMEM; 1249 1250 asrc->pdev = pdev; 1251 asrc->private = asrc_priv; 1252 1253 /* Get the addresses and IRQ */ 1254 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1255 if (IS_ERR(regs)) 1256 return PTR_ERR(regs); 1257 1258 asrc->paddr = res->start; 1259 1260 asrc->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_asrc_regmap_config); 1261 if (IS_ERR(asrc->regmap)) { 1262 dev_err(&pdev->dev, "failed to init regmap\n"); 1263 return PTR_ERR(asrc->regmap); 1264 } 1265 1266 irq = platform_get_irq(pdev, 0); 1267 if (irq < 0) 1268 return irq; 1269 1270 ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0, 1271 dev_name(&pdev->dev), asrc); 1272 if (ret) { 1273 dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret); 1274 return ret; 1275 } 1276 1277 asrc->mem_clk = devm_clk_get(&pdev->dev, "mem"); 1278 if (IS_ERR(asrc->mem_clk)) { 1279 dev_err(&pdev->dev, "failed to get mem clock\n"); 1280 return PTR_ERR(asrc->mem_clk); 1281 } 1282 1283 asrc->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 1284 if (IS_ERR(asrc->ipg_clk)) { 1285 dev_err(&pdev->dev, "failed to get ipg clock\n"); 1286 return PTR_ERR(asrc->ipg_clk); 1287 } 1288 1289 asrc->spba_clk = devm_clk_get(&pdev->dev, "spba"); 1290 if (IS_ERR(asrc->spba_clk)) 1291 dev_warn(&pdev->dev, "failed to get spba clock\n"); 1292 1293 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) { 1294 sprintf(tmp, "asrck_%x", i); 1295 asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp); 1296 if (IS_ERR(asrc_priv->asrck_clk[i])) { 1297 dev_err(&pdev->dev, "failed to get %s clock\n", tmp); 1298 return PTR_ERR(asrc_priv->asrck_clk[i]); 1299 } 1300 } 1301 1302 asrc_priv->soc = of_device_get_match_data(&pdev->dev); 1303 asrc->use_edma = asrc_priv->soc->use_edma; 1304 asrc->start_before_dma = asrc_priv->soc->start_before_dma; 1305 asrc->get_dma_channel = fsl_asrc_get_dma_channel; 1306 asrc->request_pair = fsl_asrc_request_pair; 1307 asrc->release_pair = fsl_asrc_release_pair; 1308 asrc->get_fifo_addr = fsl_asrc_get_fifo_addr; 1309 asrc->pair_priv_size = sizeof(struct fsl_asrc_pair_priv); 1310 1311 asrc->m2m_prepare = fsl_asrc_m2m_prepare; 1312 asrc->m2m_start = fsl_asrc_m2m_start; 1313 asrc->m2m_stop = fsl_asrc_m2m_stop; 1314 asrc->get_output_fifo_size = fsl_asrc_get_output_fifo_size; 1315 asrc->m2m_calc_out_len = fsl_asrc_m2m_calc_out_len; 1316 asrc->m2m_get_maxburst = fsl_asrc_m2m_get_maxburst; 1317 asrc->m2m_pair_resume = fsl_asrc_m2m_pair_resume; 1318 asrc->m2m_get_cap = fsl_asrc_m2m_get_cap; 1319 asrc->m2m_output_ready = fsl_asrc_m2m_output_ready; 1320 1321 if (of_device_is_compatible(np, "fsl,imx35-asrc")) { 1322 asrc_priv->clk_map[IN] = input_clk_map_imx35; 1323 asrc_priv->clk_map[OUT] = output_clk_map_imx35; 1324 } else if (of_device_is_compatible(np, "fsl,imx53-asrc")) { 1325 asrc_priv->clk_map[IN] = input_clk_map_imx53; 1326 asrc_priv->clk_map[OUT] = output_clk_map_imx53; 1327 } else if (of_device_is_compatible(np, "fsl,imx8qm-asrc") || 1328 of_device_is_compatible(np, "fsl,imx8qxp-asrc")) { 1329 ret = of_property_read_u32(np, "fsl,asrc-clk-map", &map_idx); 1330 if (ret) { 1331 dev_err(&pdev->dev, "failed to get clk map index\n"); 1332 return ret; 1333 } 1334 1335 if (map_idx > 1) { 1336 dev_err(&pdev->dev, "unsupported clk map index\n"); 1337 return -EINVAL; 1338 } 1339 if (of_device_is_compatible(np, "fsl,imx8qm-asrc")) { 1340 asrc_priv->clk_map[IN] = clk_map_imx8qm[map_idx]; 1341 asrc_priv->clk_map[OUT] = clk_map_imx8qm[map_idx]; 1342 } else { 1343 asrc_priv->clk_map[IN] = clk_map_imx8qxp[map_idx]; 1344 asrc_priv->clk_map[OUT] = clk_map_imx8qxp[map_idx]; 1345 } 1346 } else if (of_device_is_compatible(np, "fsl,imx952-asrc")) { 1347 asrc_priv->clk_map[IN] = clk_map_imx952; 1348 asrc_priv->clk_map[OUT] = clk_map_imx952; 1349 } 1350 1351 asrc->channel_avail = 10; 1352 1353 ret = of_property_read_u32(np, "fsl,asrc-rate", 1354 &asrc->asrc_rate); 1355 if (ret) { 1356 dev_err(&pdev->dev, "failed to get output rate\n"); 1357 return ret; 1358 } 1359 1360 ret = of_property_read_u32(np, "fsl,asrc-format", &asrc_fmt); 1361 asrc->asrc_format = (__force snd_pcm_format_t)asrc_fmt; 1362 if (ret) { 1363 ret = of_property_read_u32(np, "fsl,asrc-width", &width); 1364 if (ret) { 1365 dev_err(&pdev->dev, "failed to decide output format\n"); 1366 return ret; 1367 } 1368 1369 switch (width) { 1370 case 16: 1371 asrc->asrc_format = SNDRV_PCM_FORMAT_S16_LE; 1372 break; 1373 case 24: 1374 asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE; 1375 break; 1376 default: 1377 dev_warn(&pdev->dev, 1378 "unsupported width, use default S24_LE\n"); 1379 asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE; 1380 break; 1381 } 1382 } 1383 1384 if (!(FSL_ASRC_FORMATS & pcm_format_to_bits(asrc->asrc_format))) { 1385 dev_warn(&pdev->dev, "unsupported width, use default S24_LE\n"); 1386 asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE; 1387 } 1388 1389 platform_set_drvdata(pdev, asrc); 1390 spin_lock_init(&asrc->lock); 1391 pm_runtime_enable(&pdev->dev); 1392 if (!pm_runtime_enabled(&pdev->dev)) { 1393 ret = fsl_asrc_runtime_resume(&pdev->dev); 1394 if (ret) 1395 goto err_pm_disable; 1396 } 1397 1398 ret = pm_runtime_resume_and_get(&pdev->dev); 1399 if (ret < 0) 1400 goto err_pm_get_sync; 1401 1402 ret = fsl_asrc_init(asrc); 1403 if (ret) { 1404 dev_err(&pdev->dev, "failed to init asrc %d\n", ret); 1405 goto err_pm_get_sync; 1406 } 1407 1408 ret = pm_runtime_put_sync(&pdev->dev); 1409 if (ret < 0 && ret != -ENOSYS) 1410 goto err_pm_get_sync; 1411 1412 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component, 1413 &fsl_asrc_dai, 1); 1414 if (ret) { 1415 dev_err(&pdev->dev, "failed to register ASoC DAI\n"); 1416 goto err_pm_get_sync; 1417 } 1418 1419 ret = fsl_asrc_m2m_init(asrc); 1420 if (ret) { 1421 dev_err(&pdev->dev, "failed to init m2m device %d\n", ret); 1422 return ret; 1423 } 1424 1425 return 0; 1426 1427 err_pm_get_sync: 1428 if (!pm_runtime_status_suspended(&pdev->dev)) 1429 fsl_asrc_runtime_suspend(&pdev->dev); 1430 err_pm_disable: 1431 pm_runtime_disable(&pdev->dev); 1432 return ret; 1433 } 1434 1435 static void fsl_asrc_remove(struct platform_device *pdev) 1436 { 1437 struct fsl_asrc *asrc = dev_get_drvdata(&pdev->dev); 1438 1439 fsl_asrc_m2m_exit(asrc); 1440 1441 pm_runtime_disable(&pdev->dev); 1442 if (!pm_runtime_status_suspended(&pdev->dev)) 1443 fsl_asrc_runtime_suspend(&pdev->dev); 1444 } 1445 1446 static int fsl_asrc_runtime_resume(struct device *dev) 1447 { 1448 struct fsl_asrc *asrc = dev_get_drvdata(dev); 1449 struct fsl_asrc_priv *asrc_priv = asrc->private; 1450 int reg, retry = INIT_RETRY_NUM; 1451 int i, ret; 1452 u32 asrctr; 1453 1454 ret = clk_prepare_enable(asrc->mem_clk); 1455 if (ret) 1456 return ret; 1457 ret = clk_prepare_enable(asrc->ipg_clk); 1458 if (ret) 1459 goto disable_mem_clk; 1460 if (!IS_ERR(asrc->spba_clk)) { 1461 ret = clk_prepare_enable(asrc->spba_clk); 1462 if (ret) 1463 goto disable_ipg_clk; 1464 } 1465 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) { 1466 ret = clk_prepare_enable(asrc_priv->asrck_clk[i]); 1467 if (ret) 1468 goto disable_asrck_clk; 1469 } 1470 1471 /* Stop all pairs provisionally */ 1472 regmap_read(asrc->regmap, REG_ASRCTR, &asrctr); 1473 regmap_update_bits(asrc->regmap, REG_ASRCTR, 1474 ASRCTR_ASRCEi_ALL_MASK, 0); 1475 1476 /* Restore all registers */ 1477 regcache_cache_only(asrc->regmap, false); 1478 regcache_mark_dirty(asrc->regmap); 1479 regcache_sync(asrc->regmap); 1480 1481 regmap_update_bits(asrc->regmap, REG_ASRCFG, 1482 ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK | 1483 ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg); 1484 1485 /* Restart enabled pairs */ 1486 regmap_update_bits(asrc->regmap, REG_ASRCTR, 1487 ASRCTR_ASRCEi_ALL_MASK, asrctr); 1488 1489 /* Wait for status of initialization for all enabled pairs */ 1490 do { 1491 udelay(5); 1492 regmap_read(asrc->regmap, REG_ASRCFG, ®); 1493 reg = (reg >> ASRCFG_INIRQi_SHIFT(0)) & 0x7; 1494 } while ((reg != ((asrctr >> ASRCTR_ASRCEi_SHIFT(0)) & 0x7)) && --retry); 1495 1496 /* 1497 * NOTE: Doesn't treat initialization timeout as an error 1498 * Some of the pairs may success, then still can continue. 1499 */ 1500 if (!retry) { 1501 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) { 1502 if ((asrctr & ASRCTR_ASRCEi_MASK(i)) && !(reg & (1 << i))) 1503 dev_warn(dev, "Pair %c initialization isn't finished\n", 'A' + i); 1504 } 1505 } 1506 1507 return 0; 1508 1509 disable_asrck_clk: 1510 for (i--; i >= 0; i--) 1511 clk_disable_unprepare(asrc_priv->asrck_clk[i]); 1512 if (!IS_ERR(asrc->spba_clk)) 1513 clk_disable_unprepare(asrc->spba_clk); 1514 disable_ipg_clk: 1515 clk_disable_unprepare(asrc->ipg_clk); 1516 disable_mem_clk: 1517 clk_disable_unprepare(asrc->mem_clk); 1518 return ret; 1519 } 1520 1521 static int fsl_asrc_runtime_suspend(struct device *dev) 1522 { 1523 struct fsl_asrc *asrc = dev_get_drvdata(dev); 1524 struct fsl_asrc_priv *asrc_priv = asrc->private; 1525 int i; 1526 1527 regmap_read(asrc->regmap, REG_ASRCFG, 1528 &asrc_priv->regcache_cfg); 1529 1530 regcache_cache_only(asrc->regmap, true); 1531 1532 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) 1533 clk_disable_unprepare(asrc_priv->asrck_clk[i]); 1534 if (!IS_ERR(asrc->spba_clk)) 1535 clk_disable_unprepare(asrc->spba_clk); 1536 clk_disable_unprepare(asrc->ipg_clk); 1537 clk_disable_unprepare(asrc->mem_clk); 1538 1539 return 0; 1540 } 1541 1542 static int fsl_asrc_suspend(struct device *dev) 1543 { 1544 struct fsl_asrc *asrc = dev_get_drvdata(dev); 1545 int ret; 1546 1547 fsl_asrc_m2m_suspend(asrc); 1548 ret = pm_runtime_force_suspend(dev); 1549 return ret; 1550 } 1551 1552 static int fsl_asrc_resume(struct device *dev) 1553 { 1554 struct fsl_asrc *asrc = dev_get_drvdata(dev); 1555 int ret; 1556 1557 ret = pm_runtime_force_resume(dev); 1558 fsl_asrc_m2m_resume(asrc); 1559 return ret; 1560 } 1561 1562 static const struct dev_pm_ops fsl_asrc_pm = { 1563 RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL) 1564 SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume) 1565 }; 1566 1567 static const struct fsl_asrc_soc_data fsl_asrc_imx35_data = { 1568 .use_edma = false, 1569 .channel_bits = 3, 1570 }; 1571 1572 static const struct fsl_asrc_soc_data fsl_asrc_imx53_data = { 1573 .use_edma = false, 1574 .channel_bits = 4, 1575 }; 1576 1577 static const struct fsl_asrc_soc_data fsl_asrc_imx8qm_data = { 1578 .use_edma = true, 1579 .channel_bits = 4, 1580 }; 1581 1582 static const struct fsl_asrc_soc_data fsl_asrc_imx8qxp_data = { 1583 .use_edma = true, 1584 .channel_bits = 4, 1585 }; 1586 1587 static const struct fsl_asrc_soc_data fsl_asrc_imx952_data = { 1588 .use_edma = true, 1589 .channel_bits = 4, 1590 .start_before_dma = true, 1591 }; 1592 1593 static const struct of_device_id fsl_asrc_ids[] = { 1594 { .compatible = "fsl,imx35-asrc", .data = &fsl_asrc_imx35_data }, 1595 { .compatible = "fsl,imx53-asrc", .data = &fsl_asrc_imx53_data }, 1596 { .compatible = "fsl,imx8qm-asrc", .data = &fsl_asrc_imx8qm_data }, 1597 { .compatible = "fsl,imx8qxp-asrc", .data = &fsl_asrc_imx8qxp_data }, 1598 { .compatible = "fsl,imx952-asrc", .data = &fsl_asrc_imx952_data }, 1599 {} 1600 }; 1601 MODULE_DEVICE_TABLE(of, fsl_asrc_ids); 1602 1603 static struct platform_driver fsl_asrc_driver = { 1604 .probe = fsl_asrc_probe, 1605 .remove = fsl_asrc_remove, 1606 .driver = { 1607 .name = "fsl-asrc", 1608 .of_match_table = fsl_asrc_ids, 1609 .pm = pm_ptr(&fsl_asrc_pm), 1610 }, 1611 }; 1612 module_platform_driver(fsl_asrc_driver); 1613 1614 MODULE_DESCRIPTION("Freescale ASRC ASoC driver"); 1615 MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>"); 1616 MODULE_ALIAS("platform:fsl-asrc"); 1617 MODULE_LICENSE("GPL v2"); 1618