1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2018, Google LLC. 4 */ 5 6 #include <asm/msr-index.h> 7 8 #include "test_util.h" 9 #include "kvm_util.h" 10 #include "processor.h" 11 #include "vmx.h" 12 13 #define KVM_EPT_PAGE_TABLE_MIN_PADDR 0x1c0000 14 15 #define EPTP_MT_SHIFT 0 /* EPTP memtype bits 2:0 */ 16 #define EPTP_PWL_SHIFT 3 /* EPTP page walk length bits 5:3 */ 17 #define EPTP_AD_ENABLED_SHIFT 6 /* EPTP AD enabled bit 6 */ 18 19 #define EPTP_WB (X86_MEMTYPE_WB << EPTP_MT_SHIFT) 20 #define EPTP_PWL_4 (3ULL << EPTP_PWL_SHIFT) /* PWL is (levels - 1) */ 21 #define EPTP_AD_ENABLED (1ULL << EPTP_AD_ENABLED_SHIFT) 22 23 bool enable_evmcs; 24 25 struct hv_enlightened_vmcs *current_evmcs; 26 struct hv_vp_assist_page *current_vp_assist; 27 28 int vcpu_enable_evmcs(struct kvm_vcpu *vcpu) 29 { 30 uint16_t evmcs_ver; 31 32 vcpu_enable_cap(vcpu, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 33 (unsigned long)&evmcs_ver); 34 35 /* KVM should return supported EVMCS version range */ 36 TEST_ASSERT(((evmcs_ver >> 8) >= (evmcs_ver & 0xff)) && 37 (evmcs_ver & 0xff) > 0, 38 "Incorrect EVMCS version range: %x:%x", 39 evmcs_ver & 0xff, evmcs_ver >> 8); 40 41 return evmcs_ver; 42 } 43 44 void vm_enable_ept(struct kvm_vm *vm) 45 { 46 struct pte_masks pte_masks; 47 48 TEST_ASSERT(kvm_cpu_has_ept(), "KVM doesn't support nested EPT"); 49 50 /* 51 * EPTs do not have 'present' or 'user' bits, instead bit 0 is the 52 * 'readable' bit. 53 */ 54 pte_masks = (struct pte_masks) { 55 .present = 0, 56 .user = 0, 57 .readable = BIT_ULL(0), 58 .writable = BIT_ULL(1), 59 .executable = BIT_ULL(2), 60 .huge = BIT_ULL(7), 61 .accessed = BIT_ULL(8), 62 .dirty = BIT_ULL(9), 63 .nx = 0, 64 }; 65 66 /* TODO: Add support for 5-level EPT. */ 67 tdp_mmu_init(vm, 4, &pte_masks); 68 } 69 70 /* Allocate memory regions for nested VMX tests. 71 * 72 * Input Args: 73 * vm - The VM to allocate guest-virtual addresses in. 74 * 75 * Output Args: 76 * p_vmx_gva - The guest virtual address for the struct vmx_pages. 77 * 78 * Return: 79 * Pointer to structure with the addresses of the VMX areas. 80 */ 81 struct vmx_pages * 82 vcpu_alloc_vmx(struct kvm_vm *vm, vm_vaddr_t *p_vmx_gva) 83 { 84 vm_vaddr_t vmx_gva = vm_vaddr_alloc_page(vm); 85 struct vmx_pages *vmx = addr_gva2hva(vm, vmx_gva); 86 87 /* Setup of a region of guest memory for the vmxon region. */ 88 vmx->vmxon = (void *)vm_vaddr_alloc_page(vm); 89 vmx->vmxon_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmxon); 90 vmx->vmxon_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmxon); 91 92 /* Setup of a region of guest memory for a vmcs. */ 93 vmx->vmcs = (void *)vm_vaddr_alloc_page(vm); 94 vmx->vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmcs); 95 vmx->vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmcs); 96 97 /* Setup of a region of guest memory for the MSR bitmap. */ 98 vmx->msr = (void *)vm_vaddr_alloc_page(vm); 99 vmx->msr_hva = addr_gva2hva(vm, (uintptr_t)vmx->msr); 100 vmx->msr_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->msr); 101 memset(vmx->msr_hva, 0, getpagesize()); 102 103 /* Setup of a region of guest memory for the shadow VMCS. */ 104 vmx->shadow_vmcs = (void *)vm_vaddr_alloc_page(vm); 105 vmx->shadow_vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->shadow_vmcs); 106 vmx->shadow_vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->shadow_vmcs); 107 108 /* Setup of a region of guest memory for the VMREAD and VMWRITE bitmaps. */ 109 vmx->vmread = (void *)vm_vaddr_alloc_page(vm); 110 vmx->vmread_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmread); 111 vmx->vmread_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmread); 112 memset(vmx->vmread_hva, 0, getpagesize()); 113 114 vmx->vmwrite = (void *)vm_vaddr_alloc_page(vm); 115 vmx->vmwrite_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmwrite); 116 vmx->vmwrite_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmwrite); 117 memset(vmx->vmwrite_hva, 0, getpagesize()); 118 119 if (vm->stage2_mmu.pgd_created) 120 vmx->eptp_gpa = vm->stage2_mmu.pgd; 121 122 *p_vmx_gva = vmx_gva; 123 return vmx; 124 } 125 126 bool prepare_for_vmx_operation(struct vmx_pages *vmx) 127 { 128 uint64_t feature_control; 129 uint64_t required; 130 unsigned long cr0; 131 unsigned long cr4; 132 133 /* 134 * Ensure bits in CR0 and CR4 are valid in VMX operation: 135 * - Bit X is 1 in _FIXED0: bit X is fixed to 1 in CRx. 136 * - Bit X is 0 in _FIXED1: bit X is fixed to 0 in CRx. 137 */ 138 __asm__ __volatile__("mov %%cr0, %0" : "=r"(cr0) : : "memory"); 139 cr0 &= rdmsr(MSR_IA32_VMX_CR0_FIXED1); 140 cr0 |= rdmsr(MSR_IA32_VMX_CR0_FIXED0); 141 __asm__ __volatile__("mov %0, %%cr0" : : "r"(cr0) : "memory"); 142 143 __asm__ __volatile__("mov %%cr4, %0" : "=r"(cr4) : : "memory"); 144 cr4 &= rdmsr(MSR_IA32_VMX_CR4_FIXED1); 145 cr4 |= rdmsr(MSR_IA32_VMX_CR4_FIXED0); 146 /* Enable VMX operation */ 147 cr4 |= X86_CR4_VMXE; 148 __asm__ __volatile__("mov %0, %%cr4" : : "r"(cr4) : "memory"); 149 150 /* 151 * Configure IA32_FEATURE_CONTROL MSR to allow VMXON: 152 * Bit 0: Lock bit. If clear, VMXON causes a #GP. 153 * Bit 2: Enables VMXON outside of SMX operation. If clear, VMXON 154 * outside of SMX causes a #GP. 155 */ 156 required = FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 157 required |= FEAT_CTL_LOCKED; 158 feature_control = rdmsr(MSR_IA32_FEAT_CTL); 159 if ((feature_control & required) != required) 160 wrmsr(MSR_IA32_FEAT_CTL, feature_control | required); 161 162 /* Enter VMX root operation. */ 163 *(uint32_t *)(vmx->vmxon) = vmcs_revision(); 164 if (vmxon(vmx->vmxon_gpa)) 165 return false; 166 167 return true; 168 } 169 170 bool load_vmcs(struct vmx_pages *vmx) 171 { 172 /* Load a VMCS. */ 173 *(uint32_t *)(vmx->vmcs) = vmcs_revision(); 174 if (vmclear(vmx->vmcs_gpa)) 175 return false; 176 177 if (vmptrld(vmx->vmcs_gpa)) 178 return false; 179 180 /* Setup shadow VMCS, do not load it yet. */ 181 *(uint32_t *)(vmx->shadow_vmcs) = vmcs_revision() | 0x80000000ul; 182 if (vmclear(vmx->shadow_vmcs_gpa)) 183 return false; 184 185 return true; 186 } 187 188 static bool ept_vpid_cap_supported(uint64_t mask) 189 { 190 return rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & mask; 191 } 192 193 bool ept_1g_pages_supported(void) 194 { 195 return ept_vpid_cap_supported(VMX_EPT_VPID_CAP_1G_PAGES); 196 } 197 198 /* 199 * Initialize the control fields to the most basic settings possible. 200 */ 201 static inline void init_vmcs_control_fields(struct vmx_pages *vmx) 202 { 203 uint32_t sec_exec_ctl = 0; 204 205 vmwrite(VIRTUAL_PROCESSOR_ID, 0); 206 vmwrite(POSTED_INTR_NV, 0); 207 208 vmwrite(PIN_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS)); 209 210 if (vmx->eptp_gpa) { 211 uint64_t eptp = vmx->eptp_gpa | EPTP_WB | EPTP_PWL_4; 212 213 TEST_ASSERT((vmx->eptp_gpa & ~PHYSICAL_PAGE_MASK) == 0, 214 "Illegal bits set in vmx->eptp_gpa"); 215 216 if (ept_vpid_cap_supported(VMX_EPT_VPID_CAP_AD_BITS)) 217 eptp |= EPTP_AD_ENABLED; 218 219 vmwrite(EPT_POINTER, eptp); 220 sec_exec_ctl |= SECONDARY_EXEC_ENABLE_EPT; 221 } 222 223 if (!vmwrite(SECONDARY_VM_EXEC_CONTROL, sec_exec_ctl)) 224 vmwrite(CPU_BASED_VM_EXEC_CONTROL, 225 rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); 226 else { 227 vmwrite(CPU_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS)); 228 GUEST_ASSERT(!sec_exec_ctl); 229 } 230 231 vmwrite(EXCEPTION_BITMAP, 0); 232 vmwrite(PAGE_FAULT_ERROR_CODE_MASK, 0); 233 vmwrite(PAGE_FAULT_ERROR_CODE_MATCH, -1); /* Never match */ 234 vmwrite(CR3_TARGET_COUNT, 0); 235 vmwrite(VM_EXIT_CONTROLS, rdmsr(MSR_IA32_VMX_EXIT_CTLS) | 236 VM_EXIT_HOST_ADDR_SPACE_SIZE); /* 64-bit host */ 237 vmwrite(VM_EXIT_MSR_STORE_COUNT, 0); 238 vmwrite(VM_EXIT_MSR_LOAD_COUNT, 0); 239 vmwrite(VM_ENTRY_CONTROLS, rdmsr(MSR_IA32_VMX_ENTRY_CTLS) | 240 VM_ENTRY_IA32E_MODE); /* 64-bit guest */ 241 vmwrite(VM_ENTRY_MSR_LOAD_COUNT, 0); 242 vmwrite(VM_ENTRY_INTR_INFO_FIELD, 0); 243 vmwrite(TPR_THRESHOLD, 0); 244 245 vmwrite(CR0_GUEST_HOST_MASK, 0); 246 vmwrite(CR4_GUEST_HOST_MASK, 0); 247 vmwrite(CR0_READ_SHADOW, get_cr0()); 248 vmwrite(CR4_READ_SHADOW, get_cr4()); 249 250 vmwrite(MSR_BITMAP, vmx->msr_gpa); 251 vmwrite(VMREAD_BITMAP, vmx->vmread_gpa); 252 vmwrite(VMWRITE_BITMAP, vmx->vmwrite_gpa); 253 } 254 255 /* 256 * Initialize the host state fields based on the current host state, with 257 * the exception of HOST_RSP and HOST_RIP, which should be set by vmlaunch 258 * or vmresume. 259 */ 260 static inline void init_vmcs_host_state(void) 261 { 262 uint32_t exit_controls = vmreadz(VM_EXIT_CONTROLS); 263 264 vmwrite(HOST_ES_SELECTOR, get_es()); 265 vmwrite(HOST_CS_SELECTOR, get_cs()); 266 vmwrite(HOST_SS_SELECTOR, get_ss()); 267 vmwrite(HOST_DS_SELECTOR, get_ds()); 268 vmwrite(HOST_FS_SELECTOR, get_fs()); 269 vmwrite(HOST_GS_SELECTOR, get_gs()); 270 vmwrite(HOST_TR_SELECTOR, get_tr()); 271 272 if (exit_controls & VM_EXIT_LOAD_IA32_PAT) 273 vmwrite(HOST_IA32_PAT, rdmsr(MSR_IA32_CR_PAT)); 274 if (exit_controls & VM_EXIT_LOAD_IA32_EFER) 275 vmwrite(HOST_IA32_EFER, rdmsr(MSR_EFER)); 276 if (exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 277 vmwrite(HOST_IA32_PERF_GLOBAL_CTRL, 278 rdmsr(MSR_CORE_PERF_GLOBAL_CTRL)); 279 280 vmwrite(HOST_IA32_SYSENTER_CS, rdmsr(MSR_IA32_SYSENTER_CS)); 281 282 vmwrite(HOST_CR0, get_cr0()); 283 vmwrite(HOST_CR3, get_cr3()); 284 vmwrite(HOST_CR4, get_cr4()); 285 vmwrite(HOST_FS_BASE, rdmsr(MSR_FS_BASE)); 286 vmwrite(HOST_GS_BASE, rdmsr(MSR_GS_BASE)); 287 vmwrite(HOST_TR_BASE, 288 get_desc64_base((struct desc64 *)(get_gdt().address + get_tr()))); 289 vmwrite(HOST_GDTR_BASE, get_gdt().address); 290 vmwrite(HOST_IDTR_BASE, get_idt().address); 291 vmwrite(HOST_IA32_SYSENTER_ESP, rdmsr(MSR_IA32_SYSENTER_ESP)); 292 vmwrite(HOST_IA32_SYSENTER_EIP, rdmsr(MSR_IA32_SYSENTER_EIP)); 293 } 294 295 /* 296 * Initialize the guest state fields essentially as a clone of 297 * the host state fields. Some host state fields have fixed 298 * values, and we set the corresponding guest state fields accordingly. 299 */ 300 static inline void init_vmcs_guest_state(void *rip, void *rsp) 301 { 302 vmwrite(GUEST_ES_SELECTOR, vmreadz(HOST_ES_SELECTOR)); 303 vmwrite(GUEST_CS_SELECTOR, vmreadz(HOST_CS_SELECTOR)); 304 vmwrite(GUEST_SS_SELECTOR, vmreadz(HOST_SS_SELECTOR)); 305 vmwrite(GUEST_DS_SELECTOR, vmreadz(HOST_DS_SELECTOR)); 306 vmwrite(GUEST_FS_SELECTOR, vmreadz(HOST_FS_SELECTOR)); 307 vmwrite(GUEST_GS_SELECTOR, vmreadz(HOST_GS_SELECTOR)); 308 vmwrite(GUEST_LDTR_SELECTOR, 0); 309 vmwrite(GUEST_TR_SELECTOR, vmreadz(HOST_TR_SELECTOR)); 310 vmwrite(GUEST_INTR_STATUS, 0); 311 vmwrite(GUEST_PML_INDEX, 0); 312 313 vmwrite(VMCS_LINK_POINTER, -1ll); 314 vmwrite(GUEST_IA32_DEBUGCTL, 0); 315 vmwrite(GUEST_IA32_PAT, vmreadz(HOST_IA32_PAT)); 316 vmwrite(GUEST_IA32_EFER, vmreadz(HOST_IA32_EFER)); 317 vmwrite(GUEST_IA32_PERF_GLOBAL_CTRL, 318 vmreadz(HOST_IA32_PERF_GLOBAL_CTRL)); 319 320 vmwrite(GUEST_ES_LIMIT, -1); 321 vmwrite(GUEST_CS_LIMIT, -1); 322 vmwrite(GUEST_SS_LIMIT, -1); 323 vmwrite(GUEST_DS_LIMIT, -1); 324 vmwrite(GUEST_FS_LIMIT, -1); 325 vmwrite(GUEST_GS_LIMIT, -1); 326 vmwrite(GUEST_LDTR_LIMIT, -1); 327 vmwrite(GUEST_TR_LIMIT, 0x67); 328 vmwrite(GUEST_GDTR_LIMIT, 0xffff); 329 vmwrite(GUEST_IDTR_LIMIT, 0xffff); 330 vmwrite(GUEST_ES_AR_BYTES, 331 vmreadz(GUEST_ES_SELECTOR) == 0 ? 0x10000 : 0xc093); 332 vmwrite(GUEST_CS_AR_BYTES, 0xa09b); 333 vmwrite(GUEST_SS_AR_BYTES, 0xc093); 334 vmwrite(GUEST_DS_AR_BYTES, 335 vmreadz(GUEST_DS_SELECTOR) == 0 ? 0x10000 : 0xc093); 336 vmwrite(GUEST_FS_AR_BYTES, 337 vmreadz(GUEST_FS_SELECTOR) == 0 ? 0x10000 : 0xc093); 338 vmwrite(GUEST_GS_AR_BYTES, 339 vmreadz(GUEST_GS_SELECTOR) == 0 ? 0x10000 : 0xc093); 340 vmwrite(GUEST_LDTR_AR_BYTES, 0x10000); 341 vmwrite(GUEST_TR_AR_BYTES, 0x8b); 342 vmwrite(GUEST_INTERRUPTIBILITY_INFO, 0); 343 vmwrite(GUEST_ACTIVITY_STATE, 0); 344 vmwrite(GUEST_SYSENTER_CS, vmreadz(HOST_IA32_SYSENTER_CS)); 345 vmwrite(VMX_PREEMPTION_TIMER_VALUE, 0); 346 347 vmwrite(GUEST_CR0, vmreadz(HOST_CR0)); 348 vmwrite(GUEST_CR3, vmreadz(HOST_CR3)); 349 vmwrite(GUEST_CR4, vmreadz(HOST_CR4)); 350 vmwrite(GUEST_ES_BASE, 0); 351 vmwrite(GUEST_CS_BASE, 0); 352 vmwrite(GUEST_SS_BASE, 0); 353 vmwrite(GUEST_DS_BASE, 0); 354 vmwrite(GUEST_FS_BASE, vmreadz(HOST_FS_BASE)); 355 vmwrite(GUEST_GS_BASE, vmreadz(HOST_GS_BASE)); 356 vmwrite(GUEST_LDTR_BASE, 0); 357 vmwrite(GUEST_TR_BASE, vmreadz(HOST_TR_BASE)); 358 vmwrite(GUEST_GDTR_BASE, vmreadz(HOST_GDTR_BASE)); 359 vmwrite(GUEST_IDTR_BASE, vmreadz(HOST_IDTR_BASE)); 360 vmwrite(GUEST_DR7, 0x400); 361 vmwrite(GUEST_RSP, (uint64_t)rsp); 362 vmwrite(GUEST_RIP, (uint64_t)rip); 363 vmwrite(GUEST_RFLAGS, 2); 364 vmwrite(GUEST_PENDING_DBG_EXCEPTIONS, 0); 365 vmwrite(GUEST_SYSENTER_ESP, vmreadz(HOST_IA32_SYSENTER_ESP)); 366 vmwrite(GUEST_SYSENTER_EIP, vmreadz(HOST_IA32_SYSENTER_EIP)); 367 } 368 369 void prepare_vmcs(struct vmx_pages *vmx, void *guest_rip, void *guest_rsp) 370 { 371 init_vmcs_control_fields(vmx); 372 init_vmcs_host_state(); 373 init_vmcs_guest_state(guest_rip, guest_rsp); 374 } 375 376 bool kvm_cpu_has_ept(void) 377 { 378 uint64_t ctrl; 379 380 if (!kvm_cpu_has(X86_FEATURE_VMX)) 381 return false; 382 383 ctrl = kvm_get_feature_msr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) >> 32; 384 if (!(ctrl & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) 385 return false; 386 387 ctrl = kvm_get_feature_msr(MSR_IA32_VMX_PROCBASED_CTLS2) >> 32; 388 return ctrl & SECONDARY_EXEC_ENABLE_EPT; 389 } 390 391 void prepare_virtualize_apic_accesses(struct vmx_pages *vmx, struct kvm_vm *vm) 392 { 393 vmx->apic_access = (void *)vm_vaddr_alloc_page(vm); 394 vmx->apic_access_hva = addr_gva2hva(vm, (uintptr_t)vmx->apic_access); 395 vmx->apic_access_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->apic_access); 396 } 397