1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright © 2010-2015 Broadcom Corporation
4 */
5
6 #include <linux/clk.h>
7 #include <linux/module.h>
8 #include <linux/init.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/platform_device.h>
12 #include <linux/platform_data/brcmnand.h>
13 #include <linux/err.h>
14 #include <linux/completion.h>
15 #include <linux/interrupt.h>
16 #include <linux/spinlock.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/ioport.h>
19 #include <linux/bug.h>
20 #include <linux/kernel.h>
21 #include <linux/bitops.h>
22 #include <linux/mm.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/rawnand.h>
25 #include <linux/mtd/partitions.h>
26 #include <linux/of.h>
27 #include <linux/of_platform.h>
28 #include <linux/slab.h>
29 #include <linux/static_key.h>
30 #include <linux/list.h>
31 #include <linux/log2.h>
32 #include <linux/string_choices.h>
33
34 #include "brcmnand.h"
35
36 /*
37 * This flag controls if WP stays on between erase/write commands to mitigate
38 * flash corruption due to power glitches. Values:
39 * 0: NAND_WP is not used or not available
40 * 1: NAND_WP is set by default, cleared for erase/write operations
41 * 2: NAND_WP is always cleared
42 */
43 static int wp_on = 1;
44 module_param(wp_on, int, 0444);
45
46 /***********************************************************************
47 * Definitions
48 ***********************************************************************/
49
50 #define DRV_NAME "brcmnand"
51
52 #define CMD_NULL 0x00
53 #define CMD_PAGE_READ 0x01
54 #define CMD_SPARE_AREA_READ 0x02
55 #define CMD_STATUS_READ 0x03
56 #define CMD_PROGRAM_PAGE 0x04
57 #define CMD_PROGRAM_SPARE_AREA 0x05
58 #define CMD_COPY_BACK 0x06
59 #define CMD_DEVICE_ID_READ 0x07
60 #define CMD_BLOCK_ERASE 0x08
61 #define CMD_FLASH_RESET 0x09
62 #define CMD_BLOCKS_LOCK 0x0a
63 #define CMD_BLOCKS_LOCK_DOWN 0x0b
64 #define CMD_BLOCKS_UNLOCK 0x0c
65 #define CMD_READ_BLOCKS_LOCK_STATUS 0x0d
66 #define CMD_PARAMETER_READ 0x0e
67 #define CMD_PARAMETER_CHANGE_COL 0x0f
68 #define CMD_LOW_LEVEL_OP 0x10
69 #define CMD_NOT_SUPPORTED 0xff
70
71 struct brcm_nand_dma_desc {
72 u32 next_desc;
73 u32 next_desc_ext;
74 u32 cmd_irq;
75 u32 dram_addr;
76 u32 dram_addr_ext;
77 u32 tfr_len;
78 u32 total_len;
79 u32 flash_addr;
80 u32 flash_addr_ext;
81 u32 cs;
82 u32 pad2[5];
83 u32 status_valid;
84 } __packed;
85
86 /* Bitfields for brcm_nand_dma_desc::status_valid */
87 #define FLASH_DMA_ECC_ERROR (1 << 8)
88 #define FLASH_DMA_CORR_ERROR (1 << 9)
89
90 /* Bitfields for DMA_MODE */
91 #define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */
92 #define FLASH_DMA_MODE_MODE BIT(0) /* link list */
93 #define FLASH_DMA_MODE_MASK (FLASH_DMA_MODE_STOP_ON_ERROR | \
94 FLASH_DMA_MODE_MODE)
95
96 /* 512B flash cache in the NAND controller HW */
97 #define FC_SHIFT 9U
98 #define FC_BYTES 512U
99 #define FC_WORDS (FC_BYTES >> 2)
100
101 #define BRCMNAND_MIN_PAGESIZE 512
102 #define BRCMNAND_MIN_BLOCKSIZE (8 * 1024)
103 #define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024)
104
105 #define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY)
106 #define NAND_POLL_STATUS_TIMEOUT_MS 500
107
108 #define EDU_CMD_WRITE 0x00
109 #define EDU_CMD_READ 0x01
110 #define EDU_STATUS_ACTIVE BIT(0)
111 #define EDU_ERR_STATUS_ERRACK BIT(0)
112 #define EDU_DONE_MASK GENMASK(1, 0)
113
114 #define EDU_CONFIG_MODE_NAND BIT(0)
115 #define EDU_CONFIG_SWAP_BYTE BIT(1)
116 #ifdef CONFIG_CPU_BIG_ENDIAN
117 #define EDU_CONFIG_SWAP_CFG EDU_CONFIG_SWAP_BYTE
118 #else
119 #define EDU_CONFIG_SWAP_CFG 0
120 #endif
121
122 /* edu registers */
123 enum edu_reg {
124 EDU_CONFIG = 0,
125 EDU_DRAM_ADDR,
126 EDU_EXT_ADDR,
127 EDU_LENGTH,
128 EDU_CMD,
129 EDU_STOP,
130 EDU_STATUS,
131 EDU_DONE,
132 EDU_ERR_STATUS,
133 };
134
135 static const u16 edu_regs[] = {
136 [EDU_CONFIG] = 0x00,
137 [EDU_DRAM_ADDR] = 0x04,
138 [EDU_EXT_ADDR] = 0x08,
139 [EDU_LENGTH] = 0x0c,
140 [EDU_CMD] = 0x10,
141 [EDU_STOP] = 0x14,
142 [EDU_STATUS] = 0x18,
143 [EDU_DONE] = 0x1c,
144 [EDU_ERR_STATUS] = 0x20,
145 };
146
147 /* flash_dma registers */
148 enum flash_dma_reg {
149 FLASH_DMA_REVISION = 0,
150 FLASH_DMA_FIRST_DESC,
151 FLASH_DMA_FIRST_DESC_EXT,
152 FLASH_DMA_CTRL,
153 FLASH_DMA_MODE,
154 FLASH_DMA_STATUS,
155 FLASH_DMA_INTERRUPT_DESC,
156 FLASH_DMA_INTERRUPT_DESC_EXT,
157 FLASH_DMA_ERROR_STATUS,
158 FLASH_DMA_CURRENT_DESC,
159 FLASH_DMA_CURRENT_DESC_EXT,
160 };
161
162 /* flash_dma registers v0*/
163 static const u16 flash_dma_regs_v0[] = {
164 [FLASH_DMA_REVISION] = 0x00,
165 [FLASH_DMA_FIRST_DESC] = 0x04,
166 [FLASH_DMA_CTRL] = 0x08,
167 [FLASH_DMA_MODE] = 0x0c,
168 [FLASH_DMA_STATUS] = 0x10,
169 [FLASH_DMA_INTERRUPT_DESC] = 0x14,
170 [FLASH_DMA_ERROR_STATUS] = 0x18,
171 [FLASH_DMA_CURRENT_DESC] = 0x1c,
172 };
173
174 /* flash_dma registers v1*/
175 static const u16 flash_dma_regs_v1[] = {
176 [FLASH_DMA_REVISION] = 0x00,
177 [FLASH_DMA_FIRST_DESC] = 0x04,
178 [FLASH_DMA_FIRST_DESC_EXT] = 0x08,
179 [FLASH_DMA_CTRL] = 0x0c,
180 [FLASH_DMA_MODE] = 0x10,
181 [FLASH_DMA_STATUS] = 0x14,
182 [FLASH_DMA_INTERRUPT_DESC] = 0x18,
183 [FLASH_DMA_INTERRUPT_DESC_EXT] = 0x1c,
184 [FLASH_DMA_ERROR_STATUS] = 0x20,
185 [FLASH_DMA_CURRENT_DESC] = 0x24,
186 [FLASH_DMA_CURRENT_DESC_EXT] = 0x28,
187 };
188
189 /* flash_dma registers v4 */
190 static const u16 flash_dma_regs_v4[] = {
191 [FLASH_DMA_REVISION] = 0x00,
192 [FLASH_DMA_FIRST_DESC] = 0x08,
193 [FLASH_DMA_FIRST_DESC_EXT] = 0x0c,
194 [FLASH_DMA_CTRL] = 0x10,
195 [FLASH_DMA_MODE] = 0x14,
196 [FLASH_DMA_STATUS] = 0x18,
197 [FLASH_DMA_INTERRUPT_DESC] = 0x20,
198 [FLASH_DMA_INTERRUPT_DESC_EXT] = 0x24,
199 [FLASH_DMA_ERROR_STATUS] = 0x28,
200 [FLASH_DMA_CURRENT_DESC] = 0x30,
201 [FLASH_DMA_CURRENT_DESC_EXT] = 0x34,
202 };
203
204 /* Native command conversion for legacy controllers (< v5.0) */
205 static const u8 native_cmd_conv[] = {
206 [NAND_CMD_READ0] = CMD_NOT_SUPPORTED,
207 [NAND_CMD_READ1] = CMD_NOT_SUPPORTED,
208 [NAND_CMD_RNDOUT] = CMD_PARAMETER_CHANGE_COL,
209 [NAND_CMD_PAGEPROG] = CMD_NOT_SUPPORTED,
210 [NAND_CMD_READOOB] = CMD_NOT_SUPPORTED,
211 [NAND_CMD_ERASE1] = CMD_BLOCK_ERASE,
212 [NAND_CMD_STATUS] = CMD_NOT_SUPPORTED,
213 [NAND_CMD_SEQIN] = CMD_NOT_SUPPORTED,
214 [NAND_CMD_RNDIN] = CMD_NOT_SUPPORTED,
215 [NAND_CMD_READID] = CMD_DEVICE_ID_READ,
216 [NAND_CMD_ERASE2] = CMD_NULL,
217 [NAND_CMD_PARAM] = CMD_PARAMETER_READ,
218 [NAND_CMD_GET_FEATURES] = CMD_NOT_SUPPORTED,
219 [NAND_CMD_SET_FEATURES] = CMD_NOT_SUPPORTED,
220 [NAND_CMD_RESET] = CMD_NOT_SUPPORTED,
221 [NAND_CMD_READSTART] = CMD_NOT_SUPPORTED,
222 [NAND_CMD_READCACHESEQ] = CMD_NOT_SUPPORTED,
223 [NAND_CMD_READCACHEEND] = CMD_NOT_SUPPORTED,
224 [NAND_CMD_RNDOUTSTART] = CMD_NULL,
225 [NAND_CMD_CACHEDPROG] = CMD_NOT_SUPPORTED,
226 };
227
228 /* Controller feature flags */
229 enum {
230 BRCMNAND_HAS_1K_SECTORS = BIT(0),
231 BRCMNAND_HAS_PREFETCH = BIT(1),
232 BRCMNAND_HAS_CACHE_MODE = BIT(2),
233 BRCMNAND_HAS_WP = BIT(3),
234 };
235
236 struct brcmnand_host;
237
238 static DEFINE_STATIC_KEY_FALSE(brcmnand_soc_has_ops_key);
239
240 struct brcmnand_controller {
241 struct device *dev;
242 struct nand_controller controller;
243 void __iomem *nand_base;
244 void __iomem *nand_fc; /* flash cache */
245 void __iomem *flash_dma_base;
246 int irq;
247 unsigned int dma_irq;
248 int nand_version;
249
250 /* Some SoCs provide custom interrupt status register(s) */
251 struct brcmnand_soc *soc;
252
253 /* Some SoCs have a gateable clock for the controller */
254 struct clk *clk;
255
256 int cmd_pending;
257 bool dma_pending;
258 bool edu_pending;
259 struct completion done;
260 struct completion dma_done;
261 struct completion edu_done;
262
263 /* List of NAND hosts (one for each chip-select) */
264 struct list_head host_list;
265
266 /* Functions to be called from exec_op */
267 int (*check_instr)(struct nand_chip *chip,
268 const struct nand_operation *op);
269 int (*exec_instr)(struct nand_chip *chip,
270 const struct nand_operation *op);
271
272 /* EDU info, per-transaction */
273 const u16 *edu_offsets;
274 void __iomem *edu_base;
275 int edu_irq;
276 int edu_count;
277 u64 edu_dram_addr;
278 u32 edu_ext_addr;
279 u32 edu_cmd;
280 u32 edu_config;
281 int sas; /* spare area size, per flash cache */
282 int sector_size_1k;
283 u8 *oob;
284
285 /* flash_dma reg */
286 const u16 *flash_dma_offsets;
287 struct brcm_nand_dma_desc *dma_desc;
288 dma_addr_t dma_pa;
289
290 int (*dma_trans)(struct brcmnand_host *host, u64 addr, u32 *buf,
291 u8 *oob, u32 len, u8 dma_cmd);
292
293 /* in-memory cache of the FLASH_CACHE, used only for some commands */
294 u8 flash_cache[FC_BYTES];
295
296 /* Controller revision details */
297 const u16 *reg_offsets;
298 unsigned int reg_spacing; /* between CS1, CS2, ... regs */
299 const u8 *cs_offsets; /* within each chip-select */
300 const u8 *cs0_offsets; /* within CS0, if different */
301 unsigned int max_block_size;
302 const unsigned int *block_sizes;
303 unsigned int max_page_size;
304 const unsigned int *page_sizes;
305 unsigned int page_size_shift;
306 unsigned int max_oob;
307 u32 ecc_level_shift;
308 u32 features;
309
310 /* for low-power standby/resume only */
311 u32 nand_cs_nand_select;
312 u32 nand_cs_nand_xor;
313 u32 corr_stat_threshold;
314 u32 flash_dma_mode;
315 u32 flash_edu_mode;
316 bool pio_poll_mode;
317 };
318
319 struct brcmnand_cfg {
320 u64 device_size;
321 unsigned int block_size;
322 unsigned int page_size;
323 unsigned int spare_area_size;
324 unsigned int device_width;
325 unsigned int col_adr_bytes;
326 unsigned int blk_adr_bytes;
327 unsigned int ful_adr_bytes;
328 unsigned int sector_size_1k;
329 unsigned int ecc_level;
330 /* use for low-power standby/resume only */
331 u32 acc_control;
332 u32 config;
333 u32 config_ext;
334 u32 timing_1;
335 u32 timing_2;
336 };
337
338 struct brcmnand_host {
339 struct list_head node;
340
341 struct nand_chip chip;
342 struct platform_device *pdev;
343 int cs;
344
345 struct brcmnand_cfg hwcfg;
346 struct brcmnand_controller *ctrl;
347 };
348
349 enum brcmnand_reg {
350 BRCMNAND_CMD_START = 0,
351 BRCMNAND_CMD_EXT_ADDRESS,
352 BRCMNAND_CMD_ADDRESS,
353 BRCMNAND_INTFC_STATUS,
354 BRCMNAND_CS_SELECT,
355 BRCMNAND_CS_XOR,
356 BRCMNAND_LL_OP,
357 BRCMNAND_CS0_BASE,
358 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
359 BRCMNAND_CORR_THRESHOLD,
360 BRCMNAND_CORR_THRESHOLD_EXT,
361 BRCMNAND_UNCORR_COUNT,
362 BRCMNAND_CORR_COUNT,
363 BRCMNAND_READ_ERROR_COUNT,
364 BRCMNAND_CORR_EXT_ADDR,
365 BRCMNAND_CORR_ADDR,
366 BRCMNAND_UNCORR_EXT_ADDR,
367 BRCMNAND_UNCORR_ADDR,
368 BRCMNAND_SEMAPHORE,
369 BRCMNAND_ID,
370 BRCMNAND_ID_EXT,
371 BRCMNAND_LL_RDATA,
372 BRCMNAND_OOB_READ_BASE,
373 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
374 BRCMNAND_OOB_WRITE_BASE,
375 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
376 BRCMNAND_FC_BASE,
377 };
378
379 /* BRCMNAND v2.1-v2.2 */
380 static const u16 brcmnand_regs_v21[] = {
381 [BRCMNAND_CMD_START] = 0x04,
382 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
383 [BRCMNAND_CMD_ADDRESS] = 0x0c,
384 [BRCMNAND_INTFC_STATUS] = 0x5c,
385 [BRCMNAND_CS_SELECT] = 0x14,
386 [BRCMNAND_CS_XOR] = 0x18,
387 [BRCMNAND_LL_OP] = 0,
388 [BRCMNAND_CS0_BASE] = 0x40,
389 [BRCMNAND_CS1_BASE] = 0,
390 [BRCMNAND_CORR_THRESHOLD] = 0,
391 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
392 [BRCMNAND_UNCORR_COUNT] = 0,
393 [BRCMNAND_CORR_COUNT] = 0,
394 [BRCMNAND_READ_ERROR_COUNT] = 0,
395 [BRCMNAND_CORR_EXT_ADDR] = 0x60,
396 [BRCMNAND_CORR_ADDR] = 0x64,
397 [BRCMNAND_UNCORR_EXT_ADDR] = 0x68,
398 [BRCMNAND_UNCORR_ADDR] = 0x6c,
399 [BRCMNAND_SEMAPHORE] = 0x50,
400 [BRCMNAND_ID] = 0x54,
401 [BRCMNAND_ID_EXT] = 0,
402 [BRCMNAND_LL_RDATA] = 0,
403 [BRCMNAND_OOB_READ_BASE] = 0x20,
404 [BRCMNAND_OOB_READ_10_BASE] = 0,
405 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
406 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
407 [BRCMNAND_FC_BASE] = 0x200,
408 };
409
410 /* BRCMNAND v3.3-v4.0 */
411 static const u16 brcmnand_regs_v33[] = {
412 [BRCMNAND_CMD_START] = 0x04,
413 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
414 [BRCMNAND_CMD_ADDRESS] = 0x0c,
415 [BRCMNAND_INTFC_STATUS] = 0x6c,
416 [BRCMNAND_CS_SELECT] = 0x14,
417 [BRCMNAND_CS_XOR] = 0x18,
418 [BRCMNAND_LL_OP] = 0x178,
419 [BRCMNAND_CS0_BASE] = 0x40,
420 [BRCMNAND_CS1_BASE] = 0xd0,
421 [BRCMNAND_CORR_THRESHOLD] = 0x84,
422 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
423 [BRCMNAND_UNCORR_COUNT] = 0,
424 [BRCMNAND_CORR_COUNT] = 0,
425 [BRCMNAND_READ_ERROR_COUNT] = 0x80,
426 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
427 [BRCMNAND_CORR_ADDR] = 0x74,
428 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
429 [BRCMNAND_UNCORR_ADDR] = 0x7c,
430 [BRCMNAND_SEMAPHORE] = 0x58,
431 [BRCMNAND_ID] = 0x60,
432 [BRCMNAND_ID_EXT] = 0x64,
433 [BRCMNAND_LL_RDATA] = 0x17c,
434 [BRCMNAND_OOB_READ_BASE] = 0x20,
435 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
436 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
437 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
438 [BRCMNAND_FC_BASE] = 0x200,
439 };
440
441 /* BRCMNAND v5.0 */
442 static const u16 brcmnand_regs_v50[] = {
443 [BRCMNAND_CMD_START] = 0x04,
444 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
445 [BRCMNAND_CMD_ADDRESS] = 0x0c,
446 [BRCMNAND_INTFC_STATUS] = 0x6c,
447 [BRCMNAND_CS_SELECT] = 0x14,
448 [BRCMNAND_CS_XOR] = 0x18,
449 [BRCMNAND_LL_OP] = 0x178,
450 [BRCMNAND_CS0_BASE] = 0x40,
451 [BRCMNAND_CS1_BASE] = 0xd0,
452 [BRCMNAND_CORR_THRESHOLD] = 0x84,
453 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
454 [BRCMNAND_UNCORR_COUNT] = 0,
455 [BRCMNAND_CORR_COUNT] = 0,
456 [BRCMNAND_READ_ERROR_COUNT] = 0x80,
457 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
458 [BRCMNAND_CORR_ADDR] = 0x74,
459 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
460 [BRCMNAND_UNCORR_ADDR] = 0x7c,
461 [BRCMNAND_SEMAPHORE] = 0x58,
462 [BRCMNAND_ID] = 0x60,
463 [BRCMNAND_ID_EXT] = 0x64,
464 [BRCMNAND_LL_RDATA] = 0x17c,
465 [BRCMNAND_OOB_READ_BASE] = 0x20,
466 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
467 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
468 [BRCMNAND_OOB_WRITE_10_BASE] = 0x140,
469 [BRCMNAND_FC_BASE] = 0x200,
470 };
471
472 /* BRCMNAND v6.0 - v7.1 */
473 static const u16 brcmnand_regs_v60[] = {
474 [BRCMNAND_CMD_START] = 0x04,
475 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
476 [BRCMNAND_CMD_ADDRESS] = 0x0c,
477 [BRCMNAND_INTFC_STATUS] = 0x14,
478 [BRCMNAND_CS_SELECT] = 0x18,
479 [BRCMNAND_CS_XOR] = 0x1c,
480 [BRCMNAND_LL_OP] = 0x20,
481 [BRCMNAND_CS0_BASE] = 0x50,
482 [BRCMNAND_CS1_BASE] = 0,
483 [BRCMNAND_CORR_THRESHOLD] = 0xc0,
484 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4,
485 [BRCMNAND_UNCORR_COUNT] = 0xfc,
486 [BRCMNAND_CORR_COUNT] = 0x100,
487 [BRCMNAND_READ_ERROR_COUNT] = 0x104,
488 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
489 [BRCMNAND_CORR_ADDR] = 0x110,
490 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
491 [BRCMNAND_UNCORR_ADDR] = 0x118,
492 [BRCMNAND_SEMAPHORE] = 0x150,
493 [BRCMNAND_ID] = 0x194,
494 [BRCMNAND_ID_EXT] = 0x198,
495 [BRCMNAND_LL_RDATA] = 0x19c,
496 [BRCMNAND_OOB_READ_BASE] = 0x200,
497 [BRCMNAND_OOB_READ_10_BASE] = 0,
498 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
499 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
500 [BRCMNAND_FC_BASE] = 0x400,
501 };
502
503 /* BRCMNAND v7.1 */
504 static const u16 brcmnand_regs_v71[] = {
505 [BRCMNAND_CMD_START] = 0x04,
506 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
507 [BRCMNAND_CMD_ADDRESS] = 0x0c,
508 [BRCMNAND_INTFC_STATUS] = 0x14,
509 [BRCMNAND_CS_SELECT] = 0x18,
510 [BRCMNAND_CS_XOR] = 0x1c,
511 [BRCMNAND_LL_OP] = 0x20,
512 [BRCMNAND_CS0_BASE] = 0x50,
513 [BRCMNAND_CS1_BASE] = 0,
514 [BRCMNAND_CORR_THRESHOLD] = 0xdc,
515 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
516 [BRCMNAND_UNCORR_COUNT] = 0xfc,
517 [BRCMNAND_CORR_COUNT] = 0x100,
518 [BRCMNAND_READ_ERROR_COUNT] = 0x104,
519 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
520 [BRCMNAND_CORR_ADDR] = 0x110,
521 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
522 [BRCMNAND_UNCORR_ADDR] = 0x118,
523 [BRCMNAND_SEMAPHORE] = 0x150,
524 [BRCMNAND_ID] = 0x194,
525 [BRCMNAND_ID_EXT] = 0x198,
526 [BRCMNAND_LL_RDATA] = 0x19c,
527 [BRCMNAND_OOB_READ_BASE] = 0x200,
528 [BRCMNAND_OOB_READ_10_BASE] = 0,
529 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
530 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
531 [BRCMNAND_FC_BASE] = 0x400,
532 };
533
534 /* BRCMNAND v7.2 */
535 static const u16 brcmnand_regs_v72[] = {
536 [BRCMNAND_CMD_START] = 0x04,
537 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
538 [BRCMNAND_CMD_ADDRESS] = 0x0c,
539 [BRCMNAND_INTFC_STATUS] = 0x14,
540 [BRCMNAND_CS_SELECT] = 0x18,
541 [BRCMNAND_CS_XOR] = 0x1c,
542 [BRCMNAND_LL_OP] = 0x20,
543 [BRCMNAND_CS0_BASE] = 0x50,
544 [BRCMNAND_CS1_BASE] = 0,
545 [BRCMNAND_CORR_THRESHOLD] = 0xdc,
546 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
547 [BRCMNAND_UNCORR_COUNT] = 0xfc,
548 [BRCMNAND_CORR_COUNT] = 0x100,
549 [BRCMNAND_READ_ERROR_COUNT] = 0x104,
550 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
551 [BRCMNAND_CORR_ADDR] = 0x110,
552 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
553 [BRCMNAND_UNCORR_ADDR] = 0x118,
554 [BRCMNAND_SEMAPHORE] = 0x150,
555 [BRCMNAND_ID] = 0x194,
556 [BRCMNAND_ID_EXT] = 0x198,
557 [BRCMNAND_LL_RDATA] = 0x19c,
558 [BRCMNAND_OOB_READ_BASE] = 0x200,
559 [BRCMNAND_OOB_READ_10_BASE] = 0,
560 [BRCMNAND_OOB_WRITE_BASE] = 0x400,
561 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
562 [BRCMNAND_FC_BASE] = 0x600,
563 };
564
565 enum brcmnand_cs_reg {
566 BRCMNAND_CS_CFG_EXT = 0,
567 BRCMNAND_CS_CFG,
568 BRCMNAND_CS_ACC_CONTROL,
569 BRCMNAND_CS_TIMING1,
570 BRCMNAND_CS_TIMING2,
571 };
572
573 /* Per chip-select offsets for v7.1 */
574 static const u8 brcmnand_cs_offsets_v71[] = {
575 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
576 [BRCMNAND_CS_CFG_EXT] = 0x04,
577 [BRCMNAND_CS_CFG] = 0x08,
578 [BRCMNAND_CS_TIMING1] = 0x0c,
579 [BRCMNAND_CS_TIMING2] = 0x10,
580 };
581
582 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
583 static const u8 brcmnand_cs_offsets[] = {
584 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
585 [BRCMNAND_CS_CFG_EXT] = 0x04,
586 [BRCMNAND_CS_CFG] = 0x04,
587 [BRCMNAND_CS_TIMING1] = 0x08,
588 [BRCMNAND_CS_TIMING2] = 0x0c,
589 };
590
591 /* Per chip-select offset for <= v5.0 on CS0 only */
592 static const u8 brcmnand_cs_offsets_cs0[] = {
593 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
594 [BRCMNAND_CS_CFG_EXT] = 0x08,
595 [BRCMNAND_CS_CFG] = 0x08,
596 [BRCMNAND_CS_TIMING1] = 0x10,
597 [BRCMNAND_CS_TIMING2] = 0x14,
598 };
599
600 /*
601 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
602 * one config register, but once the bitfields overflowed, newer controllers
603 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
604 */
605 enum {
606 CFG_BLK_ADR_BYTES_SHIFT = 8,
607 CFG_COL_ADR_BYTES_SHIFT = 12,
608 CFG_FUL_ADR_BYTES_SHIFT = 16,
609 CFG_BUS_WIDTH_SHIFT = 23,
610 CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT),
611 CFG_DEVICE_SIZE_SHIFT = 24,
612
613 /* Only for v2.1 */
614 CFG_PAGE_SIZE_SHIFT_v2_1 = 30,
615
616 /* Only for pre-v7.1 (with no CFG_EXT register) */
617 CFG_PAGE_SIZE_SHIFT = 20,
618 CFG_BLK_SIZE_SHIFT = 28,
619
620 /* Only for v7.1+ (with CFG_EXT register) */
621 CFG_EXT_PAGE_SIZE_SHIFT = 0,
622 CFG_EXT_BLK_SIZE_SHIFT = 4,
623 };
624
625 /* BRCMNAND_INTFC_STATUS */
626 enum {
627 INTFC_FLASH_STATUS = GENMASK(7, 0),
628
629 INTFC_ERASED = BIT(27),
630 INTFC_OOB_VALID = BIT(28),
631 INTFC_CACHE_VALID = BIT(29),
632 INTFC_FLASH_READY = BIT(30),
633 INTFC_CTLR_READY = BIT(31),
634 };
635
636 /***********************************************************************
637 * NAND ACC CONTROL bitfield
638 *
639 * Some bits have remained constant throughout hardware revision, while
640 * others have shifted around.
641 ***********************************************************************/
642
643 /* Constant for all versions (where supported) */
644 enum {
645 /* See BRCMNAND_HAS_CACHE_MODE */
646 ACC_CONTROL_CACHE_MODE = BIT(22),
647
648 /* See BRCMNAND_HAS_PREFETCH */
649 ACC_CONTROL_PREFETCH = BIT(23),
650
651 ACC_CONTROL_PAGE_HIT = BIT(24),
652 ACC_CONTROL_WR_PREEMPT = BIT(25),
653 ACC_CONTROL_PARTIAL_PAGE = BIT(26),
654 ACC_CONTROL_RD_ERASED = BIT(27),
655 ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
656 ACC_CONTROL_WR_ECC = BIT(30),
657 ACC_CONTROL_RD_ECC = BIT(31),
658 };
659
660 #define ACC_CONTROL_ECC_SHIFT 16
661 /* Only for v7.2 */
662 #define ACC_CONTROL_ECC_EXT_SHIFT 13
663
664 static int brcmnand_status(struct brcmnand_host *host);
665
brcmnand_non_mmio_ops(struct brcmnand_controller * ctrl)666 static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl)
667 {
668 #if IS_ENABLED(CONFIG_MTD_NAND_BRCMNAND_BCMA)
669 return static_branch_unlikely(&brcmnand_soc_has_ops_key);
670 #else
671 return false;
672 #endif
673 }
674
nand_readreg(struct brcmnand_controller * ctrl,u32 offs)675 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
676 {
677 if (brcmnand_non_mmio_ops(ctrl))
678 return brcmnand_soc_read(ctrl->soc, offs);
679 return brcmnand_readl(ctrl->nand_base + offs);
680 }
681
nand_writereg(struct brcmnand_controller * ctrl,u32 offs,u32 val)682 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
683 u32 val)
684 {
685 if (brcmnand_non_mmio_ops(ctrl))
686 brcmnand_soc_write(ctrl->soc, val, offs);
687 else
688 brcmnand_writel(val, ctrl->nand_base + offs);
689 }
690
brcmnand_revision_init(struct brcmnand_controller * ctrl)691 static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
692 {
693 static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
694 static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
695 static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 };
696 static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 };
697 static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };
698 static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 };
699 static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 };
700
701 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
702
703 /* Only support v2.1+ */
704 if (ctrl->nand_version < 0x0201) {
705 dev_err(ctrl->dev, "version %#x not supported\n",
706 ctrl->nand_version);
707 return -ENODEV;
708 }
709
710 /* Register offsets */
711 if (ctrl->nand_version >= 0x0702)
712 ctrl->reg_offsets = brcmnand_regs_v72;
713 else if (ctrl->nand_version == 0x0701)
714 ctrl->reg_offsets = brcmnand_regs_v71;
715 else if (ctrl->nand_version >= 0x0600)
716 ctrl->reg_offsets = brcmnand_regs_v60;
717 else if (ctrl->nand_version >= 0x0500)
718 ctrl->reg_offsets = brcmnand_regs_v50;
719 else if (ctrl->nand_version >= 0x0303)
720 ctrl->reg_offsets = brcmnand_regs_v33;
721 else if (ctrl->nand_version >= 0x0201)
722 ctrl->reg_offsets = brcmnand_regs_v21;
723
724 /* Chip-select stride */
725 if (ctrl->nand_version >= 0x0701)
726 ctrl->reg_spacing = 0x14;
727 else
728 ctrl->reg_spacing = 0x10;
729
730 /* Per chip-select registers */
731 if (ctrl->nand_version >= 0x0701) {
732 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
733 } else {
734 ctrl->cs_offsets = brcmnand_cs_offsets;
735
736 /* v3.3-5.0 have a different CS0 offset layout */
737 if (ctrl->nand_version >= 0x0303 &&
738 ctrl->nand_version <= 0x0500)
739 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
740 }
741
742 /* Page / block sizes */
743 if (ctrl->nand_version >= 0x0701) {
744 /* >= v7.1 use nice power-of-2 values! */
745 ctrl->max_page_size = 16 * 1024;
746 ctrl->max_block_size = 2 * 1024 * 1024;
747 } else {
748 if (ctrl->nand_version >= 0x0304)
749 ctrl->page_sizes = page_sizes_v3_4;
750 else if (ctrl->nand_version >= 0x0202)
751 ctrl->page_sizes = page_sizes_v2_2;
752 else
753 ctrl->page_sizes = page_sizes_v2_1;
754
755 if (ctrl->nand_version >= 0x0202)
756 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT;
757 else
758 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1;
759
760 if (ctrl->nand_version >= 0x0600)
761 ctrl->block_sizes = block_sizes_v6;
762 else if (ctrl->nand_version >= 0x0400)
763 ctrl->block_sizes = block_sizes_v4;
764 else if (ctrl->nand_version >= 0x0202)
765 ctrl->block_sizes = block_sizes_v2_2;
766 else
767 ctrl->block_sizes = block_sizes_v2_1;
768
769 if (ctrl->nand_version < 0x0400) {
770 if (ctrl->nand_version < 0x0202)
771 ctrl->max_page_size = 2048;
772 else
773 ctrl->max_page_size = 4096;
774 ctrl->max_block_size = 512 * 1024;
775 }
776 }
777
778 /* Maximum spare area sector size (per 512B) */
779 if (ctrl->nand_version == 0x0702)
780 ctrl->max_oob = 128;
781 else if (ctrl->nand_version >= 0x0600)
782 ctrl->max_oob = 64;
783 else if (ctrl->nand_version >= 0x0500)
784 ctrl->max_oob = 32;
785 else
786 ctrl->max_oob = 16;
787
788 /* v6.0 and newer (except v6.1) have prefetch support */
789 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
790 ctrl->features |= BRCMNAND_HAS_PREFETCH;
791
792 /*
793 * v6.x has cache mode, but it's implemented differently. Ignore it for
794 * now.
795 */
796 if (ctrl->nand_version >= 0x0700)
797 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
798
799 if (ctrl->nand_version >= 0x0500)
800 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
801
802 if (ctrl->nand_version >= 0x0700)
803 ctrl->features |= BRCMNAND_HAS_WP;
804 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
805 ctrl->features |= BRCMNAND_HAS_WP;
806
807 /* v7.2 has different ecc level shift in the acc register */
808 if (ctrl->nand_version == 0x0702)
809 ctrl->ecc_level_shift = ACC_CONTROL_ECC_EXT_SHIFT;
810 else
811 ctrl->ecc_level_shift = ACC_CONTROL_ECC_SHIFT;
812
813 return 0;
814 }
815
brcmnand_flash_dma_revision_init(struct brcmnand_controller * ctrl)816 static void brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl)
817 {
818 /* flash_dma register offsets */
819 if (ctrl->nand_version >= 0x0703)
820 ctrl->flash_dma_offsets = flash_dma_regs_v4;
821 else if (ctrl->nand_version == 0x0602)
822 ctrl->flash_dma_offsets = flash_dma_regs_v0;
823 else
824 ctrl->flash_dma_offsets = flash_dma_regs_v1;
825 }
826
brcmnand_read_reg(struct brcmnand_controller * ctrl,enum brcmnand_reg reg)827 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
828 enum brcmnand_reg reg)
829 {
830 u16 offs = ctrl->reg_offsets[reg];
831
832 if (offs)
833 return nand_readreg(ctrl, offs);
834 else
835 return 0;
836 }
837
brcmnand_write_reg(struct brcmnand_controller * ctrl,enum brcmnand_reg reg,u32 val)838 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
839 enum brcmnand_reg reg, u32 val)
840 {
841 u16 offs = ctrl->reg_offsets[reg];
842
843 if (offs)
844 nand_writereg(ctrl, offs, val);
845 }
846
brcmnand_rmw_reg(struct brcmnand_controller * ctrl,enum brcmnand_reg reg,u32 mask,unsigned int shift,u32 val)847 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
848 enum brcmnand_reg reg, u32 mask, unsigned
849 int shift, u32 val)
850 {
851 u32 tmp = brcmnand_read_reg(ctrl, reg);
852
853 tmp &= ~mask;
854 tmp |= val << shift;
855 brcmnand_write_reg(ctrl, reg, tmp);
856 }
857
brcmnand_read_fc(struct brcmnand_controller * ctrl,int word)858 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
859 {
860 if (brcmnand_non_mmio_ops(ctrl))
861 return brcmnand_soc_read(ctrl->soc, BRCMNAND_NON_MMIO_FC_ADDR);
862 return __raw_readl(ctrl->nand_fc + word * 4);
863 }
864
brcmnand_write_fc(struct brcmnand_controller * ctrl,int word,u32 val)865 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
866 int word, u32 val)
867 {
868 if (brcmnand_non_mmio_ops(ctrl))
869 brcmnand_soc_write(ctrl->soc, val, BRCMNAND_NON_MMIO_FC_ADDR);
870 else
871 __raw_writel(val, ctrl->nand_fc + word * 4);
872 }
873
edu_writel(struct brcmnand_controller * ctrl,enum edu_reg reg,u32 val)874 static inline void edu_writel(struct brcmnand_controller *ctrl,
875 enum edu_reg reg, u32 val)
876 {
877 u16 offs = ctrl->edu_offsets[reg];
878
879 brcmnand_writel(val, ctrl->edu_base + offs);
880 }
881
edu_readl(struct brcmnand_controller * ctrl,enum edu_reg reg)882 static inline u32 edu_readl(struct brcmnand_controller *ctrl,
883 enum edu_reg reg)
884 {
885 u16 offs = ctrl->edu_offsets[reg];
886
887 return brcmnand_readl(ctrl->edu_base + offs);
888 }
889
brcmnand_read_data_bus(struct brcmnand_controller * ctrl,void __iomem * flash_cache,u32 * buffer,int fc_words)890 static inline void brcmnand_read_data_bus(struct brcmnand_controller *ctrl,
891 void __iomem *flash_cache, u32 *buffer, int fc_words)
892 {
893 struct brcmnand_soc *soc = ctrl->soc;
894 int i;
895
896 if (soc && soc->read_data_bus) {
897 soc->read_data_bus(soc, flash_cache, buffer, fc_words);
898 } else {
899 for (i = 0; i < fc_words; i++)
900 buffer[i] = brcmnand_read_fc(ctrl, i);
901 }
902 }
903
brcmnand_clear_ecc_addr(struct brcmnand_controller * ctrl)904 static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl)
905 {
906
907 /* Clear error addresses */
908 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
909 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
910 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);
911 brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);
912 }
913
brcmnand_get_uncorrecc_addr(struct brcmnand_controller * ctrl)914 static u64 brcmnand_get_uncorrecc_addr(struct brcmnand_controller *ctrl)
915 {
916 u64 err_addr;
917
918 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_UNCORR_ADDR);
919 err_addr |= ((u64)(brcmnand_read_reg(ctrl,
920 BRCMNAND_UNCORR_EXT_ADDR)
921 & 0xffff) << 32);
922
923 return err_addr;
924 }
925
brcmnand_get_correcc_addr(struct brcmnand_controller * ctrl)926 static u64 brcmnand_get_correcc_addr(struct brcmnand_controller *ctrl)
927 {
928 u64 err_addr;
929
930 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_CORR_ADDR);
931 err_addr |= ((u64)(brcmnand_read_reg(ctrl,
932 BRCMNAND_CORR_EXT_ADDR)
933 & 0xffff) << 32);
934
935 return err_addr;
936 }
937
brcmnand_set_cmd_addr(struct mtd_info * mtd,u64 addr)938 static void brcmnand_set_cmd_addr(struct mtd_info *mtd, u64 addr)
939 {
940 struct nand_chip *chip = mtd_to_nand(mtd);
941 struct brcmnand_host *host = nand_get_controller_data(chip);
942 struct brcmnand_controller *ctrl = host->ctrl;
943
944 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
945 (host->cs << 16) | ((addr >> 32) & 0xffff));
946 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
947 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
948 lower_32_bits(addr));
949 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
950 }
951
brcmnand_cs_offset(struct brcmnand_controller * ctrl,int cs,enum brcmnand_cs_reg reg)952 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
953 enum brcmnand_cs_reg reg)
954 {
955 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
956 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
957 u8 cs_offs;
958
959 if (cs == 0 && ctrl->cs0_offsets)
960 cs_offs = ctrl->cs0_offsets[reg];
961 else
962 cs_offs = ctrl->cs_offsets[reg];
963
964 if (cs && offs_cs1)
965 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
966
967 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
968 }
969
brcmnand_corr_total(struct brcmnand_controller * ctrl)970 static inline u32 brcmnand_corr_total(struct brcmnand_controller *ctrl)
971 {
972 if (ctrl->nand_version < 0x400)
973 return 0;
974 return brcmnand_read_reg(ctrl, BRCMNAND_READ_ERROR_COUNT);
975 }
976
brcmnand_wr_corr_thresh(struct brcmnand_host * host,u8 val)977 static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
978 {
979 struct brcmnand_controller *ctrl = host->ctrl;
980 unsigned int shift = 0, bits;
981 enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
982 int cs = host->cs;
983
984 if (!ctrl->reg_offsets[reg])
985 return;
986
987 if (ctrl->nand_version == 0x0702)
988 bits = 7;
989 else if (ctrl->nand_version >= 0x0600)
990 bits = 6;
991 else if (ctrl->nand_version >= 0x0500)
992 bits = 5;
993 else
994 bits = 4;
995
996 if (ctrl->nand_version >= 0x0702) {
997 if (cs >= 4)
998 reg = BRCMNAND_CORR_THRESHOLD_EXT;
999 shift = (cs % 4) * bits;
1000 } else if (ctrl->nand_version >= 0x0600) {
1001 if (cs >= 5)
1002 reg = BRCMNAND_CORR_THRESHOLD_EXT;
1003 shift = (cs % 5) * bits;
1004 }
1005 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
1006 }
1007
brcmnand_cmd_shift(struct brcmnand_controller * ctrl)1008 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
1009 {
1010 /* Kludge for the BCMA-based NAND controller which does not actually
1011 * shift the command
1012 */
1013 if (ctrl->nand_version == 0x0304 && brcmnand_non_mmio_ops(ctrl))
1014 return 0;
1015
1016 if (ctrl->nand_version < 0x0602)
1017 return 24;
1018 return 0;
1019 }
1020
brcmnand_spare_area_mask(struct brcmnand_controller * ctrl)1021 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
1022 {
1023 if (ctrl->nand_version == 0x0702)
1024 return GENMASK(7, 0);
1025 else if (ctrl->nand_version >= 0x0600)
1026 return GENMASK(6, 0);
1027 else if (ctrl->nand_version >= 0x0303)
1028 return GENMASK(5, 0);
1029 else
1030 return GENMASK(4, 0);
1031 }
1032
brcmnand_ecc_level_mask(struct brcmnand_controller * ctrl)1033 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
1034 {
1035 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
1036
1037 mask <<= ACC_CONTROL_ECC_SHIFT;
1038
1039 /* v7.2 includes additional ECC levels */
1040 if (ctrl->nand_version == 0x0702)
1041 mask |= 0x7 << ACC_CONTROL_ECC_EXT_SHIFT;
1042
1043 return mask;
1044 }
1045
brcmnand_set_ecc_enabled(struct brcmnand_host * host,int en)1046 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
1047 {
1048 struct brcmnand_controller *ctrl = host->ctrl;
1049 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
1050 u32 acc_control = nand_readreg(ctrl, offs);
1051 u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
1052
1053 if (en) {
1054 acc_control |= ecc_flags; /* enable RD/WR ECC */
1055 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
1056 acc_control |= host->hwcfg.ecc_level << ctrl->ecc_level_shift;
1057 } else {
1058 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
1059 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
1060 }
1061
1062 nand_writereg(ctrl, offs, acc_control);
1063 }
1064
brcmnand_sector_1k_shift(struct brcmnand_controller * ctrl)1065 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
1066 {
1067 if (ctrl->nand_version >= 0x0702)
1068 return 9;
1069 else if (ctrl->nand_version >= 0x0600)
1070 return 7;
1071 else if (ctrl->nand_version >= 0x0500)
1072 return 6;
1073 else
1074 return -1;
1075 }
1076
brcmnand_get_sector_size_1k(struct brcmnand_host * host)1077 static bool brcmnand_get_sector_size_1k(struct brcmnand_host *host)
1078 {
1079 struct brcmnand_controller *ctrl = host->ctrl;
1080 int sector_size_bit = brcmnand_sector_1k_shift(ctrl);
1081 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1082 BRCMNAND_CS_ACC_CONTROL);
1083 u32 acc_control;
1084
1085 if (sector_size_bit < 0)
1086 return false;
1087
1088 acc_control = nand_readreg(ctrl, acc_control_offs);
1089
1090 return ((acc_control & BIT(sector_size_bit)) != 0);
1091 }
1092
brcmnand_set_sector_size_1k(struct brcmnand_host * host,int val)1093 static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
1094 {
1095 struct brcmnand_controller *ctrl = host->ctrl;
1096 int shift = brcmnand_sector_1k_shift(ctrl);
1097 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1098 BRCMNAND_CS_ACC_CONTROL);
1099 u32 tmp;
1100
1101 if (shift < 0)
1102 return;
1103
1104 tmp = nand_readreg(ctrl, acc_control_offs);
1105 tmp &= ~(1 << shift);
1106 tmp |= (!!val) << shift;
1107 nand_writereg(ctrl, acc_control_offs, tmp);
1108 }
1109
brcmnand_get_spare_size(struct brcmnand_host * host)1110 static int brcmnand_get_spare_size(struct brcmnand_host *host)
1111 {
1112 struct brcmnand_controller *ctrl = host->ctrl;
1113 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1114 BRCMNAND_CS_ACC_CONTROL);
1115 u32 acc = nand_readreg(ctrl, acc_control_offs);
1116
1117 return (acc & brcmnand_spare_area_mask(ctrl));
1118 }
1119
brcmnand_get_ecc_settings(struct brcmnand_host * host,struct nand_chip * chip)1120 static void brcmnand_get_ecc_settings(struct brcmnand_host *host, struct nand_chip *chip)
1121 {
1122 struct brcmnand_controller *ctrl = host->ctrl;
1123 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1124 BRCMNAND_CS_ACC_CONTROL);
1125 bool sector_size_1k = brcmnand_get_sector_size_1k(host);
1126 int spare_area_size, ecc_level;
1127 u32 acc;
1128
1129 spare_area_size = brcmnand_get_spare_size(host);
1130 acc = nand_readreg(ctrl, acc_control_offs);
1131 ecc_level = (acc & brcmnand_ecc_level_mask(ctrl)) >> ctrl->ecc_level_shift;
1132 if (sector_size_1k)
1133 chip->ecc.strength = ecc_level * 2;
1134 else if (spare_area_size == 16 && ecc_level == 15)
1135 chip->ecc.strength = 1; /* hamming */
1136 else
1137 chip->ecc.strength = ecc_level;
1138
1139 if (chip->ecc.size == 0) {
1140 if (sector_size_1k)
1141 chip->ecc.size = 1024;
1142 else
1143 chip->ecc.size = 512;
1144 }
1145 }
1146
1147 /***********************************************************************
1148 * CS_NAND_SELECT
1149 ***********************************************************************/
1150
1151 enum {
1152 CS_SELECT_NAND_WP = BIT(29),
1153 CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30),
1154 };
1155
bcmnand_ctrl_poll_status(struct brcmnand_host * host,u32 mask,u32 expected_val,unsigned long timeout_ms)1156 static int bcmnand_ctrl_poll_status(struct brcmnand_host *host,
1157 u32 mask, u32 expected_val,
1158 unsigned long timeout_ms)
1159 {
1160 struct brcmnand_controller *ctrl = host->ctrl;
1161 unsigned long limit;
1162 u32 val;
1163
1164 if (!timeout_ms)
1165 timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS;
1166
1167 limit = jiffies + msecs_to_jiffies(timeout_ms);
1168 do {
1169 if (mask & INTFC_FLASH_STATUS)
1170 brcmnand_status(host);
1171
1172 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
1173 if ((val & mask) == expected_val)
1174 return 0;
1175
1176 cpu_relax();
1177 } while (time_after(limit, jiffies));
1178
1179 /*
1180 * do a final check after time out in case the CPU was busy and the driver
1181 * did not get enough time to perform the polling to avoid false alarms
1182 */
1183 if (mask & INTFC_FLASH_STATUS)
1184 brcmnand_status(host);
1185
1186 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
1187 if ((val & mask) == expected_val)
1188 return 0;
1189
1190 dev_err(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
1191 expected_val, val & mask);
1192
1193 return -ETIMEDOUT;
1194 }
1195
brcmnand_set_wp(struct brcmnand_controller * ctrl,bool en)1196 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
1197 {
1198 u32 val = en ? CS_SELECT_NAND_WP : 0;
1199
1200 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
1201 }
1202
1203 /***********************************************************************
1204 * Flash DMA
1205 ***********************************************************************/
1206
has_flash_dma(struct brcmnand_controller * ctrl)1207 static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
1208 {
1209 return ctrl->flash_dma_base;
1210 }
1211
has_edu(struct brcmnand_controller * ctrl)1212 static inline bool has_edu(struct brcmnand_controller *ctrl)
1213 {
1214 return ctrl->edu_base;
1215 }
1216
use_dma(struct brcmnand_controller * ctrl)1217 static inline bool use_dma(struct brcmnand_controller *ctrl)
1218 {
1219 return has_flash_dma(ctrl) || has_edu(ctrl);
1220 }
1221
disable_ctrl_irqs(struct brcmnand_controller * ctrl)1222 static inline void disable_ctrl_irqs(struct brcmnand_controller *ctrl)
1223 {
1224 if (ctrl->pio_poll_mode)
1225 return;
1226
1227 if (has_flash_dma(ctrl)) {
1228 ctrl->flash_dma_base = NULL;
1229 disable_irq(ctrl->dma_irq);
1230 }
1231
1232 disable_irq(ctrl->irq);
1233 ctrl->pio_poll_mode = true;
1234 }
1235
flash_dma_buf_ok(const void * buf)1236 static inline bool flash_dma_buf_ok(const void *buf)
1237 {
1238 return buf && !is_vmalloc_addr(buf) &&
1239 likely(IS_ALIGNED((uintptr_t)buf, 4));
1240 }
1241
flash_dma_writel(struct brcmnand_controller * ctrl,enum flash_dma_reg dma_reg,u32 val)1242 static inline void flash_dma_writel(struct brcmnand_controller *ctrl,
1243 enum flash_dma_reg dma_reg, u32 val)
1244 {
1245 u16 offs = ctrl->flash_dma_offsets[dma_reg];
1246
1247 brcmnand_writel(val, ctrl->flash_dma_base + offs);
1248 }
1249
flash_dma_readl(struct brcmnand_controller * ctrl,enum flash_dma_reg dma_reg)1250 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl,
1251 enum flash_dma_reg dma_reg)
1252 {
1253 u16 offs = ctrl->flash_dma_offsets[dma_reg];
1254
1255 return brcmnand_readl(ctrl->flash_dma_base + offs);
1256 }
1257
1258 /* Low-level operation types: command, address, write, or read */
1259 enum brcmnand_llop_type {
1260 LL_OP_CMD,
1261 LL_OP_ADDR,
1262 LL_OP_WR,
1263 LL_OP_RD,
1264 };
1265
1266 /***********************************************************************
1267 * Internal support functions
1268 ***********************************************************************/
1269
is_hamming_ecc(struct brcmnand_controller * ctrl,struct brcmnand_cfg * cfg)1270 static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl,
1271 struct brcmnand_cfg *cfg)
1272 {
1273 if (ctrl->nand_version <= 0x0701)
1274 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
1275 cfg->ecc_level == 15;
1276 else
1277 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 &&
1278 cfg->ecc_level == 15) ||
1279 (cfg->spare_area_size == 28 && cfg->ecc_level == 16));
1280 }
1281
1282 /*
1283 * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given
1284 * the layout/configuration.
1285 * Returns -ERRCODE on failure.
1286 */
brcmnand_hamming_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)1287 static int brcmnand_hamming_ooblayout_ecc(struct mtd_info *mtd, int section,
1288 struct mtd_oob_region *oobregion)
1289 {
1290 struct nand_chip *chip = mtd_to_nand(mtd);
1291 struct brcmnand_host *host = nand_get_controller_data(chip);
1292 struct brcmnand_cfg *cfg = &host->hwcfg;
1293 int sas = cfg->spare_area_size << cfg->sector_size_1k;
1294 int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
1295
1296 if (section >= sectors)
1297 return -ERANGE;
1298
1299 oobregion->offset = (section * sas) + 6;
1300 oobregion->length = 3;
1301
1302 return 0;
1303 }
1304
brcmnand_hamming_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)1305 static int brcmnand_hamming_ooblayout_free(struct mtd_info *mtd, int section,
1306 struct mtd_oob_region *oobregion)
1307 {
1308 struct nand_chip *chip = mtd_to_nand(mtd);
1309 struct brcmnand_host *host = nand_get_controller_data(chip);
1310 struct brcmnand_cfg *cfg = &host->hwcfg;
1311 int sas = cfg->spare_area_size << cfg->sector_size_1k;
1312 int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
1313 u32 next;
1314
1315 if (section > sectors)
1316 return -ERANGE;
1317
1318 next = (section * sas);
1319 if (section < sectors)
1320 next += 6;
1321
1322 if (section) {
1323 oobregion->offset = ((section - 1) * sas) + 9;
1324 } else {
1325 if (cfg->page_size > 512) {
1326 /* Large page NAND uses first 2 bytes for BBI */
1327 oobregion->offset = 2;
1328 } else {
1329 /* Small page NAND uses last byte before ECC for BBI */
1330 oobregion->offset = 0;
1331 next--;
1332 }
1333 }
1334
1335 oobregion->length = next - oobregion->offset;
1336
1337 return 0;
1338 }
1339
1340 static const struct mtd_ooblayout_ops brcmnand_hamming_ooblayout_ops = {
1341 .ecc = brcmnand_hamming_ooblayout_ecc,
1342 .free = brcmnand_hamming_ooblayout_free,
1343 };
1344
brcmnand_bch_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)1345 static int brcmnand_bch_ooblayout_ecc(struct mtd_info *mtd, int section,
1346 struct mtd_oob_region *oobregion)
1347 {
1348 struct nand_chip *chip = mtd_to_nand(mtd);
1349 struct brcmnand_host *host = nand_get_controller_data(chip);
1350 struct brcmnand_cfg *cfg = &host->hwcfg;
1351 int sas = cfg->spare_area_size << cfg->sector_size_1k;
1352 int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
1353
1354 if (section >= sectors)
1355 return -ERANGE;
1356
1357 oobregion->offset = ((section + 1) * sas) - chip->ecc.bytes;
1358 oobregion->length = chip->ecc.bytes;
1359
1360 return 0;
1361 }
1362
brcmnand_bch_ooblayout_free_lp(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)1363 static int brcmnand_bch_ooblayout_free_lp(struct mtd_info *mtd, int section,
1364 struct mtd_oob_region *oobregion)
1365 {
1366 struct nand_chip *chip = mtd_to_nand(mtd);
1367 struct brcmnand_host *host = nand_get_controller_data(chip);
1368 struct brcmnand_cfg *cfg = &host->hwcfg;
1369 int sas = cfg->spare_area_size << cfg->sector_size_1k;
1370 int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
1371
1372 if (section >= sectors)
1373 return -ERANGE;
1374
1375 if (sas <= chip->ecc.bytes)
1376 return 0;
1377
1378 oobregion->offset = section * sas;
1379 oobregion->length = sas - chip->ecc.bytes;
1380
1381 if (!section) {
1382 oobregion->offset++;
1383 oobregion->length--;
1384 }
1385
1386 return 0;
1387 }
1388
brcmnand_bch_ooblayout_free_sp(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)1389 static int brcmnand_bch_ooblayout_free_sp(struct mtd_info *mtd, int section,
1390 struct mtd_oob_region *oobregion)
1391 {
1392 struct nand_chip *chip = mtd_to_nand(mtd);
1393 struct brcmnand_host *host = nand_get_controller_data(chip);
1394 struct brcmnand_cfg *cfg = &host->hwcfg;
1395 int sas = cfg->spare_area_size << cfg->sector_size_1k;
1396
1397 if (section > 1 || sas - chip->ecc.bytes < 6 ||
1398 (section && sas - chip->ecc.bytes == 6))
1399 return -ERANGE;
1400
1401 if (!section) {
1402 oobregion->offset = 0;
1403 oobregion->length = 5;
1404 } else {
1405 oobregion->offset = 6;
1406 oobregion->length = sas - chip->ecc.bytes - 6;
1407 }
1408
1409 return 0;
1410 }
1411
1412 static const struct mtd_ooblayout_ops brcmnand_bch_lp_ooblayout_ops = {
1413 .ecc = brcmnand_bch_ooblayout_ecc,
1414 .free = brcmnand_bch_ooblayout_free_lp,
1415 };
1416
1417 static const struct mtd_ooblayout_ops brcmnand_bch_sp_ooblayout_ops = {
1418 .ecc = brcmnand_bch_ooblayout_ecc,
1419 .free = brcmnand_bch_ooblayout_free_sp,
1420 };
1421
brcmstb_choose_ecc_layout(struct brcmnand_host * host)1422 static int brcmstb_choose_ecc_layout(struct brcmnand_host *host)
1423 {
1424 struct brcmnand_cfg *p = &host->hwcfg;
1425 struct mtd_info *mtd = nand_to_mtd(&host->chip);
1426 struct nand_ecc_ctrl *ecc = &host->chip.ecc;
1427 unsigned int ecc_level = p->ecc_level;
1428 int sas = p->spare_area_size << p->sector_size_1k;
1429 int sectors = p->page_size / (512 << p->sector_size_1k);
1430
1431 if (p->sector_size_1k)
1432 ecc_level <<= 1;
1433
1434 if (is_hamming_ecc(host->ctrl, p)) {
1435 ecc->bytes = 3 * sectors;
1436 mtd_set_ooblayout(mtd, &brcmnand_hamming_ooblayout_ops);
1437 return 0;
1438 }
1439
1440 /*
1441 * CONTROLLER_VERSION:
1442 * < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
1443 * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
1444 * But we will just be conservative.
1445 */
1446 ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8);
1447 if (p->page_size == 512)
1448 mtd_set_ooblayout(mtd, &brcmnand_bch_sp_ooblayout_ops);
1449 else
1450 mtd_set_ooblayout(mtd, &brcmnand_bch_lp_ooblayout_ops);
1451
1452 if (ecc->bytes >= sas) {
1453 dev_err(&host->pdev->dev,
1454 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
1455 ecc->bytes, sas);
1456 return -EINVAL;
1457 }
1458
1459 return 0;
1460 }
1461
brcmnand_wp(struct mtd_info * mtd,int wp)1462 static void brcmnand_wp(struct mtd_info *mtd, int wp)
1463 {
1464 struct nand_chip *chip = mtd_to_nand(mtd);
1465 struct brcmnand_host *host = nand_get_controller_data(chip);
1466 struct brcmnand_controller *ctrl = host->ctrl;
1467
1468 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
1469 static int old_wp = -1;
1470 int ret;
1471
1472 if (old_wp != wp) {
1473 dev_dbg(ctrl->dev, "WP %s\n", str_on_off(wp));
1474 old_wp = wp;
1475 }
1476
1477 /*
1478 * make sure ctrl/flash ready before and after
1479 * changing state of #WP pin
1480 */
1481 ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY |
1482 NAND_STATUS_READY,
1483 NAND_CTRL_RDY |
1484 NAND_STATUS_READY, 0);
1485 if (ret)
1486 return;
1487
1488 brcmnand_set_wp(ctrl, wp);
1489 /* force controller operation to update internal copy of NAND chip status */
1490 brcmnand_status(host);
1491 /* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */
1492 ret = bcmnand_ctrl_poll_status(host,
1493 NAND_CTRL_RDY |
1494 NAND_STATUS_READY |
1495 NAND_STATUS_WP,
1496 NAND_CTRL_RDY |
1497 NAND_STATUS_READY |
1498 (wp ? 0 : NAND_STATUS_WP), 0);
1499
1500 if (ret)
1501 dev_err_ratelimited(&host->pdev->dev,
1502 "nand #WP expected %s\n",
1503 str_on_off(wp));
1504 }
1505 }
1506
1507 /* Helper functions for reading and writing OOB registers */
oob_reg_read(struct brcmnand_controller * ctrl,u32 offs)1508 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
1509 {
1510 u16 offset0, offset10, reg_offs;
1511
1512 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
1513 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
1514
1515 if (offs >= ctrl->max_oob)
1516 return 0x77;
1517
1518 if (offs >= 16 && offset10)
1519 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1520 else
1521 reg_offs = offset0 + (offs & ~0x03);
1522
1523 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
1524 }
1525
oob_reg_write(struct brcmnand_controller * ctrl,u32 offs,u32 data)1526 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
1527 u32 data)
1528 {
1529 u16 offset0, offset10, reg_offs;
1530
1531 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
1532 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
1533
1534 if (offs >= ctrl->max_oob)
1535 return;
1536
1537 if (offs >= 16 && offset10)
1538 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1539 else
1540 reg_offs = offset0 + (offs & ~0x03);
1541
1542 nand_writereg(ctrl, reg_offs, data);
1543 }
1544
1545 /*
1546 * read_oob_from_regs - read data from OOB registers
1547 * @ctrl: NAND controller
1548 * @i: sub-page sector index
1549 * @oob: buffer to read to
1550 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1551 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1552 */
read_oob_from_regs(struct brcmnand_controller * ctrl,int i,u8 * oob,int sas,int sector_1k)1553 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
1554 int sas, int sector_1k)
1555 {
1556 int tbytes = sas << sector_1k;
1557 int j;
1558
1559 /* Adjust OOB values for 1K sector size */
1560 if (sector_1k && (i & 0x01))
1561 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1562 tbytes = min_t(int, tbytes, ctrl->max_oob);
1563
1564 for (j = 0; j < tbytes; j++)
1565 oob[j] = oob_reg_read(ctrl, j);
1566 return tbytes;
1567 }
1568
1569 /*
1570 * write_oob_to_regs - write data to OOB registers
1571 * @i: sub-page sector index
1572 * @oob: buffer to write from
1573 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1574 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1575 */
write_oob_to_regs(struct brcmnand_controller * ctrl,int i,const u8 * oob,int sas,int sector_1k)1576 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
1577 const u8 *oob, int sas, int sector_1k)
1578 {
1579 int tbytes = sas << sector_1k;
1580 int j, k = 0;
1581 u32 last = 0xffffffff;
1582 u8 *plast = (u8 *)&last;
1583
1584 /* Adjust OOB values for 1K sector size */
1585 if (sector_1k && (i & 0x01))
1586 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1587 tbytes = min_t(int, tbytes, ctrl->max_oob);
1588
1589 /*
1590 * tbytes may not be multiple of words. Make sure we don't read out of
1591 * the boundary and stop at last word.
1592 */
1593 for (j = 0; (j + 3) < tbytes; j += 4)
1594 oob_reg_write(ctrl, j,
1595 (oob[j + 0] << 24) |
1596 (oob[j + 1] << 16) |
1597 (oob[j + 2] << 8) |
1598 (oob[j + 3] << 0));
1599
1600 /* handle the remaining bytes */
1601 while (j < tbytes)
1602 plast[k++] = oob[j++];
1603
1604 if (tbytes & 0x3)
1605 oob_reg_write(ctrl, (tbytes & ~0x3), (__force u32)cpu_to_be32(last));
1606
1607 return tbytes;
1608 }
1609
brcmnand_edu_init(struct brcmnand_controller * ctrl)1610 static void brcmnand_edu_init(struct brcmnand_controller *ctrl)
1611 {
1612 /* initialize edu */
1613 edu_writel(ctrl, EDU_ERR_STATUS, 0);
1614 edu_readl(ctrl, EDU_ERR_STATUS);
1615 edu_writel(ctrl, EDU_DONE, 0);
1616 edu_writel(ctrl, EDU_DONE, 0);
1617 edu_writel(ctrl, EDU_DONE, 0);
1618 edu_writel(ctrl, EDU_DONE, 0);
1619 edu_readl(ctrl, EDU_DONE);
1620 }
1621
1622 /* edu irq */
brcmnand_edu_irq(int irq,void * data)1623 static irqreturn_t brcmnand_edu_irq(int irq, void *data)
1624 {
1625 struct brcmnand_controller *ctrl = data;
1626
1627 if (ctrl->edu_count) {
1628 ctrl->edu_count--;
1629 while (!(edu_readl(ctrl, EDU_DONE) & EDU_DONE_MASK))
1630 udelay(1);
1631 edu_writel(ctrl, EDU_DONE, 0);
1632 edu_readl(ctrl, EDU_DONE);
1633 }
1634
1635 if (ctrl->edu_count) {
1636 ctrl->edu_dram_addr += FC_BYTES;
1637 ctrl->edu_ext_addr += FC_BYTES;
1638
1639 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr);
1640 edu_readl(ctrl, EDU_DRAM_ADDR);
1641 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr);
1642 edu_readl(ctrl, EDU_EXT_ADDR);
1643
1644 if (ctrl->oob) {
1645 if (ctrl->edu_cmd == EDU_CMD_READ) {
1646 ctrl->oob += read_oob_from_regs(ctrl,
1647 ctrl->edu_count + 1,
1648 ctrl->oob, ctrl->sas,
1649 ctrl->sector_size_1k);
1650 } else {
1651 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1652 ctrl->edu_ext_addr);
1653 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1654 ctrl->oob += write_oob_to_regs(ctrl,
1655 ctrl->edu_count,
1656 ctrl->oob, ctrl->sas,
1657 ctrl->sector_size_1k);
1658 }
1659 }
1660
1661 mb(); /* flush previous writes */
1662 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd);
1663 edu_readl(ctrl, EDU_CMD);
1664
1665 return IRQ_HANDLED;
1666 }
1667
1668 complete(&ctrl->edu_done);
1669
1670 return IRQ_HANDLED;
1671 }
1672
brcmnand_ctlrdy_irq(int irq,void * data)1673 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
1674 {
1675 struct brcmnand_controller *ctrl = data;
1676
1677 /* Discard all NAND_CTLRDY interrupts during DMA */
1678 if (ctrl->dma_pending)
1679 return IRQ_HANDLED;
1680
1681 /* check if you need to piggy back on the ctrlrdy irq */
1682 if (ctrl->edu_pending) {
1683 if (irq == ctrl->irq && ((int)ctrl->edu_irq >= 0))
1684 /* Discard interrupts while using dedicated edu irq */
1685 return IRQ_HANDLED;
1686
1687 /* no registered edu irq, call handler */
1688 return brcmnand_edu_irq(irq, data);
1689 }
1690
1691 complete(&ctrl->done);
1692 return IRQ_HANDLED;
1693 }
1694
1695 /* Handle SoC-specific interrupt hardware */
brcmnand_irq(int irq,void * data)1696 static irqreturn_t brcmnand_irq(int irq, void *data)
1697 {
1698 struct brcmnand_controller *ctrl = data;
1699
1700 if (ctrl->soc->ctlrdy_ack(ctrl->soc))
1701 return brcmnand_ctlrdy_irq(irq, data);
1702
1703 return IRQ_NONE;
1704 }
1705
brcmnand_dma_irq(int irq,void * data)1706 static irqreturn_t brcmnand_dma_irq(int irq, void *data)
1707 {
1708 struct brcmnand_controller *ctrl = data;
1709
1710 complete(&ctrl->dma_done);
1711
1712 return IRQ_HANDLED;
1713 }
1714
brcmnand_send_cmd(struct brcmnand_host * host,int cmd)1715 static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
1716 {
1717 struct brcmnand_controller *ctrl = host->ctrl;
1718 int ret;
1719 u64 cmd_addr;
1720
1721 cmd_addr = brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1722
1723 dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr);
1724
1725 /*
1726 * If we came here through _panic_write and there is a pending
1727 * command, try to wait for it. If it times out, rather than
1728 * hitting BUG_ON, just return so we don't crash while crashing.
1729 */
1730 if (oops_in_progress) {
1731 if (ctrl->cmd_pending &&
1732 bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0))
1733 return;
1734 } else
1735 BUG_ON(ctrl->cmd_pending != 0);
1736 ctrl->cmd_pending = cmd;
1737
1738 ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);
1739 WARN_ON(ret);
1740
1741 mb(); /* flush previous writes */
1742 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1743 cmd << brcmnand_cmd_shift(ctrl));
1744 }
1745
brcmstb_nand_wait_for_completion(struct nand_chip * chip)1746 static bool brcmstb_nand_wait_for_completion(struct nand_chip *chip)
1747 {
1748 struct brcmnand_host *host = nand_get_controller_data(chip);
1749 struct brcmnand_controller *ctrl = host->ctrl;
1750 struct mtd_info *mtd = nand_to_mtd(chip);
1751 bool err = false;
1752 int sts;
1753
1754 if (mtd->oops_panic_write || ctrl->irq < 0) {
1755 /* switch to interrupt polling and PIO mode */
1756 disable_ctrl_irqs(ctrl);
1757 sts = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY,
1758 NAND_CTRL_RDY, 0);
1759 err = sts < 0;
1760 } else {
1761 unsigned long timeo = msecs_to_jiffies(
1762 NAND_POLL_STATUS_TIMEOUT_MS);
1763 /* wait for completion interrupt */
1764 sts = wait_for_completion_timeout(&ctrl->done, timeo);
1765 err = !sts;
1766 }
1767
1768 return err;
1769 }
1770
brcmnand_waitfunc(struct nand_chip * chip)1771 static int brcmnand_waitfunc(struct nand_chip *chip)
1772 {
1773 struct brcmnand_host *host = nand_get_controller_data(chip);
1774 struct brcmnand_controller *ctrl = host->ctrl;
1775 bool err = false;
1776
1777 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1778 if (ctrl->cmd_pending)
1779 err = brcmstb_nand_wait_for_completion(chip);
1780
1781 ctrl->cmd_pending = 0;
1782 if (err) {
1783 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1784 >> brcmnand_cmd_shift(ctrl);
1785
1786 dev_err_ratelimited(ctrl->dev,
1787 "timeout waiting for command %#02x\n", cmd);
1788 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1789 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1790 return -ETIMEDOUT;
1791 }
1792 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1793 INTFC_FLASH_STATUS;
1794 }
1795
brcmnand_status(struct brcmnand_host * host)1796 static int brcmnand_status(struct brcmnand_host *host)
1797 {
1798 struct nand_chip *chip = &host->chip;
1799 struct mtd_info *mtd = nand_to_mtd(chip);
1800
1801 brcmnand_set_cmd_addr(mtd, 0);
1802 brcmnand_send_cmd(host, CMD_STATUS_READ);
1803
1804 return brcmnand_waitfunc(chip);
1805 }
1806
brcmnand_reset(struct brcmnand_host * host)1807 static int brcmnand_reset(struct brcmnand_host *host)
1808 {
1809 struct nand_chip *chip = &host->chip;
1810
1811 brcmnand_send_cmd(host, CMD_FLASH_RESET);
1812
1813 return brcmnand_waitfunc(chip);
1814 }
1815
1816 enum {
1817 LLOP_RE = BIT(16),
1818 LLOP_WE = BIT(17),
1819 LLOP_ALE = BIT(18),
1820 LLOP_CLE = BIT(19),
1821 LLOP_RETURN_IDLE = BIT(31),
1822
1823 LLOP_DATA_MASK = GENMASK(15, 0),
1824 };
1825
brcmnand_low_level_op(struct brcmnand_host * host,enum brcmnand_llop_type type,u32 data,bool last_op)1826 static int brcmnand_low_level_op(struct brcmnand_host *host,
1827 enum brcmnand_llop_type type, u32 data,
1828 bool last_op)
1829 {
1830 struct nand_chip *chip = &host->chip;
1831 struct brcmnand_controller *ctrl = host->ctrl;
1832 u32 tmp;
1833
1834 tmp = data & LLOP_DATA_MASK;
1835 switch (type) {
1836 case LL_OP_CMD:
1837 tmp |= LLOP_WE | LLOP_CLE;
1838 break;
1839 case LL_OP_ADDR:
1840 /* WE | ALE */
1841 tmp |= LLOP_WE | LLOP_ALE;
1842 break;
1843 case LL_OP_WR:
1844 /* WE */
1845 tmp |= LLOP_WE;
1846 break;
1847 case LL_OP_RD:
1848 /* RE */
1849 tmp |= LLOP_RE;
1850 break;
1851 }
1852 if (last_op)
1853 /* RETURN_IDLE */
1854 tmp |= LLOP_RETURN_IDLE;
1855
1856 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1857
1858 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1859 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1860
1861 brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1862 return brcmnand_waitfunc(chip);
1863 }
1864
1865 /*
1866 * Kick EDU engine
1867 */
brcmnand_edu_trans(struct brcmnand_host * host,u64 addr,u32 * buf,u8 * oob,u32 len,u8 cmd)1868 static int brcmnand_edu_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1869 u8 *oob, u32 len, u8 cmd)
1870 {
1871 struct brcmnand_controller *ctrl = host->ctrl;
1872 struct brcmnand_cfg *cfg = &host->hwcfg;
1873 unsigned long timeo = msecs_to_jiffies(200);
1874 int ret = 0;
1875 int dir = (cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
1876 u8 edu_cmd = (cmd == CMD_PAGE_READ ? EDU_CMD_READ : EDU_CMD_WRITE);
1877 unsigned int trans = len >> FC_SHIFT;
1878 dma_addr_t pa;
1879
1880 dev_dbg(ctrl->dev, "EDU %s %p:%p\n",
1881 str_read_write(edu_cmd == EDU_CMD_READ), buf, oob);
1882
1883 pa = dma_map_single(ctrl->dev, buf, len, dir);
1884 if (dma_mapping_error(ctrl->dev, pa)) {
1885 dev_err(ctrl->dev, "unable to map buffer for EDU DMA\n");
1886 return -ENOMEM;
1887 }
1888
1889 ctrl->edu_pending = true;
1890 ctrl->edu_dram_addr = pa;
1891 ctrl->edu_ext_addr = addr;
1892 ctrl->edu_cmd = edu_cmd;
1893 ctrl->edu_count = trans;
1894 ctrl->sas = cfg->spare_area_size;
1895 ctrl->oob = oob;
1896
1897 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr);
1898 edu_readl(ctrl, EDU_DRAM_ADDR);
1899 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr);
1900 edu_readl(ctrl, EDU_EXT_ADDR);
1901 edu_writel(ctrl, EDU_LENGTH, FC_BYTES);
1902 edu_readl(ctrl, EDU_LENGTH);
1903
1904 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_WRITE)) {
1905 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1906 ctrl->edu_ext_addr);
1907 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1908 ctrl->oob += write_oob_to_regs(ctrl,
1909 1,
1910 ctrl->oob, ctrl->sas,
1911 ctrl->sector_size_1k);
1912 }
1913
1914 /* Start edu engine */
1915 mb(); /* flush previous writes */
1916 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd);
1917 edu_readl(ctrl, EDU_CMD);
1918
1919 if (wait_for_completion_timeout(&ctrl->edu_done, timeo) <= 0) {
1920 dev_err(ctrl->dev,
1921 "timeout waiting for EDU; status %#x, error status %#x\n",
1922 edu_readl(ctrl, EDU_STATUS),
1923 edu_readl(ctrl, EDU_ERR_STATUS));
1924 }
1925
1926 dma_unmap_single(ctrl->dev, pa, len, dir);
1927
1928 /* read last subpage oob */
1929 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_READ)) {
1930 ctrl->oob += read_oob_from_regs(ctrl,
1931 1,
1932 ctrl->oob, ctrl->sas,
1933 ctrl->sector_size_1k);
1934 }
1935
1936 /* for program page check NAND status */
1937 if (((brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1938 INTFC_FLASH_STATUS) & NAND_STATUS_FAIL) &&
1939 edu_cmd == EDU_CMD_WRITE) {
1940 dev_info(ctrl->dev, "program failed at %llx\n",
1941 (unsigned long long)addr);
1942 ret = -EIO;
1943 }
1944
1945 /* Make sure the EDU status is clean */
1946 if (edu_readl(ctrl, EDU_STATUS) & EDU_STATUS_ACTIVE)
1947 dev_warn(ctrl->dev, "EDU still active: %#x\n",
1948 edu_readl(ctrl, EDU_STATUS));
1949
1950 if (unlikely(edu_readl(ctrl, EDU_ERR_STATUS) & EDU_ERR_STATUS_ERRACK)) {
1951 dev_warn(ctrl->dev, "EDU RBUS error at addr %llx\n",
1952 (unsigned long long)addr);
1953 ret = -EIO;
1954 }
1955
1956 ctrl->edu_pending = false;
1957 brcmnand_edu_init(ctrl);
1958 edu_writel(ctrl, EDU_STOP, 0); /* force stop */
1959 edu_readl(ctrl, EDU_STOP);
1960
1961 if (!ret && edu_cmd == EDU_CMD_READ) {
1962 u64 err_addr = 0;
1963
1964 /*
1965 * check for ECC errors here, subpage ECC errors are
1966 * retained in ECC error address register
1967 */
1968 err_addr = brcmnand_get_uncorrecc_addr(ctrl);
1969 if (!err_addr) {
1970 err_addr = brcmnand_get_correcc_addr(ctrl);
1971 if (err_addr)
1972 ret = -EUCLEAN;
1973 } else
1974 ret = -EBADMSG;
1975 }
1976
1977 return ret;
1978 }
1979
1980 /*
1981 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1982 * following ahead of time:
1983 * - Is this descriptor the beginning or end of a linked list?
1984 * - What is the (DMA) address of the next descriptor in the linked list?
1985 */
brcmnand_fill_dma_desc(struct brcmnand_host * host,struct brcm_nand_dma_desc * desc,u64 addr,dma_addr_t buf,u32 len,u8 dma_cmd,bool begin,bool end,dma_addr_t next_desc)1986 static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1987 struct brcm_nand_dma_desc *desc, u64 addr,
1988 dma_addr_t buf, u32 len, u8 dma_cmd,
1989 bool begin, bool end,
1990 dma_addr_t next_desc)
1991 {
1992 memset(desc, 0, sizeof(*desc));
1993 /* Descriptors are written in native byte order (wordwise) */
1994 desc->next_desc = lower_32_bits(next_desc);
1995 desc->next_desc_ext = upper_32_bits(next_desc);
1996 desc->cmd_irq = (dma_cmd << 24) |
1997 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1998 (!!begin) | ((!!end) << 1); /* head, tail */
1999 #ifdef CONFIG_CPU_BIG_ENDIAN
2000 desc->cmd_irq |= 0x01 << 12;
2001 #endif
2002 desc->dram_addr = lower_32_bits(buf);
2003 desc->dram_addr_ext = upper_32_bits(buf);
2004 desc->tfr_len = len;
2005 desc->total_len = len;
2006 desc->flash_addr = lower_32_bits(addr);
2007 desc->flash_addr_ext = upper_32_bits(addr);
2008 desc->cs = host->cs;
2009 desc->status_valid = 0x01;
2010 return 0;
2011 }
2012
2013 /*
2014 * Kick the FLASH_DMA engine, with a given DMA descriptor
2015 */
brcmnand_dma_run(struct brcmnand_host * host,dma_addr_t desc)2016 static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
2017 {
2018 struct brcmnand_controller *ctrl = host->ctrl;
2019 unsigned long timeo = msecs_to_jiffies(100);
2020
2021 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
2022 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
2023 if (ctrl->nand_version > 0x0602) {
2024 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT,
2025 upper_32_bits(desc));
2026 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
2027 }
2028
2029 /* Start FLASH_DMA engine */
2030 ctrl->dma_pending = true;
2031 mb(); /* flush previous writes */
2032 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
2033
2034 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
2035 dev_err(ctrl->dev,
2036 "timeout waiting for DMA; status %#x, error status %#x\n",
2037 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
2038 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
2039 }
2040 ctrl->dma_pending = false;
2041 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
2042 }
2043
brcmnand_dma_trans(struct brcmnand_host * host,u64 addr,u32 * buf,u8 * oob,u32 len,u8 dma_cmd)2044 static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
2045 u8 *oob, u32 len, u8 dma_cmd)
2046 {
2047 struct brcmnand_controller *ctrl = host->ctrl;
2048 dma_addr_t buf_pa;
2049 int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2050
2051 buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
2052 if (dma_mapping_error(ctrl->dev, buf_pa)) {
2053 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
2054 return -ENOMEM;
2055 }
2056
2057 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
2058 dma_cmd, true, true, 0);
2059
2060 brcmnand_dma_run(host, ctrl->dma_pa);
2061
2062 dma_unmap_single(ctrl->dev, buf_pa, len, dir);
2063
2064 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
2065 return -EBADMSG;
2066 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
2067 return -EUCLEAN;
2068
2069 return 0;
2070 }
2071
2072 /*
2073 * Assumes proper CS is already set
2074 */
brcmnand_read_by_pio(struct mtd_info * mtd,struct nand_chip * chip,u64 addr,unsigned int trans,u32 * buf,u8 * oob,u64 * err_addr,unsigned int * corr)2075 static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
2076 u64 addr, unsigned int trans, u32 *buf,
2077 u8 *oob, u64 *err_addr, unsigned int *corr)
2078 {
2079 struct brcmnand_host *host = nand_get_controller_data(chip);
2080 struct brcmnand_controller *ctrl = host->ctrl;
2081 int i, ret = 0;
2082 unsigned int prev_corr;
2083
2084 if (corr)
2085 *corr = 0;
2086
2087 brcmnand_clear_ecc_addr(ctrl);
2088
2089 for (i = 0; i < trans; i++, addr += FC_BYTES) {
2090 prev_corr = brcmnand_corr_total(ctrl);
2091 brcmnand_set_cmd_addr(mtd, addr);
2092 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
2093 brcmnand_send_cmd(host, CMD_PAGE_READ);
2094 brcmnand_waitfunc(chip);
2095
2096 if (likely(buf)) {
2097 brcmnand_soc_data_bus_prepare(ctrl->soc, false);
2098
2099 brcmnand_read_data_bus(ctrl, ctrl->nand_fc, buf, FC_WORDS);
2100 buf += FC_WORDS;
2101
2102 brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
2103 }
2104
2105 if (oob)
2106 oob += read_oob_from_regs(ctrl, i, oob,
2107 mtd->oobsize / trans,
2108 host->hwcfg.sector_size_1k);
2109
2110 if (ret != -EBADMSG) {
2111 *err_addr = brcmnand_get_uncorrecc_addr(ctrl);
2112
2113 if (*err_addr)
2114 ret = -EBADMSG;
2115 else {
2116 *err_addr = brcmnand_get_correcc_addr(ctrl);
2117
2118 if (*err_addr) {
2119 ret = -EUCLEAN;
2120
2121 if (corr && (brcmnand_corr_total(ctrl) - prev_corr) > *corr)
2122 *corr = brcmnand_corr_total(ctrl) - prev_corr;
2123 }
2124 }
2125 }
2126 }
2127
2128 return ret;
2129 }
2130
2131 /*
2132 * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC
2133 * error
2134 *
2135 * Because the HW ECC signals an ECC error if an erase paged has even a single
2136 * bitflip, we must check each ECC error to see if it is actually an erased
2137 * page with bitflips, not a truly corrupted page.
2138 *
2139 * On a real error, return a negative error code (-EBADMSG for ECC error), and
2140 * buf will contain raw data.
2141 * Otherwise, buf gets filled with 0xffs and return the maximum number of
2142 * bitflips-per-ECC-sector to the caller.
2143 *
2144 */
brcmstb_nand_verify_erased_page(struct mtd_info * mtd,struct nand_chip * chip,void * buf,u64 addr)2145 static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
2146 struct nand_chip *chip, void *buf, u64 addr)
2147 {
2148 struct mtd_oob_region ecc;
2149 int i;
2150 int bitflips = 0;
2151 int page = addr >> chip->page_shift;
2152 int ret;
2153 void *ecc_bytes;
2154 void *ecc_chunk;
2155
2156 if (!buf)
2157 buf = nand_get_data_buf(chip);
2158
2159 /* read without ecc for verification */
2160 ret = chip->ecc.read_page_raw(chip, buf, true, page);
2161 if (ret)
2162 return ret;
2163
2164 for (i = 0; i < chip->ecc.steps; i++) {
2165 ecc_chunk = buf + chip->ecc.size * i;
2166
2167 mtd_ooblayout_ecc(mtd, i, &ecc);
2168 ecc_bytes = chip->oob_poi + ecc.offset;
2169
2170 ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size,
2171 ecc_bytes, ecc.length,
2172 NULL, 0,
2173 chip->ecc.strength);
2174 if (ret < 0)
2175 return ret;
2176
2177 bitflips = max(bitflips, ret);
2178 }
2179
2180 return bitflips;
2181 }
2182
brcmnand_read(struct mtd_info * mtd,struct nand_chip * chip,u64 addr,unsigned int trans,u32 * buf,u8 * oob)2183 static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
2184 u64 addr, unsigned int trans, u32 *buf, u8 *oob)
2185 {
2186 struct brcmnand_host *host = nand_get_controller_data(chip);
2187 struct brcmnand_controller *ctrl = host->ctrl;
2188 u64 err_addr = 0;
2189 int err;
2190 bool retry = true;
2191 bool edu_err = false;
2192 unsigned int corrected = 0; /* max corrected bits per subpage */
2193 unsigned int prev_tot = brcmnand_corr_total(ctrl);
2194
2195 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
2196
2197 try_dmaread:
2198 brcmnand_clear_ecc_addr(ctrl);
2199
2200 if (ctrl->dma_trans && (has_edu(ctrl) || !oob) &&
2201 flash_dma_buf_ok(buf)) {
2202 err = ctrl->dma_trans(host, addr, buf, oob,
2203 trans * FC_BYTES,
2204 CMD_PAGE_READ);
2205
2206 if (err) {
2207 if (mtd_is_bitflip_or_eccerr(err))
2208 err_addr = addr;
2209 else
2210 return -EIO;
2211 }
2212
2213 if (has_edu(ctrl) && err_addr)
2214 edu_err = true;
2215
2216 } else {
2217 if (oob)
2218 memset(oob, 0x99, mtd->oobsize);
2219
2220 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
2221 oob, &err_addr, &corrected);
2222 }
2223
2224 mtd->ecc_stats.corrected += brcmnand_corr_total(ctrl) - prev_tot;
2225
2226 if (mtd_is_eccerr(err)) {
2227 /*
2228 * On controller version and 7.0, 7.1 , DMA read after a
2229 * prior PIO read that reported uncorrectable error,
2230 * the DMA engine captures this error following DMA read
2231 * cleared only on subsequent DMA read, so just retry once
2232 * to clear a possible false error reported for current DMA
2233 * read
2234 */
2235 if ((ctrl->nand_version == 0x0700) ||
2236 (ctrl->nand_version == 0x0701)) {
2237 if (retry) {
2238 retry = false;
2239 goto try_dmaread;
2240 }
2241 }
2242
2243 /*
2244 * Controller version 7.2 has hw encoder to detect erased page
2245 * bitflips, apply sw verification for older controllers only
2246 */
2247 if (ctrl->nand_version < 0x0702) {
2248 err = brcmstb_nand_verify_erased_page(mtd, chip, buf,
2249 addr);
2250 /* erased page bitflips corrected */
2251 if (err >= 0)
2252 return err;
2253 }
2254
2255 dev_err(ctrl->dev, "uncorrectable error at 0x%llx\n",
2256 (unsigned long long)err_addr);
2257 mtd->ecc_stats.failed++;
2258 /* NAND layer expects zero on ECC errors */
2259 return 0;
2260 }
2261
2262 if (mtd_is_bitflip(err)) {
2263 /* in case of EDU correctable error we read again using PIO */
2264 if (edu_err)
2265 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
2266 oob, &err_addr, &corrected);
2267
2268 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
2269 (unsigned long long)err_addr);
2270 /*
2271 * if flipped bits accumulator is not supported but we detected
2272 * a correction, increase stat by 1 to match previous behavior.
2273 */
2274 if (brcmnand_corr_total(ctrl) == prev_tot)
2275 mtd->ecc_stats.corrected++;
2276
2277 /* Always exceed the software-imposed threshold */
2278 return max(mtd->bitflip_threshold, corrected);
2279 }
2280
2281 return 0;
2282 }
2283
brcmnand_read_page(struct nand_chip * chip,uint8_t * buf,int oob_required,int page)2284 static int brcmnand_read_page(struct nand_chip *chip, uint8_t *buf,
2285 int oob_required, int page)
2286 {
2287 struct mtd_info *mtd = nand_to_mtd(chip);
2288 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
2289 u64 addr = (u64)page << chip->page_shift;
2290
2291 return brcmnand_read(mtd, chip, addr, mtd->writesize >> FC_SHIFT,
2292 (u32 *)buf, oob);
2293 }
2294
brcmnand_read_page_raw(struct nand_chip * chip,uint8_t * buf,int oob_required,int page)2295 static int brcmnand_read_page_raw(struct nand_chip *chip, uint8_t *buf,
2296 int oob_required, int page)
2297 {
2298 struct brcmnand_host *host = nand_get_controller_data(chip);
2299 struct mtd_info *mtd = nand_to_mtd(chip);
2300 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
2301 int ret;
2302 u64 addr = (u64)page << chip->page_shift;
2303
2304 brcmnand_set_ecc_enabled(host, 0);
2305 ret = brcmnand_read(mtd, chip, addr, mtd->writesize >> FC_SHIFT,
2306 (u32 *)buf, oob);
2307 brcmnand_set_ecc_enabled(host, 1);
2308 return ret;
2309 }
2310
brcmnand_read_oob(struct nand_chip * chip,int page)2311 static int brcmnand_read_oob(struct nand_chip *chip, int page)
2312 {
2313 struct mtd_info *mtd = nand_to_mtd(chip);
2314
2315 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
2316 mtd->writesize >> FC_SHIFT,
2317 NULL, (u8 *)chip->oob_poi);
2318 }
2319
brcmnand_read_oob_raw(struct nand_chip * chip,int page)2320 static int brcmnand_read_oob_raw(struct nand_chip *chip, int page)
2321 {
2322 struct mtd_info *mtd = nand_to_mtd(chip);
2323 struct brcmnand_host *host = nand_get_controller_data(chip);
2324
2325 brcmnand_set_ecc_enabled(host, 0);
2326 brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
2327 mtd->writesize >> FC_SHIFT,
2328 NULL, (u8 *)chip->oob_poi);
2329 brcmnand_set_ecc_enabled(host, 1);
2330 return 0;
2331 }
2332
brcmnand_write(struct mtd_info * mtd,struct nand_chip * chip,u64 addr,const u32 * buf,u8 * oob)2333 static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
2334 u64 addr, const u32 *buf, u8 *oob)
2335 {
2336 struct brcmnand_host *host = nand_get_controller_data(chip);
2337 struct brcmnand_controller *ctrl = host->ctrl;
2338 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
2339 int status, ret = 0;
2340
2341 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
2342
2343 if (unlikely((unsigned long)buf & 0x03)) {
2344 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
2345 buf = (u32 *)((unsigned long)buf & ~0x03);
2346 }
2347
2348 brcmnand_wp(mtd, 0);
2349
2350 for (i = 0; i < ctrl->max_oob; i += 4)
2351 oob_reg_write(ctrl, i, 0xffffffff);
2352
2353 if (mtd->oops_panic_write) {
2354 /* switch to interrupt polling and PIO mode */
2355 disable_ctrl_irqs(ctrl);
2356 } else if (use_dma(ctrl) && (has_edu(ctrl) || !oob) && flash_dma_buf_ok(buf)) {
2357 if (ctrl->dma_trans(host, addr, (u32 *)buf, oob, mtd->writesize,
2358 CMD_PROGRAM_PAGE))
2359 ret = -EIO;
2360
2361 goto out;
2362 }
2363
2364 for (i = 0; i < trans; i++, addr += FC_BYTES) {
2365 /* full address MUST be set before populating FC */
2366 brcmnand_set_cmd_addr(mtd, addr);
2367
2368 if (buf) {
2369 brcmnand_soc_data_bus_prepare(ctrl->soc, false);
2370
2371 for (j = 0; j < FC_WORDS; j++, buf++)
2372 brcmnand_write_fc(ctrl, j, *buf);
2373
2374 brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
2375 } else if (oob) {
2376 for (j = 0; j < FC_WORDS; j++)
2377 brcmnand_write_fc(ctrl, j, 0xffffffff);
2378 }
2379
2380 if (oob) {
2381 oob += write_oob_to_regs(ctrl, i, oob,
2382 mtd->oobsize / trans,
2383 host->hwcfg.sector_size_1k);
2384 }
2385
2386 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
2387 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
2388 status = brcmnand_waitfunc(chip);
2389
2390 if (status < 0) {
2391 ret = status;
2392 goto out;
2393 }
2394
2395 if (status & NAND_STATUS_FAIL) {
2396 dev_info(ctrl->dev, "program failed at %llx\n",
2397 (unsigned long long)addr);
2398 ret = -EIO;
2399 goto out;
2400 }
2401 }
2402 out:
2403 brcmnand_wp(mtd, 1);
2404 return ret;
2405 }
2406
brcmnand_write_page(struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2407 static int brcmnand_write_page(struct nand_chip *chip, const uint8_t *buf,
2408 int oob_required, int page)
2409 {
2410 struct mtd_info *mtd = nand_to_mtd(chip);
2411 void *oob = oob_required ? chip->oob_poi : NULL;
2412 u64 addr = (u64)page << chip->page_shift;
2413
2414 return brcmnand_write(mtd, chip, addr, (const u32 *)buf, oob);
2415 }
2416
brcmnand_write_page_raw(struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)2417 static int brcmnand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
2418 int oob_required, int page)
2419 {
2420 struct mtd_info *mtd = nand_to_mtd(chip);
2421 struct brcmnand_host *host = nand_get_controller_data(chip);
2422 void *oob = oob_required ? chip->oob_poi : NULL;
2423 u64 addr = (u64)page << chip->page_shift;
2424 int ret = 0;
2425
2426 brcmnand_set_ecc_enabled(host, 0);
2427 ret = brcmnand_write(mtd, chip, addr, (const u32 *)buf, oob);
2428 brcmnand_set_ecc_enabled(host, 1);
2429
2430 return ret;
2431 }
2432
brcmnand_write_oob(struct nand_chip * chip,int page)2433 static int brcmnand_write_oob(struct nand_chip *chip, int page)
2434 {
2435 return brcmnand_write(nand_to_mtd(chip), chip,
2436 (u64)page << chip->page_shift, NULL,
2437 chip->oob_poi);
2438 }
2439
brcmnand_write_oob_raw(struct nand_chip * chip,int page)2440 static int brcmnand_write_oob_raw(struct nand_chip *chip, int page)
2441 {
2442 struct mtd_info *mtd = nand_to_mtd(chip);
2443 struct brcmnand_host *host = nand_get_controller_data(chip);
2444 int ret;
2445
2446 brcmnand_set_ecc_enabled(host, 0);
2447 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
2448 (u8 *)chip->oob_poi);
2449 brcmnand_set_ecc_enabled(host, 1);
2450
2451 return ret;
2452 }
2453
brcmnand_exec_instr(struct brcmnand_host * host,int i,const struct nand_operation * op)2454 static int brcmnand_exec_instr(struct brcmnand_host *host, int i,
2455 const struct nand_operation *op)
2456 {
2457 const struct nand_op_instr *instr = &op->instrs[i];
2458 struct brcmnand_controller *ctrl = host->ctrl;
2459 const u8 *out;
2460 bool last_op;
2461 int ret = 0;
2462 u8 *in;
2463
2464 /*
2465 * The controller needs to be aware of the last command in the operation
2466 * (WAITRDY excepted).
2467 */
2468 last_op = ((i == (op->ninstrs - 1)) && (instr->type != NAND_OP_WAITRDY_INSTR)) ||
2469 ((i == (op->ninstrs - 2)) && (op->instrs[i + 1].type == NAND_OP_WAITRDY_INSTR));
2470
2471 switch (instr->type) {
2472 case NAND_OP_CMD_INSTR:
2473 brcmnand_low_level_op(host, LL_OP_CMD, instr->ctx.cmd.opcode, last_op);
2474 break;
2475
2476 case NAND_OP_ADDR_INSTR:
2477 for (i = 0; i < instr->ctx.addr.naddrs; i++)
2478 brcmnand_low_level_op(host, LL_OP_ADDR, instr->ctx.addr.addrs[i],
2479 last_op && (i == (instr->ctx.addr.naddrs - 1)));
2480 break;
2481
2482 case NAND_OP_DATA_IN_INSTR:
2483 in = instr->ctx.data.buf.in;
2484 for (i = 0; i < instr->ctx.data.len; i++) {
2485 brcmnand_low_level_op(host, LL_OP_RD, 0,
2486 last_op && (i == (instr->ctx.data.len - 1)));
2487 in[i] = brcmnand_read_reg(host->ctrl, BRCMNAND_LL_RDATA);
2488 }
2489 break;
2490
2491 case NAND_OP_DATA_OUT_INSTR:
2492 out = instr->ctx.data.buf.out;
2493 for (i = 0; i < instr->ctx.data.len; i++)
2494 brcmnand_low_level_op(host, LL_OP_WR, out[i],
2495 last_op && (i == (instr->ctx.data.len - 1)));
2496 break;
2497
2498 case NAND_OP_WAITRDY_INSTR:
2499 ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);
2500 break;
2501
2502 default:
2503 dev_err(ctrl->dev, "unsupported instruction type: %d\n",
2504 instr->type);
2505 ret = -EINVAL;
2506 break;
2507 }
2508
2509 return ret;
2510 }
2511
brcmnand_op_is_status(const struct nand_operation * op)2512 static int brcmnand_op_is_status(const struct nand_operation *op)
2513 {
2514 if (op->ninstrs == 2 &&
2515 op->instrs[0].type == NAND_OP_CMD_INSTR &&
2516 op->instrs[0].ctx.cmd.opcode == NAND_CMD_STATUS &&
2517 op->instrs[1].type == NAND_OP_DATA_IN_INSTR)
2518 return 1;
2519
2520 return 0;
2521 }
2522
brcmnand_op_is_reset(const struct nand_operation * op)2523 static int brcmnand_op_is_reset(const struct nand_operation *op)
2524 {
2525 if (op->ninstrs == 2 &&
2526 op->instrs[0].type == NAND_OP_CMD_INSTR &&
2527 op->instrs[0].ctx.cmd.opcode == NAND_CMD_RESET &&
2528 op->instrs[1].type == NAND_OP_WAITRDY_INSTR)
2529 return 1;
2530
2531 return 0;
2532 }
2533
brcmnand_check_instructions(struct nand_chip * chip,const struct nand_operation * op)2534 static int brcmnand_check_instructions(struct nand_chip *chip,
2535 const struct nand_operation *op)
2536 {
2537 return 0;
2538 }
2539
brcmnand_exec_instructions(struct nand_chip * chip,const struct nand_operation * op)2540 static int brcmnand_exec_instructions(struct nand_chip *chip,
2541 const struct nand_operation *op)
2542 {
2543 struct brcmnand_host *host = nand_get_controller_data(chip);
2544 unsigned int i;
2545 int ret = 0;
2546
2547 for (i = 0; i < op->ninstrs; i++) {
2548 ret = brcmnand_exec_instr(host, i, op);
2549 if (ret)
2550 break;
2551 }
2552
2553 return ret;
2554 }
2555
brcmnand_check_instructions_legacy(struct nand_chip * chip,const struct nand_operation * op)2556 static int brcmnand_check_instructions_legacy(struct nand_chip *chip,
2557 const struct nand_operation *op)
2558 {
2559 const struct nand_op_instr *instr;
2560 unsigned int i;
2561 u8 cmd;
2562
2563 for (i = 0; i < op->ninstrs; i++) {
2564 instr = &op->instrs[i];
2565
2566 switch (instr->type) {
2567 case NAND_OP_CMD_INSTR:
2568 cmd = native_cmd_conv[instr->ctx.cmd.opcode];
2569 if (cmd == CMD_NOT_SUPPORTED)
2570 return -EOPNOTSUPP;
2571 break;
2572 case NAND_OP_ADDR_INSTR:
2573 case NAND_OP_DATA_IN_INSTR:
2574 case NAND_OP_WAITRDY_INSTR:
2575 break;
2576 default:
2577 return -EOPNOTSUPP;
2578 }
2579 }
2580
2581 return 0;
2582 }
2583
brcmnand_exec_instructions_legacy(struct nand_chip * chip,const struct nand_operation * op)2584 static int brcmnand_exec_instructions_legacy(struct nand_chip *chip,
2585 const struct nand_operation *op)
2586 {
2587 struct mtd_info *mtd = nand_to_mtd(chip);
2588 struct brcmnand_host *host = nand_get_controller_data(chip);
2589 struct brcmnand_controller *ctrl = host->ctrl;
2590 const struct nand_op_instr *instr;
2591 unsigned int i, j;
2592 u8 cmd = CMD_NULL, last_cmd = CMD_NULL;
2593 int ret = 0;
2594 u64 last_addr;
2595
2596 for (i = 0; i < op->ninstrs; i++) {
2597 instr = &op->instrs[i];
2598
2599 if (instr->type == NAND_OP_CMD_INSTR) {
2600 cmd = native_cmd_conv[instr->ctx.cmd.opcode];
2601 if (cmd == CMD_NOT_SUPPORTED) {
2602 dev_err(ctrl->dev, "unsupported cmd=%d\n",
2603 instr->ctx.cmd.opcode);
2604 ret = -EOPNOTSUPP;
2605 break;
2606 }
2607 } else if (instr->type == NAND_OP_ADDR_INSTR) {
2608 u64 addr = 0;
2609
2610 if (cmd == CMD_NULL)
2611 continue;
2612
2613 if (instr->ctx.addr.naddrs > 8) {
2614 dev_err(ctrl->dev, "unsupported naddrs=%u\n",
2615 instr->ctx.addr.naddrs);
2616 ret = -EOPNOTSUPP;
2617 break;
2618 }
2619
2620 for (j = 0; j < instr->ctx.addr.naddrs; j++)
2621 addr |= (instr->ctx.addr.addrs[j]) << (j << 3);
2622
2623 if (cmd == CMD_BLOCK_ERASE)
2624 addr <<= chip->page_shift;
2625 else if (cmd == CMD_PARAMETER_CHANGE_COL)
2626 addr &= ~((u64)(FC_BYTES - 1));
2627
2628 brcmnand_set_cmd_addr(mtd, addr);
2629 brcmnand_send_cmd(host, cmd);
2630 last_addr = addr;
2631 last_cmd = cmd;
2632 cmd = CMD_NULL;
2633 brcmnand_waitfunc(chip);
2634
2635 if (last_cmd == CMD_PARAMETER_READ ||
2636 last_cmd == CMD_PARAMETER_CHANGE_COL) {
2637 /* Copy flash cache word-wise */
2638 u32 *flash_cache = (u32 *)ctrl->flash_cache;
2639
2640 brcmnand_soc_data_bus_prepare(ctrl->soc, true);
2641
2642 /*
2643 * Must cache the FLASH_CACHE now, since changes in
2644 * SECTOR_SIZE_1K may invalidate it
2645 */
2646 for (j = 0; j < FC_WORDS; j++)
2647 /*
2648 * Flash cache is big endian for parameter pages, at
2649 * least on STB SoCs
2650 */
2651 flash_cache[j] = be32_to_cpu(brcmnand_read_fc(ctrl, j));
2652
2653 brcmnand_soc_data_bus_unprepare(ctrl->soc, true);
2654 }
2655 } else if (instr->type == NAND_OP_DATA_IN_INSTR) {
2656 u8 *in = instr->ctx.data.buf.in;
2657
2658 if (last_cmd == CMD_DEVICE_ID_READ) {
2659 u32 val;
2660
2661 if (instr->ctx.data.len > 8) {
2662 dev_err(ctrl->dev, "unsupported len=%u\n",
2663 instr->ctx.data.len);
2664 ret = -EOPNOTSUPP;
2665 break;
2666 }
2667
2668 for (j = 0; j < instr->ctx.data.len; j++) {
2669 if (j == 0)
2670 val = brcmnand_read_reg(ctrl, BRCMNAND_ID);
2671 else if (j == 4)
2672 val = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT);
2673
2674 in[j] = (val >> (24 - ((j % 4) << 3))) & 0xff;
2675 }
2676 } else if (last_cmd == CMD_PARAMETER_READ ||
2677 last_cmd == CMD_PARAMETER_CHANGE_COL) {
2678 u64 addr;
2679 u32 offs;
2680
2681 for (j = 0; j < instr->ctx.data.len; j++) {
2682 addr = last_addr + j;
2683 offs = addr & (FC_BYTES - 1);
2684
2685 if (j > 0 && offs == 0)
2686 nand_change_read_column_op(chip, addr, NULL, 0,
2687 false);
2688
2689 in[j] = ctrl->flash_cache[offs];
2690 }
2691 }
2692 } else if (instr->type == NAND_OP_WAITRDY_INSTR) {
2693 ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);
2694 if (ret)
2695 break;
2696 } else {
2697 dev_err(ctrl->dev, "unsupported instruction type: %d\n", instr->type);
2698 ret = -EOPNOTSUPP;
2699 break;
2700 }
2701 }
2702
2703 return ret;
2704 }
2705
brcmnand_exec_op(struct nand_chip * chip,const struct nand_operation * op,bool check_only)2706 static int brcmnand_exec_op(struct nand_chip *chip,
2707 const struct nand_operation *op,
2708 bool check_only)
2709 {
2710 struct brcmnand_host *host = nand_get_controller_data(chip);
2711 struct brcmnand_controller *ctrl = host->ctrl;
2712 struct mtd_info *mtd = nand_to_mtd(chip);
2713 u8 *status;
2714 int ret = 0;
2715
2716 if (check_only)
2717 return ctrl->check_instr(chip, op);
2718
2719 if (brcmnand_op_is_status(op)) {
2720 status = op->instrs[1].ctx.data.buf.in;
2721 ret = brcmnand_status(host);
2722 if (ret < 0)
2723 return ret;
2724
2725 *status = ret & 0xFF;
2726
2727 return 0;
2728 } else if (brcmnand_op_is_reset(op)) {
2729 ret = brcmnand_reset(host);
2730 if (ret < 0)
2731 return ret;
2732
2733 brcmnand_wp(mtd, 1);
2734
2735 return 0;
2736 }
2737
2738 if (op->deassert_wp)
2739 brcmnand_wp(mtd, 0);
2740
2741 ret = ctrl->exec_instr(chip, op);
2742
2743 if (op->deassert_wp)
2744 brcmnand_wp(mtd, 1);
2745
2746 return ret;
2747 }
2748
2749 /***********************************************************************
2750 * Per-CS setup (1 NAND device)
2751 ***********************************************************************/
2752
brcmnand_set_cfg(struct brcmnand_host * host,struct brcmnand_cfg * cfg)2753 static int brcmnand_set_cfg(struct brcmnand_host *host,
2754 struct brcmnand_cfg *cfg)
2755 {
2756 struct brcmnand_controller *ctrl = host->ctrl;
2757 struct nand_chip *chip = &host->chip;
2758 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2759 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2760 BRCMNAND_CS_CFG_EXT);
2761 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2762 BRCMNAND_CS_ACC_CONTROL);
2763 u8 block_size = 0, page_size = 0, device_size = 0;
2764 u32 tmp;
2765
2766 if (ctrl->block_sizes) {
2767 int i, found;
2768
2769 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
2770 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
2771 block_size = i;
2772 found = 1;
2773 }
2774 if (!found) {
2775 dev_warn(ctrl->dev, "invalid block size %u\n",
2776 cfg->block_size);
2777 return -EINVAL;
2778 }
2779 } else {
2780 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
2781 }
2782
2783 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
2784 cfg->block_size > ctrl->max_block_size)) {
2785 dev_warn(ctrl->dev, "invalid block size %u\n",
2786 cfg->block_size);
2787 block_size = 0;
2788 }
2789
2790 if (ctrl->page_sizes) {
2791 int i, found;
2792
2793 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
2794 if (ctrl->page_sizes[i] == cfg->page_size) {
2795 page_size = i;
2796 found = 1;
2797 }
2798 if (!found) {
2799 dev_warn(ctrl->dev, "invalid page size %u\n",
2800 cfg->page_size);
2801 return -EINVAL;
2802 }
2803 } else {
2804 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
2805 }
2806
2807 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
2808 cfg->page_size > ctrl->max_page_size)) {
2809 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
2810 return -EINVAL;
2811 }
2812
2813 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
2814 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
2815 (unsigned long long)cfg->device_size);
2816 return -EINVAL;
2817 }
2818 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
2819
2820 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
2821 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
2822 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
2823 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
2824 (device_size << CFG_DEVICE_SIZE_SHIFT);
2825 if (cfg_offs == cfg_ext_offs) {
2826 tmp |= (page_size << ctrl->page_size_shift) |
2827 (block_size << CFG_BLK_SIZE_SHIFT);
2828 nand_writereg(ctrl, cfg_offs, tmp);
2829 } else {
2830 nand_writereg(ctrl, cfg_offs, tmp);
2831 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
2832 (block_size << CFG_EXT_BLK_SIZE_SHIFT);
2833 nand_writereg(ctrl, cfg_ext_offs, tmp);
2834 }
2835
2836 tmp = nand_readreg(ctrl, acc_control_offs);
2837 tmp &= ~brcmnand_ecc_level_mask(ctrl);
2838 tmp &= ~brcmnand_spare_area_mask(ctrl);
2839 if (ctrl->nand_version >= 0x0302) {
2840 tmp |= cfg->ecc_level << ctrl->ecc_level_shift;
2841 tmp |= cfg->spare_area_size;
2842 }
2843 nand_writereg(ctrl, acc_control_offs, tmp);
2844
2845 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
2846
2847 /* threshold = ceil(BCH-level * 0.75) */
2848 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
2849
2850 return 0;
2851 }
2852
brcmnand_print_cfg(struct brcmnand_host * host,char * buf,struct brcmnand_cfg * cfg)2853 static void brcmnand_print_cfg(struct brcmnand_host *host,
2854 char *buf, struct brcmnand_cfg *cfg)
2855 {
2856 buf += sprintf(buf,
2857 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
2858 (unsigned long long)cfg->device_size >> 20,
2859 cfg->block_size >> 10,
2860 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
2861 cfg->page_size >= 1024 ? "KiB" : "B",
2862 cfg->spare_area_size, cfg->device_width);
2863
2864 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
2865 if (is_hamming_ecc(host->ctrl, cfg))
2866 sprintf(buf, ", Hamming ECC");
2867 else if (cfg->sector_size_1k)
2868 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
2869 else
2870 sprintf(buf, ", BCH-%u", cfg->ecc_level);
2871 }
2872
2873 /*
2874 * Minimum number of bytes to address a page. Calculated as:
2875 * roundup(log2(size / page-size) / 8)
2876 *
2877 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
2878 * OK because many other things will break if 'size' is irregular...
2879 */
get_blk_adr_bytes(u64 size,u32 writesize)2880 static inline int get_blk_adr_bytes(u64 size, u32 writesize)
2881 {
2882 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
2883 }
2884
brcmnand_setup_dev(struct brcmnand_host * host)2885 static int brcmnand_setup_dev(struct brcmnand_host *host)
2886 {
2887 struct mtd_info *mtd = nand_to_mtd(&host->chip);
2888 struct nand_chip *chip = &host->chip;
2889 const struct nand_ecc_props *requirements =
2890 nanddev_get_ecc_requirements(&chip->base);
2891 struct nand_memory_organization *memorg =
2892 nanddev_get_memorg(&chip->base);
2893 struct brcmnand_controller *ctrl = host->ctrl;
2894 struct brcmnand_cfg *cfg = &host->hwcfg;
2895 struct device_node *np = nand_get_flash_node(chip);
2896 u32 offs, tmp, oob_sector;
2897 bool use_strap = false;
2898 char msg[128];
2899 int ret;
2900
2901 memset(cfg, 0, sizeof(*cfg));
2902 use_strap = of_property_read_bool(np, "brcm,nand-ecc-use-strap");
2903
2904 /*
2905 * Either nand-ecc-xxx or brcm,nand-ecc-use-strap can be set. Error out
2906 * if both exist.
2907 */
2908 if (chip->ecc.strength && use_strap) {
2909 dev_err(ctrl->dev,
2910 "ECC strap and DT ECC configuration properties are mutually exclusive\n");
2911 return -EINVAL;
2912 }
2913
2914 if (use_strap)
2915 brcmnand_get_ecc_settings(host, chip);
2916
2917 ret = of_property_read_u32(np, "brcm,nand-oob-sector-size",
2918 &oob_sector);
2919 if (ret) {
2920 if (use_strap)
2921 cfg->spare_area_size = brcmnand_get_spare_size(host);
2922 else
2923 /* Use detected size */
2924 cfg->spare_area_size = mtd->oobsize /
2925 (mtd->writesize >> FC_SHIFT);
2926 } else {
2927 cfg->spare_area_size = oob_sector;
2928 }
2929 if (cfg->spare_area_size > ctrl->max_oob)
2930 cfg->spare_area_size = ctrl->max_oob;
2931 /*
2932 * Set mtd and memorg oobsize to be consistent with controller's
2933 * spare_area_size, as the rest is inaccessible.
2934 */
2935 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
2936 memorg->oobsize = mtd->oobsize;
2937
2938 cfg->device_size = mtd->size;
2939 cfg->block_size = mtd->erasesize;
2940 cfg->page_size = mtd->writesize;
2941 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
2942 cfg->col_adr_bytes = 2;
2943 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
2944
2945 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) {
2946 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n",
2947 chip->ecc.engine_type);
2948 return -EINVAL;
2949 }
2950
2951 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) {
2952 if (chip->ecc.strength == 1 && chip->ecc.size == 512)
2953 /* Default to Hamming for 1-bit ECC, if unspecified */
2954 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
2955 else
2956 /* Otherwise, BCH */
2957 chip->ecc.algo = NAND_ECC_ALGO_BCH;
2958 }
2959
2960 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING &&
2961 (chip->ecc.strength != 1 || chip->ecc.size != 512)) {
2962 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n",
2963 chip->ecc.strength, chip->ecc.size);
2964 return -EINVAL;
2965 }
2966
2967 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_NONE &&
2968 (!chip->ecc.size || !chip->ecc.strength)) {
2969 if (requirements->step_size && requirements->strength) {
2970 /* use detected ECC parameters */
2971 chip->ecc.size = requirements->step_size;
2972 chip->ecc.strength = requirements->strength;
2973 dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n",
2974 chip->ecc.size, chip->ecc.strength);
2975 }
2976 }
2977
2978 switch (chip->ecc.size) {
2979 case 512:
2980 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING)
2981 cfg->ecc_level = 15;
2982 else
2983 cfg->ecc_level = chip->ecc.strength;
2984 cfg->sector_size_1k = 0;
2985 break;
2986 case 1024:
2987 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
2988 dev_err(ctrl->dev, "1KB sectors not supported\n");
2989 return -EINVAL;
2990 }
2991 if (chip->ecc.strength & 0x1) {
2992 dev_err(ctrl->dev,
2993 "odd ECC not supported with 1KB sectors\n");
2994 return -EINVAL;
2995 }
2996
2997 cfg->ecc_level = chip->ecc.strength >> 1;
2998 cfg->sector_size_1k = 1;
2999 break;
3000 default:
3001 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
3002 chip->ecc.size);
3003 return -EINVAL;
3004 }
3005
3006 cfg->ful_adr_bytes = cfg->blk_adr_bytes;
3007 if (mtd->writesize > 512)
3008 cfg->ful_adr_bytes += cfg->col_adr_bytes;
3009 else
3010 cfg->ful_adr_bytes += 1;
3011
3012 ret = brcmnand_set_cfg(host, cfg);
3013 if (ret)
3014 return ret;
3015
3016 brcmnand_set_ecc_enabled(host, 1);
3017
3018 brcmnand_print_cfg(host, msg, cfg);
3019 dev_info(ctrl->dev, "detected %s\n", msg);
3020
3021 /* Configure ACC_CONTROL */
3022 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
3023 tmp = nand_readreg(ctrl, offs);
3024 tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
3025 tmp &= ~ACC_CONTROL_RD_ERASED;
3026
3027 /* We need to turn on Read from erased paged protected by ECC */
3028 if (ctrl->nand_version >= 0x0702)
3029 tmp |= ACC_CONTROL_RD_ERASED;
3030 tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
3031 if (ctrl->features & BRCMNAND_HAS_PREFETCH)
3032 tmp &= ~ACC_CONTROL_PREFETCH;
3033
3034 nand_writereg(ctrl, offs, tmp);
3035
3036 return 0;
3037 }
3038
brcmnand_attach_chip(struct nand_chip * chip)3039 static int brcmnand_attach_chip(struct nand_chip *chip)
3040 {
3041 struct mtd_info *mtd = nand_to_mtd(chip);
3042 struct brcmnand_host *host = nand_get_controller_data(chip);
3043 int ret;
3044
3045 chip->options |= NAND_NO_SUBPAGE_WRITE;
3046 /*
3047 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
3048 * to/from, and have nand_base pass us a bounce buffer instead, as
3049 * needed.
3050 */
3051 chip->options |= NAND_USES_DMA;
3052
3053 if (chip->bbt_options & NAND_BBT_USE_FLASH)
3054 chip->bbt_options |= NAND_BBT_NO_OOB;
3055
3056 if (brcmnand_setup_dev(host))
3057 return -ENXIO;
3058
3059 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
3060
3061 /* only use our internal HW threshold */
3062 mtd->bitflip_threshold = 1;
3063
3064 ret = brcmstb_choose_ecc_layout(host);
3065
3066 /* If OOB is written with ECC enabled it will cause ECC errors */
3067 if (is_hamming_ecc(host->ctrl, &host->hwcfg)) {
3068 chip->ecc.write_oob = brcmnand_write_oob_raw;
3069 chip->ecc.read_oob = brcmnand_read_oob_raw;
3070 }
3071
3072 return ret;
3073 }
3074
3075 static const struct nand_controller_ops brcmnand_controller_ops = {
3076 .attach_chip = brcmnand_attach_chip,
3077 .exec_op = brcmnand_exec_op,
3078 };
3079
brcmnand_init_cs(struct brcmnand_host * host,const char * const * part_probe_types)3080 static int brcmnand_init_cs(struct brcmnand_host *host,
3081 const char * const *part_probe_types)
3082 {
3083 struct brcmnand_controller *ctrl = host->ctrl;
3084 struct device *dev = ctrl->dev;
3085 struct mtd_info *mtd;
3086 struct nand_chip *chip;
3087 int ret;
3088 u16 cfg_offs;
3089
3090 mtd = nand_to_mtd(&host->chip);
3091 chip = &host->chip;
3092
3093 nand_set_controller_data(chip, host);
3094 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d",
3095 host->cs);
3096 if (!mtd->name)
3097 return -ENOMEM;
3098
3099 mtd->owner = THIS_MODULE;
3100 mtd->dev.parent = dev;
3101
3102 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
3103 chip->ecc.read_page = brcmnand_read_page;
3104 chip->ecc.write_page = brcmnand_write_page;
3105 chip->ecc.read_page_raw = brcmnand_read_page_raw;
3106 chip->ecc.write_page_raw = brcmnand_write_page_raw;
3107 chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
3108 chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
3109 chip->ecc.read_oob = brcmnand_read_oob;
3110 chip->ecc.write_oob = brcmnand_write_oob;
3111
3112 chip->controller = &ctrl->controller;
3113 ctrl->controller.controller_wp = 1;
3114
3115 /*
3116 * The bootloader might have configured 16bit mode but
3117 * NAND READID command only works in 8bit mode. We force
3118 * 8bit mode here to ensure that NAND READID commands works.
3119 */
3120 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
3121 nand_writereg(ctrl, cfg_offs,
3122 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
3123
3124 ret = nand_scan(chip, 1);
3125 if (ret)
3126 return ret;
3127
3128 ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
3129 if (ret)
3130 nand_cleanup(chip);
3131
3132 return ret;
3133 }
3134
brcmnand_save_restore_cs_config(struct brcmnand_host * host,int restore)3135 static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
3136 int restore)
3137 {
3138 struct brcmnand_controller *ctrl = host->ctrl;
3139 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
3140 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
3141 BRCMNAND_CS_CFG_EXT);
3142 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
3143 BRCMNAND_CS_ACC_CONTROL);
3144 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
3145 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
3146
3147 if (restore) {
3148 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
3149 if (cfg_offs != cfg_ext_offs)
3150 nand_writereg(ctrl, cfg_ext_offs,
3151 host->hwcfg.config_ext);
3152 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
3153 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
3154 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
3155 } else {
3156 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
3157 if (cfg_offs != cfg_ext_offs)
3158 host->hwcfg.config_ext =
3159 nand_readreg(ctrl, cfg_ext_offs);
3160 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
3161 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
3162 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
3163 }
3164 }
3165
brcmnand_suspend(struct device * dev)3166 static int brcmnand_suspend(struct device *dev)
3167 {
3168 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
3169 struct brcmnand_host *host;
3170
3171 list_for_each_entry(host, &ctrl->host_list, node)
3172 brcmnand_save_restore_cs_config(host, 0);
3173
3174 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
3175 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
3176 ctrl->corr_stat_threshold =
3177 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
3178
3179 if (has_flash_dma(ctrl))
3180 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
3181 else if (has_edu(ctrl))
3182 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG);
3183
3184 return 0;
3185 }
3186
brcmnand_resume(struct device * dev)3187 static int brcmnand_resume(struct device *dev)
3188 {
3189 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
3190 struct brcmnand_host *host;
3191
3192 if (has_flash_dma(ctrl)) {
3193 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
3194 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
3195 }
3196
3197 if (has_edu(ctrl)) {
3198 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG);
3199 edu_writel(ctrl, EDU_CONFIG, ctrl->edu_config);
3200 edu_readl(ctrl, EDU_CONFIG);
3201 brcmnand_edu_init(ctrl);
3202 }
3203
3204 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
3205 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
3206 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
3207 ctrl->corr_stat_threshold);
3208 if (ctrl->soc) {
3209 /* Clear/re-enable interrupt */
3210 ctrl->soc->ctlrdy_ack(ctrl->soc);
3211 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
3212 }
3213
3214 list_for_each_entry(host, &ctrl->host_list, node) {
3215 struct nand_chip *chip = &host->chip;
3216
3217 brcmnand_save_restore_cs_config(host, 1);
3218
3219 /* Reset the chip, required by some chips after power-up */
3220 nand_reset(chip, 0);
3221 }
3222
3223 return 0;
3224 }
3225
3226 const struct dev_pm_ops brcmnand_pm_ops = {
3227 .suspend = brcmnand_suspend,
3228 .resume = brcmnand_resume,
3229 };
3230 EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
3231
3232 static const struct of_device_id __maybe_unused brcmnand_of_match[] = {
3233 { .compatible = "brcm,brcmnand-v2.1" },
3234 { .compatible = "brcm,brcmnand-v2.2" },
3235 { .compatible = "brcm,brcmnand-v4.0" },
3236 { .compatible = "brcm,brcmnand-v5.0" },
3237 { .compatible = "brcm,brcmnand-v6.0" },
3238 { .compatible = "brcm,brcmnand-v6.1" },
3239 { .compatible = "brcm,brcmnand-v6.2" },
3240 { .compatible = "brcm,brcmnand-v7.0" },
3241 { .compatible = "brcm,brcmnand-v7.1" },
3242 { .compatible = "brcm,brcmnand-v7.2" },
3243 { .compatible = "brcm,brcmnand-v7.3" },
3244 {},
3245 };
3246 MODULE_DEVICE_TABLE(of, brcmnand_of_match);
3247
3248 /***********************************************************************
3249 * Platform driver setup (per controller)
3250 ***********************************************************************/
brcmnand_edu_setup(struct platform_device * pdev)3251 static int brcmnand_edu_setup(struct platform_device *pdev)
3252 {
3253 struct device *dev = &pdev->dev;
3254 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
3255 struct resource *res;
3256 int ret;
3257
3258 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-edu");
3259 if (res) {
3260 ctrl->edu_base = devm_ioremap_resource(dev, res);
3261 if (IS_ERR(ctrl->edu_base))
3262 return PTR_ERR(ctrl->edu_base);
3263
3264 ctrl->edu_offsets = edu_regs;
3265
3266 edu_writel(ctrl, EDU_CONFIG, EDU_CONFIG_MODE_NAND |
3267 EDU_CONFIG_SWAP_CFG);
3268 edu_readl(ctrl, EDU_CONFIG);
3269
3270 /* initialize edu */
3271 brcmnand_edu_init(ctrl);
3272
3273 ctrl->edu_irq = platform_get_irq_optional(pdev, 1);
3274 if (ctrl->edu_irq < 0) {
3275 dev_warn(dev,
3276 "FLASH EDU enabled, using ctlrdy irq\n");
3277 } else {
3278 ret = devm_request_irq(dev, ctrl->edu_irq,
3279 brcmnand_edu_irq, 0,
3280 "brcmnand-edu", ctrl);
3281 if (ret < 0) {
3282 dev_err(ctrl->dev, "can't allocate IRQ %d: error %d\n",
3283 ctrl->edu_irq, ret);
3284 return ret;
3285 }
3286
3287 dev_info(dev, "FLASH EDU enabled using irq %u\n",
3288 ctrl->edu_irq);
3289 }
3290 }
3291
3292 return 0;
3293 }
3294
brcmnand_probe(struct platform_device * pdev,struct brcmnand_soc * soc)3295 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
3296 {
3297 struct brcmnand_platform_data *pd = dev_get_platdata(&pdev->dev);
3298 struct device *dev = &pdev->dev;
3299 struct device_node *dn = dev->of_node;
3300 struct brcmnand_controller *ctrl;
3301 struct brcmnand_host *host;
3302 struct resource *res;
3303 int ret;
3304
3305 if (dn && !of_match_node(brcmnand_of_match, dn))
3306 return -ENODEV;
3307
3308 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
3309 if (!ctrl)
3310 return -ENOMEM;
3311
3312 dev_set_drvdata(dev, ctrl);
3313 ctrl->dev = dev;
3314 ctrl->soc = soc;
3315
3316 /* Enable the static key if the soc provides I/O operations indicating
3317 * that a non-memory mapped IO access path must be used
3318 */
3319 if (brcmnand_soc_has_ops(ctrl->soc))
3320 static_branch_enable(&brcmnand_soc_has_ops_key);
3321
3322 init_completion(&ctrl->done);
3323 init_completion(&ctrl->dma_done);
3324 init_completion(&ctrl->edu_done);
3325 nand_controller_init(&ctrl->controller);
3326 ctrl->controller.ops = &brcmnand_controller_ops;
3327 INIT_LIST_HEAD(&ctrl->host_list);
3328
3329 /* NAND register range */
3330 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3331 ctrl->nand_base = devm_ioremap_resource(dev, res);
3332 if (IS_ERR(ctrl->nand_base) && !brcmnand_soc_has_ops(soc))
3333 return PTR_ERR(ctrl->nand_base);
3334
3335 /* Enable clock before using NAND registers */
3336 ctrl->clk = devm_clk_get(dev, "nand");
3337 if (!IS_ERR(ctrl->clk)) {
3338 ret = clk_prepare_enable(ctrl->clk);
3339 if (ret)
3340 return ret;
3341 } else {
3342 ret = PTR_ERR(ctrl->clk);
3343 if (ret == -EPROBE_DEFER)
3344 return ret;
3345
3346 ctrl->clk = NULL;
3347 }
3348
3349 /* Initialize NAND revision */
3350 ret = brcmnand_revision_init(ctrl);
3351 if (ret)
3352 goto err;
3353
3354 /* Only v5.0+ controllers have low level ops support */
3355 if (ctrl->nand_version >= 0x0500) {
3356 ctrl->check_instr = brcmnand_check_instructions;
3357 ctrl->exec_instr = brcmnand_exec_instructions;
3358 } else {
3359 ctrl->check_instr = brcmnand_check_instructions_legacy;
3360 ctrl->exec_instr = brcmnand_exec_instructions_legacy;
3361 }
3362
3363 /*
3364 * Most chips have this cache at a fixed offset within 'nand' block.
3365 * Some must specify this region separately.
3366 */
3367 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
3368 if (res) {
3369 ctrl->nand_fc = devm_ioremap_resource(dev, res);
3370 if (IS_ERR(ctrl->nand_fc)) {
3371 ret = PTR_ERR(ctrl->nand_fc);
3372 goto err;
3373 }
3374 } else {
3375 ctrl->nand_fc = ctrl->nand_base +
3376 ctrl->reg_offsets[BRCMNAND_FC_BASE];
3377 }
3378
3379 /* FLASH_DMA */
3380 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
3381 if (res) {
3382 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
3383 if (IS_ERR(ctrl->flash_dma_base)) {
3384 ret = PTR_ERR(ctrl->flash_dma_base);
3385 goto err;
3386 }
3387
3388 /* initialize the dma version */
3389 brcmnand_flash_dma_revision_init(ctrl);
3390
3391 ret = -EIO;
3392 if (ctrl->nand_version >= 0x0700)
3393 ret = dma_set_mask_and_coherent(&pdev->dev,
3394 DMA_BIT_MASK(40));
3395 if (ret)
3396 ret = dma_set_mask_and_coherent(&pdev->dev,
3397 DMA_BIT_MASK(32));
3398 if (ret)
3399 goto err;
3400
3401 /* linked-list and stop on error */
3402 flash_dma_writel(ctrl, FLASH_DMA_MODE, FLASH_DMA_MODE_MASK);
3403 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
3404
3405 /* Allocate descriptor(s) */
3406 ctrl->dma_desc = dmam_alloc_coherent(dev,
3407 sizeof(*ctrl->dma_desc),
3408 &ctrl->dma_pa, GFP_KERNEL);
3409 if (!ctrl->dma_desc) {
3410 ret = -ENOMEM;
3411 goto err;
3412 }
3413
3414 ctrl->dma_irq = platform_get_irq(pdev, 1);
3415 if ((int)ctrl->dma_irq < 0) {
3416 dev_err(dev, "missing FLASH_DMA IRQ\n");
3417 ret = -ENODEV;
3418 goto err;
3419 }
3420
3421 ret = devm_request_irq(dev, ctrl->dma_irq,
3422 brcmnand_dma_irq, 0, DRV_NAME,
3423 ctrl);
3424 if (ret < 0) {
3425 dev_err(dev, "can't allocate IRQ %d: error %d\n",
3426 ctrl->dma_irq, ret);
3427 goto err;
3428 }
3429
3430 dev_info(dev, "enabling FLASH_DMA\n");
3431 /* set flash dma transfer function to call */
3432 ctrl->dma_trans = brcmnand_dma_trans;
3433 } else {
3434 ret = brcmnand_edu_setup(pdev);
3435 if (ret < 0)
3436 goto err;
3437
3438 if (has_edu(ctrl))
3439 /* set edu transfer function to call */
3440 ctrl->dma_trans = brcmnand_edu_trans;
3441 }
3442
3443 /* Disable automatic device ID config, direct addressing */
3444 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
3445 CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
3446 /* Disable XOR addressing */
3447 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
3448
3449 /* Check if the board connects the WP pin */
3450 if (of_property_read_bool(dn, "brcm,wp-not-connected"))
3451 wp_on = 0;
3452
3453 if (ctrl->features & BRCMNAND_HAS_WP) {
3454 /* Permanently disable write protection */
3455 if (wp_on == 2)
3456 brcmnand_set_wp(ctrl, false);
3457 } else {
3458 wp_on = 0;
3459 }
3460
3461 /* IRQ */
3462 ctrl->irq = platform_get_irq_optional(pdev, 0);
3463 if (ctrl->irq > 0) {
3464 /*
3465 * Some SoCs integrate this controller (e.g., its interrupt bits) in
3466 * interesting ways
3467 */
3468 if (soc) {
3469 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
3470 DRV_NAME, ctrl);
3471
3472 /* Enable interrupt */
3473 ctrl->soc->ctlrdy_ack(ctrl->soc);
3474 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
3475 } else {
3476 /* Use standard interrupt infrastructure */
3477 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
3478 DRV_NAME, ctrl);
3479 }
3480 if (ret < 0) {
3481 dev_err(dev, "can't allocate IRQ %d: error %d\n",
3482 ctrl->irq, ret);
3483 goto err;
3484 }
3485 }
3486
3487 for_each_available_child_of_node_scoped(dn, child) {
3488 if (of_device_is_compatible(child, "brcm,nandcs")) {
3489
3490 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
3491 if (!host) {
3492 ret = -ENOMEM;
3493 goto err;
3494 }
3495 host->pdev = pdev;
3496 host->ctrl = ctrl;
3497
3498 ret = of_property_read_u32(child, "reg", &host->cs);
3499 if (ret) {
3500 dev_err(dev, "can't get chip-select\n");
3501 devm_kfree(dev, host);
3502 continue;
3503 }
3504
3505 nand_set_flash_node(&host->chip, child);
3506
3507 ret = brcmnand_init_cs(host, NULL);
3508 if (ret) {
3509 if (ret == -EPROBE_DEFER)
3510 goto err;
3511
3512 devm_kfree(dev, host);
3513 continue; /* Try all chip-selects */
3514 }
3515
3516 list_add_tail(&host->node, &ctrl->host_list);
3517 }
3518 }
3519
3520 if (!list_empty(&ctrl->host_list))
3521 return 0;
3522
3523 if (!pd) {
3524 ret = -ENODEV;
3525 goto err;
3526 }
3527
3528 /* If we got there we must have been probing via platform data */
3529 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
3530 if (!host) {
3531 ret = -ENOMEM;
3532 goto err;
3533 }
3534 host->pdev = pdev;
3535 host->ctrl = ctrl;
3536 host->cs = pd->chip_select;
3537 host->chip.ecc.size = pd->ecc_stepsize;
3538 host->chip.ecc.strength = pd->ecc_strength;
3539
3540 ret = brcmnand_init_cs(host, pd->part_probe_types);
3541 if (ret)
3542 goto err;
3543
3544 list_add_tail(&host->node, &ctrl->host_list);
3545
3546 /* No chip-selects could initialize properly */
3547 if (list_empty(&ctrl->host_list)) {
3548 ret = -ENODEV;
3549 goto err;
3550 }
3551
3552 return 0;
3553
3554 err:
3555 clk_disable_unprepare(ctrl->clk);
3556 return ret;
3557
3558 }
3559 EXPORT_SYMBOL_GPL(brcmnand_probe);
3560
brcmnand_remove(struct platform_device * pdev)3561 void brcmnand_remove(struct platform_device *pdev)
3562 {
3563 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
3564 struct brcmnand_host *host;
3565 struct nand_chip *chip;
3566 int ret;
3567
3568 list_for_each_entry(host, &ctrl->host_list, node) {
3569 chip = &host->chip;
3570 ret = mtd_device_unregister(nand_to_mtd(chip));
3571 WARN_ON(ret);
3572 nand_cleanup(chip);
3573 }
3574
3575 clk_disable_unprepare(ctrl->clk);
3576
3577 dev_set_drvdata(&pdev->dev, NULL);
3578 }
3579 EXPORT_SYMBOL_GPL(brcmnand_remove);
3580
3581 MODULE_LICENSE("GPL v2");
3582 MODULE_AUTHOR("Kevin Cernekee");
3583 MODULE_AUTHOR("Brian Norris");
3584 MODULE_DESCRIPTION("NAND driver for Broadcom chips");
3585 MODULE_ALIAS("platform:brcmnand");
3586