1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with 4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c 5 * 6 * Copyright (C) 2005, Intec Automation Inc. 7 * Copyright (C) 2014, Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/cleanup.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/err.h> 14 #include <linux/errno.h> 15 #include <linux/math64.h> 16 #include <linux/module.h> 17 #include <linux/mtd/mtd.h> 18 #include <linux/mtd/spi-nor.h> 19 #include <linux/mutex.h> 20 #include <linux/of.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/sched/task_stack.h> 23 #include <linux/sizes.h> 24 #include <linux/slab.h> 25 #include <linux/spi/flash.h> 26 27 #include "core.h" 28 29 /* Define max times to check status register before we give up. */ 30 31 /* 32 * For everything but full-chip erase; probably could be much smaller, but kept 33 * around for safety for now 34 */ 35 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) 36 37 /* 38 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up 39 * for larger flash 40 */ 41 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) 42 43 #define SPI_NOR_MAX_ADDR_NBYTES 4 44 45 #define SPI_NOR_SRST_SLEEP_MIN 200 46 #define SPI_NOR_SRST_SLEEP_MAX 400 47 48 /** 49 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the 50 * extension type. 51 * @nor: pointer to a 'struct spi_nor' 52 * @op: pointer to the 'struct spi_mem_op' whose properties 53 * need to be initialized. 54 * 55 * Right now, only "repeat" and "invert" are supported. 56 * 57 * Return: The opcode extension. 58 */ 59 static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor, 60 const struct spi_mem_op *op) 61 { 62 switch (nor->cmd_ext_type) { 63 case SPI_NOR_EXT_INVERT: 64 return ~op->cmd.opcode; 65 66 case SPI_NOR_EXT_REPEAT: 67 return op->cmd.opcode; 68 69 default: 70 dev_err(nor->dev, "Unknown command extension type\n"); 71 return 0; 72 } 73 } 74 75 /** 76 * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op. 77 * @nor: pointer to a 'struct spi_nor' 78 * @op: pointer to the 'struct spi_mem_op' whose properties 79 * need to be initialized. 80 * @proto: the protocol from which the properties need to be set. 81 */ 82 void spi_nor_spimem_setup_op(const struct spi_nor *nor, 83 struct spi_mem_op *op, 84 const enum spi_nor_protocol proto) 85 { 86 u8 ext; 87 88 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto); 89 90 if (op->addr.nbytes) 91 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto); 92 93 if (op->dummy.nbytes) 94 op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto); 95 96 if (op->data.nbytes) 97 op->data.buswidth = spi_nor_get_protocol_data_nbits(proto); 98 99 if (spi_nor_protocol_is_dtr(proto)) { 100 /* 101 * SPIMEM supports mixed DTR modes, but right now we can only 102 * have all phases either DTR or STR. IOW, SPIMEM can have 103 * something like 4S-4D-4D, but SPI NOR can't. So, set all 4 104 * phases to either DTR or STR. 105 */ 106 op->cmd.dtr = true; 107 op->addr.dtr = true; 108 op->dummy.dtr = true; 109 op->data.dtr = true; 110 111 /* 2 bytes per clock cycle in DTR mode. */ 112 op->dummy.nbytes *= 2; 113 114 ext = spi_nor_get_cmd_ext(nor, op); 115 op->cmd.opcode = (op->cmd.opcode << 8) | ext; 116 op->cmd.nbytes = 2; 117 } 118 119 if (proto == SNOR_PROTO_8_8_8_DTR && nor->flags & SNOR_F_SWAP16) 120 op->data.swap16 = true; 121 } 122 123 /** 124 * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data 125 * transfer 126 * @nor: pointer to 'struct spi_nor' 127 * @op: pointer to 'struct spi_mem_op' template for transfer 128 * 129 * If we have to use the bounce buffer, the data field in @op will be updated. 130 * 131 * Return: true if the bounce buffer is needed, false if not 132 */ 133 static bool spi_nor_spimem_bounce(struct spi_nor *nor, struct spi_mem_op *op) 134 { 135 /* op->data.buf.in occupies the same memory as op->data.buf.out */ 136 if (object_is_on_stack(op->data.buf.in) || 137 !virt_addr_valid(op->data.buf.in)) { 138 if (op->data.nbytes > nor->bouncebuf_size) 139 op->data.nbytes = nor->bouncebuf_size; 140 op->data.buf.in = nor->bouncebuf; 141 return true; 142 } 143 144 return false; 145 } 146 147 /** 148 * spi_nor_spimem_exec_op() - execute a memory operation 149 * @nor: pointer to 'struct spi_nor' 150 * @op: pointer to 'struct spi_mem_op' template for transfer 151 * 152 * Return: 0 on success, -error otherwise. 153 */ 154 static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op) 155 { 156 int error; 157 158 error = spi_mem_adjust_op_size(nor->spimem, op); 159 if (error) 160 return error; 161 162 return spi_mem_exec_op(nor->spimem, op); 163 } 164 165 int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode, 166 u8 *buf, size_t len) 167 { 168 if (spi_nor_protocol_is_dtr(nor->reg_proto)) 169 return -EOPNOTSUPP; 170 171 return nor->controller_ops->read_reg(nor, opcode, buf, len); 172 } 173 174 int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode, 175 const u8 *buf, size_t len) 176 { 177 if (spi_nor_protocol_is_dtr(nor->reg_proto)) 178 return -EOPNOTSUPP; 179 180 return nor->controller_ops->write_reg(nor, opcode, buf, len); 181 } 182 183 static int spi_nor_controller_ops_erase(struct spi_nor *nor, loff_t offs) 184 { 185 if (spi_nor_protocol_is_dtr(nor->reg_proto)) 186 return -EOPNOTSUPP; 187 188 return nor->controller_ops->erase(nor, offs); 189 } 190 191 /** 192 * spi_nor_spimem_read_data() - read data from flash's memory region via 193 * spi-mem 194 * @nor: pointer to 'struct spi_nor' 195 * @from: offset to read from 196 * @len: number of bytes to read 197 * @buf: pointer to dst buffer 198 * 199 * Return: number of bytes read successfully, -errno otherwise 200 */ 201 static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from, 202 size_t len, u8 *buf) 203 { 204 struct spi_mem_op op = 205 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), 206 SPI_MEM_OP_ADDR(nor->addr_nbytes, from, 0), 207 SPI_MEM_OP_DUMMY(nor->read_dummy, 0), 208 SPI_MEM_OP_DATA_IN(len, buf, 0)); 209 bool usebouncebuf; 210 ssize_t nbytes; 211 int error; 212 213 spi_nor_spimem_setup_op(nor, &op, nor->read_proto); 214 215 /* convert the dummy cycles to the number of bytes */ 216 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; 217 if (spi_nor_protocol_is_dtr(nor->read_proto)) 218 op.dummy.nbytes *= 2; 219 220 usebouncebuf = spi_nor_spimem_bounce(nor, &op); 221 222 if (nor->dirmap.rdesc) { 223 nbytes = spi_mem_dirmap_read(nor->dirmap.rdesc, op.addr.val, 224 op.data.nbytes, op.data.buf.in); 225 } else { 226 error = spi_nor_spimem_exec_op(nor, &op); 227 if (error) 228 return error; 229 nbytes = op.data.nbytes; 230 } 231 232 if (usebouncebuf && nbytes > 0) 233 memcpy(buf, op.data.buf.in, nbytes); 234 235 return nbytes; 236 } 237 238 /** 239 * spi_nor_read_data() - read data from flash memory 240 * @nor: pointer to 'struct spi_nor' 241 * @from: offset to read from 242 * @len: number of bytes to read 243 * @buf: pointer to dst buffer 244 * 245 * Return: number of bytes read successfully, -errno otherwise 246 */ 247 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf) 248 { 249 if (nor->spimem) 250 return spi_nor_spimem_read_data(nor, from, len, buf); 251 252 return nor->controller_ops->read(nor, from, len, buf); 253 } 254 255 /** 256 * spi_nor_spimem_write_data() - write data to flash memory via 257 * spi-mem 258 * @nor: pointer to 'struct spi_nor' 259 * @to: offset to write to 260 * @len: number of bytes to write 261 * @buf: pointer to src buffer 262 * 263 * Return: number of bytes written successfully, -errno otherwise 264 */ 265 static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to, 266 size_t len, const u8 *buf) 267 { 268 struct spi_mem_op op = 269 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0), 270 SPI_MEM_OP_ADDR(nor->addr_nbytes, to, 0), 271 SPI_MEM_OP_NO_DUMMY, 272 SPI_MEM_OP_DATA_OUT(len, buf, 0)); 273 ssize_t nbytes; 274 int error; 275 276 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 277 op.addr.nbytes = 0; 278 279 spi_nor_spimem_setup_op(nor, &op, nor->write_proto); 280 281 if (spi_nor_spimem_bounce(nor, &op)) 282 memcpy(nor->bouncebuf, buf, op.data.nbytes); 283 284 if (nor->dirmap.wdesc) { 285 nbytes = spi_mem_dirmap_write(nor->dirmap.wdesc, op.addr.val, 286 op.data.nbytes, op.data.buf.out); 287 } else { 288 error = spi_nor_spimem_exec_op(nor, &op); 289 if (error) 290 return error; 291 nbytes = op.data.nbytes; 292 } 293 294 return nbytes; 295 } 296 297 /** 298 * spi_nor_write_data() - write data to flash memory 299 * @nor: pointer to 'struct spi_nor' 300 * @to: offset to write to 301 * @len: number of bytes to write 302 * @buf: pointer to src buffer 303 * 304 * Return: number of bytes written successfully, -errno otherwise 305 */ 306 ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 307 const u8 *buf) 308 { 309 if (nor->spimem) 310 return spi_nor_spimem_write_data(nor, to, len, buf); 311 312 return nor->controller_ops->write(nor, to, len, buf); 313 } 314 315 /** 316 * spi_nor_read_any_reg() - read any register from flash memory, nonvolatile or 317 * volatile. 318 * @nor: pointer to 'struct spi_nor'. 319 * @op: SPI memory operation. op->data.buf must be DMA-able. 320 * @proto: SPI protocol to use for the register operation. 321 * 322 * Return: zero on success, -errno otherwise 323 */ 324 int spi_nor_read_any_reg(struct spi_nor *nor, struct spi_mem_op *op, 325 enum spi_nor_protocol proto) 326 { 327 if (!nor->spimem) 328 return -EOPNOTSUPP; 329 330 spi_nor_spimem_setup_op(nor, op, proto); 331 return spi_nor_spimem_exec_op(nor, op); 332 } 333 334 /** 335 * spi_nor_write_any_volatile_reg() - write any volatile register to flash 336 * memory. 337 * @nor: pointer to 'struct spi_nor' 338 * @op: SPI memory operation. op->data.buf must be DMA-able. 339 * @proto: SPI protocol to use for the register operation. 340 * 341 * Writing volatile registers are instant according to some manufacturers 342 * (Cypress, Micron) and do not need any status polling. 343 * 344 * Return: zero on success, -errno otherwise 345 */ 346 int spi_nor_write_any_volatile_reg(struct spi_nor *nor, struct spi_mem_op *op, 347 enum spi_nor_protocol proto) 348 { 349 int ret; 350 351 if (!nor->spimem) 352 return -EOPNOTSUPP; 353 354 ret = spi_nor_write_enable(nor); 355 if (ret) 356 return ret; 357 spi_nor_spimem_setup_op(nor, op, proto); 358 return spi_nor_spimem_exec_op(nor, op); 359 } 360 361 /** 362 * spi_nor_write_enable() - Set write enable latch with Write Enable command. 363 * @nor: pointer to 'struct spi_nor'. 364 * 365 * Return: 0 on success, -errno otherwise. 366 */ 367 int spi_nor_write_enable(struct spi_nor *nor) 368 { 369 int ret; 370 371 if (nor->spimem) { 372 struct spi_mem_op op = SPI_NOR_WREN_OP; 373 374 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 375 376 ret = spi_mem_exec_op(nor->spimem, &op); 377 } else { 378 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREN, 379 NULL, 0); 380 } 381 382 if (ret) 383 dev_dbg(nor->dev, "error %d on Write Enable\n", ret); 384 385 return ret; 386 } 387 388 /** 389 * spi_nor_write_disable() - Send Write Disable instruction to the chip. 390 * @nor: pointer to 'struct spi_nor'. 391 * 392 * Return: 0 on success, -errno otherwise. 393 */ 394 int spi_nor_write_disable(struct spi_nor *nor) 395 { 396 int ret; 397 398 if (nor->spimem) { 399 struct spi_mem_op op = SPI_NOR_WRDI_OP; 400 401 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 402 403 ret = spi_mem_exec_op(nor->spimem, &op); 404 } else { 405 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRDI, 406 NULL, 0); 407 } 408 409 if (ret) 410 dev_dbg(nor->dev, "error %d on Write Disable\n", ret); 411 412 return ret; 413 } 414 415 /** 416 * spi_nor_read_id() - Read the JEDEC ID. 417 * @nor: pointer to 'struct spi_nor'. 418 * @naddr: number of address bytes to send. Can be zero if the operation 419 * does not need to send an address. 420 * @ndummy: number of dummy bytes to send after an opcode or address. Can 421 * be zero if the operation does not require dummy bytes. 422 * @id: pointer to a DMA-able buffer where the value of the JEDEC ID 423 * will be written. 424 * @proto: the SPI protocol for register operation. 425 * 426 * Return: 0 on success, -errno otherwise. 427 */ 428 int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, 429 enum spi_nor_protocol proto) 430 { 431 int ret; 432 433 if (nor->spimem) { 434 struct spi_mem_op op = 435 SPI_NOR_READID_OP(naddr, ndummy, id, SPI_NOR_MAX_ID_LEN); 436 437 spi_nor_spimem_setup_op(nor, &op, proto); 438 ret = spi_mem_exec_op(nor->spimem, &op); 439 } else { 440 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id, 441 SPI_NOR_MAX_ID_LEN); 442 } 443 return ret; 444 } 445 446 /** 447 * spi_nor_read_sr() - Read the Status Register. 448 * @nor: pointer to 'struct spi_nor'. 449 * @sr: pointer to a DMA-able buffer where the value of the 450 * Status Register will be written. Should be at least 2 bytes. 451 * 452 * Return: 0 on success, -errno otherwise. 453 */ 454 int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) 455 { 456 int ret; 457 458 if (nor->spimem) { 459 struct spi_mem_op op = SPI_NOR_RDSR_OP(sr); 460 461 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { 462 op.addr.nbytes = nor->params->rdsr_addr_nbytes; 463 op.dummy.nbytes = nor->params->rdsr_dummy; 464 /* 465 * We don't want to read only one byte in DTR mode. So, 466 * read 2 and then discard the second byte. 467 */ 468 op.data.nbytes = 2; 469 } 470 471 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 472 473 ret = spi_mem_exec_op(nor->spimem, &op); 474 } else { 475 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr, 476 1); 477 } 478 479 if (ret) 480 dev_dbg(nor->dev, "error %d reading SR\n", ret); 481 482 return ret; 483 } 484 485 /** 486 * spi_nor_read_cr() - Read the Configuration Register using the 487 * SPINOR_OP_RDCR (35h) command. 488 * @nor: pointer to 'struct spi_nor' 489 * @cr: pointer to a DMA-able buffer where the value of the 490 * Configuration Register will be written. 491 * 492 * Return: 0 on success, -errno otherwise. 493 */ 494 int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) 495 { 496 int ret; 497 498 if (nor->spimem) { 499 struct spi_mem_op op = SPI_NOR_RDCR_OP(cr); 500 501 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 502 503 ret = spi_mem_exec_op(nor->spimem, &op); 504 } else { 505 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr, 506 1); 507 } 508 509 if (ret) 510 dev_dbg(nor->dev, "error %d reading CR\n", ret); 511 512 return ret; 513 } 514 515 /** 516 * spi_nor_set_4byte_addr_mode_en4b_ex4b() - Enter/Exit 4-byte address mode 517 * using SPINOR_OP_EN4B/SPINOR_OP_EX4B. Typically used by 518 * Winbond and Macronix. 519 * @nor: pointer to 'struct spi_nor'. 520 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 521 * address mode. 522 * 523 * Return: 0 on success, -errno otherwise. 524 */ 525 int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor *nor, bool enable) 526 { 527 int ret; 528 529 if (nor->spimem) { 530 struct spi_mem_op op = SPI_NOR_EN4B_EX4B_OP(enable); 531 532 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 533 534 ret = spi_mem_exec_op(nor->spimem, &op); 535 } else { 536 ret = spi_nor_controller_ops_write_reg(nor, 537 enable ? SPINOR_OP_EN4B : 538 SPINOR_OP_EX4B, 539 NULL, 0); 540 } 541 542 if (ret) 543 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); 544 545 return ret; 546 } 547 548 /** 549 * spi_nor_set_4byte_addr_mode_wren_en4b_ex4b() - Set 4-byte address mode using 550 * SPINOR_OP_WREN followed by SPINOR_OP_EN4B or SPINOR_OP_EX4B. Typically used 551 * by ST and Micron flashes. 552 * @nor: pointer to 'struct spi_nor'. 553 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 554 * address mode. 555 * 556 * Return: 0 on success, -errno otherwise. 557 */ 558 int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool enable) 559 { 560 int ret; 561 562 ret = spi_nor_write_enable(nor); 563 if (ret) 564 return ret; 565 566 ret = spi_nor_set_4byte_addr_mode_en4b_ex4b(nor, enable); 567 if (ret) 568 return ret; 569 570 return spi_nor_write_disable(nor); 571 } 572 573 /** 574 * spi_nor_set_4byte_addr_mode_brwr() - Set 4-byte address mode using 575 * SPINOR_OP_BRWR. Typically used by Spansion flashes. 576 * @nor: pointer to 'struct spi_nor'. 577 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 578 * address mode. 579 * 580 * 8-bit volatile bank register used to define A[30:A24] bits. MSB (bit[7]) is 581 * used to enable/disable 4-byte address mode. When MSB is set to ‘1’, 4-byte 582 * address mode is active and A[30:24] bits are don’t care. Write instruction is 583 * SPINOR_OP_BRWR(17h) with 1 byte of data. 584 * 585 * Return: 0 on success, -errno otherwise. 586 */ 587 int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable) 588 { 589 int ret; 590 591 nor->bouncebuf[0] = enable << 7; 592 593 if (nor->spimem) { 594 struct spi_mem_op op = SPI_NOR_BRWR_OP(nor->bouncebuf); 595 596 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 597 598 ret = spi_mem_exec_op(nor->spimem, &op); 599 } else { 600 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_BRWR, 601 nor->bouncebuf, 1); 602 } 603 604 if (ret) 605 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); 606 607 return ret; 608 } 609 610 /** 611 * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready 612 * for new commands. 613 * @nor: pointer to 'struct spi_nor'. 614 * 615 * Return: 1 if ready, 0 if not ready, -errno on errors. 616 */ 617 int spi_nor_sr_ready(struct spi_nor *nor) 618 { 619 int ret; 620 621 ret = spi_nor_read_sr(nor, nor->bouncebuf); 622 if (ret) 623 return ret; 624 625 return !(nor->bouncebuf[0] & SR_WIP); 626 } 627 628 /** 629 * spi_nor_use_parallel_locking() - Checks if RWW locking scheme shall be used 630 * @nor: pointer to 'struct spi_nor'. 631 * 632 * Return: true if parallel locking is enabled, false otherwise. 633 */ 634 static bool spi_nor_use_parallel_locking(struct spi_nor *nor) 635 { 636 return nor->flags & SNOR_F_RWW; 637 } 638 639 /* Locking helpers for status read operations */ 640 static int spi_nor_rww_start_rdst(struct spi_nor *nor) 641 { 642 struct spi_nor_rww *rww = &nor->rww; 643 644 guard(mutex)(&nor->lock); 645 646 if (rww->ongoing_io || rww->ongoing_rd) 647 return -EAGAIN; 648 649 rww->ongoing_io = true; 650 rww->ongoing_rd = true; 651 652 return 0; 653 } 654 655 static void spi_nor_rww_end_rdst(struct spi_nor *nor) 656 { 657 struct spi_nor_rww *rww = &nor->rww; 658 659 guard(mutex)(&nor->lock); 660 661 rww->ongoing_io = false; 662 rww->ongoing_rd = false; 663 } 664 665 static int spi_nor_lock_rdst(struct spi_nor *nor) 666 { 667 if (spi_nor_use_parallel_locking(nor)) 668 return spi_nor_rww_start_rdst(nor); 669 670 return 0; 671 } 672 673 static void spi_nor_unlock_rdst(struct spi_nor *nor) 674 { 675 if (spi_nor_use_parallel_locking(nor)) { 676 spi_nor_rww_end_rdst(nor); 677 wake_up(&nor->rww.wait); 678 } 679 } 680 681 /** 682 * spi_nor_ready() - Query the flash to see if it is ready for new commands. 683 * @nor: pointer to 'struct spi_nor'. 684 * 685 * Return: 1 if ready, 0 if not ready, -errno on errors. 686 */ 687 static int spi_nor_ready(struct spi_nor *nor) 688 { 689 int ret; 690 691 ret = spi_nor_lock_rdst(nor); 692 if (ret) 693 return 0; 694 695 /* Flashes might override the standard routine. */ 696 if (nor->params->ready) 697 ret = nor->params->ready(nor); 698 else 699 ret = spi_nor_sr_ready(nor); 700 701 spi_nor_unlock_rdst(nor); 702 703 return ret; 704 } 705 706 /** 707 * spi_nor_wait_till_ready_with_timeout() - Service routine to read the 708 * Status Register until ready, or timeout occurs. 709 * @nor: pointer to "struct spi_nor". 710 * @timeout_jiffies: jiffies to wait until timeout. 711 * 712 * Return: 0 on success, -errno otherwise. 713 */ 714 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, 715 unsigned long timeout_jiffies) 716 { 717 unsigned long deadline; 718 int timeout = 0, ret; 719 720 deadline = jiffies + timeout_jiffies; 721 722 while (!timeout) { 723 if (time_after_eq(jiffies, deadline)) 724 timeout = 1; 725 726 ret = spi_nor_ready(nor); 727 if (ret < 0) 728 return ret; 729 if (ret) 730 return 0; 731 732 cond_resched(); 733 } 734 735 dev_dbg(nor->dev, "flash operation timed out\n"); 736 737 return -ETIMEDOUT; 738 } 739 740 /** 741 * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the 742 * flash to be ready, or timeout occurs. 743 * @nor: pointer to "struct spi_nor". 744 * 745 * Return: 0 on success, -errno otherwise. 746 */ 747 int spi_nor_wait_till_ready(struct spi_nor *nor) 748 { 749 return spi_nor_wait_till_ready_with_timeout(nor, 750 DEFAULT_READY_WAIT_JIFFIES); 751 } 752 753 /** 754 * spi_nor_global_block_unlock() - Unlock Global Block Protection. 755 * @nor: pointer to 'struct spi_nor'. 756 * 757 * Return: 0 on success, -errno otherwise. 758 */ 759 int spi_nor_global_block_unlock(struct spi_nor *nor) 760 { 761 int ret; 762 763 ret = spi_nor_write_enable(nor); 764 if (ret) 765 return ret; 766 767 if (nor->spimem) { 768 struct spi_mem_op op = SPI_NOR_GBULK_OP; 769 770 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 771 772 ret = spi_mem_exec_op(nor->spimem, &op); 773 } else { 774 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_GBULK, 775 NULL, 0); 776 } 777 778 if (ret) { 779 dev_dbg(nor->dev, "error %d on Global Block Unlock\n", ret); 780 return ret; 781 } 782 783 return spi_nor_wait_till_ready(nor); 784 } 785 786 /** 787 * spi_nor_write_sr() - Write the Status Register. 788 * @nor: pointer to 'struct spi_nor'. 789 * @sr: pointer to DMA-able buffer to write to the Status Register. 790 * @len: number of bytes to write to the Status Register. 791 * 792 * Return: 0 on success, -errno otherwise. 793 */ 794 int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) 795 { 796 int ret; 797 798 ret = spi_nor_write_enable(nor); 799 if (ret) 800 return ret; 801 802 if (nor->spimem) { 803 struct spi_mem_op op = SPI_NOR_WRSR_OP(sr, len); 804 805 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 806 807 ret = spi_mem_exec_op(nor->spimem, &op); 808 } else { 809 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr, 810 len); 811 } 812 813 if (ret) { 814 dev_dbg(nor->dev, "error %d writing SR\n", ret); 815 return ret; 816 } 817 818 return spi_nor_wait_till_ready(nor); 819 } 820 821 /** 822 * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and 823 * ensure that the byte written match the received value. 824 * @nor: pointer to a 'struct spi_nor'. 825 * @sr1: byte value to be written to the Status Register. 826 * 827 * Return: 0 on success, -errno otherwise. 828 */ 829 static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1) 830 { 831 int ret; 832 833 nor->bouncebuf[0] = sr1; 834 835 ret = spi_nor_write_sr(nor, nor->bouncebuf, 1); 836 if (ret) 837 return ret; 838 839 ret = spi_nor_read_sr(nor, nor->bouncebuf); 840 if (ret) 841 return ret; 842 843 if (nor->bouncebuf[0] != sr1) { 844 dev_dbg(nor->dev, "SR1: read back test failed\n"); 845 return -EIO; 846 } 847 848 return 0; 849 } 850 851 /** 852 * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the 853 * Status Register 2 in one shot. Ensure that the byte written in the Status 854 * Register 1 match the received value, and that the 16-bit Write did not 855 * affect what was already in the Status Register 2. 856 * @nor: pointer to a 'struct spi_nor'. 857 * @sr1: byte value to be written to the Status Register 1. 858 * 859 * Return: 0 on success, -errno otherwise. 860 */ 861 static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1) 862 { 863 int ret; 864 u8 *sr_cr = nor->bouncebuf; 865 u8 cr_written; 866 867 /* Make sure we don't overwrite the contents of Status Register 2. */ 868 if (!(nor->flags & SNOR_F_NO_READ_CR)) { 869 ret = spi_nor_read_cr(nor, &sr_cr[1]); 870 if (ret) 871 return ret; 872 } else if ((spi_nor_get_protocol_width(nor->read_proto) == 4 || 873 spi_nor_get_protocol_width(nor->write_proto) == 4) && 874 nor->params->quad_enable) { 875 /* 876 * If the Status Register 2 Read command (35h) is not 877 * supported, we should at least be sure we don't 878 * change the value of the SR2 Quad Enable bit. 879 * 880 * When the Quad Enable method is set and the buswidth is 4, we 881 * can safely assume that the value of the QE bit is one, as a 882 * consequence of the nor->params->quad_enable() call. 883 * 884 * According to the JESD216 revB standard, BFPT DWORDS[15], 885 * bits 22:20, the 16-bit Write Status (01h) command is 886 * available just for the cases in which the QE bit is 887 * described in SR2 at BIT(1). 888 */ 889 sr_cr[1] = SR2_QUAD_EN_BIT1; 890 } else { 891 sr_cr[1] = 0; 892 } 893 894 sr_cr[0] = sr1; 895 896 ret = spi_nor_write_sr(nor, sr_cr, 2); 897 if (ret) 898 return ret; 899 900 ret = spi_nor_read_sr(nor, sr_cr); 901 if (ret) 902 return ret; 903 904 if (sr1 != sr_cr[0]) { 905 dev_dbg(nor->dev, "SR: Read back test failed\n"); 906 return -EIO; 907 } 908 909 if (nor->flags & SNOR_F_NO_READ_CR) 910 return 0; 911 912 cr_written = sr_cr[1]; 913 914 ret = spi_nor_read_cr(nor, &sr_cr[1]); 915 if (ret) 916 return ret; 917 918 if (cr_written != sr_cr[1]) { 919 dev_dbg(nor->dev, "CR: read back test failed\n"); 920 return -EIO; 921 } 922 923 return 0; 924 } 925 926 /** 927 * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the 928 * Configuration Register in one shot. Ensure that the byte written in the 929 * Configuration Register match the received value, and that the 16-bit Write 930 * did not affect what was already in the Status Register 1. 931 * @nor: pointer to a 'struct spi_nor'. 932 * @cr: byte value to be written to the Configuration Register. 933 * 934 * Return: 0 on success, -errno otherwise. 935 */ 936 int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr) 937 { 938 int ret; 939 u8 *sr_cr = nor->bouncebuf; 940 u8 sr_written; 941 942 /* Keep the current value of the Status Register 1. */ 943 ret = spi_nor_read_sr(nor, sr_cr); 944 if (ret) 945 return ret; 946 947 sr_cr[1] = cr; 948 949 ret = spi_nor_write_sr(nor, sr_cr, 2); 950 if (ret) 951 return ret; 952 953 sr_written = sr_cr[0]; 954 955 ret = spi_nor_read_sr(nor, sr_cr); 956 if (ret) 957 return ret; 958 959 if (sr_written != sr_cr[0]) { 960 dev_dbg(nor->dev, "SR: Read back test failed\n"); 961 return -EIO; 962 } 963 964 if (nor->flags & SNOR_F_NO_READ_CR) 965 return 0; 966 967 ret = spi_nor_read_cr(nor, &sr_cr[1]); 968 if (ret) 969 return ret; 970 971 if (cr != sr_cr[1]) { 972 dev_dbg(nor->dev, "CR: read back test failed\n"); 973 return -EIO; 974 } 975 976 return 0; 977 } 978 979 /** 980 * spi_nor_write_16bit_sr_cr_and_check() - Write the Status Register 1 and the 981 * Configuration Register in one shot. Ensure that the bytes written in both 982 * registers match the received value. 983 * @nor: pointer to a 'struct spi_nor'. 984 * @regs: two-byte array with values to be written to the status and 985 * configuration registers. 986 * 987 * Return: 0 on success, -errno otherwise. 988 */ 989 static int spi_nor_write_16bit_sr_cr_and_check(struct spi_nor *nor, const u8 *regs) 990 { 991 u8 written_regs[2]; 992 int ret; 993 994 written_regs[0] = regs[0]; 995 written_regs[1] = regs[1]; 996 nor->bouncebuf[0] = regs[0]; 997 nor->bouncebuf[1] = regs[1]; 998 999 ret = spi_nor_write_sr(nor, nor->bouncebuf, 2); 1000 if (ret) 1001 return ret; 1002 1003 ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]); 1004 if (ret) 1005 return ret; 1006 1007 if (written_regs[0] != nor->bouncebuf[0]) { 1008 dev_dbg(nor->dev, "SR: Read back test failed\n"); 1009 return -EIO; 1010 } 1011 1012 if (nor->flags & SNOR_F_NO_READ_CR) 1013 return 0; 1014 1015 ret = spi_nor_read_cr(nor, &nor->bouncebuf[1]); 1016 if (ret) 1017 return ret; 1018 1019 if (written_regs[1] != nor->bouncebuf[1]) { 1020 dev_dbg(nor->dev, "CR: read back test failed\n"); 1021 return -EIO; 1022 } 1023 1024 return 0; 1025 } 1026 1027 /** 1028 * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that 1029 * the byte written match the received value without affecting other bits in the 1030 * Status Register 1 and 2. 1031 * @nor: pointer to a 'struct spi_nor'. 1032 * @sr1: byte value to be written to the Status Register. 1033 * 1034 * Return: 0 on success, -errno otherwise. 1035 */ 1036 int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1) 1037 { 1038 if (nor->flags & SNOR_F_HAS_16BIT_SR) 1039 return spi_nor_write_16bit_sr_and_check(nor, sr1); 1040 1041 return spi_nor_write_sr1_and_check(nor, sr1); 1042 } 1043 1044 /** 1045 * spi_nor_write_sr_cr_and_check() - Write the Status Register 1 and ensure that 1046 * the byte written match the received value. Same for the Control Register if 1047 * available. 1048 * @nor: pointer to a 'struct spi_nor'. 1049 * @regs: byte array to be written to the registers. 1050 * 1051 * Return: 0 on success, -errno otherwise. 1052 */ 1053 int spi_nor_write_sr_cr_and_check(struct spi_nor *nor, const u8 *regs) 1054 { 1055 if (nor->flags & SNOR_F_HAS_16BIT_SR) 1056 return spi_nor_write_16bit_sr_cr_and_check(nor, regs); 1057 1058 return spi_nor_write_sr1_and_check(nor, regs[0]); 1059 } 1060 1061 /** 1062 * spi_nor_write_sr2() - Write the Status Register 2 using the 1063 * SPINOR_OP_WRSR2 (3eh) command. 1064 * @nor: pointer to 'struct spi_nor'. 1065 * @sr2: pointer to DMA-able buffer to write to the Status Register 2. 1066 * 1067 * Return: 0 on success, -errno otherwise. 1068 */ 1069 static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2) 1070 { 1071 int ret; 1072 1073 ret = spi_nor_write_enable(nor); 1074 if (ret) 1075 return ret; 1076 1077 if (nor->spimem) { 1078 struct spi_mem_op op = SPI_NOR_WRSR2_OP(sr2); 1079 1080 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 1081 1082 ret = spi_mem_exec_op(nor->spimem, &op); 1083 } else { 1084 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2, 1085 sr2, 1); 1086 } 1087 1088 if (ret) { 1089 dev_dbg(nor->dev, "error %d writing SR2\n", ret); 1090 return ret; 1091 } 1092 1093 return spi_nor_wait_till_ready(nor); 1094 } 1095 1096 /** 1097 * spi_nor_read_sr2() - Read the Status Register 2 using the 1098 * SPINOR_OP_RDSR2 (3fh) command. 1099 * @nor: pointer to 'struct spi_nor'. 1100 * @sr2: pointer to DMA-able buffer where the value of the 1101 * Status Register 2 will be written. 1102 * 1103 * Return: 0 on success, -errno otherwise. 1104 */ 1105 static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) 1106 { 1107 int ret; 1108 1109 if (nor->spimem) { 1110 struct spi_mem_op op = SPI_NOR_RDSR2_OP(sr2); 1111 1112 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 1113 1114 ret = spi_mem_exec_op(nor->spimem, &op); 1115 } else { 1116 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2, 1117 1); 1118 } 1119 1120 if (ret) 1121 dev_dbg(nor->dev, "error %d reading SR2\n", ret); 1122 1123 return ret; 1124 } 1125 1126 /** 1127 * spi_nor_erase_die() - Erase the entire die. 1128 * @nor: pointer to 'struct spi_nor'. 1129 * @addr: address of the die. 1130 * @die_size: size of the die. 1131 * 1132 * Return: 0 on success, -errno otherwise. 1133 */ 1134 static int spi_nor_erase_die(struct spi_nor *nor, loff_t addr, size_t die_size) 1135 { 1136 bool multi_die = nor->mtd.size != die_size; 1137 int ret; 1138 1139 dev_dbg(nor->dev, " %lldKiB\n", (long long)(die_size >> 10)); 1140 1141 if (nor->spimem) { 1142 struct spi_mem_op op = 1143 SPI_NOR_DIE_ERASE_OP(nor->params->die_erase_opcode, 1144 nor->addr_nbytes, addr, multi_die); 1145 1146 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 1147 1148 ret = spi_mem_exec_op(nor->spimem, &op); 1149 } else { 1150 if (multi_die) 1151 return -EOPNOTSUPP; 1152 1153 ret = spi_nor_controller_ops_write_reg(nor, 1154 SPINOR_OP_CHIP_ERASE, 1155 NULL, 0); 1156 } 1157 1158 if (ret) 1159 dev_dbg(nor->dev, "error %d erasing chip\n", ret); 1160 1161 return ret; 1162 } 1163 1164 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) 1165 { 1166 size_t i; 1167 1168 for (i = 0; i < size; i++) 1169 if (table[i][0] == opcode) 1170 return table[i][1]; 1171 1172 /* No conversion found, keep input op code. */ 1173 return opcode; 1174 } 1175 1176 u8 spi_nor_convert_3to4_read(u8 opcode) 1177 { 1178 static const u8 spi_nor_3to4_read[][2] = { 1179 { SPINOR_OP_READ, SPINOR_OP_READ_4B }, 1180 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B }, 1181 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B }, 1182 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, 1183 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, 1184 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, 1185 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B }, 1186 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B }, 1187 1188 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B }, 1189 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B }, 1190 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B }, 1191 }; 1192 1193 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, 1194 ARRAY_SIZE(spi_nor_3to4_read)); 1195 } 1196 1197 static u8 spi_nor_convert_3to4_program(u8 opcode) 1198 { 1199 static const u8 spi_nor_3to4_program[][2] = { 1200 { SPINOR_OP_PP, SPINOR_OP_PP_4B }, 1201 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B }, 1202 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B }, 1203 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B }, 1204 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B }, 1205 }; 1206 1207 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, 1208 ARRAY_SIZE(spi_nor_3to4_program)); 1209 } 1210 1211 static u8 spi_nor_convert_3to4_erase(u8 opcode) 1212 { 1213 static const u8 spi_nor_3to4_erase[][2] = { 1214 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B }, 1215 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B }, 1216 { SPINOR_OP_SE, SPINOR_OP_SE_4B }, 1217 }; 1218 1219 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase, 1220 ARRAY_SIZE(spi_nor_3to4_erase)); 1221 } 1222 1223 static bool spi_nor_has_uniform_erase(const struct spi_nor *nor) 1224 { 1225 return !!nor->params->erase_map.uniform_region.erase_mask; 1226 } 1227 1228 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor) 1229 { 1230 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); 1231 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode); 1232 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode); 1233 1234 if (!spi_nor_has_uniform_erase(nor)) { 1235 struct spi_nor_erase_map *map = &nor->params->erase_map; 1236 struct spi_nor_erase_type *erase; 1237 int i; 1238 1239 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { 1240 erase = &map->erase_type[i]; 1241 erase->opcode = 1242 spi_nor_convert_3to4_erase(erase->opcode); 1243 } 1244 } 1245 } 1246 1247 static int spi_nor_prep(struct spi_nor *nor) 1248 { 1249 int ret = 0; 1250 1251 if (nor->controller_ops && nor->controller_ops->prepare) 1252 ret = nor->controller_ops->prepare(nor); 1253 1254 return ret; 1255 } 1256 1257 static void spi_nor_unprep(struct spi_nor *nor) 1258 { 1259 if (nor->controller_ops && nor->controller_ops->unprepare) 1260 nor->controller_ops->unprepare(nor); 1261 } 1262 1263 static void spi_nor_offset_to_banks(u64 bank_size, loff_t start, size_t len, 1264 u8 *first, u8 *last) 1265 { 1266 /* This is currently safe, the number of banks being very small */ 1267 *first = DIV_ROUND_DOWN_ULL(start, bank_size); 1268 *last = DIV_ROUND_DOWN_ULL(start + len - 1, bank_size); 1269 } 1270 1271 /* Generic helpers for internal locking and serialization */ 1272 static bool spi_nor_rww_start_io(struct spi_nor *nor) 1273 { 1274 struct spi_nor_rww *rww = &nor->rww; 1275 1276 guard(mutex)(&nor->lock); 1277 1278 if (rww->ongoing_io) 1279 return false; 1280 1281 rww->ongoing_io = true; 1282 1283 return true; 1284 } 1285 1286 static void spi_nor_rww_end_io(struct spi_nor *nor) 1287 { 1288 guard(mutex)(&nor->lock); 1289 nor->rww.ongoing_io = false; 1290 } 1291 1292 static int spi_nor_lock_device(struct spi_nor *nor) 1293 { 1294 if (!spi_nor_use_parallel_locking(nor)) 1295 return 0; 1296 1297 return wait_event_killable(nor->rww.wait, spi_nor_rww_start_io(nor)); 1298 } 1299 1300 static void spi_nor_unlock_device(struct spi_nor *nor) 1301 { 1302 if (spi_nor_use_parallel_locking(nor)) { 1303 spi_nor_rww_end_io(nor); 1304 wake_up(&nor->rww.wait); 1305 } 1306 } 1307 1308 /* Generic helpers for internal locking and serialization */ 1309 static bool spi_nor_rww_start_exclusive(struct spi_nor *nor) 1310 { 1311 struct spi_nor_rww *rww = &nor->rww; 1312 1313 mutex_lock(&nor->lock); 1314 1315 if (rww->ongoing_io || rww->ongoing_rd || rww->ongoing_pe) 1316 return false; 1317 1318 rww->ongoing_io = true; 1319 rww->ongoing_rd = true; 1320 rww->ongoing_pe = true; 1321 1322 return true; 1323 } 1324 1325 static void spi_nor_rww_end_exclusive(struct spi_nor *nor) 1326 { 1327 struct spi_nor_rww *rww = &nor->rww; 1328 1329 guard(mutex)(&nor->lock); 1330 rww->ongoing_io = false; 1331 rww->ongoing_rd = false; 1332 rww->ongoing_pe = false; 1333 } 1334 1335 int spi_nor_prep_and_lock(struct spi_nor *nor) 1336 { 1337 int ret; 1338 1339 ret = spi_nor_prep(nor); 1340 if (ret) 1341 return ret; 1342 1343 if (!spi_nor_use_parallel_locking(nor)) 1344 mutex_lock(&nor->lock); 1345 else 1346 ret = wait_event_killable(nor->rww.wait, 1347 spi_nor_rww_start_exclusive(nor)); 1348 1349 return ret; 1350 } 1351 1352 void spi_nor_unlock_and_unprep(struct spi_nor *nor) 1353 { 1354 if (!spi_nor_use_parallel_locking(nor)) { 1355 mutex_unlock(&nor->lock); 1356 } else { 1357 spi_nor_rww_end_exclusive(nor); 1358 wake_up(&nor->rww.wait); 1359 } 1360 1361 spi_nor_unprep(nor); 1362 } 1363 1364 /* Internal locking helpers for program and erase operations */ 1365 static bool spi_nor_rww_start_pe(struct spi_nor *nor, loff_t start, size_t len) 1366 { 1367 struct spi_nor_rww *rww = &nor->rww; 1368 unsigned int used_banks = 0; 1369 u8 first, last; 1370 int bank; 1371 1372 guard(mutex)(&nor->lock); 1373 1374 if (rww->ongoing_io || rww->ongoing_rd || rww->ongoing_pe) 1375 return false; 1376 1377 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last); 1378 for (bank = first; bank <= last; bank++) { 1379 if (rww->used_banks & BIT(bank)) 1380 return false; 1381 1382 used_banks |= BIT(bank); 1383 } 1384 1385 rww->used_banks |= used_banks; 1386 rww->ongoing_pe = true; 1387 1388 return true; 1389 } 1390 1391 static void spi_nor_rww_end_pe(struct spi_nor *nor, loff_t start, size_t len) 1392 { 1393 struct spi_nor_rww *rww = &nor->rww; 1394 u8 first, last; 1395 int bank; 1396 1397 guard(mutex)(&nor->lock); 1398 1399 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last); 1400 for (bank = first; bank <= last; bank++) 1401 rww->used_banks &= ~BIT(bank); 1402 1403 rww->ongoing_pe = false; 1404 } 1405 1406 static int spi_nor_prep_and_lock_pe(struct spi_nor *nor, loff_t start, size_t len) 1407 { 1408 int ret; 1409 1410 ret = spi_nor_prep(nor); 1411 if (ret) 1412 return ret; 1413 1414 if (!spi_nor_use_parallel_locking(nor)) 1415 mutex_lock(&nor->lock); 1416 else 1417 ret = wait_event_killable(nor->rww.wait, 1418 spi_nor_rww_start_pe(nor, start, len)); 1419 1420 return ret; 1421 } 1422 1423 static void spi_nor_unlock_and_unprep_pe(struct spi_nor *nor, loff_t start, size_t len) 1424 { 1425 if (!spi_nor_use_parallel_locking(nor)) { 1426 mutex_unlock(&nor->lock); 1427 } else { 1428 spi_nor_rww_end_pe(nor, start, len); 1429 wake_up(&nor->rww.wait); 1430 } 1431 1432 spi_nor_unprep(nor); 1433 } 1434 1435 /* Internal locking helpers for read operations */ 1436 static bool spi_nor_rww_start_rd(struct spi_nor *nor, loff_t start, size_t len) 1437 { 1438 struct spi_nor_rww *rww = &nor->rww; 1439 unsigned int used_banks = 0; 1440 u8 first, last; 1441 int bank; 1442 1443 guard(mutex)(&nor->lock); 1444 1445 if (rww->ongoing_io || rww->ongoing_rd) 1446 return false; 1447 1448 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last); 1449 for (bank = first; bank <= last; bank++) { 1450 if (rww->used_banks & BIT(bank)) 1451 return false; 1452 1453 used_banks |= BIT(bank); 1454 } 1455 1456 rww->used_banks |= used_banks; 1457 rww->ongoing_io = true; 1458 rww->ongoing_rd = true; 1459 1460 return true; 1461 } 1462 1463 static void spi_nor_rww_end_rd(struct spi_nor *nor, loff_t start, size_t len) 1464 { 1465 struct spi_nor_rww *rww = &nor->rww; 1466 u8 first, last; 1467 int bank; 1468 1469 guard(mutex)(&nor->lock); 1470 1471 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last); 1472 for (bank = first; bank <= last; bank++) 1473 nor->rww.used_banks &= ~BIT(bank); 1474 1475 rww->ongoing_io = false; 1476 rww->ongoing_rd = false; 1477 } 1478 1479 static int spi_nor_prep_and_lock_rd(struct spi_nor *nor, loff_t start, size_t len) 1480 { 1481 int ret; 1482 1483 ret = spi_nor_prep(nor); 1484 if (ret) 1485 return ret; 1486 1487 if (!spi_nor_use_parallel_locking(nor)) 1488 mutex_lock(&nor->lock); 1489 else 1490 ret = wait_event_killable(nor->rww.wait, 1491 spi_nor_rww_start_rd(nor, start, len)); 1492 1493 return ret; 1494 } 1495 1496 static void spi_nor_unlock_and_unprep_rd(struct spi_nor *nor, loff_t start, size_t len) 1497 { 1498 if (!spi_nor_use_parallel_locking(nor)) { 1499 mutex_unlock(&nor->lock); 1500 } else { 1501 spi_nor_rww_end_rd(nor, start, len); 1502 wake_up(&nor->rww.wait); 1503 } 1504 1505 spi_nor_unprep(nor); 1506 } 1507 1508 /* 1509 * Initiate the erasure of a single sector 1510 */ 1511 int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) 1512 { 1513 int i; 1514 1515 if (nor->spimem) { 1516 struct spi_mem_op op = 1517 SPI_NOR_SECTOR_ERASE_OP(nor->erase_opcode, 1518 nor->addr_nbytes, addr); 1519 1520 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 1521 1522 return spi_mem_exec_op(nor->spimem, &op); 1523 } else if (nor->controller_ops->erase) { 1524 return spi_nor_controller_ops_erase(nor, addr); 1525 } 1526 1527 /* 1528 * Default implementation, if driver doesn't have a specialized HW 1529 * control 1530 */ 1531 for (i = nor->addr_nbytes - 1; i >= 0; i--) { 1532 nor->bouncebuf[i] = addr & 0xff; 1533 addr >>= 8; 1534 } 1535 1536 return spi_nor_controller_ops_write_reg(nor, nor->erase_opcode, 1537 nor->bouncebuf, nor->addr_nbytes); 1538 } 1539 1540 /** 1541 * spi_nor_div_by_erase_size() - calculate remainder and update new dividend 1542 * @erase: pointer to a structure that describes a SPI NOR erase type 1543 * @dividend: dividend value 1544 * @remainder: pointer to u32 remainder (will be updated) 1545 * 1546 * Return: the result of the division 1547 */ 1548 static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase, 1549 u64 dividend, u32 *remainder) 1550 { 1551 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */ 1552 *remainder = (u32)dividend & erase->size_mask; 1553 return dividend >> erase->size_shift; 1554 } 1555 1556 /** 1557 * spi_nor_find_best_erase_type() - find the best erase type for the given 1558 * offset in the serial flash memory and the 1559 * number of bytes to erase. The region in 1560 * which the address fits is expected to be 1561 * provided. 1562 * @map: the erase map of the SPI NOR 1563 * @region: pointer to a structure that describes a SPI NOR erase region 1564 * @addr: offset in the serial flash memory 1565 * @len: number of bytes to erase 1566 * 1567 * Return: a pointer to the best fitted erase type, NULL otherwise. 1568 */ 1569 static const struct spi_nor_erase_type * 1570 spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map, 1571 const struct spi_nor_erase_region *region, 1572 u64 addr, u32 len) 1573 { 1574 const struct spi_nor_erase_type *erase; 1575 u32 rem; 1576 int i; 1577 1578 /* 1579 * Erase types are ordered by size, with the smallest erase type at 1580 * index 0. 1581 */ 1582 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 1583 /* Does the erase region support the tested erase type? */ 1584 if (!(region->erase_mask & BIT(i))) 1585 continue; 1586 1587 erase = &map->erase_type[i]; 1588 if (!erase->size) 1589 continue; 1590 1591 /* Alignment is not mandatory for overlaid regions */ 1592 if (region->overlaid && region->size <= len) 1593 return erase; 1594 1595 /* Don't erase more than what the user has asked for. */ 1596 if (erase->size > len) 1597 continue; 1598 1599 spi_nor_div_by_erase_size(erase, addr, &rem); 1600 if (!rem) 1601 return erase; 1602 } 1603 1604 return NULL; 1605 } 1606 1607 /** 1608 * spi_nor_init_erase_cmd() - initialize an erase command 1609 * @region: pointer to a structure that describes a SPI NOR erase region 1610 * @erase: pointer to a structure that describes a SPI NOR erase type 1611 * 1612 * Return: the pointer to the allocated erase command, ERR_PTR(-errno) 1613 * otherwise. 1614 */ 1615 static struct spi_nor_erase_command * 1616 spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region, 1617 const struct spi_nor_erase_type *erase) 1618 { 1619 struct spi_nor_erase_command *cmd; 1620 1621 cmd = kmalloc_obj(*cmd); 1622 if (!cmd) 1623 return ERR_PTR(-ENOMEM); 1624 1625 INIT_LIST_HEAD(&cmd->list); 1626 cmd->opcode = erase->opcode; 1627 cmd->count = 1; 1628 1629 if (region->overlaid) 1630 cmd->size = region->size; 1631 else 1632 cmd->size = erase->size; 1633 1634 return cmd; 1635 } 1636 1637 /** 1638 * spi_nor_destroy_erase_cmd_list() - destroy erase command list 1639 * @erase_list: list of erase commands 1640 */ 1641 static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list) 1642 { 1643 struct spi_nor_erase_command *cmd, *next; 1644 1645 list_for_each_entry_safe(cmd, next, erase_list, list) { 1646 list_del(&cmd->list); 1647 kfree(cmd); 1648 } 1649 } 1650 1651 /** 1652 * spi_nor_init_erase_cmd_list() - initialize erase command list 1653 * @nor: pointer to a 'struct spi_nor' 1654 * @erase_list: list of erase commands to be executed once we validate that the 1655 * erase can be performed 1656 * @addr: offset in the serial flash memory 1657 * @len: number of bytes to erase 1658 * 1659 * Builds the list of best fitted erase commands and verifies if the erase can 1660 * be performed. 1661 * 1662 * Return: 0 on success, -errno otherwise. 1663 */ 1664 static int spi_nor_init_erase_cmd_list(struct spi_nor *nor, 1665 struct list_head *erase_list, 1666 u64 addr, u32 len) 1667 { 1668 const struct spi_nor_erase_map *map = &nor->params->erase_map; 1669 const struct spi_nor_erase_type *erase, *prev_erase = NULL; 1670 struct spi_nor_erase_region *region; 1671 struct spi_nor_erase_command *cmd = NULL; 1672 u64 region_end; 1673 unsigned int i; 1674 int ret = -EINVAL; 1675 1676 for (i = 0; i < map->n_regions && len; i++) { 1677 region = &map->regions[i]; 1678 region_end = region->offset + region->size; 1679 1680 while (len && addr >= region->offset && addr < region_end) { 1681 erase = spi_nor_find_best_erase_type(map, region, addr, 1682 len); 1683 if (!erase) 1684 goto destroy_erase_cmd_list; 1685 1686 if (prev_erase != erase || erase->size != cmd->size || 1687 region->overlaid) { 1688 cmd = spi_nor_init_erase_cmd(region, erase); 1689 if (IS_ERR(cmd)) { 1690 ret = PTR_ERR(cmd); 1691 goto destroy_erase_cmd_list; 1692 } 1693 1694 list_add_tail(&cmd->list, erase_list); 1695 } else { 1696 cmd->count++; 1697 } 1698 1699 len -= cmd->size; 1700 addr += cmd->size; 1701 prev_erase = erase; 1702 } 1703 } 1704 1705 return 0; 1706 1707 destroy_erase_cmd_list: 1708 spi_nor_destroy_erase_cmd_list(erase_list); 1709 return ret; 1710 } 1711 1712 /** 1713 * spi_nor_erase_multi_sectors() - perform a non-uniform erase 1714 * @nor: pointer to a 'struct spi_nor' 1715 * @addr: offset in the serial flash memory 1716 * @len: number of bytes to erase 1717 * 1718 * Build a list of best fitted erase commands and execute it once we validate 1719 * that the erase can be performed. 1720 * 1721 * Return: 0 on success, -errno otherwise. 1722 */ 1723 static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len) 1724 { 1725 LIST_HEAD(erase_list); 1726 struct spi_nor_erase_command *cmd, *next; 1727 int ret; 1728 1729 ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len); 1730 if (ret) 1731 return ret; 1732 1733 list_for_each_entry_safe(cmd, next, &erase_list, list) { 1734 nor->erase_opcode = cmd->opcode; 1735 while (cmd->count) { 1736 dev_vdbg(nor->dev, "erase_cmd->size = 0x%08x, erase_cmd->opcode = 0x%02x, erase_cmd->count = %u\n", 1737 cmd->size, cmd->opcode, cmd->count); 1738 1739 ret = spi_nor_lock_device(nor); 1740 if (ret) 1741 goto destroy_erase_cmd_list; 1742 1743 ret = spi_nor_write_enable(nor); 1744 if (ret) { 1745 spi_nor_unlock_device(nor); 1746 goto destroy_erase_cmd_list; 1747 } 1748 1749 ret = spi_nor_erase_sector(nor, addr); 1750 spi_nor_unlock_device(nor); 1751 if (ret) 1752 goto destroy_erase_cmd_list; 1753 1754 ret = spi_nor_wait_till_ready(nor); 1755 if (ret) 1756 goto destroy_erase_cmd_list; 1757 1758 addr += cmd->size; 1759 cmd->count--; 1760 } 1761 list_del(&cmd->list); 1762 kfree(cmd); 1763 } 1764 1765 return 0; 1766 1767 destroy_erase_cmd_list: 1768 spi_nor_destroy_erase_cmd_list(&erase_list); 1769 return ret; 1770 } 1771 1772 static int spi_nor_erase_dice(struct spi_nor *nor, loff_t addr, 1773 size_t len, size_t die_size) 1774 { 1775 unsigned long timeout; 1776 int ret; 1777 1778 /* 1779 * Scale the timeout linearly with the size of the flash, with 1780 * a minimum calibrated to an old 2MB flash. We could try to 1781 * pull these from CFI/SFDP, but these values should be good 1782 * enough for now. 1783 */ 1784 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, 1785 CHIP_ERASE_2MB_READY_WAIT_JIFFIES * 1786 (unsigned long)(nor->mtd.size / SZ_2M)); 1787 1788 do { 1789 ret = spi_nor_lock_device(nor); 1790 if (ret) 1791 return ret; 1792 1793 ret = spi_nor_write_enable(nor); 1794 if (ret) { 1795 spi_nor_unlock_device(nor); 1796 return ret; 1797 } 1798 1799 ret = spi_nor_erase_die(nor, addr, die_size); 1800 1801 spi_nor_unlock_device(nor); 1802 if (ret) 1803 return ret; 1804 1805 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); 1806 if (ret) 1807 return ret; 1808 1809 addr += die_size; 1810 len -= die_size; 1811 1812 } while (len); 1813 1814 return 0; 1815 } 1816 1817 /* 1818 * Erase an address range on the nor chip. The address range may extend 1819 * one or more erase sectors. Return an error if there is a problem erasing. 1820 */ 1821 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) 1822 { 1823 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1824 u8 n_dice = nor->params->n_dice; 1825 bool multi_die_erase = false; 1826 u32 addr, len, rem; 1827 size_t die_size; 1828 int ret; 1829 1830 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, 1831 (long long)instr->len); 1832 1833 if (spi_nor_has_uniform_erase(nor)) { 1834 div_u64_rem(instr->len, mtd->erasesize, &rem); 1835 if (rem) 1836 return -EINVAL; 1837 } 1838 1839 addr = instr->addr; 1840 len = instr->len; 1841 1842 if (n_dice) { 1843 die_size = div_u64(mtd->size, n_dice); 1844 if (!(len & (die_size - 1)) && !(addr & (die_size - 1))) 1845 multi_die_erase = true; 1846 } else { 1847 die_size = mtd->size; 1848 } 1849 1850 ret = spi_nor_prep_and_lock_pe(nor, instr->addr, instr->len); 1851 if (ret) 1852 return ret; 1853 1854 /* chip (die) erase? */ 1855 if ((len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) || 1856 multi_die_erase) { 1857 ret = spi_nor_erase_dice(nor, addr, len, die_size); 1858 if (ret) 1859 goto erase_err; 1860 1861 /* REVISIT in some cases we could speed up erasing large regions 1862 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up 1863 * to use "small sector erase", but that's not always optimal. 1864 */ 1865 1866 /* "sector"-at-a-time erase */ 1867 } else if (spi_nor_has_uniform_erase(nor)) { 1868 while (len) { 1869 ret = spi_nor_lock_device(nor); 1870 if (ret) 1871 goto erase_err; 1872 1873 ret = spi_nor_write_enable(nor); 1874 if (ret) { 1875 spi_nor_unlock_device(nor); 1876 goto erase_err; 1877 } 1878 1879 ret = spi_nor_erase_sector(nor, addr); 1880 spi_nor_unlock_device(nor); 1881 if (ret) 1882 goto erase_err; 1883 1884 ret = spi_nor_wait_till_ready(nor); 1885 if (ret) 1886 goto erase_err; 1887 1888 addr += mtd->erasesize; 1889 len -= mtd->erasesize; 1890 } 1891 1892 /* erase multiple sectors */ 1893 } else { 1894 ret = spi_nor_erase_multi_sectors(nor, addr, len); 1895 if (ret) 1896 goto erase_err; 1897 } 1898 1899 ret = spi_nor_write_disable(nor); 1900 1901 erase_err: 1902 spi_nor_unlock_and_unprep_pe(nor, instr->addr, instr->len); 1903 1904 return ret; 1905 } 1906 1907 /** 1908 * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status 1909 * Register 1. 1910 * @nor: pointer to a 'struct spi_nor' 1911 * 1912 * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. 1913 * 1914 * Return: 0 on success, -errno otherwise. 1915 */ 1916 int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) 1917 { 1918 int ret; 1919 1920 ret = spi_nor_read_sr(nor, nor->bouncebuf); 1921 if (ret) 1922 return ret; 1923 1924 if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) 1925 return 0; 1926 1927 nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; 1928 1929 return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); 1930 } 1931 1932 /** 1933 * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status 1934 * Register 2. 1935 * @nor: pointer to a 'struct spi_nor'. 1936 * 1937 * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories. 1938 * 1939 * Return: 0 on success, -errno otherwise. 1940 */ 1941 int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) 1942 { 1943 int ret; 1944 1945 if (nor->flags & SNOR_F_NO_READ_CR) 1946 return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1); 1947 1948 ret = spi_nor_read_cr(nor, nor->bouncebuf); 1949 if (ret) 1950 return ret; 1951 1952 if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1) 1953 return 0; 1954 1955 nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1; 1956 1957 return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]); 1958 } 1959 1960 /** 1961 * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2. 1962 * @nor: pointer to a 'struct spi_nor' 1963 * 1964 * Set the Quad Enable (QE) bit in the Status Register 2. 1965 * 1966 * This is one of the procedures to set the QE bit described in the SFDP 1967 * (JESD216 rev B) specification but no manufacturer using this procedure has 1968 * been identified yet, hence the name of the function. 1969 * 1970 * Return: 0 on success, -errno otherwise. 1971 */ 1972 int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) 1973 { 1974 u8 *sr2 = nor->bouncebuf; 1975 int ret; 1976 u8 sr2_written; 1977 1978 /* Check current Quad Enable bit value. */ 1979 ret = spi_nor_read_sr2(nor, sr2); 1980 if (ret) 1981 return ret; 1982 if (*sr2 & SR2_QUAD_EN_BIT7) 1983 return 0; 1984 1985 /* Update the Quad Enable bit. */ 1986 *sr2 |= SR2_QUAD_EN_BIT7; 1987 1988 ret = spi_nor_write_sr2(nor, sr2); 1989 if (ret) 1990 return ret; 1991 1992 sr2_written = *sr2; 1993 1994 /* Read back and check it. */ 1995 ret = spi_nor_read_sr2(nor, sr2); 1996 if (ret) 1997 return ret; 1998 1999 if (*sr2 != sr2_written) { 2000 dev_dbg(nor->dev, "SR2: Read back test failed\n"); 2001 return -EIO; 2002 } 2003 2004 return 0; 2005 } 2006 2007 static const struct spi_nor_manufacturer *manufacturers[] = { 2008 &spi_nor_atmel, 2009 &spi_nor_eon, 2010 &spi_nor_esmt, 2011 &spi_nor_everspin, 2012 &spi_nor_gigadevice, 2013 &spi_nor_intel, 2014 &spi_nor_issi, 2015 &spi_nor_macronix, 2016 &spi_nor_micron, 2017 &spi_nor_st, 2018 &spi_nor_spansion, 2019 &spi_nor_sst, 2020 &spi_nor_winbond, 2021 &spi_nor_xmc, 2022 }; 2023 2024 static const struct flash_info spi_nor_generic_flash = { 2025 .name = "spi-nor-generic", 2026 }; 2027 2028 static const struct flash_info *spi_nor_match_id(struct spi_nor *nor, 2029 const u8 *id) 2030 { 2031 const struct flash_info *part; 2032 unsigned int i, j; 2033 2034 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) { 2035 for (j = 0; j < manufacturers[i]->nparts; j++) { 2036 part = &manufacturers[i]->parts[j]; 2037 if (part->id && 2038 !memcmp(part->id->bytes, id, part->id->len)) { 2039 nor->manufacturer = manufacturers[i]; 2040 return part; 2041 } 2042 } 2043 } 2044 2045 return NULL; 2046 } 2047 2048 static const struct flash_info *spi_nor_detect(struct spi_nor *nor) 2049 { 2050 const struct flash_info *info; 2051 u8 *id = nor->bouncebuf; 2052 int ret; 2053 2054 ret = spi_nor_read_id(nor, 0, 0, id, nor->reg_proto); 2055 if (ret) { 2056 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret); 2057 return ERR_PTR(ret); 2058 } 2059 2060 /* Cache the complete flash ID. */ 2061 nor->id = devm_kmemdup(nor->dev, id, SPI_NOR_MAX_ID_LEN, GFP_KERNEL); 2062 if (!nor->id) 2063 return ERR_PTR(-ENOMEM); 2064 2065 info = spi_nor_match_id(nor, id); 2066 2067 /* Fallback to a generic flash described only by its SFDP data. */ 2068 if (!info) { 2069 ret = spi_nor_check_sfdp_signature(nor); 2070 if (!ret) 2071 info = &spi_nor_generic_flash; 2072 } 2073 2074 if (!info) { 2075 dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n", 2076 SPI_NOR_MAX_ID_LEN, id); 2077 return ERR_PTR(-ENODEV); 2078 } 2079 return info; 2080 } 2081 2082 /* 2083 * On Octal DTR capable flashes, reads cannot start or end at an odd 2084 * address in Octal DTR mode. Extra bytes need to be read at the start 2085 * or end to make sure both the start address and length remain even. 2086 */ 2087 static int spi_nor_octal_dtr_read(struct spi_nor *nor, loff_t from, size_t len, 2088 u_char *buf) 2089 { 2090 u_char *tmp_buf; 2091 size_t tmp_len; 2092 loff_t start, end; 2093 int ret, bytes_read; 2094 2095 if (IS_ALIGNED(from, 2) && IS_ALIGNED(len, 2)) 2096 return spi_nor_read_data(nor, from, len, buf); 2097 else if (IS_ALIGNED(from, 2) && len > PAGE_SIZE) 2098 return spi_nor_read_data(nor, from, round_down(len, PAGE_SIZE), 2099 buf); 2100 2101 tmp_buf = kmalloc(PAGE_SIZE, GFP_KERNEL); 2102 if (!tmp_buf) 2103 return -ENOMEM; 2104 2105 start = round_down(from, 2); 2106 end = round_up(from + len, 2); 2107 2108 /* 2109 * Avoid allocating too much memory. The requested read length might be 2110 * quite large. Allocating a buffer just as large (slightly bigger, in 2111 * fact) would put unnecessary memory pressure on the system. 2112 * 2113 * For example if the read is from 3 to 1M, then this will read from 2 2114 * to 4098. The reads from 4098 to 1M will then not need a temporary 2115 * buffer so they can proceed as normal. 2116 */ 2117 tmp_len = min_t(size_t, end - start, PAGE_SIZE); 2118 2119 ret = spi_nor_read_data(nor, start, tmp_len, tmp_buf); 2120 if (ret == 0) { 2121 ret = -EIO; 2122 goto out; 2123 } 2124 if (ret < 0) 2125 goto out; 2126 2127 /* 2128 * More bytes are read than actually requested, but that number can't be 2129 * reported to the calling function or it will confuse its calculations. 2130 * Calculate how many of the _requested_ bytes were read. 2131 */ 2132 bytes_read = ret; 2133 2134 if (from != start) 2135 ret -= from - start; 2136 2137 /* 2138 * Only account for extra bytes at the end if they were actually read. 2139 * For example, if the total length was truncated because of temporary 2140 * buffer size limit then the adjustment for the extra bytes at the end 2141 * is not needed. 2142 */ 2143 if (start + bytes_read == end) 2144 ret -= end - (from + len); 2145 2146 memcpy(buf, tmp_buf + (from - start), ret); 2147 out: 2148 kfree(tmp_buf); 2149 return ret; 2150 } 2151 2152 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, 2153 size_t *retlen, u_char *buf) 2154 { 2155 struct spi_nor *nor = mtd_to_spi_nor(mtd); 2156 loff_t from_lock = from; 2157 size_t len_lock = len; 2158 ssize_t ret; 2159 2160 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); 2161 2162 ret = spi_nor_prep_and_lock_rd(nor, from_lock, len_lock); 2163 if (ret) 2164 return ret; 2165 2166 while (len) { 2167 loff_t addr = from; 2168 2169 if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) 2170 ret = spi_nor_octal_dtr_read(nor, addr, len, buf); 2171 else 2172 ret = spi_nor_read_data(nor, addr, len, buf); 2173 2174 if (ret == 0) { 2175 /* We shouldn't see 0-length reads */ 2176 ret = -EIO; 2177 goto read_err; 2178 } 2179 if (ret < 0) 2180 goto read_err; 2181 2182 WARN_ON(ret > len); 2183 *retlen += ret; 2184 buf += ret; 2185 from += ret; 2186 len -= ret; 2187 } 2188 ret = 0; 2189 2190 read_err: 2191 spi_nor_unlock_and_unprep_rd(nor, from_lock, len_lock); 2192 2193 return ret; 2194 } 2195 2196 /* 2197 * On Octal DTR capable flashes, writes cannot start or end at an odd address 2198 * in Octal DTR mode. Extra 0xff bytes need to be appended or prepended to 2199 * make sure the start address and end address are even. 0xff is used because 2200 * on NOR flashes a program operation can only flip bits from 1 to 0, not the 2201 * other way round. 0 to 1 flip needs to happen via erases. 2202 */ 2203 static int spi_nor_octal_dtr_write(struct spi_nor *nor, loff_t to, size_t len, 2204 const u8 *buf) 2205 { 2206 u8 *tmp_buf; 2207 size_t bytes_written; 2208 loff_t start, end; 2209 int ret; 2210 2211 if (IS_ALIGNED(to, 2) && IS_ALIGNED(len, 2)) 2212 return spi_nor_write_data(nor, to, len, buf); 2213 2214 tmp_buf = kmalloc(nor->params->page_size, GFP_KERNEL); 2215 if (!tmp_buf) 2216 return -ENOMEM; 2217 2218 memset(tmp_buf, 0xff, nor->params->page_size); 2219 2220 start = round_down(to, 2); 2221 end = round_up(to + len, 2); 2222 2223 memcpy(tmp_buf + (to - start), buf, len); 2224 2225 ret = spi_nor_write_data(nor, start, end - start, tmp_buf); 2226 if (ret == 0) { 2227 ret = -EIO; 2228 goto out; 2229 } 2230 if (ret < 0) 2231 goto out; 2232 2233 /* 2234 * More bytes are written than actually requested, but that number can't 2235 * be reported to the calling function or it will confuse its 2236 * calculations. Calculate how many of the _requested_ bytes were 2237 * written. 2238 */ 2239 bytes_written = ret; 2240 2241 if (to != start) 2242 ret -= to - start; 2243 2244 /* 2245 * Only account for extra bytes at the end if they were actually 2246 * written. For example, if for some reason the controller could only 2247 * complete a partial write then the adjustment for the extra bytes at 2248 * the end is not needed. 2249 */ 2250 if (start + bytes_written == end) 2251 ret -= end - (to + len); 2252 2253 out: 2254 kfree(tmp_buf); 2255 return ret; 2256 } 2257 2258 /* 2259 * Write an address range to the nor chip. Data must be written in 2260 * FLASH_PAGESIZE chunks. The address range may be any size provided 2261 * it is within the physical boundaries. 2262 */ 2263 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, 2264 size_t *retlen, const u_char *buf) 2265 { 2266 struct spi_nor *nor = mtd_to_spi_nor(mtd); 2267 size_t i; 2268 ssize_t ret; 2269 u32 page_size = nor->params->page_size; 2270 2271 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 2272 2273 ret = spi_nor_prep_and_lock_pe(nor, to, len); 2274 if (ret) 2275 return ret; 2276 2277 for (i = 0; i < len; ) { 2278 ssize_t written; 2279 loff_t addr = to + i; 2280 size_t page_offset = addr & (page_size - 1); 2281 /* the size of data remaining on the first page */ 2282 size_t page_remain = min_t(size_t, page_size - page_offset, len - i); 2283 2284 ret = spi_nor_lock_device(nor); 2285 if (ret) 2286 goto write_err; 2287 2288 ret = spi_nor_write_enable(nor); 2289 if (ret) { 2290 spi_nor_unlock_device(nor); 2291 goto write_err; 2292 } 2293 2294 if (nor->write_proto == SNOR_PROTO_8_8_8_DTR) 2295 ret = spi_nor_octal_dtr_write(nor, addr, page_remain, 2296 buf + i); 2297 else 2298 ret = spi_nor_write_data(nor, addr, page_remain, 2299 buf + i); 2300 spi_nor_unlock_device(nor); 2301 if (ret < 0) 2302 goto write_err; 2303 written = ret; 2304 2305 ret = spi_nor_wait_till_ready(nor); 2306 if (ret) 2307 goto write_err; 2308 *retlen += written; 2309 i += written; 2310 } 2311 2312 write_err: 2313 spi_nor_unlock_and_unprep_pe(nor, to, len); 2314 2315 return ret; 2316 } 2317 2318 static int spi_nor_check(struct spi_nor *nor) 2319 { 2320 if (!nor->dev || 2321 (!nor->spimem && !nor->controller_ops) || 2322 (!nor->spimem && nor->controller_ops && 2323 (!nor->controller_ops->read || 2324 !nor->controller_ops->write || 2325 !nor->controller_ops->read_reg || 2326 !nor->controller_ops->write_reg))) { 2327 pr_err("spi-nor: please fill all the necessary fields!\n"); 2328 return -EINVAL; 2329 } 2330 2331 if (nor->spimem && nor->controller_ops) { 2332 dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n"); 2333 return -EINVAL; 2334 } 2335 2336 return 0; 2337 } 2338 2339 void 2340 spi_nor_set_read_settings(struct spi_nor_read_command *read, 2341 u8 num_mode_clocks, 2342 u8 num_wait_states, 2343 u8 opcode, 2344 enum spi_nor_protocol proto) 2345 { 2346 read->num_mode_clocks = num_mode_clocks; 2347 read->num_wait_states = num_wait_states; 2348 read->opcode = opcode; 2349 read->proto = proto; 2350 } 2351 2352 void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode, 2353 enum spi_nor_protocol proto) 2354 { 2355 pp->opcode = opcode; 2356 pp->proto = proto; 2357 } 2358 2359 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) 2360 { 2361 size_t i; 2362 2363 for (i = 0; i < size; i++) 2364 if (table[i][0] == (int)hwcaps) 2365 return table[i][1]; 2366 2367 return -EINVAL; 2368 } 2369 2370 int spi_nor_hwcaps_read2cmd(u32 hwcaps) 2371 { 2372 static const int hwcaps_read2cmd[][2] = { 2373 { SNOR_HWCAPS_READ, SNOR_CMD_READ }, 2374 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST }, 2375 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR }, 2376 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 }, 2377 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 }, 2378 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 }, 2379 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR }, 2380 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 }, 2381 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 }, 2382 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 }, 2383 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR }, 2384 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 }, 2385 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, 2386 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, 2387 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, 2388 { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8_8_8_DTR }, 2389 }; 2390 2391 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, 2392 ARRAY_SIZE(hwcaps_read2cmd)); 2393 } 2394 2395 int spi_nor_hwcaps_pp2cmd(u32 hwcaps) 2396 { 2397 static const int hwcaps_pp2cmd[][2] = { 2398 { SNOR_HWCAPS_PP, SNOR_CMD_PP }, 2399 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 }, 2400 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 }, 2401 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 }, 2402 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, 2403 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, 2404 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, 2405 { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8_8_8_DTR }, 2406 }; 2407 2408 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, 2409 ARRAY_SIZE(hwcaps_pp2cmd)); 2410 } 2411 2412 /** 2413 * spi_nor_spimem_check_read_pp_op - check if a read or a page program operation is 2414 * supported by controller 2415 *@nor: pointer to a 'struct spi_nor' 2416 *@op: pointer to op template to be checked 2417 * 2418 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise. 2419 */ 2420 static int spi_nor_spimem_check_read_pp_op(struct spi_nor *nor, 2421 struct spi_mem_op *op) 2422 { 2423 /* 2424 * First test with 4 address bytes. The opcode itself might 2425 * be a 3B addressing opcode but we don't care, because 2426 * SPI controller implementation should not check the opcode, 2427 * but just the sequence. 2428 */ 2429 op->addr.nbytes = 4; 2430 if (!spi_mem_supports_op(nor->spimem, op)) { 2431 if (nor->params->size > SZ_16M) 2432 return -EOPNOTSUPP; 2433 2434 /* If flash size <= 16MB, 3 address bytes are sufficient */ 2435 op->addr.nbytes = 3; 2436 if (!spi_mem_supports_op(nor->spimem, op)) 2437 return -EOPNOTSUPP; 2438 } 2439 2440 return 0; 2441 } 2442 2443 /** 2444 * spi_nor_spimem_check_readop - check if the read op is supported 2445 * by controller 2446 *@nor: pointer to a 'struct spi_nor' 2447 *@read: pointer to op template to be checked 2448 * 2449 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise. 2450 */ 2451 static int spi_nor_spimem_check_readop(struct spi_nor *nor, 2452 const struct spi_nor_read_command *read) 2453 { 2454 struct spi_mem_op op = SPI_NOR_READ_OP(read->opcode); 2455 2456 spi_nor_spimem_setup_op(nor, &op, read->proto); 2457 2458 /* convert the dummy cycles to the number of bytes */ 2459 op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) * 2460 op.dummy.buswidth / 8; 2461 if (spi_nor_protocol_is_dtr(read->proto)) 2462 op.dummy.nbytes *= 2; 2463 2464 return spi_nor_spimem_check_read_pp_op(nor, &op); 2465 } 2466 2467 /** 2468 * spi_nor_spimem_check_pp - check if the page program op is supported 2469 * by controller 2470 *@nor: pointer to a 'struct spi_nor' 2471 *@pp: pointer to op template to be checked 2472 * 2473 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise. 2474 */ 2475 static int spi_nor_spimem_check_pp(struct spi_nor *nor, 2476 const struct spi_nor_pp_command *pp) 2477 { 2478 struct spi_mem_op op = SPI_NOR_PP_OP(pp->opcode); 2479 2480 spi_nor_spimem_setup_op(nor, &op, pp->proto); 2481 2482 return spi_nor_spimem_check_read_pp_op(nor, &op); 2483 } 2484 2485 /** 2486 * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol 2487 * based on SPI controller capabilities 2488 * @nor: pointer to a 'struct spi_nor' 2489 * @hwcaps: pointer to resulting capabilities after adjusting 2490 * according to controller and flash's capability 2491 */ 2492 static void 2493 spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps) 2494 { 2495 struct spi_nor_flash_parameter *params = nor->params; 2496 unsigned int cap; 2497 2498 /* X-X-X modes are not supported yet, mask them all. */ 2499 *hwcaps &= ~SNOR_HWCAPS_X_X_X; 2500 2501 /* 2502 * If the reset line is broken, we do not want to enter a stateful 2503 * mode. 2504 */ 2505 if (nor->flags & SNOR_F_BROKEN_RESET) 2506 *hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR); 2507 2508 for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) { 2509 int rdidx, ppidx; 2510 2511 if (!(*hwcaps & BIT(cap))) 2512 continue; 2513 2514 rdidx = spi_nor_hwcaps_read2cmd(BIT(cap)); 2515 if (rdidx >= 0 && 2516 spi_nor_spimem_check_readop(nor, ¶ms->reads[rdidx])) 2517 *hwcaps &= ~BIT(cap); 2518 2519 ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap)); 2520 if (ppidx < 0) 2521 continue; 2522 2523 if (spi_nor_spimem_check_pp(nor, 2524 ¶ms->page_programs[ppidx])) 2525 *hwcaps &= ~BIT(cap); 2526 } 2527 2528 /* Some SPI controllers might not support CR read opcode. */ 2529 if (!(nor->flags & SNOR_F_NO_READ_CR)) { 2530 struct spi_mem_op op = SPI_NOR_RDCR_OP(nor->bouncebuf); 2531 2532 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 2533 2534 if (!spi_mem_supports_op(nor->spimem, &op)) 2535 nor->flags |= SNOR_F_NO_READ_CR; 2536 } 2537 } 2538 2539 /** 2540 * spi_nor_set_erase_type() - set a SPI NOR erase type 2541 * @erase: pointer to a structure that describes a SPI NOR erase type 2542 * @size: the size of the sector/block erased by the erase type 2543 * @opcode: the SPI command op code to erase the sector/block 2544 */ 2545 void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size, 2546 u8 opcode) 2547 { 2548 erase->size = size; 2549 erase->opcode = opcode; 2550 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */ 2551 erase->size_shift = ffs(erase->size) - 1; 2552 erase->size_mask = (1 << erase->size_shift) - 1; 2553 } 2554 2555 /** 2556 * spi_nor_mask_erase_type() - mask out a SPI NOR erase type 2557 * @erase: pointer to a structure that describes a SPI NOR erase type 2558 */ 2559 void spi_nor_mask_erase_type(struct spi_nor_erase_type *erase) 2560 { 2561 erase->size = 0; 2562 } 2563 2564 /** 2565 * spi_nor_init_uniform_erase_map() - Initialize uniform erase map 2566 * @map: the erase map of the SPI NOR 2567 * @erase_mask: bitmask encoding erase types that can erase the entire 2568 * flash memory 2569 * @flash_size: the spi nor flash memory size 2570 */ 2571 void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map, 2572 u8 erase_mask, u64 flash_size) 2573 { 2574 map->uniform_region.offset = 0; 2575 map->uniform_region.size = flash_size; 2576 map->uniform_region.erase_mask = erase_mask; 2577 map->regions = &map->uniform_region; 2578 map->n_regions = 1; 2579 } 2580 2581 int spi_nor_post_bfpt_fixups(struct spi_nor *nor, 2582 const struct sfdp_parameter_header *bfpt_header, 2583 const struct sfdp_bfpt *bfpt) 2584 { 2585 int ret; 2586 2587 if (nor->manufacturer && nor->manufacturer->fixups && 2588 nor->manufacturer->fixups->post_bfpt) { 2589 ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header, 2590 bfpt); 2591 if (ret) 2592 return ret; 2593 } 2594 2595 if (nor->info->fixups && nor->info->fixups->post_bfpt) 2596 return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt); 2597 2598 return 0; 2599 } 2600 2601 static int spi_nor_select_read(struct spi_nor *nor, 2602 u32 shared_hwcaps) 2603 { 2604 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1; 2605 const struct spi_nor_read_command *read; 2606 2607 if (best_match < 0) 2608 return -EINVAL; 2609 2610 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match)); 2611 if (cmd < 0) 2612 return -EINVAL; 2613 2614 read = &nor->params->reads[cmd]; 2615 nor->read_opcode = read->opcode; 2616 nor->read_proto = read->proto; 2617 2618 /* 2619 * In the SPI NOR framework, we don't need to make the difference 2620 * between mode clock cycles and wait state clock cycles. 2621 * Indeed, the value of the mode clock cycles is used by a QSPI 2622 * flash memory to know whether it should enter or leave its 0-4-4 2623 * (Continuous Read / XIP) mode. 2624 * eXecution In Place is out of the scope of the mtd sub-system. 2625 * Hence we choose to merge both mode and wait state clock cycles 2626 * into the so called dummy clock cycles. 2627 */ 2628 nor->read_dummy = read->num_mode_clocks + read->num_wait_states; 2629 return 0; 2630 } 2631 2632 static int spi_nor_select_pp(struct spi_nor *nor, 2633 u32 shared_hwcaps) 2634 { 2635 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1; 2636 const struct spi_nor_pp_command *pp; 2637 2638 if (best_match < 0) 2639 return -EINVAL; 2640 2641 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match)); 2642 if (cmd < 0) 2643 return -EINVAL; 2644 2645 pp = &nor->params->page_programs[cmd]; 2646 nor->program_opcode = pp->opcode; 2647 nor->write_proto = pp->proto; 2648 return 0; 2649 } 2650 2651 /** 2652 * spi_nor_select_uniform_erase() - select optimum uniform erase type 2653 * @map: the erase map of the SPI NOR 2654 * 2655 * Once the optimum uniform sector erase command is found, disable all the 2656 * other. 2657 * 2658 * Return: pointer to erase type on success, NULL otherwise. 2659 */ 2660 static const struct spi_nor_erase_type * 2661 spi_nor_select_uniform_erase(struct spi_nor_erase_map *map) 2662 { 2663 const struct spi_nor_erase_type *tested_erase, *erase = NULL; 2664 int i; 2665 u8 uniform_erase_type = map->uniform_region.erase_mask; 2666 2667 /* 2668 * Search for the biggest erase size, except for when compiled 2669 * to use 4k erases. 2670 */ 2671 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 2672 if (!(uniform_erase_type & BIT(i))) 2673 continue; 2674 2675 tested_erase = &map->erase_type[i]; 2676 2677 /* Skip masked erase types. */ 2678 if (!tested_erase->size) 2679 continue; 2680 2681 /* 2682 * If the current erase size is the 4k one, stop here, 2683 * we have found the right uniform Sector Erase command. 2684 */ 2685 if (IS_ENABLED(CONFIG_MTD_SPI_NOR_USE_4K_SECTORS) && 2686 tested_erase->size == SZ_4K) { 2687 erase = tested_erase; 2688 break; 2689 } 2690 2691 /* 2692 * Otherwise, the current erase size is still a valid candidate. 2693 * Select the biggest valid candidate. 2694 */ 2695 if (!erase && tested_erase->size) 2696 erase = tested_erase; 2697 /* keep iterating to find the wanted_size */ 2698 } 2699 2700 if (!erase) 2701 return NULL; 2702 2703 /* Disable all other Sector Erase commands. */ 2704 map->uniform_region.erase_mask = BIT(erase - map->erase_type); 2705 return erase; 2706 } 2707 2708 static int spi_nor_select_erase(struct spi_nor *nor) 2709 { 2710 struct spi_nor_erase_map *map = &nor->params->erase_map; 2711 const struct spi_nor_erase_type *erase = NULL; 2712 struct mtd_info *mtd = &nor->mtd; 2713 int i; 2714 2715 /* 2716 * The previous implementation handling Sector Erase commands assumed 2717 * that the SPI flash memory has an uniform layout then used only one 2718 * of the supported erase sizes for all Sector Erase commands. 2719 * So to be backward compatible, the new implementation also tries to 2720 * manage the SPI flash memory as uniform with a single erase sector 2721 * size, when possible. 2722 */ 2723 if (spi_nor_has_uniform_erase(nor)) { 2724 erase = spi_nor_select_uniform_erase(map); 2725 if (!erase) 2726 return -EINVAL; 2727 nor->erase_opcode = erase->opcode; 2728 mtd->erasesize = erase->size; 2729 return 0; 2730 } 2731 2732 /* 2733 * For non-uniform SPI flash memory, set mtd->erasesize to the 2734 * maximum erase sector size. No need to set nor->erase_opcode. 2735 */ 2736 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 2737 if (map->erase_type[i].size) { 2738 erase = &map->erase_type[i]; 2739 break; 2740 } 2741 } 2742 2743 if (!erase) 2744 return -EINVAL; 2745 2746 mtd->erasesize = erase->size; 2747 return 0; 2748 } 2749 2750 static int spi_nor_set_addr_nbytes(struct spi_nor *nor) 2751 { 2752 if (nor->params->addr_nbytes) { 2753 nor->addr_nbytes = nor->params->addr_nbytes; 2754 } else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) { 2755 /* 2756 * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So 2757 * in this protocol an odd addr_nbytes cannot be used because 2758 * then the address phase would only span a cycle and a half. 2759 * Half a cycle would be left over. We would then have to start 2760 * the dummy phase in the middle of a cycle and so too the data 2761 * phase, and we will end the transaction with half a cycle left 2762 * over. 2763 * 2764 * Force all 8D-8D-8D flashes to use an addr_nbytes of 4 to 2765 * avoid this situation. 2766 */ 2767 nor->addr_nbytes = 4; 2768 } else if (nor->info->addr_nbytes) { 2769 nor->addr_nbytes = nor->info->addr_nbytes; 2770 } else { 2771 nor->addr_nbytes = 3; 2772 } 2773 2774 if (nor->addr_nbytes == 3 && nor->params->size > 0x1000000) { 2775 /* enable 4-byte addressing if the device exceeds 16MiB */ 2776 nor->addr_nbytes = 4; 2777 } 2778 2779 if (nor->addr_nbytes > SPI_NOR_MAX_ADDR_NBYTES) { 2780 dev_dbg(nor->dev, "The number of address bytes is too large: %u\n", 2781 nor->addr_nbytes); 2782 return -EINVAL; 2783 } 2784 2785 /* Set 4byte opcodes when possible. */ 2786 if (nor->addr_nbytes == 4 && nor->flags & SNOR_F_4B_OPCODES && 2787 !(nor->flags & SNOR_F_HAS_4BAIT)) 2788 spi_nor_set_4byte_opcodes(nor); 2789 2790 return 0; 2791 } 2792 2793 static int spi_nor_setup(struct spi_nor *nor, 2794 const struct spi_nor_hwcaps *hwcaps) 2795 { 2796 struct spi_nor_flash_parameter *params = nor->params; 2797 u32 ignored_mask, shared_mask; 2798 int err; 2799 2800 /* 2801 * Keep only the hardware capabilities supported by both the SPI 2802 * controller and the SPI flash memory. 2803 */ 2804 shared_mask = hwcaps->mask & params->hwcaps.mask; 2805 2806 if (nor->spimem) { 2807 /* 2808 * When called from spi_nor_probe(), all caps are set and we 2809 * need to discard some of them based on what the SPI 2810 * controller actually supports (using spi_mem_supports_op()). 2811 */ 2812 spi_nor_spimem_adjust_hwcaps(nor, &shared_mask); 2813 } else { 2814 /* 2815 * SPI n-n-n protocols are not supported when the SPI 2816 * controller directly implements the spi_nor interface. 2817 * Yet another reason to switch to spi-mem. 2818 */ 2819 ignored_mask = SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR; 2820 if (shared_mask & ignored_mask) { 2821 dev_dbg(nor->dev, 2822 "SPI n-n-n protocols are not supported.\n"); 2823 shared_mask &= ~ignored_mask; 2824 } 2825 } 2826 2827 /* Select the (Fast) Read command. */ 2828 err = spi_nor_select_read(nor, shared_mask); 2829 if (err) { 2830 dev_dbg(nor->dev, 2831 "can't select read settings supported by both the SPI controller and memory.\n"); 2832 return err; 2833 } 2834 2835 /* Select the Page Program command. */ 2836 err = spi_nor_select_pp(nor, shared_mask); 2837 if (err) { 2838 dev_dbg(nor->dev, 2839 "can't select write settings supported by both the SPI controller and memory.\n"); 2840 return err; 2841 } 2842 2843 /* Select the Sector Erase command. */ 2844 err = spi_nor_select_erase(nor); 2845 if (err) { 2846 dev_dbg(nor->dev, 2847 "can't select erase settings supported by both the SPI controller and memory.\n"); 2848 return err; 2849 } 2850 2851 return spi_nor_set_addr_nbytes(nor); 2852 } 2853 2854 /** 2855 * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and 2856 * settings based on MFR register and ->default_init() hook. 2857 * @nor: pointer to a 'struct spi_nor'. 2858 */ 2859 static void spi_nor_manufacturer_init_params(struct spi_nor *nor) 2860 { 2861 if (nor->manufacturer && nor->manufacturer->fixups && 2862 nor->manufacturer->fixups->default_init) 2863 nor->manufacturer->fixups->default_init(nor); 2864 2865 if (nor->info->fixups && nor->info->fixups->default_init) 2866 nor->info->fixups->default_init(nor); 2867 } 2868 2869 /** 2870 * spi_nor_no_sfdp_init_params() - Initialize the flash's parameters and 2871 * settings based on nor->info->sfdp_flags. This method should be called only by 2872 * flashes that do not define SFDP tables. If the flash supports SFDP but the 2873 * information is wrong and the settings from this function can not be retrieved 2874 * by parsing SFDP, one should instead use the fixup hooks and update the wrong 2875 * bits. 2876 * @nor: pointer to a 'struct spi_nor'. 2877 */ 2878 static void spi_nor_no_sfdp_init_params(struct spi_nor *nor) 2879 { 2880 struct spi_nor_flash_parameter *params = nor->params; 2881 struct spi_nor_erase_map *map = ¶ms->erase_map; 2882 const struct flash_info *info = nor->info; 2883 const u8 no_sfdp_flags = info->no_sfdp_flags; 2884 u8 i, erase_mask; 2885 2886 if (no_sfdp_flags & SPI_NOR_DUAL_READ) { 2887 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 2888 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], 2889 0, 8, SPINOR_OP_READ_1_1_2, 2890 SNOR_PROTO_1_1_2); 2891 } 2892 2893 if (no_sfdp_flags & SPI_NOR_QUAD_READ) { 2894 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 2895 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], 2896 0, 8, SPINOR_OP_READ_1_1_4, 2897 SNOR_PROTO_1_1_4); 2898 } 2899 2900 if (no_sfdp_flags & SPI_NOR_OCTAL_READ) { 2901 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8; 2902 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8], 2903 0, 8, SPINOR_OP_READ_1_1_8, 2904 SNOR_PROTO_1_1_8); 2905 } 2906 2907 if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_READ) { 2908 params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; 2909 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR], 2910 0, 20, SPINOR_OP_READ_FAST, 2911 SNOR_PROTO_8_8_8_DTR); 2912 } 2913 2914 if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_PP) { 2915 params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR; 2916 /* 2917 * Since xSPI Page Program opcode is backward compatible with 2918 * Legacy SPI, use Legacy SPI opcode there as well. 2919 */ 2920 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], 2921 SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR); 2922 } 2923 2924 /* 2925 * Sector Erase settings. Sort Erase Types in ascending order, with the 2926 * smallest erase size starting at BIT(0). 2927 */ 2928 erase_mask = 0; 2929 i = 0; 2930 if (no_sfdp_flags & SECT_4K) { 2931 erase_mask |= BIT(i); 2932 spi_nor_set_erase_type(&map->erase_type[i], 4096u, 2933 SPINOR_OP_BE_4K); 2934 i++; 2935 } 2936 erase_mask |= BIT(i); 2937 spi_nor_set_erase_type(&map->erase_type[i], 2938 info->sector_size ?: SPI_NOR_DEFAULT_SECTOR_SIZE, 2939 SPINOR_OP_SE); 2940 spi_nor_init_uniform_erase_map(map, erase_mask, params->size); 2941 } 2942 2943 /** 2944 * spi_nor_init_flags() - Initialize NOR flags for settings that are not defined 2945 * in the JESD216 SFDP standard, thus can not be retrieved when parsing SFDP. 2946 * @nor: pointer to a 'struct spi_nor' 2947 */ 2948 static void spi_nor_init_flags(struct spi_nor *nor) 2949 { 2950 struct device_node *np = spi_nor_get_flash_node(nor); 2951 const u16 flags = nor->info->flags; 2952 2953 if (of_property_read_bool(np, "broken-flash-reset")) 2954 nor->flags |= SNOR_F_BROKEN_RESET; 2955 2956 if (of_property_read_bool(np, "no-wp")) 2957 nor->flags |= SNOR_F_NO_WP; 2958 2959 if (flags & SPI_NOR_SWP_IS_VOLATILE) 2960 nor->flags |= SNOR_F_SWP_IS_VOLATILE; 2961 2962 if (flags & SPI_NOR_HAS_LOCK) 2963 nor->flags |= SNOR_F_HAS_LOCK; 2964 2965 if (flags & SPI_NOR_HAS_TB) { 2966 nor->flags |= SNOR_F_HAS_SR_TB; 2967 if (flags & SPI_NOR_TB_SR_BIT6) 2968 nor->flags |= SNOR_F_HAS_SR_TB_BIT6; 2969 } 2970 2971 if (flags & SPI_NOR_4BIT_BP) { 2972 nor->flags |= SNOR_F_HAS_4BIT_BP; 2973 if (flags & SPI_NOR_BP3_SR_BIT6) 2974 nor->flags |= SNOR_F_HAS_SR_BP3_BIT6; 2975 } 2976 2977 if (flags & SPI_NOR_HAS_CMP) 2978 nor->flags |= SNOR_F_HAS_SR2_CMP_BIT6; 2979 2980 if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 && 2981 !nor->controller_ops) 2982 nor->flags |= SNOR_F_RWW; 2983 } 2984 2985 /** 2986 * spi_nor_init_fixup_flags() - Initialize NOR flags for settings that can not 2987 * be discovered by SFDP for this particular flash because the SFDP table that 2988 * indicates this support is not defined in the flash. In case the table for 2989 * this support is defined but has wrong values, one should instead use a 2990 * post_sfdp() hook to set the SNOR_F equivalent flag. 2991 * @nor: pointer to a 'struct spi_nor' 2992 */ 2993 static void spi_nor_init_fixup_flags(struct spi_nor *nor) 2994 { 2995 const u8 fixup_flags = nor->info->fixup_flags; 2996 2997 if (fixup_flags & SPI_NOR_4B_OPCODES) 2998 nor->flags |= SNOR_F_4B_OPCODES; 2999 3000 if (fixup_flags & SPI_NOR_IO_MODE_EN_VOLATILE) 3001 nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; 3002 } 3003 3004 /** 3005 * spi_nor_late_init_params() - Late initialization of default flash parameters. 3006 * @nor: pointer to a 'struct spi_nor' 3007 * 3008 * Used to initialize flash parameters that are not declared in the JESD216 3009 * SFDP standard, or where SFDP tables are not defined at all. 3010 * Will replace the spi_nor_manufacturer_init_params() method. 3011 */ 3012 static int spi_nor_late_init_params(struct spi_nor *nor) 3013 { 3014 struct spi_nor_flash_parameter *params = nor->params; 3015 int ret; 3016 3017 if (nor->manufacturer && nor->manufacturer->fixups && 3018 nor->manufacturer->fixups->late_init) { 3019 ret = nor->manufacturer->fixups->late_init(nor); 3020 if (ret) 3021 return ret; 3022 } 3023 3024 /* Needed by some flashes late_init hooks. */ 3025 spi_nor_init_flags(nor); 3026 3027 if (nor->info->fixups && nor->info->fixups->late_init) { 3028 ret = nor->info->fixups->late_init(nor); 3029 if (ret) 3030 return ret; 3031 } 3032 3033 if (!nor->params->die_erase_opcode) 3034 nor->params->die_erase_opcode = SPINOR_OP_CHIP_ERASE; 3035 3036 /* Default method kept for backward compatibility. */ 3037 if (!params->set_4byte_addr_mode) 3038 params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr; 3039 3040 spi_nor_init_fixup_flags(nor); 3041 3042 /* 3043 * NOR protection support. When locking_ops are not provided, we pick 3044 * the default ones. 3045 */ 3046 if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops) 3047 spi_nor_init_default_locking_ops(nor); 3048 3049 if (params->n_banks > 1) 3050 params->bank_size = div_u64(params->size, params->n_banks); 3051 3052 return 0; 3053 } 3054 3055 /** 3056 * spi_nor_sfdp_init_params_deprecated() - Deprecated way of initializing flash 3057 * parameters and settings based on JESD216 SFDP standard. 3058 * @nor: pointer to a 'struct spi_nor'. 3059 * 3060 * The method has a roll-back mechanism: in case the SFDP parsing fails, the 3061 * legacy flash parameters and settings will be restored. 3062 */ 3063 static void spi_nor_sfdp_init_params_deprecated(struct spi_nor *nor) 3064 { 3065 struct spi_nor_flash_parameter sfdp_params; 3066 3067 memcpy(&sfdp_params, nor->params, sizeof(sfdp_params)); 3068 3069 if (spi_nor_parse_sfdp(nor)) { 3070 memcpy(nor->params, &sfdp_params, sizeof(*nor->params)); 3071 nor->flags &= ~SNOR_F_4B_OPCODES; 3072 } 3073 } 3074 3075 /** 3076 * spi_nor_init_params_deprecated() - Deprecated way of initializing flash 3077 * parameters and settings. 3078 * @nor: pointer to a 'struct spi_nor'. 3079 * 3080 * The method assumes that flash doesn't support SFDP so it initializes flash 3081 * parameters in spi_nor_no_sfdp_init_params() which later on can be overwritten 3082 * when parsing SFDP, if supported. 3083 */ 3084 static void spi_nor_init_params_deprecated(struct spi_nor *nor) 3085 { 3086 spi_nor_no_sfdp_init_params(nor); 3087 3088 spi_nor_manufacturer_init_params(nor); 3089 3090 if (nor->info->no_sfdp_flags & (SPI_NOR_DUAL_READ | 3091 SPI_NOR_QUAD_READ | 3092 SPI_NOR_OCTAL_READ | 3093 SPI_NOR_OCTAL_DTR_READ)) 3094 spi_nor_sfdp_init_params_deprecated(nor); 3095 } 3096 3097 /** 3098 * spi_nor_init_default_params() - Default initialization of flash parameters 3099 * and settings. Done for all flashes, regardless is they define SFDP tables 3100 * or not. 3101 * @nor: pointer to a 'struct spi_nor'. 3102 */ 3103 static void spi_nor_init_default_params(struct spi_nor *nor) 3104 { 3105 struct spi_nor_flash_parameter *params = nor->params; 3106 const struct flash_info *info = nor->info; 3107 struct device_node *np = spi_nor_get_flash_node(nor); 3108 3109 params->quad_enable = spi_nor_sr2_bit1_quad_enable; 3110 params->otp.org = info->otp; 3111 3112 /* Default to 16-bit Write Status (01h) Command */ 3113 nor->flags |= SNOR_F_HAS_16BIT_SR; 3114 3115 /* Set SPI NOR sizes. */ 3116 params->writesize = 1; 3117 params->size = info->size; 3118 params->bank_size = params->size; 3119 params->page_size = info->page_size ?: SPI_NOR_DEFAULT_PAGE_SIZE; 3120 params->n_banks = info->n_banks ?: SPI_NOR_DEFAULT_N_BANKS; 3121 3122 /* Default to Fast Read for non-DT and enable it if requested by DT. */ 3123 if (!np || of_property_read_bool(np, "m25p,fast-read")) 3124 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; 3125 3126 /* (Fast) Read settings. */ 3127 params->hwcaps.mask |= SNOR_HWCAPS_READ; 3128 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], 3129 0, 0, SPINOR_OP_READ, 3130 SNOR_PROTO_1_1_1); 3131 3132 if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST) 3133 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], 3134 0, 8, SPINOR_OP_READ_FAST, 3135 SNOR_PROTO_1_1_1); 3136 /* Page Program settings. */ 3137 params->hwcaps.mask |= SNOR_HWCAPS_PP; 3138 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], 3139 SPINOR_OP_PP, SNOR_PROTO_1_1_1); 3140 3141 if (info->flags & SPI_NOR_QUAD_PP) { 3142 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; 3143 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], 3144 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4); 3145 } 3146 } 3147 3148 /** 3149 * spi_nor_init_params() - Initialize the flash's parameters and settings. 3150 * @nor: pointer to a 'struct spi_nor'. 3151 * 3152 * The flash parameters and settings are initialized based on a sequence of 3153 * calls that are ordered by priority: 3154 * 3155 * 1/ Default flash parameters initialization. The initializations are done 3156 * based on nor->info data: 3157 * spi_nor_info_init_params() 3158 * 3159 * which can be overwritten by: 3160 * 2/ Manufacturer flash parameters initialization. The initializations are 3161 * done based on MFR register, or when the decisions can not be done solely 3162 * based on MFR, by using specific flash_info tweeks, ->default_init(): 3163 * spi_nor_manufacturer_init_params() 3164 * 3165 * which can be overwritten by: 3166 * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and 3167 * should be more accurate that the above. 3168 * spi_nor_parse_sfdp() or spi_nor_no_sfdp_init_params() 3169 * 3170 * Please note that there is a ->post_bfpt() fixup hook that can overwrite 3171 * the flash parameters and settings immediately after parsing the Basic 3172 * Flash Parameter Table. 3173 * spi_nor_post_sfdp_fixups() is called after the SFDP tables are parsed. 3174 * It is used to tweak various flash parameters when information provided 3175 * by the SFDP tables are wrong. 3176 * 3177 * which can be overwritten by: 3178 * 4/ Late flash parameters initialization, used to initialize flash 3179 * parameters that are not declared in the JESD216 SFDP standard, or where SFDP 3180 * tables are not defined at all. 3181 * spi_nor_late_init_params() 3182 * 3183 * Return: 0 on success, -errno otherwise. 3184 */ 3185 static int spi_nor_init_params(struct spi_nor *nor) 3186 { 3187 int ret; 3188 3189 nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL); 3190 if (!nor->params) 3191 return -ENOMEM; 3192 3193 spi_nor_init_default_params(nor); 3194 3195 if (spi_nor_needs_sfdp(nor)) { 3196 ret = spi_nor_parse_sfdp(nor); 3197 if (ret) { 3198 dev_err(nor->dev, "BFPT parsing failed. Please consider using SPI_NOR_SKIP_SFDP when declaring the flash\n"); 3199 return ret; 3200 } 3201 } else if (nor->info->no_sfdp_flags & SPI_NOR_SKIP_SFDP) { 3202 spi_nor_no_sfdp_init_params(nor); 3203 } else { 3204 spi_nor_init_params_deprecated(nor); 3205 } 3206 3207 ret = spi_nor_late_init_params(nor); 3208 if (ret) 3209 return ret; 3210 3211 if (WARN_ON(!is_power_of_2(nor->params->page_size))) 3212 return -EINVAL; 3213 3214 return 0; 3215 } 3216 3217 /** spi_nor_set_octal_dtr() - enable or disable Octal DTR I/O. 3218 * @nor: pointer to a 'struct spi_nor' 3219 * @enable: whether to enable or disable Octal DTR 3220 * 3221 * Return: 0 on success, -errno otherwise. 3222 */ 3223 static int spi_nor_set_octal_dtr(struct spi_nor *nor, bool enable) 3224 { 3225 int ret; 3226 3227 if (!nor->params->set_octal_dtr) 3228 return 0; 3229 3230 if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR && 3231 nor->write_proto == SNOR_PROTO_8_8_8_DTR)) 3232 return 0; 3233 3234 if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE)) 3235 return 0; 3236 3237 ret = nor->params->set_octal_dtr(nor, enable); 3238 if (ret) 3239 return ret; 3240 3241 if (enable) 3242 nor->reg_proto = SNOR_PROTO_8_8_8_DTR; 3243 else 3244 nor->reg_proto = SNOR_PROTO_1_1_1; 3245 3246 return 0; 3247 } 3248 3249 /** 3250 * spi_nor_quad_enable() - enable Quad I/O if needed. 3251 * @nor: pointer to a 'struct spi_nor' 3252 * 3253 * Return: 0 on success, -errno otherwise. 3254 */ 3255 static int spi_nor_quad_enable(struct spi_nor *nor) 3256 { 3257 if (!nor->params->quad_enable) 3258 return 0; 3259 3260 if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 || 3261 spi_nor_get_protocol_width(nor->write_proto) == 4)) 3262 return 0; 3263 3264 return nor->params->quad_enable(nor); 3265 } 3266 3267 /** 3268 * spi_nor_set_4byte_addr_mode() - Set address mode. 3269 * @nor: pointer to a 'struct spi_nor'. 3270 * @enable: enable/disable 4 byte address mode. 3271 * 3272 * Return: 0 on success, -errno otherwise. 3273 */ 3274 int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) 3275 { 3276 struct spi_nor_flash_parameter *params = nor->params; 3277 int ret; 3278 3279 if (enable) { 3280 /* 3281 * If the RESET# pin isn't hooked up properly, or the system 3282 * otherwise doesn't perform a reset command in the boot 3283 * sequence, it's impossible to 100% protect against unexpected 3284 * reboots (e.g., crashes). Warn the user (or hopefully, system 3285 * designer) that this is bad. 3286 */ 3287 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, 3288 "enabling reset hack; may not recover from unexpected reboots\n"); 3289 } 3290 3291 ret = params->set_4byte_addr_mode(nor, enable); 3292 if (ret && ret != -EOPNOTSUPP) 3293 return ret; 3294 3295 if (enable) { 3296 params->addr_nbytes = 4; 3297 params->addr_mode_nbytes = 4; 3298 } else { 3299 params->addr_nbytes = 3; 3300 params->addr_mode_nbytes = 3; 3301 } 3302 3303 return 0; 3304 } 3305 3306 static int spi_nor_init(struct spi_nor *nor) 3307 { 3308 int err; 3309 3310 err = spi_nor_set_octal_dtr(nor, true); 3311 if (err) { 3312 dev_dbg(nor->dev, "octal mode not supported\n"); 3313 return err; 3314 } 3315 3316 err = spi_nor_quad_enable(nor); 3317 if (err) { 3318 dev_dbg(nor->dev, "quad mode not supported\n"); 3319 return err; 3320 } 3321 3322 /* 3323 * Some SPI NOR flashes are write protected by default after a power-on 3324 * reset cycle, in order to avoid inadvertent writes during power-up. 3325 * Backward compatibility imposes to unlock the entire flash memory 3326 * array at power-up by default. Depending on the kernel configuration 3327 * (1) do nothing, (2) always unlock the entire flash array or (3) 3328 * unlock the entire flash array only when the software write 3329 * protection bits are volatile. The latter is indicated by 3330 * SNOR_F_SWP_IS_VOLATILE. 3331 */ 3332 spi_nor_cache_sr_lock_bits(nor, NULL); 3333 if (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE) || 3334 (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE) && 3335 nor->flags & SNOR_F_SWP_IS_VOLATILE)) { 3336 spi_nor_try_unlock_all(nor); 3337 } 3338 3339 if (nor->addr_nbytes == 4 && 3340 nor->read_proto != SNOR_PROTO_8_8_8_DTR && 3341 !(nor->flags & SNOR_F_4B_OPCODES)) 3342 return spi_nor_set_4byte_addr_mode(nor, true); 3343 3344 return 0; 3345 } 3346 3347 /** 3348 * spi_nor_soft_reset() - Perform a software reset 3349 * @nor: pointer to 'struct spi_nor' 3350 * 3351 * Performs a "Soft Reset and Enter Default Protocol Mode" sequence which resets 3352 * the device to its power-on-reset state. This is useful when the software has 3353 * made some changes to device (volatile) registers and needs to reset it before 3354 * shutting down, for example. 3355 * 3356 * Not every flash supports this sequence. The same set of opcodes might be used 3357 * for some other operation on a flash that does not support this. Support for 3358 * this sequence can be discovered via SFDP in the BFPT table. 3359 * 3360 * Return: 0 on success, -errno otherwise. 3361 */ 3362 static void spi_nor_soft_reset(struct spi_nor *nor) 3363 { 3364 struct spi_mem_op op; 3365 int ret; 3366 3367 op = (struct spi_mem_op)SPINOR_SRSTEN_OP; 3368 3369 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 3370 3371 ret = spi_mem_exec_op(nor->spimem, &op); 3372 if (ret) { 3373 if (ret != -EOPNOTSUPP) 3374 dev_warn(nor->dev, "Software reset failed: %d\n", ret); 3375 return; 3376 } 3377 3378 op = (struct spi_mem_op)SPINOR_SRST_OP; 3379 3380 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 3381 3382 ret = spi_mem_exec_op(nor->spimem, &op); 3383 if (ret) { 3384 dev_warn(nor->dev, "Software reset failed: %d\n", ret); 3385 return; 3386 } 3387 3388 /* 3389 * Software Reset is not instant, and the delay varies from flash to 3390 * flash. Looking at a few flashes, most range somewhere below 100 3391 * microseconds. So, sleep for a range of 200-400 us. 3392 */ 3393 usleep_range(SPI_NOR_SRST_SLEEP_MIN, SPI_NOR_SRST_SLEEP_MAX); 3394 } 3395 3396 /* mtd suspend handler */ 3397 static int spi_nor_suspend(struct mtd_info *mtd) 3398 { 3399 struct spi_nor *nor = mtd_to_spi_nor(mtd); 3400 int ret; 3401 3402 /* Disable octal DTR mode if we enabled it. */ 3403 ret = spi_nor_set_octal_dtr(nor, false); 3404 if (ret) 3405 dev_err(nor->dev, "suspend() failed\n"); 3406 3407 return ret; 3408 } 3409 3410 /* mtd resume handler */ 3411 static void spi_nor_resume(struct mtd_info *mtd) 3412 { 3413 struct spi_nor *nor = mtd_to_spi_nor(mtd); 3414 struct device *dev = nor->dev; 3415 int ret; 3416 3417 /* re-initialize the nor chip */ 3418 ret = spi_nor_init(nor); 3419 if (ret) 3420 dev_err(dev, "resume() failed\n"); 3421 } 3422 3423 static int spi_nor_get_device(struct mtd_info *mtd) 3424 { 3425 struct mtd_info *master = mtd_get_master(mtd); 3426 struct spi_nor *nor = mtd_to_spi_nor(master); 3427 struct device *dev; 3428 3429 if (nor->spimem) 3430 dev = nor->spimem->spi->controller->dev.parent; 3431 else 3432 dev = nor->dev; 3433 3434 if (!try_module_get(dev->driver->owner)) 3435 return -ENODEV; 3436 3437 return 0; 3438 } 3439 3440 static void spi_nor_put_device(struct mtd_info *mtd) 3441 { 3442 struct mtd_info *master = mtd_get_master(mtd); 3443 struct spi_nor *nor = mtd_to_spi_nor(master); 3444 struct device *dev; 3445 3446 if (nor->spimem) 3447 dev = nor->spimem->spi->controller->dev.parent; 3448 else 3449 dev = nor->dev; 3450 3451 module_put(dev->driver->owner); 3452 } 3453 3454 static void spi_nor_restore(struct spi_nor *nor) 3455 { 3456 int ret; 3457 3458 /* restore the addressing mode */ 3459 if (nor->addr_nbytes == 4 && !(nor->flags & SNOR_F_4B_OPCODES) && 3460 nor->flags & SNOR_F_BROKEN_RESET) { 3461 ret = spi_nor_set_4byte_addr_mode(nor, false); 3462 if (ret) 3463 /* 3464 * Do not stop the execution in the hope that the flash 3465 * will default to the 3-byte address mode after the 3466 * software reset. 3467 */ 3468 dev_err(nor->dev, "Failed to exit 4-byte address mode, err = %d\n", ret); 3469 } 3470 3471 if (nor->flags & SNOR_F_SOFT_RESET) 3472 spi_nor_soft_reset(nor); 3473 } 3474 3475 static const struct flash_info *spi_nor_match_name(struct spi_nor *nor, 3476 const char *name) 3477 { 3478 unsigned int i, j; 3479 3480 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) { 3481 for (j = 0; j < manufacturers[i]->nparts; j++) { 3482 if (manufacturers[i]->parts[j].name && 3483 !strcmp(name, manufacturers[i]->parts[j].name)) { 3484 nor->manufacturer = manufacturers[i]; 3485 return &manufacturers[i]->parts[j]; 3486 } 3487 } 3488 } 3489 3490 return NULL; 3491 } 3492 3493 static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, 3494 const char *name) 3495 { 3496 const struct flash_info *info = NULL; 3497 3498 if (name) 3499 info = spi_nor_match_name(nor, name); 3500 /* 3501 * Auto-detect if chip name wasn't specified or not found, or the chip 3502 * has an ID. If the chip supposedly has an ID, we also do an 3503 * auto-detection to compare it later. 3504 */ 3505 if (!info || info->id) { 3506 const struct flash_info *jinfo; 3507 3508 jinfo = spi_nor_detect(nor); 3509 if (IS_ERR(jinfo)) 3510 return jinfo; 3511 3512 /* 3513 * If caller has specified name of flash model that can normally 3514 * be detected using JEDEC, let's verify it. 3515 */ 3516 if (info && jinfo != info) 3517 dev_warn(nor->dev, "found %s, expected %s\n", 3518 jinfo->name, info->name); 3519 3520 /* If info was set before, JEDEC knows better. */ 3521 info = jinfo; 3522 } 3523 3524 return info; 3525 } 3526 3527 static u32 3528 spi_nor_get_region_erasesize(const struct spi_nor_erase_region *region, 3529 const struct spi_nor_erase_type *erase_type) 3530 { 3531 int i; 3532 3533 if (region->overlaid) 3534 return region->size; 3535 3536 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 3537 if (region->erase_mask & BIT(i)) 3538 return erase_type[i].size; 3539 } 3540 3541 return 0; 3542 } 3543 3544 static int spi_nor_set_mtd_eraseregions(struct spi_nor *nor) 3545 { 3546 const struct spi_nor_erase_map *map = &nor->params->erase_map; 3547 const struct spi_nor_erase_region *region = map->regions; 3548 struct mtd_erase_region_info *mtd_region; 3549 struct mtd_info *mtd = &nor->mtd; 3550 u32 erasesize, i; 3551 3552 mtd_region = devm_kcalloc(nor->dev, map->n_regions, sizeof(*mtd_region), 3553 GFP_KERNEL); 3554 if (!mtd_region) 3555 return -ENOMEM; 3556 3557 for (i = 0; i < map->n_regions; i++) { 3558 erasesize = spi_nor_get_region_erasesize(®ion[i], 3559 map->erase_type); 3560 if (!erasesize) 3561 return -EINVAL; 3562 3563 mtd_region[i].erasesize = erasesize; 3564 mtd_region[i].numblocks = div_u64(region[i].size, erasesize); 3565 mtd_region[i].offset = region[i].offset; 3566 } 3567 3568 mtd->numeraseregions = map->n_regions; 3569 mtd->eraseregions = mtd_region; 3570 3571 return 0; 3572 } 3573 3574 static int spi_nor_set_mtd_info(struct spi_nor *nor) 3575 { 3576 struct mtd_info *mtd = &nor->mtd; 3577 struct device *dev = nor->dev; 3578 3579 spi_nor_set_mtd_locking_ops(nor); 3580 spi_nor_set_mtd_otp_ops(nor); 3581 3582 mtd->dev.parent = dev; 3583 if (!mtd->name) 3584 mtd->name = dev_name(dev); 3585 mtd->type = MTD_NORFLASH; 3586 mtd->flags = MTD_CAP_NORFLASH; 3587 /* Unset BIT_WRITEABLE to enable JFFS2 write buffer for ECC'd NOR */ 3588 if (nor->flags & SNOR_F_ECC) 3589 mtd->flags &= ~MTD_BIT_WRITEABLE; 3590 if (nor->info->flags & SPI_NOR_NO_ERASE) 3591 mtd->flags |= MTD_NO_ERASE; 3592 else 3593 mtd->_erase = spi_nor_erase; 3594 mtd->writesize = nor->params->writesize; 3595 mtd->writebufsize = nor->params->page_size; 3596 mtd->size = nor->params->size; 3597 mtd->_read = spi_nor_read; 3598 /* Might be already set by some SST flashes. */ 3599 if (!mtd->_write) 3600 mtd->_write = spi_nor_write; 3601 mtd->_suspend = spi_nor_suspend; 3602 mtd->_resume = spi_nor_resume; 3603 mtd->_get_device = spi_nor_get_device; 3604 mtd->_put_device = spi_nor_put_device; 3605 3606 if (!spi_nor_has_uniform_erase(nor)) 3607 return spi_nor_set_mtd_eraseregions(nor); 3608 3609 return 0; 3610 } 3611 3612 static int spi_nor_hw_reset(struct spi_nor *nor) 3613 { 3614 struct gpio_desc *reset; 3615 3616 reset = devm_gpiod_get_optional(nor->dev, "reset", GPIOD_OUT_LOW); 3617 if (IS_ERR_OR_NULL(reset)) 3618 return PTR_ERR_OR_ZERO(reset); 3619 3620 /* 3621 * Experimental delay values by looking at different flash device 3622 * vendors datasheets. 3623 */ 3624 usleep_range(1, 5); 3625 gpiod_set_value_cansleep(reset, 1); 3626 usleep_range(100, 150); 3627 gpiod_set_value_cansleep(reset, 0); 3628 usleep_range(1000, 1200); 3629 3630 return 0; 3631 } 3632 3633 int spi_nor_scan(struct spi_nor *nor, const char *name, 3634 const struct spi_nor_hwcaps *hwcaps) 3635 { 3636 const struct flash_info *info; 3637 struct device *dev = nor->dev; 3638 int ret; 3639 3640 ret = spi_nor_check(nor); 3641 if (ret) 3642 return ret; 3643 3644 /* Reset SPI protocol for all commands. */ 3645 nor->reg_proto = SNOR_PROTO_1_1_1; 3646 nor->read_proto = SNOR_PROTO_1_1_1; 3647 nor->write_proto = SNOR_PROTO_1_1_1; 3648 3649 /* 3650 * We need the bounce buffer early to read/write registers when going 3651 * through the spi-mem layer (buffers have to be DMA-able). 3652 * For spi-mem drivers, we'll reallocate a new buffer if 3653 * nor->params->page_size turns out to be greater than PAGE_SIZE (which 3654 * shouldn't happen before long since NOR pages are usually less 3655 * than 1KB) after spi_nor_scan() returns. 3656 */ 3657 nor->bouncebuf_size = PAGE_SIZE; 3658 nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size, 3659 GFP_KERNEL); 3660 if (!nor->bouncebuf) 3661 return -ENOMEM; 3662 3663 ret = spi_nor_hw_reset(nor); 3664 if (ret) 3665 return ret; 3666 3667 info = spi_nor_get_flash_info(nor, name); 3668 if (IS_ERR(info)) 3669 return PTR_ERR(info); 3670 3671 nor->info = info; 3672 3673 mutex_init(&nor->lock); 3674 3675 /* Init flash parameters based on flash_info struct and SFDP */ 3676 ret = spi_nor_init_params(nor); 3677 if (ret) 3678 return ret; 3679 3680 if (spi_nor_use_parallel_locking(nor)) 3681 init_waitqueue_head(&nor->rww.wait); 3682 3683 /* 3684 * Configure the SPI memory: 3685 * - select op codes for (Fast) Read, Page Program and Sector Erase. 3686 * - set the number of dummy cycles (mode cycles + wait states). 3687 * - set the SPI protocols for register and memory accesses. 3688 * - set the number of address bytes. 3689 */ 3690 ret = spi_nor_setup(nor, hwcaps); 3691 if (ret) 3692 return ret; 3693 3694 /* Send all the required SPI flash commands to initialize device */ 3695 ret = spi_nor_init(nor); 3696 if (ret) 3697 return ret; 3698 3699 /* No mtd_info fields should be used up to this point. */ 3700 ret = spi_nor_set_mtd_info(nor); 3701 if (ret) 3702 return ret; 3703 3704 dev_dbg(dev, "Manufacturer and device ID: %*phN\n", 3705 SPI_NOR_MAX_ID_LEN, nor->id); 3706 3707 return 0; 3708 } 3709 EXPORT_SYMBOL_GPL(spi_nor_scan); 3710 3711 static int spi_nor_create_read_dirmap(struct spi_nor *nor) 3712 { 3713 struct spi_mem_dirmap_info info = { 3714 .op_tmpl = &info.primary_op_tmpl, 3715 .primary_op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), 3716 SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0), 3717 SPI_MEM_OP_DUMMY(nor->read_dummy, 0), 3718 SPI_MEM_OP_DATA_IN(0, NULL, 0)), 3719 .offset = 0, 3720 .length = nor->params->size, 3721 }; 3722 struct spi_mem_op *op = info.op_tmpl; 3723 3724 spi_nor_spimem_setup_op(nor, op, nor->read_proto); 3725 3726 /* convert the dummy cycles to the number of bytes */ 3727 op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8; 3728 if (spi_nor_protocol_is_dtr(nor->read_proto)) 3729 op->dummy.nbytes *= 2; 3730 3731 /* 3732 * Since spi_nor_spimem_setup_op() only sets buswidth when the number 3733 * of data bytes is non-zero, the data buswidth won't be set here. So, 3734 * do it explicitly. 3735 */ 3736 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); 3737 3738 nor->dirmap.rdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem, 3739 &info); 3740 return PTR_ERR_OR_ZERO(nor->dirmap.rdesc); 3741 } 3742 3743 static int spi_nor_create_write_dirmap(struct spi_nor *nor) 3744 { 3745 struct spi_mem_dirmap_info info = { 3746 .op_tmpl = &info.primary_op_tmpl, 3747 .primary_op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0), 3748 SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0), 3749 SPI_MEM_OP_NO_DUMMY, 3750 SPI_MEM_OP_DATA_OUT(0, NULL, 0)), 3751 .offset = 0, 3752 .length = nor->params->size, 3753 }; 3754 struct spi_mem_op *op = info.op_tmpl; 3755 3756 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 3757 op->addr.nbytes = 0; 3758 3759 spi_nor_spimem_setup_op(nor, op, nor->write_proto); 3760 3761 /* 3762 * Since spi_nor_spimem_setup_op() only sets buswidth when the number 3763 * of data bytes is non-zero, the data buswidth won't be set here. So, 3764 * do it explicitly. 3765 */ 3766 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); 3767 3768 nor->dirmap.wdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem, 3769 &info); 3770 return PTR_ERR_OR_ZERO(nor->dirmap.wdesc); 3771 } 3772 3773 static int spi_nor_probe(struct spi_mem *spimem) 3774 { 3775 struct spi_device *spi = spimem->spi; 3776 struct device *dev = &spi->dev; 3777 struct flash_platform_data *data = dev_get_platdata(dev); 3778 struct spi_nor *nor; 3779 /* 3780 * Enable all caps by default. The core will mask them after 3781 * checking what's really supported using spi_mem_supports_op(). 3782 */ 3783 const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL }; 3784 char *flash_name; 3785 int ret; 3786 3787 ret = devm_regulator_get_enable(dev, "vcc"); 3788 if (ret) 3789 return ret; 3790 3791 nor = devm_kzalloc(dev, sizeof(*nor), GFP_KERNEL); 3792 if (!nor) 3793 return -ENOMEM; 3794 3795 nor->spimem = spimem; 3796 nor->dev = dev; 3797 spi_nor_set_flash_node(nor, dev->of_node); 3798 3799 spi_mem_set_drvdata(spimem, nor); 3800 3801 if (data && data->name) 3802 nor->mtd.name = data->name; 3803 3804 if (!nor->mtd.name) 3805 nor->mtd.name = spi_mem_get_name(spimem); 3806 3807 /* 3808 * For some (historical?) reason many platforms provide two different 3809 * names in flash_platform_data: "name" and "type". Quite often name is 3810 * set to "m25p80" and then "type" provides a real chip name. 3811 * If that's the case, respect "type" and ignore a "name". 3812 */ 3813 if (data && data->type) 3814 flash_name = data->type; 3815 else if (!strcmp(spi->modalias, "spi-nor")) 3816 flash_name = NULL; /* auto-detect */ 3817 else 3818 flash_name = spi->modalias; 3819 3820 ret = spi_nor_scan(nor, flash_name, &hwcaps); 3821 if (ret) 3822 return ret; 3823 3824 spi_nor_debugfs_register(nor); 3825 3826 /* 3827 * None of the existing parts have > 512B pages, but let's play safe 3828 * and add this logic so that if anyone ever adds support for such 3829 * a NOR we don't end up with buffer overflows. 3830 */ 3831 if (nor->params->page_size > PAGE_SIZE) { 3832 nor->bouncebuf_size = nor->params->page_size; 3833 devm_kfree(dev, nor->bouncebuf); 3834 nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size, 3835 GFP_KERNEL); 3836 if (!nor->bouncebuf) 3837 return -ENOMEM; 3838 } 3839 3840 ret = spi_nor_create_read_dirmap(nor); 3841 if (ret) 3842 return ret; 3843 3844 ret = spi_nor_create_write_dirmap(nor); 3845 if (ret) 3846 return ret; 3847 3848 return mtd_device_register(&nor->mtd, data ? data->parts : NULL, 3849 data ? data->nr_parts : 0); 3850 } 3851 3852 static int spi_nor_remove(struct spi_mem *spimem) 3853 { 3854 struct spi_nor *nor = spi_mem_get_drvdata(spimem); 3855 3856 spi_nor_restore(nor); 3857 3858 /* Clean up MTD stuff. */ 3859 return mtd_device_unregister(&nor->mtd); 3860 } 3861 3862 static void spi_nor_shutdown(struct spi_mem *spimem) 3863 { 3864 struct spi_nor *nor = spi_mem_get_drvdata(spimem); 3865 3866 spi_nor_restore(nor); 3867 } 3868 3869 /* 3870 * Do NOT add to this array without reading the following: 3871 * 3872 * Historically, many flash devices are bound to this driver by their name. But 3873 * since most of these flash are compatible to some extent, and their 3874 * differences can often be differentiated by the JEDEC read-ID command, we 3875 * encourage new users to add support to the spi-nor library, and simply bind 3876 * against a generic string here (e.g., "jedec,spi-nor"). 3877 * 3878 * Many flash names are kept here in this list to keep them available 3879 * as module aliases for existing platforms. 3880 */ 3881 static const struct spi_device_id spi_nor_dev_ids[] = { 3882 /* 3883 * Allow non-DT platform devices to bind to the "spi-nor" modalias, and 3884 * hack around the fact that the SPI core does not provide uevent 3885 * matching for .of_match_table 3886 */ 3887 {"spi-nor"}, 3888 3889 /* 3890 * Entries not used in DTs that should be safe to drop after replacing 3891 * them with "spi-nor" in platform data. 3892 */ 3893 {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"}, 3894 3895 /* 3896 * Entries that were used in DTs without "jedec,spi-nor" fallback and 3897 * should be kept for backward compatibility. 3898 */ 3899 {"at25df321a"}, {"at25df641"}, {"at26df081a"}, 3900 {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"}, 3901 {"mx25l25635e"},{"mx66l51235l"}, 3902 {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"}, 3903 {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"}, 3904 {"s25fl064k"}, 3905 {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"}, 3906 {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"}, 3907 {"m25p64"}, {"m25p128"}, 3908 {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"}, 3909 {"w25q80bl"}, {"w25q128"}, {"w25q256"}, 3910 3911 /* Flashes that can't be detected using JEDEC */ 3912 {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"}, 3913 {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"}, 3914 {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"}, 3915 3916 /* Everspin MRAMs (non-JEDEC) */ 3917 { "mr25h128" }, /* 128 Kib, 40 MHz */ 3918 { "mr25h256" }, /* 256 Kib, 40 MHz */ 3919 { "mr25h10" }, /* 1 Mib, 40 MHz */ 3920 { "mr25h40" }, /* 4 Mib, 40 MHz */ 3921 3922 { }, 3923 }; 3924 MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids); 3925 3926 static const struct of_device_id spi_nor_of_table[] = { 3927 /* 3928 * Generic compatibility for SPI NOR that can be identified by the 3929 * JEDEC READ ID opcode (0x9F). Use this, if possible. 3930 */ 3931 { .compatible = "jedec,spi-nor" }, 3932 { /* sentinel */ }, 3933 }; 3934 MODULE_DEVICE_TABLE(of, spi_nor_of_table); 3935 3936 /* 3937 * REVISIT: many of these chips have deep power-down modes, which 3938 * should clearly be entered on suspend() to minimize power use. 3939 * And also when they're otherwise idle... 3940 */ 3941 static struct spi_mem_driver spi_nor_driver = { 3942 .spidrv = { 3943 .driver = { 3944 .name = "spi-nor", 3945 .of_match_table = spi_nor_of_table, 3946 .dev_groups = spi_nor_sysfs_groups, 3947 }, 3948 .id_table = spi_nor_dev_ids, 3949 }, 3950 .probe = spi_nor_probe, 3951 .remove = spi_nor_remove, 3952 .shutdown = spi_nor_shutdown, 3953 }; 3954 3955 static int __init spi_nor_module_init(void) 3956 { 3957 return spi_mem_driver_register(&spi_nor_driver); 3958 } 3959 module_init(spi_nor_module_init); 3960 3961 static void __exit spi_nor_module_exit(void) 3962 { 3963 spi_mem_driver_unregister(&spi_nor_driver); 3964 spi_nor_debugfs_shutdown(); 3965 } 3966 module_exit(spi_nor_module_exit); 3967 3968 MODULE_LICENSE("GPL v2"); 3969 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>"); 3970 MODULE_AUTHOR("Mike Lavender"); 3971 MODULE_DESCRIPTION("framework for SPI NOR"); 3972