1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_TDX_H
3 #define __KVM_X86_VMX_TDX_H
4
5 #include "tdx_arch.h"
6
7 #ifdef CONFIG_KVM_INTEL_TDX
8 #include "common.h"
9
10 int tdx_hardware_setup(void);
11 void tdx_hardware_unsetup(void);
12
13 extern bool enable_tdx;
14
15 /* TDX module hardware states. These follow the TDX module OP_STATEs. */
16 enum kvm_tdx_state {
17 TD_STATE_UNINITIALIZED = 0,
18 TD_STATE_INITIALIZED,
19 TD_STATE_RUNNABLE,
20 };
21
22 struct kvm_tdx {
23 struct kvm kvm;
24
25 struct misc_cg *misc_cg;
26 int hkid;
27 enum kvm_tdx_state state;
28
29 u64 attributes;
30 u64 xfam;
31
32 u64 tsc_offset;
33 u64 tsc_multiplier;
34
35 struct tdx_td td;
36
37 /*
38 * Scratch pointer used to pass the source page to tdx_mem_page_add().
39 * Protected by slots_lock, and non-NULL only when mapping a private
40 * pfn via tdx_gmem_post_populate().
41 */
42 struct page *page_add_src;
43
44 /*
45 * Prevent vCPUs from TD entry to ensure SEPT zap related SEAMCALLs do
46 * not contend with tdh_vp_enter() and TDCALLs.
47 * Set/unset is protected with kvm->mmu_lock.
48 */
49 bool wait_for_sept_zap;
50 };
51
52 /* TDX module vCPU states */
53 enum vcpu_tdx_state {
54 VCPU_TD_STATE_UNINITIALIZED = 0,
55 VCPU_TD_STATE_INITIALIZED,
56 };
57
58 struct vcpu_tdx {
59 struct kvm_vcpu vcpu;
60 struct vcpu_vt vt;
61 u64 ext_exit_qualification;
62 gpa_t exit_gpa;
63 struct tdx_module_args vp_enter_args;
64
65 struct tdx_vp vp;
66
67 struct list_head cpu_list;
68
69 u64 vp_enter_ret;
70
71 enum vcpu_tdx_state state;
72
73 u64 map_gpa_next;
74 u64 map_gpa_end;
75
76 struct tdx_pamt_cache pamt_cache;
77 };
78
79 void tdh_vp_rd_failed(struct vcpu_tdx *tdx, char *uclass, u32 field, u64 err);
80 void tdh_vp_wr_failed(struct vcpu_tdx *tdx, char *uclass, char *op, u32 field,
81 u64 val, u64 err);
82
td_tdcs_exec_read64(struct kvm_tdx * kvm_tdx,u32 field)83 static __always_inline u64 td_tdcs_exec_read64(struct kvm_tdx *kvm_tdx, u32 field)
84 {
85 u64 err, data;
86
87 err = tdh_mng_rd(&kvm_tdx->td, TDCS_EXEC(field), &data);
88 if (unlikely(err)) {
89 pr_err("TDH_MNG_RD[EXEC.0x%x] failed: 0x%llx\n", field, err);
90 return 0;
91 }
92 return data;
93 }
94
tdvps_vmcs_check(u32 field,u8 bits)95 static __always_inline void tdvps_vmcs_check(u32 field, u8 bits)
96 {
97 #define VMCS_ENC_ACCESS_TYPE_MASK 0x1UL
98 #define VMCS_ENC_ACCESS_TYPE_FULL 0x0UL
99 #define VMCS_ENC_ACCESS_TYPE_HIGH 0x1UL
100 #define VMCS_ENC_ACCESS_TYPE(field) ((field) & VMCS_ENC_ACCESS_TYPE_MASK)
101
102 /* TDX is 64bit only. HIGH field isn't supported. */
103 BUILD_BUG_ON_MSG(__builtin_constant_p(field) &&
104 VMCS_ENC_ACCESS_TYPE(field) == VMCS_ENC_ACCESS_TYPE_HIGH,
105 "Read/Write to TD VMCS *_HIGH fields not supported");
106
107 BUILD_BUG_ON(bits != 16 && bits != 32 && bits != 64);
108
109 #define VMCS_ENC_WIDTH_MASK GENMASK(14, 13)
110 #define VMCS_ENC_WIDTH_16BIT (0UL << 13)
111 #define VMCS_ENC_WIDTH_64BIT (1UL << 13)
112 #define VMCS_ENC_WIDTH_32BIT (2UL << 13)
113 #define VMCS_ENC_WIDTH_NATURAL (3UL << 13)
114 #define VMCS_ENC_WIDTH(field) ((field) & VMCS_ENC_WIDTH_MASK)
115
116 /* TDX is 64bit only. i.e. natural width = 64bit. */
117 BUILD_BUG_ON_MSG(bits != 64 && __builtin_constant_p(field) &&
118 (VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_64BIT ||
119 VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_NATURAL),
120 "Invalid TD VMCS access for 64-bit field");
121 BUILD_BUG_ON_MSG(bits != 32 && __builtin_constant_p(field) &&
122 VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_32BIT,
123 "Invalid TD VMCS access for 32-bit field");
124 BUILD_BUG_ON_MSG(bits != 16 && __builtin_constant_p(field) &&
125 VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_16BIT,
126 "Invalid TD VMCS access for 16-bit field");
127 }
128
tdvps_management_check(u64 field,u8 bits)129 static __always_inline void tdvps_management_check(u64 field, u8 bits) {}
tdvps_state_non_arch_check(u64 field,u8 bits)130 static __always_inline void tdvps_state_non_arch_check(u64 field, u8 bits) {}
131
132 #define TDX_BUILD_TDVPS_ACCESSORS(bits, uclass, lclass) \
133 static __always_inline u##bits td_##lclass##_read##bits(struct vcpu_tdx *tdx, \
134 u32 field) \
135 { \
136 u64 err, data; \
137 \
138 tdvps_##lclass##_check(field, bits); \
139 err = tdh_vp_rd(&tdx->vp, TDVPS_##uclass(field), &data); \
140 if (unlikely(err)) { \
141 tdh_vp_rd_failed(tdx, #uclass, field, err); \
142 return 0; \
143 } \
144 return (u##bits)data; \
145 } \
146 static __always_inline void td_##lclass##_write##bits(struct vcpu_tdx *tdx, \
147 u32 field, u##bits val) \
148 { \
149 u64 err; \
150 \
151 tdvps_##lclass##_check(field, bits); \
152 err = tdh_vp_wr(&tdx->vp, TDVPS_##uclass(field), val, \
153 GENMASK_ULL(bits - 1, 0)); \
154 if (unlikely(err)) \
155 tdh_vp_wr_failed(tdx, #uclass, " = ", field, (u64)val, err); \
156 } \
157 static __always_inline void td_##lclass##_setbit##bits(struct vcpu_tdx *tdx, \
158 u32 field, u64 bit) \
159 { \
160 u64 err; \
161 \
162 tdvps_##lclass##_check(field, bits); \
163 err = tdh_vp_wr(&tdx->vp, TDVPS_##uclass(field), bit, bit); \
164 if (unlikely(err)) \
165 tdh_vp_wr_failed(tdx, #uclass, " |= ", field, bit, err); \
166 } \
167 static __always_inline void td_##lclass##_clearbit##bits(struct vcpu_tdx *tdx, \
168 u32 field, u64 bit) \
169 { \
170 u64 err; \
171 \
172 tdvps_##lclass##_check(field, bits); \
173 err = tdh_vp_wr(&tdx->vp, TDVPS_##uclass(field), 0, bit); \
174 if (unlikely(err)) \
175 tdh_vp_wr_failed(tdx, #uclass, " &= ~", field, bit, err);\
176 }
177
178
179 bool tdx_interrupt_allowed(struct kvm_vcpu *vcpu);
180 int tdx_complete_emulated_msr(struct kvm_vcpu *vcpu, int err);
181
182 TDX_BUILD_TDVPS_ACCESSORS(16, VMCS, vmcs);
183 TDX_BUILD_TDVPS_ACCESSORS(32, VMCS, vmcs);
184 TDX_BUILD_TDVPS_ACCESSORS(64, VMCS, vmcs);
185
186 TDX_BUILD_TDVPS_ACCESSORS(8, MANAGEMENT, management);
187 TDX_BUILD_TDVPS_ACCESSORS(64, STATE_NON_ARCH, state_non_arch);
188
189 #else
190 #define enable_tdx 0
191
192 struct kvm_tdx {
193 struct kvm kvm;
194 };
195
196 struct vcpu_tdx {
197 struct kvm_vcpu vcpu;
198 };
199
tdx_interrupt_allowed(struct kvm_vcpu * vcpu)200 static inline bool tdx_interrupt_allowed(struct kvm_vcpu *vcpu) { return false; }
tdx_complete_emulated_msr(struct kvm_vcpu * vcpu,int err)201 static inline int tdx_complete_emulated_msr(struct kvm_vcpu *vcpu, int err) { return 0; }
202
203 #endif
204
205 #endif
206