1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cryptographic API. 4 * 5 * Support for VIA PadLock hardware crypto engine. 6 * 7 * Copyright (c) 2004 Michal Ludvig <michal@logix.cz> 8 * 9 */ 10 11 #include <crypto/algapi.h> 12 #include <crypto/aes.h> 13 #include <crypto/internal/skcipher.h> 14 #include <crypto/padlock.h> 15 #include <linux/module.h> 16 #include <linux/init.h> 17 #include <linux/types.h> 18 #include <linux/errno.h> 19 #include <linux/interrupt.h> 20 #include <linux/kernel.h> 21 #include <linux/mm.h> 22 #include <linux/percpu.h> 23 #include <linux/smp.h> 24 #include <linux/slab.h> 25 #include <asm/cpu_device_id.h> 26 #include <asm/byteorder.h> 27 #include <asm/processor.h> 28 #include <asm/fpu/api.h> 29 30 /* 31 * Number of data blocks actually fetched for each xcrypt insn. 32 * Processors with prefetch errata will fetch extra blocks. 33 */ 34 static unsigned int ecb_fetch_blocks = 2; 35 #define MAX_ECB_FETCH_BLOCKS (8) 36 #define ecb_fetch_bytes (ecb_fetch_blocks * AES_BLOCK_SIZE) 37 38 static unsigned int cbc_fetch_blocks = 1; 39 #define MAX_CBC_FETCH_BLOCKS (4) 40 #define cbc_fetch_bytes (cbc_fetch_blocks * AES_BLOCK_SIZE) 41 42 /* Control word. */ 43 struct cword { 44 unsigned int __attribute__ ((__packed__)) 45 rounds:4, 46 algo:3, 47 keygen:1, 48 interm:1, 49 encdec:1, 50 ksize:2; 51 } __attribute__ ((__aligned__(PADLOCK_ALIGNMENT))); 52 53 /* Whenever making any changes to the following 54 * structure *make sure* you keep E, d_data 55 * and cword aligned on 16 Bytes boundaries and 56 * the Hardware can access 16 * 16 bytes of E and d_data 57 * (only the first 15 * 16 bytes matter but the HW reads 58 * more). 59 */ 60 struct aes_ctx { 61 u32 E[AES_MAX_KEYLENGTH_U32] 62 __attribute__ ((__aligned__(PADLOCK_ALIGNMENT))); 63 u32 d_data[AES_MAX_KEYLENGTH_U32] 64 __attribute__ ((__aligned__(PADLOCK_ALIGNMENT))); 65 struct { 66 struct cword encrypt; 67 struct cword decrypt; 68 } cword; 69 u32 *D; 70 }; 71 72 static DEFINE_PER_CPU(struct cword *, paes_last_cword); 73 74 /* Tells whether the ACE is capable to generate 75 the extended key for a given key_len. */ 76 static inline int 77 aes_hw_extkey_available(uint8_t key_len) 78 { 79 /* TODO: We should check the actual CPU model/stepping 80 as it's possible that the capability will be 81 added in the next CPU revisions. */ 82 if (key_len == 16) 83 return 1; 84 return 0; 85 } 86 87 static inline struct aes_ctx *aes_ctx_common(void *ctx) 88 { 89 unsigned long addr = (unsigned long)ctx; 90 unsigned long align = PADLOCK_ALIGNMENT; 91 92 if (align <= crypto_tfm_ctx_alignment()) 93 align = 1; 94 return (struct aes_ctx *)ALIGN(addr, align); 95 } 96 97 static inline struct aes_ctx *aes_ctx(struct crypto_tfm *tfm) 98 { 99 return aes_ctx_common(crypto_tfm_ctx(tfm)); 100 } 101 102 static inline struct aes_ctx *skcipher_aes_ctx(struct crypto_skcipher *tfm) 103 { 104 return aes_ctx_common(crypto_skcipher_ctx(tfm)); 105 } 106 107 static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key, 108 unsigned int key_len) 109 { 110 struct aes_ctx *ctx = aes_ctx(tfm); 111 const __le32 *key = (const __le32 *)in_key; 112 struct crypto_aes_ctx gen_aes __cleanup(aes_zeroize_ctx); 113 int cpu; 114 115 if (key_len % 8) 116 return -EINVAL; 117 118 /* 119 * If the hardware is capable of generating the extended key 120 * itself we must supply the plain key for both encryption 121 * and decryption. 122 */ 123 ctx->D = ctx->E; 124 125 ctx->E[0] = le32_to_cpu(key[0]); 126 ctx->E[1] = le32_to_cpu(key[1]); 127 ctx->E[2] = le32_to_cpu(key[2]); 128 ctx->E[3] = le32_to_cpu(key[3]); 129 130 /* Prepare control words. */ 131 memset(&ctx->cword, 0, sizeof(ctx->cword)); 132 133 ctx->cword.decrypt.encdec = 1; 134 ctx->cword.encrypt.rounds = 10 + (key_len - 16) / 4; 135 ctx->cword.decrypt.rounds = ctx->cword.encrypt.rounds; 136 ctx->cword.encrypt.ksize = (key_len - 16) / 8; 137 ctx->cword.decrypt.ksize = ctx->cword.encrypt.ksize; 138 139 /* Don't generate extended keys if the hardware can do it. */ 140 if (!aes_hw_extkey_available(key_len)) { 141 ctx->D = ctx->d_data; 142 ctx->cword.encrypt.keygen = 1; 143 ctx->cword.decrypt.keygen = 1; 144 145 if (aes_expandkey(&gen_aes, in_key, key_len)) 146 return -EINVAL; 147 148 memcpy(ctx->E, gen_aes.key_enc, AES_MAX_KEYLENGTH); 149 memcpy(ctx->D, gen_aes.key_dec, AES_MAX_KEYLENGTH); 150 } 151 152 for_each_online_cpu(cpu) 153 if (&ctx->cword.encrypt == per_cpu(paes_last_cword, cpu) || 154 &ctx->cword.decrypt == per_cpu(paes_last_cword, cpu)) 155 per_cpu(paes_last_cword, cpu) = NULL; 156 157 return 0; 158 } 159 160 static int aes_set_key_skcipher(struct crypto_skcipher *tfm, const u8 *in_key, 161 unsigned int key_len) 162 { 163 return aes_set_key(crypto_skcipher_tfm(tfm), in_key, key_len); 164 } 165 166 /* ====== Encryption/decryption routines ====== */ 167 168 /* These are the real call to PadLock. */ 169 static inline void padlock_reset_key(struct cword *cword) 170 { 171 int cpu = raw_smp_processor_id(); 172 173 if (cword != per_cpu(paes_last_cword, cpu)) 174 #ifndef CONFIG_X86_64 175 asm volatile ("pushfl; popfl"); 176 #else 177 asm volatile ("pushfq; popfq"); 178 #endif 179 } 180 181 static inline void padlock_store_cword(struct cword *cword) 182 { 183 per_cpu(paes_last_cword, raw_smp_processor_id()) = cword; 184 } 185 186 /* 187 * While the padlock instructions don't use FP/SSE registers, they 188 * generate a spurious DNA fault when CR0.TS is '1'. Fortunately, 189 * the kernel doesn't use CR0.TS. 190 */ 191 192 static inline void rep_xcrypt_ecb(const u8 *input, u8 *output, void *key, 193 struct cword *control_word, int count) 194 { 195 asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */ 196 : "+S"(input), "+D"(output) 197 : "d"(control_word), "b"(key), "c"(count)); 198 } 199 200 static inline u8 *rep_xcrypt_cbc(const u8 *input, u8 *output, void *key, 201 u8 *iv, struct cword *control_word, int count) 202 { 203 asm volatile (".byte 0xf3,0x0f,0xa7,0xd0" /* rep xcryptcbc */ 204 : "+S" (input), "+D" (output), "+a" (iv) 205 : "d" (control_word), "b" (key), "c" (count)); 206 return iv; 207 } 208 209 static void ecb_crypt_copy(const u8 *in, u8 *out, u32 *key, 210 struct cword *cword, int count) 211 { 212 /* 213 * Padlock prefetches extra data so we must provide mapped input buffers. 214 * Assume there are at least 16 bytes of stack already in use. 215 */ 216 u8 buf[AES_BLOCK_SIZE * (MAX_ECB_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1]; 217 u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT); 218 219 memcpy(tmp, in, count * AES_BLOCK_SIZE); 220 rep_xcrypt_ecb(tmp, out, key, cword, count); 221 } 222 223 static u8 *cbc_crypt_copy(const u8 *in, u8 *out, u32 *key, 224 u8 *iv, struct cword *cword, int count) 225 { 226 /* 227 * Padlock prefetches extra data so we must provide mapped input buffers. 228 * Assume there are at least 16 bytes of stack already in use. 229 */ 230 u8 buf[AES_BLOCK_SIZE * (MAX_CBC_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1]; 231 u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT); 232 233 memcpy(tmp, in, count * AES_BLOCK_SIZE); 234 return rep_xcrypt_cbc(tmp, out, key, iv, cword, count); 235 } 236 237 static inline void ecb_crypt(const u8 *in, u8 *out, u32 *key, 238 struct cword *cword, int count) 239 { 240 /* Padlock in ECB mode fetches at least ecb_fetch_bytes of data. 241 * We could avoid some copying here but it's probably not worth it. 242 */ 243 if (unlikely(offset_in_page(in) + ecb_fetch_bytes > PAGE_SIZE)) { 244 ecb_crypt_copy(in, out, key, cword, count); 245 return; 246 } 247 248 rep_xcrypt_ecb(in, out, key, cword, count); 249 } 250 251 static inline u8 *cbc_crypt(const u8 *in, u8 *out, u32 *key, 252 u8 *iv, struct cword *cword, int count) 253 { 254 /* Padlock in CBC mode fetches at least cbc_fetch_bytes of data. */ 255 if (unlikely(offset_in_page(in) + cbc_fetch_bytes > PAGE_SIZE)) 256 return cbc_crypt_copy(in, out, key, iv, cword, count); 257 258 return rep_xcrypt_cbc(in, out, key, iv, cword, count); 259 } 260 261 static inline void padlock_xcrypt_ecb(const u8 *input, u8 *output, void *key, 262 void *control_word, u32 count) 263 { 264 u32 initial = count & (ecb_fetch_blocks - 1); 265 266 if (count < ecb_fetch_blocks) { 267 ecb_crypt(input, output, key, control_word, count); 268 return; 269 } 270 271 count -= initial; 272 273 if (initial) 274 asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */ 275 : "+S"(input), "+D"(output) 276 : "d"(control_word), "b"(key), "c"(initial)); 277 278 asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */ 279 : "+S"(input), "+D"(output) 280 : "d"(control_word), "b"(key), "c"(count)); 281 } 282 283 static inline u8 *padlock_xcrypt_cbc(const u8 *input, u8 *output, void *key, 284 u8 *iv, void *control_word, u32 count) 285 { 286 u32 initial = count & (cbc_fetch_blocks - 1); 287 288 if (count < cbc_fetch_blocks) 289 return cbc_crypt(input, output, key, iv, control_word, count); 290 291 count -= initial; 292 293 if (initial) 294 asm volatile (".byte 0xf3,0x0f,0xa7,0xd0" /* rep xcryptcbc */ 295 : "+S" (input), "+D" (output), "+a" (iv) 296 : "d" (control_word), "b" (key), "c" (initial)); 297 298 asm volatile (".byte 0xf3,0x0f,0xa7,0xd0" /* rep xcryptcbc */ 299 : "+S" (input), "+D" (output), "+a" (iv) 300 : "d" (control_word), "b" (key), "c" (count)); 301 return iv; 302 } 303 304 static void padlock_aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in) 305 { 306 struct aes_ctx *ctx = aes_ctx(tfm); 307 308 padlock_reset_key(&ctx->cword.encrypt); 309 ecb_crypt(in, out, ctx->E, &ctx->cword.encrypt, 1); 310 padlock_store_cword(&ctx->cword.encrypt); 311 } 312 313 static void padlock_aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in) 314 { 315 struct aes_ctx *ctx = aes_ctx(tfm); 316 317 padlock_reset_key(&ctx->cword.encrypt); 318 ecb_crypt(in, out, ctx->D, &ctx->cword.decrypt, 1); 319 padlock_store_cword(&ctx->cword.encrypt); 320 } 321 322 static struct crypto_alg aes_alg = { 323 .cra_name = "aes", 324 .cra_driver_name = "aes-padlock", 325 .cra_priority = PADLOCK_CRA_PRIORITY, 326 .cra_flags = CRYPTO_ALG_TYPE_CIPHER, 327 .cra_blocksize = AES_BLOCK_SIZE, 328 .cra_ctxsize = sizeof(struct aes_ctx), 329 .cra_alignmask = PADLOCK_ALIGNMENT - 1, 330 .cra_module = THIS_MODULE, 331 .cra_u = { 332 .cipher = { 333 .cia_min_keysize = AES_MIN_KEY_SIZE, 334 .cia_max_keysize = AES_MAX_KEY_SIZE, 335 .cia_setkey = aes_set_key, 336 .cia_encrypt = padlock_aes_encrypt, 337 .cia_decrypt = padlock_aes_decrypt, 338 } 339 } 340 }; 341 342 static int ecb_aes_encrypt(struct skcipher_request *req) 343 { 344 struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); 345 struct aes_ctx *ctx = skcipher_aes_ctx(tfm); 346 struct skcipher_walk walk; 347 unsigned int nbytes; 348 int err; 349 350 padlock_reset_key(&ctx->cword.encrypt); 351 352 err = skcipher_walk_virt(&walk, req, false); 353 354 while ((nbytes = walk.nbytes) != 0) { 355 padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr, 356 ctx->E, &ctx->cword.encrypt, 357 nbytes / AES_BLOCK_SIZE); 358 nbytes &= AES_BLOCK_SIZE - 1; 359 err = skcipher_walk_done(&walk, nbytes); 360 } 361 362 padlock_store_cword(&ctx->cword.encrypt); 363 364 return err; 365 } 366 367 static int ecb_aes_decrypt(struct skcipher_request *req) 368 { 369 struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); 370 struct aes_ctx *ctx = skcipher_aes_ctx(tfm); 371 struct skcipher_walk walk; 372 unsigned int nbytes; 373 int err; 374 375 padlock_reset_key(&ctx->cword.decrypt); 376 377 err = skcipher_walk_virt(&walk, req, false); 378 379 while ((nbytes = walk.nbytes) != 0) { 380 padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr, 381 ctx->D, &ctx->cword.decrypt, 382 nbytes / AES_BLOCK_SIZE); 383 nbytes &= AES_BLOCK_SIZE - 1; 384 err = skcipher_walk_done(&walk, nbytes); 385 } 386 387 padlock_store_cword(&ctx->cword.encrypt); 388 389 return err; 390 } 391 392 static struct skcipher_alg ecb_aes_alg = { 393 .base.cra_name = "ecb(aes)", 394 .base.cra_driver_name = "ecb-aes-padlock", 395 .base.cra_priority = PADLOCK_COMPOSITE_PRIORITY, 396 .base.cra_blocksize = AES_BLOCK_SIZE, 397 .base.cra_ctxsize = sizeof(struct aes_ctx), 398 .base.cra_alignmask = PADLOCK_ALIGNMENT - 1, 399 .base.cra_module = THIS_MODULE, 400 .min_keysize = AES_MIN_KEY_SIZE, 401 .max_keysize = AES_MAX_KEY_SIZE, 402 .setkey = aes_set_key_skcipher, 403 .encrypt = ecb_aes_encrypt, 404 .decrypt = ecb_aes_decrypt, 405 }; 406 407 static int cbc_aes_encrypt(struct skcipher_request *req) 408 { 409 struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); 410 struct aes_ctx *ctx = skcipher_aes_ctx(tfm); 411 struct skcipher_walk walk; 412 unsigned int nbytes; 413 int err; 414 415 padlock_reset_key(&ctx->cword.encrypt); 416 417 err = skcipher_walk_virt(&walk, req, false); 418 419 while ((nbytes = walk.nbytes) != 0) { 420 u8 *iv = padlock_xcrypt_cbc(walk.src.virt.addr, 421 walk.dst.virt.addr, ctx->E, 422 walk.iv, &ctx->cword.encrypt, 423 nbytes / AES_BLOCK_SIZE); 424 memcpy(walk.iv, iv, AES_BLOCK_SIZE); 425 nbytes &= AES_BLOCK_SIZE - 1; 426 err = skcipher_walk_done(&walk, nbytes); 427 } 428 429 padlock_store_cword(&ctx->cword.decrypt); 430 431 return err; 432 } 433 434 static int cbc_aes_decrypt(struct skcipher_request *req) 435 { 436 struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); 437 struct aes_ctx *ctx = skcipher_aes_ctx(tfm); 438 struct skcipher_walk walk; 439 unsigned int nbytes; 440 int err; 441 442 padlock_reset_key(&ctx->cword.encrypt); 443 444 err = skcipher_walk_virt(&walk, req, false); 445 446 while ((nbytes = walk.nbytes) != 0) { 447 padlock_xcrypt_cbc(walk.src.virt.addr, walk.dst.virt.addr, 448 ctx->D, walk.iv, &ctx->cword.decrypt, 449 nbytes / AES_BLOCK_SIZE); 450 nbytes &= AES_BLOCK_SIZE - 1; 451 err = skcipher_walk_done(&walk, nbytes); 452 } 453 454 padlock_store_cword(&ctx->cword.encrypt); 455 456 return err; 457 } 458 459 static struct skcipher_alg cbc_aes_alg = { 460 .base.cra_name = "cbc(aes)", 461 .base.cra_driver_name = "cbc-aes-padlock", 462 .base.cra_priority = PADLOCK_COMPOSITE_PRIORITY, 463 .base.cra_blocksize = AES_BLOCK_SIZE, 464 .base.cra_ctxsize = sizeof(struct aes_ctx), 465 .base.cra_alignmask = PADLOCK_ALIGNMENT - 1, 466 .base.cra_module = THIS_MODULE, 467 .min_keysize = AES_MIN_KEY_SIZE, 468 .max_keysize = AES_MAX_KEY_SIZE, 469 .ivsize = AES_BLOCK_SIZE, 470 .setkey = aes_set_key_skcipher, 471 .encrypt = cbc_aes_encrypt, 472 .decrypt = cbc_aes_decrypt, 473 }; 474 475 static const struct x86_cpu_id padlock_cpu_id[] = { 476 X86_MATCH_FEATURE(X86_FEATURE_XCRYPT, NULL), 477 {} 478 }; 479 MODULE_DEVICE_TABLE(x86cpu, padlock_cpu_id); 480 481 static int __init padlock_init(void) 482 { 483 int ret; 484 struct cpuinfo_x86 *c = &cpu_data(0); 485 486 if (!x86_match_cpu(padlock_cpu_id)) 487 return -ENODEV; 488 489 if (!boot_cpu_has(X86_FEATURE_XCRYPT_EN)) { 490 printk(KERN_NOTICE PFX "VIA PadLock detected, but not enabled. Hmm, strange...\n"); 491 return -ENODEV; 492 } 493 494 if ((ret = crypto_register_alg(&aes_alg)) != 0) 495 goto aes_err; 496 497 if ((ret = crypto_register_skcipher(&ecb_aes_alg)) != 0) 498 goto ecb_aes_err; 499 500 if ((ret = crypto_register_skcipher(&cbc_aes_alg)) != 0) 501 goto cbc_aes_err; 502 503 printk(KERN_NOTICE PFX "Using VIA PadLock ACE for AES algorithm.\n"); 504 505 if (c->x86 == 6 && c->x86_model == 15 && c->x86_stepping == 2) { 506 ecb_fetch_blocks = MAX_ECB_FETCH_BLOCKS; 507 cbc_fetch_blocks = MAX_CBC_FETCH_BLOCKS; 508 printk(KERN_NOTICE PFX "VIA Nano stepping 2 detected: enabling workaround.\n"); 509 } 510 511 out: 512 return ret; 513 514 cbc_aes_err: 515 crypto_unregister_skcipher(&ecb_aes_alg); 516 ecb_aes_err: 517 crypto_unregister_alg(&aes_alg); 518 aes_err: 519 printk(KERN_ERR PFX "VIA PadLock AES initialization failed.\n"); 520 goto out; 521 } 522 523 static void __exit padlock_fini(void) 524 { 525 crypto_unregister_skcipher(&cbc_aes_alg); 526 crypto_unregister_skcipher(&ecb_aes_alg); 527 crypto_unregister_alg(&aes_alg); 528 } 529 530 module_init(padlock_init); 531 module_exit(padlock_fini); 532 533 MODULE_DESCRIPTION("VIA PadLock AES algorithm support"); 534 MODULE_LICENSE("GPL"); 535 MODULE_AUTHOR("Michal Ludvig"); 536 537 MODULE_ALIAS_CRYPTO("aes"); 538