1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/pci.h>
4 #include <linux/vmalloc.h>
5
6 #include <drm/drm_atomic.h>
7 #include <drm/drm_atomic_helper.h>
8 #include <drm/drm_drv.h>
9 #include <drm/drm_gem_atomic_helper.h>
10 #include <drm/drm_probe_helper.h>
11
12 #include "mgag200_drv.h"
13
mgag200_g200_init_pci_options(struct pci_dev * pdev)14 static int mgag200_g200_init_pci_options(struct pci_dev *pdev)
15 {
16 struct device *dev = &pdev->dev;
17 bool has_sgram;
18 u32 option;
19 int err;
20
21 err = pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
22 if (err != PCIBIOS_SUCCESSFUL) {
23 dev_err(dev, "pci_read_config_dword(PCI_MGA_OPTION) failed: %d\n", err);
24 return pcibios_err_to_errno(err);
25 }
26
27 has_sgram = !!(option & PCI_MGA_OPTION_HARDPWMSK);
28
29 if (has_sgram)
30 option = 0x4049cd21;
31 else
32 option = 0x40499121;
33
34 return mgag200_init_pci_options(pdev, option, 0x00008000);
35 }
36
mgag200_g200_init_registers(struct mgag200_g200_device * g200)37 static void mgag200_g200_init_registers(struct mgag200_g200_device *g200)
38 {
39 static const u8 dacvalue[] = {
40 MGAG200_DAC_DEFAULT(0x00, 0xc9, 0x1f,
41 0x04, 0x2d, 0x19)
42 };
43
44 struct mga_device *mdev = &g200->base;
45 size_t i;
46
47 for (i = 0; i < ARRAY_SIZE(dacvalue); ++i) {
48 if ((i <= 0x17) ||
49 (i == 0x1b) ||
50 (i == 0x1c) ||
51 ((i >= 0x1f) && (i <= 0x29)) ||
52 ((i >= 0x30) && (i <= 0x37)))
53 continue;
54 WREG_DAC(i, dacvalue[i]);
55 }
56
57 mgag200_init_registers(mdev);
58 }
59
60 /*
61 * PIXPLLC
62 */
63
mgag200_g200_pixpllc_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * new_state)64 static int mgag200_g200_pixpllc_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state)
65 {
66 static const int post_div_max = 7;
67 static const int in_div_min = 1;
68 static const int in_div_max = 6;
69 static const int feed_div_min = 7;
70 static const int feed_div_max = 127;
71
72 struct drm_device *dev = crtc->dev;
73 struct mgag200_g200_device *g200 = to_mgag200_g200_device(dev);
74 struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(new_state, crtc);
75 struct mgag200_crtc_state *new_mgag200_crtc_state = to_mgag200_crtc_state(new_crtc_state);
76 long clock = new_crtc_state->mode.clock;
77 struct mgag200_pll_values *pixpllc = &new_mgag200_crtc_state->pixpllc;
78 u8 testp, testm, testn;
79 u8 n = 0, m = 0, p, s;
80 long f_vco;
81 long computed;
82 long delta, tmp_delta;
83 long ref_clk = g200->ref_clk;
84 long p_clk_min = g200->pclk_min;
85 long p_clk_max = g200->pclk_max;
86
87 if (clock > p_clk_max) {
88 drm_err(dev, "Pixel Clock %ld too high\n", clock);
89 return -EINVAL;
90 }
91
92 if (clock < p_clk_min >> 3)
93 clock = p_clk_min >> 3;
94
95 f_vco = clock;
96 for (testp = 0;
97 testp <= post_div_max && f_vco < p_clk_min;
98 testp = (testp << 1) + 1, f_vco <<= 1)
99 ;
100 p = testp + 1;
101
102 delta = clock;
103
104 for (testm = in_div_min; testm <= in_div_max; testm++) {
105 for (testn = feed_div_min; testn <= feed_div_max; testn++) {
106 computed = ref_clk * (testn + 1) / (testm + 1);
107 if (computed < f_vco)
108 tmp_delta = f_vco - computed;
109 else
110 tmp_delta = computed - f_vco;
111 if (tmp_delta < delta) {
112 delta = tmp_delta;
113 m = testm + 1;
114 n = testn + 1;
115 }
116 }
117 }
118 f_vco = ref_clk * n / m;
119 if (f_vco < 100000)
120 s = 0;
121 else if (f_vco < 140000)
122 s = 1;
123 else if (f_vco < 180000)
124 s = 2;
125 else
126 s = 3;
127
128 drm_dbg_kms(dev, "clock: %ld vco: %ld m: %d n: %d p: %d s: %d\n",
129 clock, f_vco, m, n, p, s);
130
131 pixpllc->m = m;
132 pixpllc->n = n;
133 pixpllc->p = p;
134 pixpllc->s = s;
135
136 return 0;
137 }
138
mgag200_g200_pixpllc_atomic_update(struct drm_crtc * crtc,struct drm_atomic_state * old_state)139 static void mgag200_g200_pixpllc_atomic_update(struct drm_crtc *crtc,
140 struct drm_atomic_state *old_state)
141 {
142 struct drm_device *dev = crtc->dev;
143 struct mga_device *mdev = to_mga_device(dev);
144 struct drm_crtc_state *crtc_state = crtc->state;
145 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);
146 struct mgag200_pll_values *pixpllc = &mgag200_crtc_state->pixpllc;
147 unsigned int pixpllcm, pixpllcn, pixpllcp, pixpllcs;
148 u8 xpixpllcm, xpixpllcn, xpixpllcp;
149
150 pixpllcm = pixpllc->m - 1;
151 pixpllcn = pixpllc->n - 1;
152 pixpllcp = pixpllc->p - 1;
153 pixpllcs = pixpllc->s;
154
155 xpixpllcm = pixpllcm;
156 xpixpllcn = pixpllcn;
157 xpixpllcp = (pixpllcs << 3) | pixpllcp;
158
159 WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
160
161 WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm);
162 WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn);
163 WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp);
164 }
165
166 /*
167 * Mode-setting pipeline
168 */
169
170 static const struct drm_plane_helper_funcs mgag200_g200_primary_plane_helper_funcs = {
171 MGAG200_PRIMARY_PLANE_HELPER_FUNCS,
172 };
173
174 static const struct drm_plane_funcs mgag200_g200_primary_plane_funcs = {
175 MGAG200_PRIMARY_PLANE_FUNCS,
176 };
177
178 static const struct drm_crtc_helper_funcs mgag200_g200_crtc_helper_funcs = {
179 MGAG200_CRTC_HELPER_FUNCS,
180 };
181
182 static const struct drm_crtc_funcs mgag200_g200_crtc_funcs = {
183 MGAG200_CRTC_FUNCS,
184 };
185
mgag200_g200_pipeline_init(struct mga_device * mdev)186 static int mgag200_g200_pipeline_init(struct mga_device *mdev)
187 {
188 struct drm_device *dev = &mdev->base;
189 struct drm_plane *primary_plane = &mdev->primary_plane;
190 struct drm_crtc *crtc = &mdev->crtc;
191 int ret;
192
193 ret = drm_universal_plane_init(dev, primary_plane, 0,
194 &mgag200_g200_primary_plane_funcs,
195 mgag200_primary_plane_formats,
196 mgag200_primary_plane_formats_size,
197 mgag200_primary_plane_fmtmods,
198 DRM_PLANE_TYPE_PRIMARY, NULL);
199 if (ret) {
200 drm_err(dev, "drm_universal_plane_init() failed: %d\n", ret);
201 return ret;
202 }
203 drm_plane_helper_add(primary_plane, &mgag200_g200_primary_plane_helper_funcs);
204 drm_plane_enable_fb_damage_clips(primary_plane);
205
206 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL,
207 &mgag200_g200_crtc_funcs, NULL);
208 if (ret) {
209 drm_err(dev, "drm_crtc_init_with_planes() failed: %d\n", ret);
210 return ret;
211 }
212 drm_crtc_helper_add(crtc, &mgag200_g200_crtc_helper_funcs);
213
214 /* FIXME: legacy gamma tables, but atomic gamma doesn't work without */
215 drm_mode_crtc_set_gamma_size(crtc, MGAG200_LUT_SIZE);
216 drm_crtc_enable_color_mgmt(crtc, 0, false, MGAG200_LUT_SIZE);
217
218 ret = mgag200_vga_output_init(mdev);
219 if (ret)
220 return ret;
221
222 return 0;
223 }
224
225 /*
226 * DRM Device
227 */
228
229 static const struct mgag200_device_info mgag200_g200_device_info =
230 MGAG200_DEVICE_INFO_INIT(2048, 2048, 0, false, 1, 3, false);
231
mgag200_g200_interpret_bios(struct mgag200_g200_device * g200,const unsigned char * bios,size_t size)232 static void mgag200_g200_interpret_bios(struct mgag200_g200_device *g200,
233 const unsigned char *bios, size_t size)
234 {
235 static const char matrox[] = {'M', 'A', 'T', 'R', 'O', 'X'};
236 static const unsigned int expected_length[6] = {
237 0, 64, 64, 64, 128, 128
238 };
239 struct mga_device *mdev = &g200->base;
240 struct drm_device *dev = &mdev->base;
241 const unsigned char *pins;
242 unsigned int pins_len, version;
243 int offset;
244 int tmp;
245
246 /* Test for MATROX string. */
247 if (size < 45 + sizeof(matrox))
248 return;
249 if (memcmp(&bios[45], matrox, sizeof(matrox)) != 0)
250 return;
251
252 /* Get the PInS offset. */
253 if (size < MGA_BIOS_OFFSET + 2)
254 return;
255 offset = (bios[MGA_BIOS_OFFSET + 1] << 8) | bios[MGA_BIOS_OFFSET];
256
257 /* Get PInS data structure. */
258
259 if (size < offset + 6)
260 return;
261 pins = bios + offset;
262 if (pins[0] == 0x2e && pins[1] == 0x41) {
263 version = pins[5];
264 pins_len = pins[2];
265 } else {
266 version = 1;
267 pins_len = pins[0] + (pins[1] << 8);
268 }
269
270 if (version < 1 || version > 5) {
271 drm_warn(dev, "Unknown BIOS PInS version: %d\n", version);
272 return;
273 }
274 if (pins_len != expected_length[version]) {
275 drm_warn(dev, "Unexpected BIOS PInS size: %d expected: %d\n",
276 pins_len, expected_length[version]);
277 return;
278 }
279 if (size < offset + pins_len)
280 return;
281
282 drm_dbg_kms(dev, "MATROX BIOS PInS version %d size: %d found\n", version, pins_len);
283
284 /* Extract the clock values */
285
286 switch (version) {
287 case 1:
288 tmp = pins[24] + (pins[25] << 8);
289 if (tmp)
290 g200->pclk_max = tmp * 10;
291 break;
292 case 2:
293 if (pins[41] != 0xff)
294 g200->pclk_max = (pins[41] + 100) * 1000;
295 break;
296 case 3:
297 if (pins[36] != 0xff)
298 g200->pclk_max = (pins[36] + 100) * 1000;
299 if (pins[52] & 0x20)
300 g200->ref_clk = 14318;
301 break;
302 case 4:
303 if (pins[39] != 0xff)
304 g200->pclk_max = pins[39] * 4 * 1000;
305 if (pins[92] & 0x01)
306 g200->ref_clk = 14318;
307 break;
308 case 5:
309 tmp = pins[4] ? 8000 : 6000;
310 if (pins[123] != 0xff)
311 g200->pclk_min = pins[123] * tmp;
312 if (pins[38] != 0xff)
313 g200->pclk_max = pins[38] * tmp;
314 if (pins[110] & 0x01)
315 g200->ref_clk = 14318;
316 break;
317 default:
318 break;
319 }
320 }
321
mgag200_g200_init_refclk(struct mgag200_g200_device * g200)322 static void mgag200_g200_init_refclk(struct mgag200_g200_device *g200)
323 {
324 struct mga_device *mdev = &g200->base;
325 struct drm_device *dev = &mdev->base;
326 struct pci_dev *pdev = to_pci_dev(dev->dev);
327 unsigned char __iomem *rom;
328 unsigned char *bios;
329 size_t size;
330
331 g200->pclk_min = 50000;
332 g200->pclk_max = 230000;
333 g200->ref_clk = 27050;
334
335 rom = pci_map_rom(pdev, &size);
336 if (!rom)
337 return;
338
339 bios = vmalloc(size);
340 if (!bios)
341 goto out;
342 memcpy_fromio(bios, rom, size);
343
344 if (size != 0 && bios[0] == 0x55 && bios[1] == 0xaa)
345 mgag200_g200_interpret_bios(g200, bios, size);
346
347 drm_dbg_kms(dev, "pclk_min: %ld pclk_max: %ld ref_clk: %ld\n",
348 g200->pclk_min, g200->pclk_max, g200->ref_clk);
349
350 vfree(bios);
351 out:
352 pci_unmap_rom(pdev, rom);
353 }
354
355 static const struct mgag200_device_funcs mgag200_g200_device_funcs = {
356 .pixpllc_atomic_check = mgag200_g200_pixpllc_atomic_check,
357 .pixpllc_atomic_update = mgag200_g200_pixpllc_atomic_update,
358 };
359
mgag200_g200_device_create(struct pci_dev * pdev,const struct drm_driver * drv)360 struct mga_device *mgag200_g200_device_create(struct pci_dev *pdev, const struct drm_driver *drv)
361 {
362 struct mgag200_g200_device *g200;
363 struct mga_device *mdev;
364 struct drm_device *dev;
365 resource_size_t vram_available;
366 int ret;
367
368 g200 = devm_drm_dev_alloc(&pdev->dev, drv, struct mgag200_g200_device, base.base);
369 if (IS_ERR(g200))
370 return ERR_CAST(g200);
371 mdev = &g200->base;
372 dev = &mdev->base;
373
374 pci_set_drvdata(pdev, dev);
375
376 ret = mgag200_g200_init_pci_options(pdev);
377 if (ret)
378 return ERR_PTR(ret);
379
380 ret = mgag200_device_preinit(mdev);
381 if (ret)
382 return ERR_PTR(ret);
383
384 mgag200_g200_init_refclk(g200);
385
386 ret = mgag200_device_init(mdev, &mgag200_g200_device_info,
387 &mgag200_g200_device_funcs);
388 if (ret)
389 return ERR_PTR(ret);
390
391 mgag200_g200_init_registers(g200);
392
393 vram_available = mgag200_device_probe_vram(mdev);
394
395 ret = mgag200_mode_config_init(mdev, vram_available);
396 if (ret)
397 return ERR_PTR(ret);
398
399 ret = mgag200_g200_pipeline_init(mdev);
400 if (ret)
401 return ERR_PTR(ret);
402
403 drm_mode_config_reset(dev);
404 drm_kms_helper_poll_init(dev);
405
406 return mdev;
407 }
408