1 /*- 2 * Copyright 2000-2020 Broadcom Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. Neither the name of the author nor the names of any co-contributors 13 * may be used to endorse or promote products derived from this software 14 * without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD 29 */ 30 31 /* 32 * Copyright 2000-2020 Broadcom Inc. All rights reserved. 33 * 34 * 35 * Name: mpi2_ioc.h 36 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 37 * Creation Date: October 11, 2006 38 * 39 * mpi2_ioc.h Version: 02.00.36 40 * 41 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 42 * prefix are for use only on MPI v2.5 products, and must not be used 43 * with MPI v2.0 products. Unless otherwise noted, names beginning with 44 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 45 * 46 * Version History 47 * --------------- 48 * 49 * Date Version Description 50 * -------- -------- ------------------------------------------------------ 51 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 52 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to 53 * MaxTargets. 54 * Added TotalImageSize field to FWDownload Request. 55 * Added reserved words to FWUpload Request. 56 * 06-26-07 02.00.02 Added IR Configuration Change List Event. 57 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit 58 * request and replaced it with 59 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. 60 * Replaced the MinReplyQueueDepth field of the IOCFacts 61 * reply with MaxReplyDescriptorPostQueueDepth. 62 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum 63 * depth for the Reply Descriptor Post Queue. 64 * Added SASAddress field to Initiator Device Table 65 * Overflow Event data. 66 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING 67 * for SAS Initiator Device Status Change Event data. 68 * Modified Reason Code defines for SAS Topology Change 69 * List Event data, including adding a bit for PHY Vacant 70 * status, and adding a mask for the Reason Code. 71 * Added define for 72 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. 73 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. 74 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of 75 * the IOCFacts Reply. 76 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 77 * Moved MPI2_VERSION_UNION to mpi2.h. 78 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks 79 * instead of enables, and added SASBroadcastPrimitiveMasks 80 * field. 81 * Added Log Entry Added Event and related structure. 82 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. 83 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. 84 * Added MaxVolumes and MaxPersistentEntries fields to 85 * IOCFacts reply. 86 * Added ProtocalFlags and IOCCapabilities fields to 87 * MPI2_FW_IMAGE_HEADER. 88 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. 89 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to 90 * a U16 (from a U32). 91 * Removed extra 's' from EventMasks name. 92 * 06-27-08 02.00.08 Fixed an offset in a comment. 93 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. 94 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and 95 * renamed MinReplyFrameSize to ReplyFrameSize. 96 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. 97 * Added two new RAIDOperation values for Integrated RAID 98 * Operations Status Event data. 99 * Added four new IR Configuration Change List Event data 100 * ReasonCode values. 101 * Added two new ReasonCode defines for SAS Device Status 102 * Change Event data. 103 * Added three new DiscoveryStatus bits for the SAS 104 * Discovery event data. 105 * Added Multiplexing Status Change bit to the PhyStatus 106 * field of the SAS Topology Change List event data. 107 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. 108 * BootFlags are now product-specific. 109 * Added defines for the indivdual signature bytes 110 * for MPI2_INIT_IMAGE_FOOTER. 111 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. 112 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR 113 * define. 114 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE 115 * define. 116 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. 117 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define. 118 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define. 119 * Added two new reason codes for SAS Device Status Change 120 * Event. 121 * Added new event: SAS PHY Counter. 122 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure. 123 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 124 * Added new product id family for 2208. 125 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST. 126 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY. 127 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY. 128 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY. 129 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define. 130 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define. 131 * Added Host Based Discovery Phy Event data. 132 * Added defines for ProductID Product field 133 * (MPI2_FW_HEADER_PID_). 134 * Modified values for SAS ProductID Family 135 * (MPI2_FW_HEADER_PID_FAMILY_). 136 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines. 137 * Added PowerManagementControl Request structures and 138 * defines. 139 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete. 140 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define. 141 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC. 142 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added 143 * SASNotifyPrimitiveMasks field to 144 * MPI2_EVENT_NOTIFICATION_REQUEST. 145 * Added Temperature Threshold Event. 146 * Added Host Message Event. 147 * Added Send Host Message request and reply. 148 * 05-25-11 02.00.18 For Extended Image Header, added 149 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and 150 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines. 151 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define. 152 * 08-24-11 02.00.19 Added PhysicalPort field to 153 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure. 154 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete. 155 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5. 156 * 03-29-12 02.00.21 Added a product specific range to event values. 157 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE. 158 * Added ElapsedSeconds field to 159 * MPI2_EVENT_DATA_IR_OPERATION_STATUS. 160 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE 161 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY. 162 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE. 163 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY. 164 * Added Encrypted Hash Extended Image. 165 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS. 166 * 11-18-14 02.00.25 Updated copyright information. 167 * 03-16-15 02.00.26 Updated for MPI v2.6. 168 * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and 169 * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT. 170 * Added MPI2_EVENT_PCIE_LINK_COUNTER and 171 * MPI26_EVENT_DATA_PCIE_LINK_COUNTER. 172 * Added MPI26_CTRL_OP_SHUTDOWN. 173 * Added MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG 174 * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and 175 * MPI26_FW_HEADER_PID_FAMILY_3516_SAS. 176 * 08-25-15 02.00.27 Added IC ARCH Class based signature defines. 177 * Added MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED event. 178 * Added ConigurationFlags field to IOCInit message to 179 * support NVMe SGL format control. 180 * Added PCIe SRIOV support. 181 * 02-17-16 02.00.28 Added SAS 4 22.5 gbs speed support. 182 * Added PCIe 4 16.0 GT/sec speec support. 183 * Removed AHCI support. 184 * Removed SOP support. 185 * 07-01-16 02.00.29 Added Archclass for 4008 product. 186 * Added IOCException MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED 187 * 08-23-16 02.00.30 Added new defines for the ImageType field of FWDownload 188 * Request Message. 189 * Added new defines for the ImageType field of FWUpload 190 * Request Message. 191 * Added new values for the RegionType field in the Layout 192 * Data sections of the FLASH Layout Extended Image Data. 193 * Added new defines for the ReasonCode field of 194 * Active Cable Exception Event. 195 * Added MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE and 196 * MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE. 197 * 11-23-16 02.00.31 Added MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR and 198 * MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR. 199 * 02-02-17 02.00.32 Added MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP. 200 * Added MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT and related 201 * defines for the ReasonCode field. 202 * 06-13-17 02.00.33 Added MPI2_FW_DOWNLOAD_ITYPE_CPLD. 203 * 09-29-17 02.00.34 Added MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED 204 * to the ReasonCode field in PCIe Device Status Change 205 * Event Data. 206 * 07-22-18 02.00.35 Added FW_DOWNLOAD_ITYPE_CPLD and _PSOC. 207 * Moved FW image definitions ionto new mpi2_image,h 208 * 08-14-18 02.00.36 Fixed definition of MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16) 209 * -------------------------------------------------------------------------- 210 */ 211 212 #ifndef MPI2_IOC_H 213 #define MPI2_IOC_H 214 215 /***************************************************************************** 216 * 217 * IOC Messages 218 * 219 *****************************************************************************/ 220 221 /**************************************************************************** 222 * IOCInit message 223 ****************************************************************************/ 224 225 /* IOCInit Request message */ 226 typedef struct _MPI2_IOC_INIT_REQUEST 227 { 228 U8 WhoInit; /* 0x00 */ 229 U8 Reserved1; /* 0x01 */ 230 U8 ChainOffset; /* 0x02 */ 231 U8 Function; /* 0x03 */ 232 U16 Reserved2; /* 0x04 */ 233 U8 Reserved3; /* 0x06 */ 234 U8 MsgFlags; /* 0x07 */ 235 U8 VP_ID; /* 0x08 */ 236 U8 VF_ID; /* 0x09 */ 237 U16 Reserved4; /* 0x0A */ 238 U16 MsgVersion; /* 0x0C */ 239 U16 HeaderVersion; /* 0x0E */ 240 U32 Reserved5; /* 0x10 */ 241 U16 ConfigurationFlags; /* 0x14 */ 242 U8 HostPageSize; /* 0x16 */ 243 U8 HostMSIxVectors; /* 0x17 */ 244 U16 Reserved8; /* 0x18 */ 245 U16 SystemRequestFrameSize; /* 0x1A */ 246 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 247 U16 ReplyFreeQueueDepth; /* 0x1E */ 248 U32 SenseBufferAddressHigh; /* 0x20 */ 249 U32 SystemReplyAddressHigh; /* 0x24 */ 250 U64 SystemRequestFrameBaseAddress; /* 0x28 */ 251 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 252 U64 ReplyFreeQueueAddress; /* 0x38 */ 253 U64 TimeStamp; /* 0x40 */ 254 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 255 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 256 257 /* WhoInit values */ 258 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 259 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 260 #define MPI2_WHOINIT_ROM_BIOS (0x02) 261 #define MPI2_WHOINIT_PCI_PEER (0x03) 262 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 263 #define MPI2_WHOINIT_MANUFACTURER (0x05) 264 265 /* MsgFlags */ 266 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) 267 268 /* MsgVersion */ 269 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 270 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 271 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 272 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 273 274 /* HeaderVersion */ 275 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00) 276 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8) 277 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) 278 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) 279 280 /* ConfigurationFlags */ 281 #define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT (0x0001) 282 283 /* minimum depth for a Reply Descriptor Post Queue */ 284 #define MPI2_RDPQ_DEPTH_MIN (16) 285 286 /* Reply Descriptor Post Queue Array Entry */ 287 typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY 288 { 289 U64 RDPQBaseAddress; /* 0x00 */ 290 U32 Reserved1; /* 0x08 */ 291 U32 Reserved2; /* 0x0C */ 292 } MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, 293 MPI2_POINTER PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, 294 Mpi2IOCInitRDPQArrayEntry, MPI2_POINTER pMpi2IOCInitRDPQArrayEntry; 295 296 /* IOCInit Reply message */ 297 typedef struct _MPI2_IOC_INIT_REPLY 298 { 299 U8 WhoInit; /* 0x00 */ 300 U8 Reserved1; /* 0x01 */ 301 U8 MsgLength; /* 0x02 */ 302 U8 Function; /* 0x03 */ 303 U16 Reserved2; /* 0x04 */ 304 U8 Reserved3; /* 0x06 */ 305 U8 MsgFlags; /* 0x07 */ 306 U8 VP_ID; /* 0x08 */ 307 U8 VF_ID; /* 0x09 */ 308 U16 Reserved4; /* 0x0A */ 309 U16 Reserved5; /* 0x0C */ 310 U16 IOCStatus; /* 0x0E */ 311 U32 IOCLogInfo; /* 0x10 */ 312 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY, 313 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t; 314 315 /**************************************************************************** 316 * IOCFacts message 317 ****************************************************************************/ 318 319 /* IOCFacts Request message */ 320 typedef struct _MPI2_IOC_FACTS_REQUEST 321 { 322 U16 Reserved1; /* 0x00 */ 323 U8 ChainOffset; /* 0x02 */ 324 U8 Function; /* 0x03 */ 325 U16 Reserved2; /* 0x04 */ 326 U8 Reserved3; /* 0x06 */ 327 U8 MsgFlags; /* 0x07 */ 328 U8 VP_ID; /* 0x08 */ 329 U8 VF_ID; /* 0x09 */ 330 U16 Reserved4; /* 0x0A */ 331 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST, 332 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t; 333 334 /* IOCFacts Reply message */ 335 typedef struct _MPI2_IOC_FACTS_REPLY 336 { 337 U16 MsgVersion; /* 0x00 */ 338 U8 MsgLength; /* 0x02 */ 339 U8 Function; /* 0x03 */ 340 U16 HeaderVersion; /* 0x04 */ 341 U8 IOCNumber; /* 0x06 */ 342 U8 MsgFlags; /* 0x07 */ 343 U8 VP_ID; /* 0x08 */ 344 U8 VF_ID; /* 0x09 */ 345 U16 Reserved1; /* 0x0A */ 346 U16 IOCExceptions; /* 0x0C */ 347 U16 IOCStatus; /* 0x0E */ 348 U32 IOCLogInfo; /* 0x10 */ 349 U8 MaxChainDepth; /* 0x14 */ 350 U8 WhoInit; /* 0x15 */ 351 U8 NumberOfPorts; /* 0x16 */ 352 U8 MaxMSIxVectors; /* 0x17 */ 353 U16 RequestCredit; /* 0x18 */ 354 U16 ProductID; /* 0x1A */ 355 U32 IOCCapabilities; /* 0x1C */ 356 MPI2_VERSION_UNION FWVersion; /* 0x20 */ 357 U16 IOCRequestFrameSize; /* 0x24 */ 358 U16 IOCMaxChainSegmentSize; /* 0x26 */ /* MPI 2.5 only; Reserved in MPI 2.0 */ 359 U16 MaxInitiators; /* 0x28 */ 360 U16 MaxTargets; /* 0x2A */ 361 U16 MaxSasExpanders; /* 0x2C */ 362 U16 MaxEnclosures; /* 0x2E */ 363 U16 ProtocolFlags; /* 0x30 */ 364 U16 HighPriorityCredit; /* 0x32 */ 365 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */ 366 U8 ReplyFrameSize; /* 0x36 */ 367 U8 MaxVolumes; /* 0x37 */ 368 U16 MaxDevHandle; /* 0x38 */ 369 U16 MaxPersistentEntries; /* 0x3A */ 370 U16 MinDevHandle; /* 0x3C */ 371 U8 CurrentHostPageSize; /* 0x3E */ 372 U8 Reserved4; /* 0x3F */ 373 U8 SGEModifierMask; /* 0x40 */ 374 U8 SGEModifierValue; /* 0x41 */ 375 U8 SGEModifierShift; /* 0x42 */ 376 U8 Reserved5; /* 0x43 */ 377 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY, 378 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t; 379 380 /* MsgVersion */ 381 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 382 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 383 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 384 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 385 386 /* HeaderVersion */ 387 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 388 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 389 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 390 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 391 392 /* IOCExceptions */ 393 #define MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0400) 394 #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200) 395 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) 396 397 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0) 398 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000) 399 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020) 400 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040) 401 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060) 402 403 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 404 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008) 405 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 406 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 407 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 408 409 /* defines for WhoInit field are after the IOCInit Request */ 410 411 /* ProductID field uses MPI2_FW_HEADER_PID_ */ 412 413 /* IOCCapabilities */ 414 #define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV (0x00100000) 415 #define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ (0x00080000) 416 #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000) 417 #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000) 418 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000) 419 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000) 420 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000) 421 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000) 422 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000) 423 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800) 424 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 425 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) 426 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) 427 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 428 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 429 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 430 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) 431 432 /* ProtocolFlags */ 433 #define MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES (0x0008) /* MPI v2.6 and later */ 434 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 435 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 436 437 /**************************************************************************** 438 * PortFacts message 439 ****************************************************************************/ 440 441 /* PortFacts Request message */ 442 typedef struct _MPI2_PORT_FACTS_REQUEST 443 { 444 U16 Reserved1; /* 0x00 */ 445 U8 ChainOffset; /* 0x02 */ 446 U8 Function; /* 0x03 */ 447 U16 Reserved2; /* 0x04 */ 448 U8 PortNumber; /* 0x06 */ 449 U8 MsgFlags; /* 0x07 */ 450 U8 VP_ID; /* 0x08 */ 451 U8 VF_ID; /* 0x09 */ 452 U16 Reserved3; /* 0x0A */ 453 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST, 454 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t; 455 456 /* PortFacts Reply message */ 457 typedef struct _MPI2_PORT_FACTS_REPLY 458 { 459 U16 Reserved1; /* 0x00 */ 460 U8 MsgLength; /* 0x02 */ 461 U8 Function; /* 0x03 */ 462 U16 Reserved2; /* 0x04 */ 463 U8 PortNumber; /* 0x06 */ 464 U8 MsgFlags; /* 0x07 */ 465 U8 VP_ID; /* 0x08 */ 466 U8 VF_ID; /* 0x09 */ 467 U16 Reserved3; /* 0x0A */ 468 U16 Reserved4; /* 0x0C */ 469 U16 IOCStatus; /* 0x0E */ 470 U32 IOCLogInfo; /* 0x10 */ 471 U8 Reserved5; /* 0x14 */ 472 U8 PortType; /* 0x15 */ 473 U16 Reserved6; /* 0x16 */ 474 U16 MaxPostedCmdBuffers; /* 0x18 */ 475 U16 Reserved7; /* 0x1A */ 476 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY, 477 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t; 478 479 /* PortType values */ 480 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00) 481 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10) 482 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) 483 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 484 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 485 #define MPI2_PORTFACTS_PORTTYPE_TRI_MODE (0x40) /* MPI v2.6 and later */ 486 487 /**************************************************************************** 488 * PortEnable message 489 ****************************************************************************/ 490 491 /* PortEnable Request message */ 492 typedef struct _MPI2_PORT_ENABLE_REQUEST 493 { 494 U16 Reserved1; /* 0x00 */ 495 U8 ChainOffset; /* 0x02 */ 496 U8 Function; /* 0x03 */ 497 U8 Reserved2; /* 0x04 */ 498 U8 PortFlags; /* 0x05 */ 499 U8 Reserved3; /* 0x06 */ 500 U8 MsgFlags; /* 0x07 */ 501 U8 VP_ID; /* 0x08 */ 502 U8 VF_ID; /* 0x09 */ 503 U16 Reserved4; /* 0x0A */ 504 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST, 505 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t; 506 507 /* PortEnable Reply message */ 508 typedef struct _MPI2_PORT_ENABLE_REPLY 509 { 510 U16 Reserved1; /* 0x00 */ 511 U8 MsgLength; /* 0x02 */ 512 U8 Function; /* 0x03 */ 513 U8 Reserved2; /* 0x04 */ 514 U8 PortFlags; /* 0x05 */ 515 U8 Reserved3; /* 0x06 */ 516 U8 MsgFlags; /* 0x07 */ 517 U8 VP_ID; /* 0x08 */ 518 U8 VF_ID; /* 0x09 */ 519 U16 Reserved4; /* 0x0A */ 520 U16 Reserved5; /* 0x0C */ 521 U16 IOCStatus; /* 0x0E */ 522 U32 IOCLogInfo; /* 0x10 */ 523 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY, 524 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t; 525 526 /**************************************************************************** 527 * EventNotification message 528 ****************************************************************************/ 529 530 /* EventNotification Request message */ 531 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4) 532 533 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST 534 { 535 U16 Reserved1; /* 0x00 */ 536 U8 ChainOffset; /* 0x02 */ 537 U8 Function; /* 0x03 */ 538 U16 Reserved2; /* 0x04 */ 539 U8 Reserved3; /* 0x06 */ 540 U8 MsgFlags; /* 0x07 */ 541 U8 VP_ID; /* 0x08 */ 542 U8 VF_ID; /* 0x09 */ 543 U16 Reserved4; /* 0x0A */ 544 U32 Reserved5; /* 0x0C */ 545 U32 Reserved6; /* 0x10 */ 546 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */ 547 U16 SASBroadcastPrimitiveMasks; /* 0x24 */ 548 U16 SASNotifyPrimitiveMasks; /* 0x26 */ 549 U32 Reserved8; /* 0x28 */ 550 } MPI2_EVENT_NOTIFICATION_REQUEST, 551 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST, 552 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t; 553 554 /* EventNotification Reply message */ 555 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY 556 { 557 U16 EventDataLength; /* 0x00 */ 558 U8 MsgLength; /* 0x02 */ 559 U8 Function; /* 0x03 */ 560 U16 Reserved1; /* 0x04 */ 561 U8 AckRequired; /* 0x06 */ 562 U8 MsgFlags; /* 0x07 */ 563 U8 VP_ID; /* 0x08 */ 564 U8 VF_ID; /* 0x09 */ 565 U16 Reserved2; /* 0x0A */ 566 U16 Reserved3; /* 0x0C */ 567 U16 IOCStatus; /* 0x0E */ 568 U32 IOCLogInfo; /* 0x10 */ 569 U16 Event; /* 0x14 */ 570 U16 Reserved4; /* 0x16 */ 571 U32 EventContext; /* 0x18 */ 572 U32 EventData[1]; /* 0x1C */ 573 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY, 574 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t; 575 576 /* AckRequired */ 577 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 578 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 579 580 /* Event */ 581 #define MPI2_EVENT_LOG_DATA (0x0001) 582 #define MPI2_EVENT_STATE_CHANGE (0x0002) 583 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005) 584 #define MPI2_EVENT_EVENT_CHANGE (0x000A) 585 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */ 586 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F) 587 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014) 588 #define MPI2_EVENT_SAS_DISCOVERY (0x0016) 589 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017) 590 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018) 591 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) 592 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) 593 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) 594 #define MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x001D) /* MPI v2.6 and later */ 595 #define MPI2_EVENT_IR_VOLUME (0x001E) 596 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) 597 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) 598 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) 599 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022) 600 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023) 601 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024) 602 #define MPI2_EVENT_SAS_QUIESCE (0x0025) 603 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026) 604 #define MPI2_EVENT_TEMP_THRESHOLD (0x0027) 605 #define MPI2_EVENT_HOST_MESSAGE (0x0028) 606 #define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029) 607 #define MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE (0x0030) /* MPI v2.6 and later */ 608 #define MPI2_EVENT_PCIE_ENUMERATION (0x0031) /* MPI v2.6 and later */ 609 #define MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x0032) /* MPI v2.6 and later */ 610 #define MPI2_EVENT_PCIE_LINK_COUNTER (0x0033) /* MPI v2.6 and later */ 611 #define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034) /* MPI v2.6 and later */ 612 #define MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x0035) /* MPI v2.5 and later */ 613 #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E) 614 #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F) 615 616 /* Log Entry Added Event data */ 617 618 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */ 619 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C) 620 621 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED 622 { 623 U64 TimeStamp; /* 0x00 */ 624 U32 Reserved1; /* 0x08 */ 625 U16 LogSequence; /* 0x0C */ 626 U16 LogEntryQualifier; /* 0x0E */ 627 U8 VP_ID; /* 0x10 */ 628 U8 VF_ID; /* 0x11 */ 629 U16 Reserved2; /* 0x12 */ 630 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */ 631 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 632 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 633 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t; 634 635 /* GPIO Interrupt Event data */ 636 637 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT 638 { 639 U8 GPIONum; /* 0x00 */ 640 U8 Reserved1; /* 0x01 */ 641 U16 Reserved2; /* 0x02 */ 642 } MPI2_EVENT_DATA_GPIO_INTERRUPT, 643 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT, 644 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t; 645 646 /* Temperature Threshold Event data */ 647 648 typedef struct _MPI2_EVENT_DATA_TEMPERATURE 649 { 650 U16 Status; /* 0x00 */ 651 U8 SensorNum; /* 0x02 */ 652 U8 Reserved1; /* 0x03 */ 653 U16 CurrentTemperature; /* 0x04 */ 654 U16 Reserved2; /* 0x06 */ 655 U32 Reserved3; /* 0x08 */ 656 U32 Reserved4; /* 0x0C */ 657 } MPI2_EVENT_DATA_TEMPERATURE, 658 MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE, 659 Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t; 660 661 /* Temperature Threshold Event data Status bits */ 662 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008) 663 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004) 664 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002) 665 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001) 666 667 /* Host Message Event data */ 668 669 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE 670 { 671 U8 SourceVF_ID; /* 0x00 */ 672 U8 Reserved1; /* 0x01 */ 673 U16 Reserved2; /* 0x02 */ 674 U32 Reserved3; /* 0x04 */ 675 U32 HostData[1]; /* 0x08 */ 676 } MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE, 677 Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t; 678 679 /* Power Performance Change Event data */ 680 681 typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE 682 { 683 U8 CurrentPowerMode; /* 0x00 */ 684 U8 PreviousPowerMode; /* 0x01 */ 685 U16 Reserved1; /* 0x02 */ 686 } MPI2_EVENT_DATA_POWER_PERF_CHANGE, 687 MPI2_POINTER PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE, 688 Mpi2EventDataPowerPerfChange_t, MPI2_POINTER pMpi2EventDataPowerPerfChange_t; 689 690 /* defines for CurrentPowerMode and PreviousPowerMode fields */ 691 #define MPI2_EVENT_PM_INIT_MASK (0xC0) 692 #define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00) 693 #define MPI2_EVENT_PM_INIT_HOST (0x40) 694 #define MPI2_EVENT_PM_INIT_IO_UNIT (0x80) 695 #define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0) 696 697 #define MPI2_EVENT_PM_MODE_MASK (0x07) 698 #define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00) 699 #define MPI2_EVENT_PM_MODE_UNKNOWN (0x01) 700 #define MPI2_EVENT_PM_MODE_FULL_POWER (0x04) 701 #define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05) 702 #define MPI2_EVENT_PM_MODE_STANDBY (0x06) 703 704 /* Active Cable Exception Event data */ 705 706 typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT 707 { 708 U32 ActiveCablePowerRequirement; /* 0x00 */ 709 U8 ReasonCode; /* 0x04 */ 710 U8 ReceptacleID; /* 0x05 */ 711 U16 Reserved1; /* 0x06 */ 712 } MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT, 713 MPI2_POINTER PTR_MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT, 714 Mpi25EventDataActiveCableExcept_t, 715 MPI2_POINTER pMpi25EventDataActiveCableExcept_t, 716 MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT, 717 MPI2_POINTER PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT, 718 Mpi26EventDataActiveCableExcept_t, 719 MPI2_POINTER pMpi26EventDataActiveCableExcept_t; 720 721 /* MPI2.5 defines for the ReasonCode field */ 722 #define MPI25_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00) 723 #define MPI25_EVENT_ACTIVE_CABLE_PRESENT (0x01) 724 #define MPI25_EVENT_ACTIVE_CABLE_DEGRADED (0x02) 725 726 /* MPI2.6 defines for the ReasonCode field */ 727 #define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00) 728 #define MPI26_EVENT_ACTIVE_CABLE_PRESENT (0x01) 729 #define MPI26_EVENT_ACTIVE_CABLE_DEGRADED (0x02) 730 731 /* Hard Reset Received Event data */ 732 733 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED 734 { 735 U8 Reserved1; /* 0x00 */ 736 U8 Port; /* 0x01 */ 737 U16 Reserved2; /* 0x02 */ 738 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 739 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 740 Mpi2EventDataHardResetReceived_t, 741 MPI2_POINTER pMpi2EventDataHardResetReceived_t; 742 743 /* Task Set Full Event data */ 744 /* this event is obsolete */ 745 746 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL 747 { 748 U16 DevHandle; /* 0x00 */ 749 U16 CurrentDepth; /* 0x02 */ 750 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL, 751 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t; 752 753 /* SAS Device Status Change Event data */ 754 755 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE 756 { 757 U16 TaskTag; /* 0x00 */ 758 U8 ReasonCode; /* 0x02 */ 759 U8 PhysicalPort; /* 0x03 */ 760 U8 ASC; /* 0x04 */ 761 U8 ASCQ; /* 0x05 */ 762 U16 DevHandle; /* 0x06 */ 763 U32 Reserved2; /* 0x08 */ 764 U64 SASAddress; /* 0x0C */ 765 U8 LUN[8]; /* 0x14 */ 766 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 767 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 768 Mpi2EventDataSasDeviceStatusChange_t, 769 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t; 770 771 /* SAS Device Status Change Event data ReasonCode values */ 772 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 773 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 774 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 775 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 776 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 777 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 778 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 779 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 780 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 781 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 782 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10) 783 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11) 784 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12) 785 786 /* Integrated RAID Operation Status Event data */ 787 788 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS 789 { 790 U16 VolDevHandle; /* 0x00 */ 791 U16 Reserved1; /* 0x02 */ 792 U8 RAIDOperation; /* 0x04 */ 793 U8 PercentComplete; /* 0x05 */ 794 U16 Reserved2; /* 0x06 */ 795 U32 ElapsedSeconds; /* 0x08 */ 796 } MPI2_EVENT_DATA_IR_OPERATION_STATUS, 797 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS, 798 Mpi2EventDataIrOperationStatus_t, 799 MPI2_POINTER pMpi2EventDataIrOperationStatus_t; 800 801 /* Integrated RAID Operation Status Event data RAIDOperation values */ 802 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00) 803 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01) 804 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02) 805 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03) 806 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04) 807 808 /* Integrated RAID Volume Event data */ 809 810 typedef struct _MPI2_EVENT_DATA_IR_VOLUME 811 { 812 U16 VolDevHandle; /* 0x00 */ 813 U8 ReasonCode; /* 0x02 */ 814 U8 Reserved1; /* 0x03 */ 815 U32 NewValue; /* 0x04 */ 816 U32 PreviousValue; /* 0x08 */ 817 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME, 818 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t; 819 820 /* Integrated RAID Volume Event data ReasonCode values */ 821 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01) 822 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02) 823 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03) 824 825 /* Integrated RAID Physical Disk Event data */ 826 827 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK 828 { 829 U16 Reserved1; /* 0x00 */ 830 U8 ReasonCode; /* 0x02 */ 831 U8 PhysDiskNum; /* 0x03 */ 832 U16 PhysDiskDevHandle; /* 0x04 */ 833 U16 Reserved2; /* 0x06 */ 834 U16 Slot; /* 0x08 */ 835 U16 EnclosureHandle; /* 0x0A */ 836 U32 NewValue; /* 0x0C */ 837 U32 PreviousValue; /* 0x10 */ 838 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 839 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 840 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t; 841 842 /* Integrated RAID Physical Disk Event data ReasonCode values */ 843 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01) 844 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02) 845 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03) 846 847 /* Integrated RAID Configuration Change List Event data */ 848 849 /* 850 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 851 * one and check NumElements at runtime. 852 */ 853 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT 854 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1) 855 #endif 856 857 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT 858 { 859 U16 ElementFlags; /* 0x00 */ 860 U16 VolDevHandle; /* 0x02 */ 861 U8 ReasonCode; /* 0x04 */ 862 U8 PhysDiskNum; /* 0x05 */ 863 U16 PhysDiskDevHandle; /* 0x06 */ 864 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT, 865 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t; 866 867 /* IR Configuration Change List Event data ElementFlags values */ 868 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F) 869 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000) 870 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001) 871 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002) 872 873 /* IR Configuration Change List Event data ReasonCode values */ 874 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01) 875 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02) 876 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03) 877 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04) 878 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05) 879 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06) 880 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07) 881 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08) 882 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09) 883 884 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST 885 { 886 U8 NumElements; /* 0x00 */ 887 U8 Reserved1; /* 0x01 */ 888 U8 Reserved2; /* 0x02 */ 889 U8 ConfigNum; /* 0x03 */ 890 U32 Flags; /* 0x04 */ 891 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */ 892 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 893 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 894 Mpi2EventDataIrConfigChangeList_t, 895 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t; 896 897 /* IR Configuration Change List Event data Flags values */ 898 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001) 899 900 /* SAS Discovery Event data */ 901 902 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY 903 { 904 U8 Flags; /* 0x00 */ 905 U8 ReasonCode; /* 0x01 */ 906 U8 PhysicalPort; /* 0x02 */ 907 U8 Reserved1; /* 0x03 */ 908 U32 DiscoveryStatus; /* 0x04 */ 909 } MPI2_EVENT_DATA_SAS_DISCOVERY, 910 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY, 911 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t; 912 913 /* SAS Discovery Event data Flags values */ 914 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02) 915 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01) 916 917 /* SAS Discovery Event data ReasonCode values */ 918 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01) 919 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02) 920 921 /* SAS Discovery Event data DiscoveryStatus values */ 922 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 923 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000) 924 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000) 925 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 926 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000) 927 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 928 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 929 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000) 930 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 931 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800) 932 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400) 933 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200) 934 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100) 935 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080) 936 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040) 937 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020) 938 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010) 939 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004) 940 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002) 941 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001) 942 943 /* SAS Broadcast Primitive Event data */ 944 945 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE 946 { 947 U8 PhyNum; /* 0x00 */ 948 U8 Port; /* 0x01 */ 949 U8 PortWidth; /* 0x02 */ 950 U8 Primitive; /* 0x03 */ 951 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 952 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 953 Mpi2EventDataSasBroadcastPrimitive_t, 954 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t; 955 956 /* defines for the Primitive field */ 957 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01) 958 #define MPI2_EVENT_PRIMITIVE_SES (0x02) 959 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03) 960 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 961 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05) 962 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06) 963 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 964 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 965 966 /* SAS Notify Primitive Event data */ 967 968 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE 969 { 970 U8 PhyNum; /* 0x00 */ 971 U8 Port; /* 0x01 */ 972 U8 Reserved1; /* 0x02 */ 973 U8 Primitive; /* 0x03 */ 974 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, 975 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, 976 Mpi2EventDataSasNotifyPrimitive_t, 977 MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t; 978 979 /* defines for the Primitive field */ 980 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01) 981 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02) 982 #define MPI2_EVENT_NOTIFY_RESERVED1 (0x03) 983 #define MPI2_EVENT_NOTIFY_RESERVED2 (0x04) 984 985 /* SAS Initiator Device Status Change Event data */ 986 987 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE 988 { 989 U8 ReasonCode; /* 0x00 */ 990 U8 PhysicalPort; /* 0x01 */ 991 U16 DevHandle; /* 0x02 */ 992 U64 SASAddress; /* 0x04 */ 993 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 994 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 995 Mpi2EventDataSasInitDevStatusChange_t, 996 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t; 997 998 /* SAS Initiator Device Status Change event ReasonCode values */ 999 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01) 1000 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 1001 1002 /* SAS Initiator Device Table Overflow Event data */ 1003 1004 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW 1005 { 1006 U16 MaxInit; /* 0x00 */ 1007 U16 CurrentInit; /* 0x02 */ 1008 U64 SASAddress; /* 0x04 */ 1009 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 1010 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 1011 Mpi2EventDataSasInitTableOverflow_t, 1012 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t; 1013 1014 /* SAS Topology Change List Event data */ 1015 1016 /* 1017 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1018 * one and check NumEntries at runtime. 1019 */ 1020 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT 1021 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1) 1022 #endif 1023 1024 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY 1025 { 1026 U16 AttachedDevHandle; /* 0x00 */ 1027 U8 LinkRate; /* 0x02 */ 1028 U8 PhyStatus; /* 0x03 */ 1029 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY, 1030 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t; 1031 1032 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST 1033 { 1034 U16 EnclosureHandle; /* 0x00 */ 1035 U16 ExpanderDevHandle; /* 0x02 */ 1036 U8 NumPhys; /* 0x04 */ 1037 U8 Reserved1; /* 0x05 */ 1038 U16 Reserved2; /* 0x06 */ 1039 U8 NumEntries; /* 0x08 */ 1040 U8 StartPhyNum; /* 0x09 */ 1041 U8 ExpStatus; /* 0x0A */ 1042 U8 PhysicalPort; /* 0x0B */ 1043 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/ 1044 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 1045 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 1046 Mpi2EventDataSasTopologyChangeList_t, 1047 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t; 1048 1049 /* values for the ExpStatus field */ 1050 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 1051 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01) 1052 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 1053 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 1054 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 1055 1056 /* defines for the LinkRate field */ 1057 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) 1058 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 1059 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) 1060 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 1061 1062 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 1063 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 1064 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 1065 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 1066 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 1067 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 1068 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 1069 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08) 1070 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) 1071 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) 1072 #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B) 1073 #define MPI26_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0C) 1074 1075 /* values for the PhyStatus field */ 1076 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) 1077 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10) 1078 /* values for the PhyStatus ReasonCode sub-field */ 1079 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F) 1080 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01) 1081 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02) 1082 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03) 1083 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04) 1084 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05) 1085 1086 /* SAS Enclosure Device Status Change Event data */ 1087 1088 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE 1089 { 1090 U16 EnclosureHandle; /* 0x00 */ 1091 U8 ReasonCode; /* 0x02 */ 1092 U8 PhysicalPort; /* 0x03 */ 1093 U64 EnclosureLogicalID; /* 0x04 */ 1094 U16 NumSlots; /* 0x0C */ 1095 U16 StartSlot; /* 0x0E */ 1096 U32 PhyBits; /* 0x10 */ 1097 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 1098 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 1099 Mpi2EventDataSasEnclDevStatusChange_t, 1100 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t, 1101 MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE, 1102 MPI2_POINTER PTR_MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE, 1103 Mpi26EventDataEnclDevStatusChange_t, 1104 MPI2_POINTER pMpi26EventDataEnclDevStatusChange_t; 1105 1106 /* SAS Enclosure Device Status Change event ReasonCode values */ 1107 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) 1108 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) 1109 1110 /* Enclosure Device Status Change event ReasonCode values */ 1111 #define MPI26_EVENT_ENCL_RC_ADDED (0x01) 1112 #define MPI26_EVENT_ENCL_RC_NOT_RESPONDING (0x02) 1113 1114 /* SAS PHY Counter Event data */ 1115 1116 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER 1117 { 1118 U64 TimeStamp; /* 0x00 */ 1119 U32 Reserved1; /* 0x08 */ 1120 U8 PhyEventCode; /* 0x0C */ 1121 U8 PhyNum; /* 0x0D */ 1122 U16 Reserved2; /* 0x0E */ 1123 U32 PhyEventInfo; /* 0x10 */ 1124 U8 CounterType; /* 0x14 */ 1125 U8 ThresholdWindow; /* 0x15 */ 1126 U8 TimeUnits; /* 0x16 */ 1127 U8 Reserved3; /* 0x17 */ 1128 U32 EventThreshold; /* 0x18 */ 1129 U16 ThresholdFlags; /* 0x1C */ 1130 U16 Reserved4; /* 0x1E */ 1131 } MPI2_EVENT_DATA_SAS_PHY_COUNTER, 1132 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER, 1133 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t; 1134 1135 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */ 1136 1137 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */ 1138 1139 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */ 1140 1141 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */ 1142 1143 /* SAS Quiesce Event data */ 1144 1145 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE 1146 { 1147 U8 ReasonCode; /* 0x00 */ 1148 U8 Reserved1; /* 0x01 */ 1149 U16 Reserved2; /* 0x02 */ 1150 U32 Reserved3; /* 0x04 */ 1151 } MPI2_EVENT_DATA_SAS_QUIESCE, 1152 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE, 1153 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t; 1154 1155 /* SAS Quiesce Event data ReasonCode values */ 1156 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01) 1157 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02) 1158 1159 typedef struct _MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR 1160 { 1161 U16 DevHandle; /* 0x00 */ 1162 U8 ReasonCode; /* 0x02 */ 1163 U8 PhysicalPort; /* 0x03 */ 1164 U32 Reserved1[2]; /* 0x04 */ 1165 U64 SASAddress; /* 0x0C */ 1166 U32 Reserved2[2]; /* 0x14 */ 1167 } MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR, 1168 MPI2_POINTER PTR_MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR, 1169 Mpi25EventDataSasDeviceDiscoveryError_t, 1170 MPI2_POINTER pMpi25EventDataSasDeviceDiscoveryError_t; 1171 1172 /* SAS Device Discovery Error Event data ReasonCode values */ 1173 #define MPI25_EVENT_SAS_DISC_ERR_SMP_FAILED (0x01) 1174 #define MPI25_EVENT_SAS_DISC_ERR_SMP_TIMEOUT (0x02) 1175 1176 /* Host Based Discovery Phy Event data */ 1177 1178 typedef struct _MPI2_EVENT_HBD_PHY_SAS 1179 { 1180 U8 Flags; /* 0x00 */ 1181 U8 NegotiatedLinkRate; /* 0x01 */ 1182 U8 PhyNum; /* 0x02 */ 1183 U8 PhysicalPort; /* 0x03 */ 1184 U32 Reserved1; /* 0x04 */ 1185 U8 InitialFrame[28]; /* 0x08 */ 1186 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS, 1187 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t; 1188 1189 /* values for the Flags field */ 1190 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02) 1191 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01) 1192 1193 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */ 1194 1195 typedef union _MPI2_EVENT_HBD_DESCRIPTOR 1196 { 1197 MPI2_EVENT_HBD_PHY_SAS Sas; 1198 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR, 1199 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t; 1200 1201 typedef struct _MPI2_EVENT_DATA_HBD_PHY 1202 { 1203 U8 DescriptorType; /* 0x00 */ 1204 U8 Reserved1; /* 0x01 */ 1205 U16 Reserved2; /* 0x02 */ 1206 U32 Reserved3; /* 0x04 */ 1207 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */ 1208 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY, 1209 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t; 1210 1211 /* values for the DescriptorType field */ 1212 #define MPI2_EVENT_HBD_DT_SAS (0x01) 1213 1214 /* PCIe Device Status Change Event data (MPI v2.6 and later) */ 1215 1216 typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE 1217 { 1218 U16 TaskTag; /* 0x00 */ 1219 U8 ReasonCode; /* 0x02 */ 1220 U8 PhysicalPort; /* 0x03 */ 1221 U8 ASC; /* 0x04 */ 1222 U8 ASCQ; /* 0x05 */ 1223 U16 DevHandle; /* 0x06 */ 1224 U32 Reserved2; /* 0x08 */ 1225 U64 WWID; /* 0x0C */ 1226 U8 LUN[8]; /* 0x14 */ 1227 } MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE, 1228 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE, 1229 Mpi26EventDataPCIeDeviceStatusChange_t, 1230 MPI2_POINTER pMpi26EventDataPCIeDeviceStatusChange_t; 1231 1232 /* PCIe Device Status Change Event data ReasonCode values */ 1233 #define MPI26_EVENT_PCIDEV_STAT_RC_SMART_DATA (0x05) 1234 #define MPI26_EVENT_PCIDEV_STAT_RC_UNSUPPORTED (0x07) 1235 #define MPI26_EVENT_PCIDEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 1236 #define MPI26_EVENT_PCIDEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 1237 #define MPI26_EVENT_PCIDEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 1238 #define MPI26_EVENT_PCIDEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 1239 #define MPI26_EVENT_PCIDEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 1240 #define MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 1241 #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 1242 #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 1243 #define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE (0x10) 1244 #define MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x11) 1245 1246 /* PCIe Enumeration Event data (MPI v2.6 and later) */ 1247 1248 typedef struct _MPI26_EVENT_DATA_PCIE_ENUMERATION 1249 { 1250 U8 Flags; /* 0x00 */ 1251 U8 ReasonCode; /* 0x01 */ 1252 U8 PhysicalPort; /* 0x02 */ 1253 U8 Reserved1; /* 0x03 */ 1254 U32 EnumerationStatus; /* 0x04 */ 1255 } MPI26_EVENT_DATA_PCIE_ENUMERATION, 1256 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_ENUMERATION, 1257 Mpi26EventDataPCIeEnumeration_t, 1258 MPI2_POINTER pMpi26EventDataPCIeEnumeration_t; 1259 1260 /* PCIe Enumeration Event data Flags values */ 1261 #define MPI26_EVENT_PCIE_ENUM_DEVICE_CHANGE (0x02) 1262 #define MPI26_EVENT_PCIE_ENUM_IN_PROGRESS (0x01) 1263 1264 /* PCIe Enumeration Event data ReasonCode values */ 1265 #define MPI26_EVENT_PCIE_ENUM_RC_STARTED (0x01) 1266 #define MPI26_EVENT_PCIE_ENUM_RC_COMPLETED (0x02) 1267 1268 /* PCIe Enumeration Event data EnumerationStatus values */ 1269 #define MPI26_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000) 1270 #define MPI26_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000) 1271 #define MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000) 1272 1273 /* PCIe Topology Change List Event data (MPI v2.6 and later) */ 1274 1275 /* 1276 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1277 * one and check NumEntries at runtime. 1278 */ 1279 #ifndef MPI26_EVENT_PCIE_TOPO_PORT_COUNT 1280 #define MPI26_EVENT_PCIE_TOPO_PORT_COUNT (1) 1281 #endif 1282 1283 typedef struct _MPI26_EVENT_PCIE_TOPO_PORT_ENTRY 1284 { 1285 U16 AttachedDevHandle; /* 0x00 */ 1286 U8 PortStatus; /* 0x02 */ 1287 U8 Reserved1; /* 0x03 */ 1288 U8 CurrentPortInfo; /* 0x04 */ 1289 U8 Reserved2; /* 0x05 */ 1290 U8 PreviousPortInfo; /* 0x06 */ 1291 U8 Reserved3; /* 0x07 */ 1292 } MPI26_EVENT_PCIE_TOPO_PORT_ENTRY, 1293 MPI2_POINTER PTR_MPI26_EVENT_PCIE_TOPO_PORT_ENTRY, 1294 Mpi26EventPCIeTopoPortEntry_t, 1295 MPI2_POINTER pMpi26EventPCIeTopoPortEntry_t; 1296 1297 /* PCIe Topology Change List Event data PortStatus values */ 1298 #define MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED (0x01) 1299 #define MPI26_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02) 1300 #define MPI26_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03) 1301 #define MPI26_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04) 1302 #define MPI26_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05) 1303 1304 /* PCIe Topology Change List Event data defines for CurrentPortInfo and PreviousPortInfo */ 1305 #define MPI26_EVENT_PCIE_TOPO_PI_LANE_MASK (0xF0) 1306 #define MPI26_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00) 1307 #define MPI26_EVENT_PCIE_TOPO_PI_1_LANE (0x10) 1308 #define MPI26_EVENT_PCIE_TOPO_PI_2_LANES (0x20) 1309 #define MPI26_EVENT_PCIE_TOPO_PI_4_LANES (0x30) 1310 #define MPI26_EVENT_PCIE_TOPO_PI_8_LANES (0x40) 1311 1312 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F) 1313 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00) 1314 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01) 1315 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02) 1316 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03) 1317 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04) 1318 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05) 1319 1320 typedef struct _MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST 1321 { 1322 U16 EnclosureHandle; /* 0x00 */ 1323 U16 SwitchDevHandle; /* 0x02 */ 1324 U8 NumPorts; /* 0x04 */ 1325 U8 Reserved1; /* 0x05 */ 1326 U16 Reserved2; /* 0x06 */ 1327 U8 NumEntries; /* 0x08 */ 1328 U8 StartPortNum; /* 0x09 */ 1329 U8 SwitchStatus; /* 0x0A */ 1330 U8 PhysicalPort; /* 0x0B */ 1331 MPI26_EVENT_PCIE_TOPO_PORT_ENTRY PortEntry[MPI26_EVENT_PCIE_TOPO_PORT_COUNT]; /* 0x0C */ 1332 } MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST, 1333 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST, 1334 Mpi26EventDataPCIeTopologyChangeList_t, 1335 MPI2_POINTER pMpi26EventDataPCIeTopologyChangeList_t; 1336 1337 /* PCIe Topology Change List Event data SwitchStatus values */ 1338 #define MPI26_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00) 1339 #define MPI26_EVENT_PCIE_TOPO_SS_ADDED (0x01) 1340 #define MPI26_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02) 1341 #define MPI26_EVENT_PCIE_TOPO_SS_RESPONDING (0x03) 1342 #define MPI26_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04) 1343 1344 /* PCIe Link Counter Event data (MPI v2.6 and later) */ 1345 1346 typedef struct _MPI26_EVENT_DATA_PCIE_LINK_COUNTER 1347 { 1348 U64 TimeStamp; /* 0x00 */ 1349 U32 Reserved1; /* 0x08 */ 1350 U8 LinkEventCode; /* 0x0C */ 1351 U8 LinkNum; /* 0x0D */ 1352 U16 Reserved2; /* 0x0E */ 1353 U32 LinkEventInfo; /* 0x10 */ 1354 U8 CounterType; /* 0x14 */ 1355 U8 ThresholdWindow; /* 0x15 */ 1356 U8 TimeUnits; /* 0x16 */ 1357 U8 Reserved3; /* 0x17 */ 1358 U32 EventThreshold; /* 0x18 */ 1359 U16 ThresholdFlags; /* 0x1C */ 1360 U16 Reserved4; /* 0x1E */ 1361 } MPI26_EVENT_DATA_PCIE_LINK_COUNTER, 1362 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_LINK_COUNTER, 1363 Mpi26EventDataPcieLinkCounter_t, MPI2_POINTER pMpi26EventDataPcieLinkCounter_t; 1364 1365 /* use MPI26_PCIELINK3_EVTCODE_ values from mpi2_cnfg.h for the LinkEventCode field */ 1366 1367 /* use MPI26_PCIELINK3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */ 1368 1369 /* use MPI26_PCIELINK3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */ 1370 1371 /* use MPI26_PCIELINK3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */ 1372 1373 /**************************************************************************** 1374 * EventAck message 1375 ****************************************************************************/ 1376 1377 /* EventAck Request message */ 1378 typedef struct _MPI2_EVENT_ACK_REQUEST 1379 { 1380 U16 Reserved1; /* 0x00 */ 1381 U8 ChainOffset; /* 0x02 */ 1382 U8 Function; /* 0x03 */ 1383 U16 Reserved2; /* 0x04 */ 1384 U8 Reserved3; /* 0x06 */ 1385 U8 MsgFlags; /* 0x07 */ 1386 U8 VP_ID; /* 0x08 */ 1387 U8 VF_ID; /* 0x09 */ 1388 U16 Reserved4; /* 0x0A */ 1389 U16 Event; /* 0x0C */ 1390 U16 Reserved5; /* 0x0E */ 1391 U32 EventContext; /* 0x10 */ 1392 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST, 1393 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t; 1394 1395 /* EventAck Reply message */ 1396 typedef struct _MPI2_EVENT_ACK_REPLY 1397 { 1398 U16 Reserved1; /* 0x00 */ 1399 U8 MsgLength; /* 0x02 */ 1400 U8 Function; /* 0x03 */ 1401 U16 Reserved2; /* 0x04 */ 1402 U8 Reserved3; /* 0x06 */ 1403 U8 MsgFlags; /* 0x07 */ 1404 U8 VP_ID; /* 0x08 */ 1405 U8 VF_ID; /* 0x09 */ 1406 U16 Reserved4; /* 0x0A */ 1407 U16 Reserved5; /* 0x0C */ 1408 U16 IOCStatus; /* 0x0E */ 1409 U32 IOCLogInfo; /* 0x10 */ 1410 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY, 1411 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t; 1412 1413 /**************************************************************************** 1414 * SendHostMessage message 1415 ****************************************************************************/ 1416 1417 /* SendHostMessage Request message */ 1418 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST 1419 { 1420 U16 HostDataLength; /* 0x00 */ 1421 U8 ChainOffset; /* 0x02 */ 1422 U8 Function; /* 0x03 */ 1423 U16 Reserved1; /* 0x04 */ 1424 U8 Reserved2; /* 0x06 */ 1425 U8 MsgFlags; /* 0x07 */ 1426 U8 VP_ID; /* 0x08 */ 1427 U8 VF_ID; /* 0x09 */ 1428 U16 Reserved3; /* 0x0A */ 1429 U8 Reserved4; /* 0x0C */ 1430 U8 DestVF_ID; /* 0x0D */ 1431 U16 Reserved5; /* 0x0E */ 1432 U32 Reserved6; /* 0x10 */ 1433 U32 Reserved7; /* 0x14 */ 1434 U32 Reserved8; /* 0x18 */ 1435 U32 Reserved9; /* 0x1C */ 1436 U32 Reserved10; /* 0x20 */ 1437 U32 HostData[1]; /* 0x24 */ 1438 } MPI2_SEND_HOST_MESSAGE_REQUEST, 1439 MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST, 1440 Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t; 1441 1442 /* SendHostMessage Reply message */ 1443 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY 1444 { 1445 U16 HostDataLength; /* 0x00 */ 1446 U8 MsgLength; /* 0x02 */ 1447 U8 Function; /* 0x03 */ 1448 U16 Reserved1; /* 0x04 */ 1449 U8 Reserved2; /* 0x06 */ 1450 U8 MsgFlags; /* 0x07 */ 1451 U8 VP_ID; /* 0x08 */ 1452 U8 VF_ID; /* 0x09 */ 1453 U16 Reserved3; /* 0x0A */ 1454 U16 Reserved4; /* 0x0C */ 1455 U16 IOCStatus; /* 0x0E */ 1456 U32 IOCLogInfo; /* 0x10 */ 1457 } MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY, 1458 Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t; 1459 1460 /**************************************************************************** 1461 * FWDownload message 1462 ****************************************************************************/ 1463 1464 /* MPI v2.0 FWDownload Request message */ 1465 typedef struct _MPI2_FW_DOWNLOAD_REQUEST 1466 { 1467 U8 ImageType; /* 0x00 */ 1468 U8 Reserved1; /* 0x01 */ 1469 U8 ChainOffset; /* 0x02 */ 1470 U8 Function; /* 0x03 */ 1471 U16 Reserved2; /* 0x04 */ 1472 U8 Reserved3; /* 0x06 */ 1473 U8 MsgFlags; /* 0x07 */ 1474 U8 VP_ID; /* 0x08 */ 1475 U8 VF_ID; /* 0x09 */ 1476 U16 Reserved4; /* 0x0A */ 1477 U32 TotalImageSize; /* 0x0C */ 1478 U32 Reserved5; /* 0x10 */ 1479 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1480 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST, 1481 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest; 1482 1483 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1484 1485 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01) 1486 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1487 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1488 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1489 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1490 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1491 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A) 1492 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1493 #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C) /* MPI v2.5 and newer */ 1494 #define MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP (0x0D) 1495 #define MPI2_FW_DOWNLOAD_ITYPE_SBR (0x0E) 1496 #define MPI2_FW_DOWNLOAD_ITYPE_SBR_BACKUP (0x0F) 1497 #define MPI2_FW_DOWNLOAD_ITYPE_HIIM (0x10) 1498 #define MPI2_FW_DOWNLOAD_ITYPE_HIIA (0x11) 1499 #define MPI2_FW_DOWNLOAD_ITYPE_CTLR (0x12) 1500 #define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE (0x13) 1501 #define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA (0x14) 1502 #define MPI2_FW_DOWNLOAD_ITYPE_CPLD (0x15) /* MPI v2.6 and newer */ 1503 #define MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16) /* MPI v2.6 and newer */ 1504 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) 1505 #define MPI2_FW_DOWNLOAD_ITYPE_TERMINATE (0xFF) /* MPI v2.6 and newer */ 1506 1507 /* MPI v2.0 FWDownload TransactionContext Element */ 1508 typedef struct _MPI2_FW_DOWNLOAD_TCSGE 1509 { 1510 U8 Reserved1; /* 0x00 */ 1511 U8 ContextSize; /* 0x01 */ 1512 U8 DetailsLength; /* 0x02 */ 1513 U8 Flags; /* 0x03 */ 1514 U32 Reserved2; /* 0x04 */ 1515 U32 ImageOffset; /* 0x08 */ 1516 U32 ImageSize; /* 0x0C */ 1517 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE, 1518 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t; 1519 1520 /* MPI v2.5 FWDownload Request message */ 1521 typedef struct _MPI25_FW_DOWNLOAD_REQUEST 1522 { 1523 U8 ImageType; /* 0x00 */ 1524 U8 Reserved1; /* 0x01 */ 1525 U8 ChainOffset; /* 0x02 */ 1526 U8 Function; /* 0x03 */ 1527 U16 Reserved2; /* 0x04 */ 1528 U8 Reserved3; /* 0x06 */ 1529 U8 MsgFlags; /* 0x07 */ 1530 U8 VP_ID; /* 0x08 */ 1531 U8 VF_ID; /* 0x09 */ 1532 U16 Reserved4; /* 0x0A */ 1533 U32 TotalImageSize; /* 0x0C */ 1534 U32 Reserved5; /* 0x10 */ 1535 U32 Reserved6; /* 0x14 */ 1536 U32 ImageOffset; /* 0x18 */ 1537 U32 ImageSize; /* 0x1C */ 1538 MPI25_SGE_IO_UNION SGL; /* 0x20 */ 1539 } MPI25_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_DOWNLOAD_REQUEST, 1540 Mpi25FWDownloadRequest, MPI2_POINTER pMpi25FWDownloadRequest; 1541 1542 /* FWDownload Reply message */ 1543 typedef struct _MPI2_FW_DOWNLOAD_REPLY 1544 { 1545 U8 ImageType; /* 0x00 */ 1546 U8 Reserved1; /* 0x01 */ 1547 U8 MsgLength; /* 0x02 */ 1548 U8 Function; /* 0x03 */ 1549 U16 Reserved2; /* 0x04 */ 1550 U8 Reserved3; /* 0x06 */ 1551 U8 MsgFlags; /* 0x07 */ 1552 U8 VP_ID; /* 0x08 */ 1553 U8 VF_ID; /* 0x09 */ 1554 U16 Reserved4; /* 0x0A */ 1555 U16 Reserved5; /* 0x0C */ 1556 U16 IOCStatus; /* 0x0E */ 1557 U32 IOCLogInfo; /* 0x10 */ 1558 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY, 1559 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t; 1560 1561 /**************************************************************************** 1562 * FWUpload message 1563 ****************************************************************************/ 1564 1565 /* MPI v2.0 FWUpload Request message */ 1566 typedef struct _MPI2_FW_UPLOAD_REQUEST 1567 { 1568 U8 ImageType; /* 0x00 */ 1569 U8 Reserved1; /* 0x01 */ 1570 U8 ChainOffset; /* 0x02 */ 1571 U8 Function; /* 0x03 */ 1572 U16 Reserved2; /* 0x04 */ 1573 U8 Reserved3; /* 0x06 */ 1574 U8 MsgFlags; /* 0x07 */ 1575 U8 VP_ID; /* 0x08 */ 1576 U8 VF_ID; /* 0x09 */ 1577 U16 Reserved4; /* 0x0A */ 1578 U32 Reserved5; /* 0x0C */ 1579 U32 Reserved6; /* 0x10 */ 1580 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1581 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST, 1582 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t; 1583 1584 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00) 1585 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1586 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1587 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1588 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1589 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1590 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1591 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1592 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1593 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1594 #define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D) 1595 #define MPI2_FW_UPLOAD_ITYPE_SBR (0x0E) 1596 #define MPI2_FW_UPLOAD_ITYPE_SBR_BACKUP (0x0F) 1597 #define MPI2_FW_UPLOAD_ITYPE_HIIM (0x10) 1598 #define MPI2_FW_UPLOAD_ITYPE_HIIA (0x11) 1599 #define MPI2_FW_UPLOAD_ITYPE_CTLR (0x12) 1600 #define MPI2_FW_UPLOAD_ITYPE_IMR_FIRMWARE (0x13) 1601 #define MPI2_FW_UPLOAD_ITYPE_MR_NVDATA (0x14) 1602 1603 /* MPI v2.0 FWUpload TransactionContext Element */ 1604 typedef struct _MPI2_FW_UPLOAD_TCSGE 1605 { 1606 U8 Reserved1; /* 0x00 */ 1607 U8 ContextSize; /* 0x01 */ 1608 U8 DetailsLength; /* 0x02 */ 1609 U8 Flags; /* 0x03 */ 1610 U32 Reserved2; /* 0x04 */ 1611 U32 ImageOffset; /* 0x08 */ 1612 U32 ImageSize; /* 0x0C */ 1613 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE, 1614 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t; 1615 1616 /* MPI v2.5 FWUpload Request message */ 1617 typedef struct _MPI25_FW_UPLOAD_REQUEST 1618 { 1619 U8 ImageType; /* 0x00 */ 1620 U8 Reserved1; /* 0x01 */ 1621 U8 ChainOffset; /* 0x02 */ 1622 U8 Function; /* 0x03 */ 1623 U16 Reserved2; /* 0x04 */ 1624 U8 Reserved3; /* 0x06 */ 1625 U8 MsgFlags; /* 0x07 */ 1626 U8 VP_ID; /* 0x08 */ 1627 U8 VF_ID; /* 0x09 */ 1628 U16 Reserved4; /* 0x0A */ 1629 U32 Reserved5; /* 0x0C */ 1630 U32 Reserved6; /* 0x10 */ 1631 U32 Reserved7; /* 0x14 */ 1632 U32 ImageOffset; /* 0x18 */ 1633 U32 ImageSize; /* 0x1C */ 1634 MPI25_SGE_IO_UNION SGL; /* 0x20 */ 1635 } MPI25_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_UPLOAD_REQUEST, 1636 Mpi25FWUploadRequest_t, MPI2_POINTER pMpi25FWUploadRequest_t; 1637 1638 /* FWUpload Reply message */ 1639 typedef struct _MPI2_FW_UPLOAD_REPLY 1640 { 1641 U8 ImageType; /* 0x00 */ 1642 U8 Reserved1; /* 0x01 */ 1643 U8 MsgLength; /* 0x02 */ 1644 U8 Function; /* 0x03 */ 1645 U16 Reserved2; /* 0x04 */ 1646 U8 Reserved3; /* 0x06 */ 1647 U8 MsgFlags; /* 0x07 */ 1648 U8 VP_ID; /* 0x08 */ 1649 U8 VF_ID; /* 0x09 */ 1650 U16 Reserved4; /* 0x0A */ 1651 U16 Reserved5; /* 0x0C */ 1652 U16 IOCStatus; /* 0x0E */ 1653 U32 IOCLogInfo; /* 0x10 */ 1654 U32 ActualImageSize; /* 0x14 */ 1655 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY, 1656 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t; 1657 1658 /**************************************************************************** 1659 * PowerManagementControl message 1660 ****************************************************************************/ 1661 1662 /* PowerManagementControl Request message */ 1663 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST 1664 { 1665 U8 Feature; /* 0x00 */ 1666 U8 Reserved1; /* 0x01 */ 1667 U8 ChainOffset; /* 0x02 */ 1668 U8 Function; /* 0x03 */ 1669 U16 Reserved2; /* 0x04 */ 1670 U8 Reserved3; /* 0x06 */ 1671 U8 MsgFlags; /* 0x07 */ 1672 U8 VP_ID; /* 0x08 */ 1673 U8 VF_ID; /* 0x09 */ 1674 U16 Reserved4; /* 0x0A */ 1675 U8 Parameter1; /* 0x0C */ 1676 U8 Parameter2; /* 0x0D */ 1677 U8 Parameter3; /* 0x0E */ 1678 U8 Parameter4; /* 0x0F */ 1679 U32 Reserved5; /* 0x10 */ 1680 U32 Reserved6; /* 0x14 */ 1681 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST, 1682 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t; 1683 1684 /* defines for the Feature field */ 1685 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01) 1686 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02) 1687 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /* obsolete */ 1688 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04) 1689 #define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05) /* reserved in MPI 2.0 */ 1690 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80) 1691 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF) 1692 1693 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */ 1694 /* Parameter1 contains a PHY number */ 1695 /* Parameter2 indicates power condition action using these defines */ 1696 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01) 1697 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02) 1698 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03) 1699 /* Parameter3 and Parameter4 are reserved */ 1700 1701 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */ 1702 /* Parameter1 contains SAS port width modulation group number */ 1703 /* Parameter2 indicates IOC action using these defines */ 1704 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01) 1705 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02) 1706 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03) 1707 /* Parameter3 indicates desired modulation level using these defines */ 1708 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00) 1709 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01) 1710 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02) 1711 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03) 1712 /* Parameter4 is reserved */ 1713 1714 /* this next set (_PCIE_LINK) is obsolete */ 1715 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */ 1716 /* Parameter1 indicates desired PCIe link speed using these defines */ 1717 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /* obsolete */ 1718 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /* obsolete */ 1719 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /* obsolete */ 1720 /* Parameter2 indicates desired PCIe link width using these defines */ 1721 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /* obsolete */ 1722 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /* obsolete */ 1723 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /* obsolete */ 1724 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /* obsolete */ 1725 /* Parameter3 and Parameter4 are reserved */ 1726 1727 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */ 1728 /* Parameter1 indicates desired IOC hardware clock speed using these defines */ 1729 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01) 1730 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02) 1731 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04) 1732 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08) 1733 /* Parameter2, Parameter3, and Parameter4 are reserved */ 1734 1735 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature */ 1736 /* Parameter1 indicates host action regarding global power management mode */ 1737 #define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01) 1738 #define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02) 1739 #define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03) 1740 /* Parameter2 indicates the requested global power management mode */ 1741 #define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01) 1742 #define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08) 1743 #define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40) 1744 /* Parameter3 and Parameter4 are reserved */ 1745 1746 /* PowerManagementControl Reply message */ 1747 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY 1748 { 1749 U8 Feature; /* 0x00 */ 1750 U8 Reserved1; /* 0x01 */ 1751 U8 MsgLength; /* 0x02 */ 1752 U8 Function; /* 0x03 */ 1753 U16 Reserved2; /* 0x04 */ 1754 U8 Reserved3; /* 0x06 */ 1755 U8 MsgFlags; /* 0x07 */ 1756 U8 VP_ID; /* 0x08 */ 1757 U8 VF_ID; /* 0x09 */ 1758 U16 Reserved4; /* 0x0A */ 1759 U16 Reserved5; /* 0x0C */ 1760 U16 IOCStatus; /* 0x0E */ 1761 U32 IOCLogInfo; /* 0x10 */ 1762 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY, 1763 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t; 1764 1765 /**************************************************************************** 1766 * IO Unit Control messages (MPI v2.6 and later only.) 1767 ****************************************************************************/ 1768 1769 /* IO Unit Control Request Message */ 1770 typedef struct _MPI26_IOUNIT_CONTROL_REQUEST 1771 { 1772 U8 Operation; /* 0x00 */ 1773 U8 Reserved1; /* 0x01 */ 1774 U8 ChainOffset; /* 0x02 */ 1775 U8 Function; /* 0x03 */ 1776 U16 DevHandle; /* 0x04 */ 1777 U8 IOCParameter; /* 0x06 */ 1778 U8 MsgFlags; /* 0x07 */ 1779 U8 VP_ID; /* 0x08 */ 1780 U8 VF_ID; /* 0x09 */ 1781 U16 Reserved3; /* 0x0A */ 1782 U16 Reserved4; /* 0x0C */ 1783 U8 PhyNum; /* 0x0E */ 1784 U8 PrimFlags; /* 0x0F */ 1785 U32 Primitive; /* 0x10 */ 1786 U8 LookupMethod; /* 0x14 */ 1787 U8 Reserved5; /* 0x15 */ 1788 U16 SlotNumber; /* 0x16 */ 1789 U64 LookupAddress; /* 0x18 */ 1790 U32 IOCParameterValue; /* 0x20 */ 1791 U32 Reserved7; /* 0x24 */ 1792 U32 Reserved8; /* 0x28 */ 1793 } MPI26_IOUNIT_CONTROL_REQUEST, 1794 MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REQUEST, 1795 Mpi26IoUnitControlRequest_t, MPI2_POINTER pMpi26IoUnitControlRequest_t; 1796 1797 /* values for the Operation field */ 1798 #define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT (0x02) 1799 #define MPI26_CTRL_OP_SAS_PHY_LINK_RESET (0x06) 1800 #define MPI26_CTRL_OP_SAS_PHY_HARD_RESET (0x07) 1801 #define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG (0x08) 1802 #define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG (0x09) 1803 #define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE (0x0A) 1804 #define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY (0x0B) 1805 #define MPI26_CTRL_OP_REMOVE_DEVICE (0x0D) 1806 #define MPI26_CTRL_OP_LOOKUP_MAPPING (0x0E) 1807 #define MPI26_CTRL_OP_SET_IOC_PARAMETER (0x0F) 1808 #define MPI26_CTRL_OP_ENABLE_FP_DEVICE (0x10) 1809 #define MPI26_CTRL_OP_DISABLE_FP_DEVICE (0x11) 1810 #define MPI26_CTRL_OP_ENABLE_FP_ALL (0x12) 1811 #define MPI26_CTRL_OP_DISABLE_FP_ALL (0x13) 1812 #define MPI26_CTRL_OP_DEV_ENABLE_NCQ (0x14) 1813 #define MPI26_CTRL_OP_DEV_DISABLE_NCQ (0x15) 1814 #define MPI26_CTRL_OP_SHUTDOWN (0x16) 1815 #define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17) 1816 #define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18) 1817 #define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19) 1818 #define MPI26_CTRL_OP_ENABLE_NVME_SGL_FORMAT (0x1A) 1819 #define MPI26_CTRL_OP_DISABLE_NVME_SGL_FORMAT (0x1B) 1820 #define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80) 1821 1822 /* values for the PrimFlags field */ 1823 #define MPI26_CTRL_PRIMFLAGS_SINGLE (0x08) 1824 #define MPI26_CTRL_PRIMFLAGS_TRIPLE (0x02) 1825 #define MPI26_CTRL_PRIMFLAGS_REDUNDANT (0x01) 1826 1827 /* values for the LookupMethod field */ 1828 #define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01) 1829 #define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02) 1830 #define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03) 1831 1832 /* IO Unit Control Reply Message */ 1833 typedef struct _MPI26_IOUNIT_CONTROL_REPLY 1834 { 1835 U8 Operation; /* 0x00 */ 1836 U8 Reserved1; /* 0x01 */ 1837 U8 MsgLength; /* 0x02 */ 1838 U8 Function; /* 0x03 */ 1839 U16 DevHandle; /* 0x04 */ 1840 U8 IOCParameter; /* 0x06 */ 1841 U8 MsgFlags; /* 0x07 */ 1842 U8 VP_ID; /* 0x08 */ 1843 U8 VF_ID; /* 0x09 */ 1844 U16 Reserved3; /* 0x0A */ 1845 U16 Reserved4; /* 0x0C */ 1846 U16 IOCStatus; /* 0x0E */ 1847 U32 IOCLogInfo; /* 0x10 */ 1848 } MPI26_IOUNIT_CONTROL_REPLY, MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REPLY, 1849 Mpi26IoUnitControlReply_t, MPI2_POINTER pMpi26IoUnitControlReply_t; 1850 1851 #endif 1852