1 // SPDX-License-Identifier: GPL-2.0-or-later
2 //
3 // sma1303.c -- sma1303 ALSA SoC Audio driver
4 //
5 // Copyright 2023 Iron Device Corporation
6 //
7 // Auther: Gyuhwa Park <gyuhwa.park@irondevice.com>
8 // Kiseok Jo <kiseok.jo@irondevice.com>
9
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/pm.h>
16 #include <linux/i2c.h>
17 #include <linux/regmap.h>
18 #include <sound/core.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/initval.h>
23 #include <sound/tlv.h>
24 #include <linux/slab.h>
25 #include <asm/div64.h>
26
27 #include "sma1303.h"
28
29 #define CHECK_PERIOD_TIME 1 /* sec per HZ */
30 #define MAX_CONTROL_NAME 48
31
32 #define PLL_MATCH(_input_clk_name, _output_clk_name, _input_clk,\
33 _post_n, _n, _vco, _p_cp)\
34 {\
35 .input_clk_name = _input_clk_name,\
36 .output_clk_name = _output_clk_name,\
37 .input_clk = _input_clk,\
38 .post_n = _post_n,\
39 .n = _n,\
40 .vco = _vco,\
41 .p_cp = _p_cp,\
42 }
43
44 enum sma1303_type {
45 SMA1303,
46 };
47
48 struct sma1303_pll_match {
49 char *input_clk_name;
50 char *output_clk_name;
51 unsigned int input_clk;
52 unsigned int post_n;
53 unsigned int n;
54 unsigned int vco;
55 unsigned int p_cp;
56 };
57
58 struct sma1303_priv {
59 enum sma1303_type devtype;
60 struct attribute_group *attr_grp;
61 struct delayed_work check_fault_work;
62 struct device *dev;
63 struct kobject *kobj;
64 struct regmap *regmap;
65 struct sma1303_pll_match *pll_matches;
66 bool amp_power_status;
67 bool force_mute_status;
68 int num_of_pll_matches;
69 int retry_cnt;
70 unsigned int amp_mode;
71 unsigned int cur_vol;
72 unsigned int format;
73 unsigned int frame_size;
74 unsigned int init_vol;
75 unsigned int last_bclk;
76 unsigned int last_ocp_val;
77 unsigned int last_over_temp;
78 unsigned int rev_num;
79 unsigned int sys_clk_id;
80 unsigned int tdm_slot_rx;
81 unsigned int tdm_slot_tx;
82 unsigned int tsdw_cnt;
83 long check_fault_period;
84 long check_fault_status;
85 };
86
87 static struct sma1303_pll_match sma1303_pll_matches[] = {
88 PLL_MATCH("1.411MHz", "24.595MHz", 1411200, 0x07, 0xF4, 0x8B, 0x03),
89 PLL_MATCH("1.536MHz", "24.576MHz", 1536000, 0x07, 0xE0, 0x8B, 0x03),
90 PLL_MATCH("3.072MHz", "24.576MHz", 3072000, 0x07, 0x70, 0x8B, 0x03),
91 PLL_MATCH("6.144MHz", "24.576MHz", 6144000, 0x07, 0x70, 0x8B, 0x07),
92 PLL_MATCH("12.288MHz", "24.576MHz", 12288000, 0x07, 0x70, 0x8B, 0x0B),
93 PLL_MATCH("19.2MHz", "24.343MHz", 19200000, 0x07, 0x47, 0x8B, 0x0A),
94 PLL_MATCH("24.576MHz", "24.576MHz", 24576000, 0x07, 0x70, 0x8B, 0x0F),
95 };
96
97 static int sma1303_startup(struct snd_soc_component *);
98 static int sma1303_shutdown(struct snd_soc_component *);
99
100 static const struct reg_default sma1303_reg_def[] = {
101 { 0x00, 0x80 },
102 { 0x01, 0x00 },
103 { 0x02, 0x00 },
104 { 0x03, 0x11 },
105 { 0x04, 0x17 },
106 { 0x09, 0x00 },
107 { 0x0A, 0x31 },
108 { 0x0B, 0x98 },
109 { 0x0C, 0x84 },
110 { 0x0D, 0x07 },
111 { 0x0E, 0x3F },
112 { 0x10, 0x00 },
113 { 0x11, 0x00 },
114 { 0x12, 0x00 },
115 { 0x14, 0x5C },
116 { 0x15, 0x01 },
117 { 0x16, 0x0F },
118 { 0x17, 0x0F },
119 { 0x18, 0x0F },
120 { 0x19, 0x00 },
121 { 0x1A, 0x00 },
122 { 0x1B, 0x00 },
123 { 0x23, 0x19 },
124 { 0x24, 0x00 },
125 { 0x25, 0x00 },
126 { 0x26, 0x04 },
127 { 0x33, 0x00 },
128 { 0x36, 0x92 },
129 { 0x37, 0x27 },
130 { 0x3B, 0x5A },
131 { 0x3C, 0x20 },
132 { 0x3D, 0x00 },
133 { 0x3E, 0x03 },
134 { 0x3F, 0x0C },
135 { 0x8B, 0x07 },
136 { 0x8C, 0x70 },
137 { 0x8D, 0x8B },
138 { 0x8E, 0x6F },
139 { 0x8F, 0x03 },
140 { 0x90, 0x26 },
141 { 0x91, 0x42 },
142 { 0x92, 0xE0 },
143 { 0x94, 0x35 },
144 { 0x95, 0x0C },
145 { 0x96, 0x42 },
146 { 0x97, 0x95 },
147 { 0xA0, 0x00 },
148 { 0xA1, 0x3B },
149 { 0xA2, 0xC8 },
150 { 0xA3, 0x28 },
151 { 0xA4, 0x40 },
152 { 0xA5, 0x01 },
153 { 0xA6, 0x41 },
154 { 0xA7, 0x00 },
155 };
156
sma1303_readable_register(struct device * dev,unsigned int reg)157 static bool sma1303_readable_register(struct device *dev, unsigned int reg)
158 {
159 bool result;
160
161 if (reg > SMA1303_FF_DEVICE_INDEX)
162 return false;
163
164 switch (reg) {
165 case SMA1303_00_SYSTEM_CTRL ... SMA1303_04_INPUT1_CTRL4:
166 case SMA1303_09_OUTPUT_CTRL ... SMA1303_0E_MUTE_VOL_CTRL:
167 case SMA1303_10_SYSTEM_CTRL1 ... SMA1303_12_SYSTEM_CTRL3:
168 case SMA1303_14_MODULATOR ... SMA1303_1B_BASS_SPK7:
169 case SMA1303_23_COMP_LIM1 ... SMA1303_26_COMP_LIM4:
170 case SMA1303_33_SDM_CTRL ... SMA1303_34_OTP_DATA1:
171 case SMA1303_36_PROTECTION ... SMA1303_38_OTP_TRM0:
172 case SMA1303_3B_TEST1 ... SMA1303_3F_ATEST2:
173 case SMA1303_8B_PLL_POST_N ... SMA1303_92_FDPEC_CTRL:
174 case SMA1303_94_BOOST_CTRL1 ... SMA1303_97_BOOST_CTRL4:
175 case SMA1303_A0_PAD_CTRL0 ... SMA1303_A7_CLK_MON:
176 case SMA1303_FA_STATUS1 ... SMA1303_FB_STATUS2:
177 result = true;
178 break;
179 case SMA1303_FF_DEVICE_INDEX:
180 result = true;
181 break;
182 default:
183 result = false;
184 break;
185 }
186 return result;
187 }
188
sma1303_writeable_register(struct device * dev,unsigned int reg)189 static bool sma1303_writeable_register(struct device *dev, unsigned int reg)
190 {
191 bool result;
192
193 if (reg > SMA1303_FF_DEVICE_INDEX)
194 return false;
195
196 switch (reg) {
197 case SMA1303_00_SYSTEM_CTRL ... SMA1303_04_INPUT1_CTRL4:
198 case SMA1303_09_OUTPUT_CTRL ... SMA1303_0E_MUTE_VOL_CTRL:
199 case SMA1303_10_SYSTEM_CTRL1 ... SMA1303_12_SYSTEM_CTRL3:
200 case SMA1303_14_MODULATOR ... SMA1303_1B_BASS_SPK7:
201 case SMA1303_23_COMP_LIM1 ... SMA1303_26_COMP_LIM4:
202 case SMA1303_33_SDM_CTRL:
203 case SMA1303_36_PROTECTION ... SMA1303_37_SLOPE_CTRL:
204 case SMA1303_3B_TEST1 ... SMA1303_3F_ATEST2:
205 case SMA1303_8B_PLL_POST_N ... SMA1303_92_FDPEC_CTRL:
206 case SMA1303_94_BOOST_CTRL1 ... SMA1303_97_BOOST_CTRL4:
207 case SMA1303_A0_PAD_CTRL0 ... SMA1303_A7_CLK_MON:
208 result = true;
209 break;
210 default:
211 result = false;
212 break;
213 }
214 return result;
215 }
216
sma1303_volatile_register(struct device * dev,unsigned int reg)217 static bool sma1303_volatile_register(struct device *dev, unsigned int reg)
218 {
219 bool result;
220
221 switch (reg) {
222 case SMA1303_FA_STATUS1 ... SMA1303_FB_STATUS2:
223 result = true;
224 break;
225 case SMA1303_FF_DEVICE_INDEX:
226 result = true;
227 break;
228 default:
229 result = false;
230 break;
231 }
232 return result;
233 }
234
235 static const DECLARE_TLV_DB_SCALE(sma1303_spk_tlv, -6000, 50, 0);
236
sma1303_regmap_write(struct sma1303_priv * sma1303,unsigned int reg,unsigned int val)237 static int sma1303_regmap_write(struct sma1303_priv *sma1303,
238 unsigned int reg, unsigned int val)
239 {
240 int ret = 0;
241 int cnt = sma1303->retry_cnt;
242
243 while (cnt--) {
244 ret = regmap_write(sma1303->regmap, reg, val);
245 if (ret < 0) {
246 dev_err(sma1303->dev,
247 "Failed to write [0x%02X]\n", reg);
248 } else
249 break;
250 }
251 return ret;
252 }
253
sma1303_regmap_update_bits(struct sma1303_priv * sma1303,unsigned int reg,unsigned int mask,unsigned int val,bool * change)254 static int sma1303_regmap_update_bits(struct sma1303_priv *sma1303,
255 unsigned int reg, unsigned int mask, unsigned int val, bool *change)
256 {
257 int ret = 0;
258 int cnt = sma1303->retry_cnt;
259
260 while (cnt--) {
261 ret = regmap_update_bits_check(sma1303->regmap, reg,
262 mask, val, change);
263 if (ret < 0) {
264 dev_err(sma1303->dev,
265 "Failed to update [0x%02X]\n", reg);
266 } else
267 break;
268 }
269 return ret;
270 }
271
sma1303_regmap_read(struct sma1303_priv * sma1303,unsigned int reg,unsigned int * val)272 static int sma1303_regmap_read(struct sma1303_priv *sma1303,
273 unsigned int reg, unsigned int *val)
274 {
275 int ret = 0;
276 int cnt = sma1303->retry_cnt;
277
278 while (cnt--) {
279 ret = regmap_read(sma1303->regmap, reg, val);
280 if (ret < 0) {
281 dev_err(sma1303->dev,
282 "Failed to read [0x%02X]\n", reg);
283 } else
284 break;
285 }
286 return ret;
287 }
288
289 static const char * const sma1303_aif_in_source_text[] = {
290 "Mono", "Left", "Right"};
291 static const char * const sma1303_aif_out_source_text[] = {
292 "Disable", "After_FmtC", "After_Mixer", "After_DSP", "After_Post",
293 "Clk_PLL", "Clk_OSC"};
294 static const char * const sma1303_tdm_slot_text[] = {
295 "Slot0", "Slot1", "Slot2", "Slot3",
296 "Slot4", "Slot5", "Slot6", "Slot7"};
297
298 static const struct soc_enum sma1303_aif_in_source_enum =
299 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1303_aif_in_source_text),
300 sma1303_aif_in_source_text);
301 static const struct soc_enum sma1303_aif_out_source_enum =
302 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1303_aif_out_source_text),
303 sma1303_aif_out_source_text);
304 static const struct soc_enum sma1303_tdm_slot_enum =
305 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1303_tdm_slot_text),
306 sma1303_tdm_slot_text);
307
sma1303_force_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)308 static int sma1303_force_mute_get(struct snd_kcontrol *kcontrol,
309 struct snd_ctl_elem_value *ucontrol)
310 {
311 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
312 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
313
314 ucontrol->value.integer.value[0] = (int)sma1303->force_mute_status;
315 dev_dbg(sma1303->dev, "%s : Force Mute %s\n", __func__,
316 sma1303->force_mute_status ? "ON" : "OFF");
317
318 return 0;
319 }
320
sma1303_force_mute_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)321 static int sma1303_force_mute_put(struct snd_kcontrol *kcontrol,
322 struct snd_ctl_elem_value *ucontrol)
323 {
324 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
325 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
326 bool change = false, val = (bool)ucontrol->value.integer.value[0];
327
328 if (sma1303->force_mute_status == val)
329 change = false;
330 else {
331 change = true;
332 sma1303->force_mute_status = val;
333 }
334 dev_dbg(sma1303->dev, "%s : Force Mute %s\n", __func__,
335 sma1303->force_mute_status ? "ON" : "OFF");
336
337 return change;
338 }
339
sma1303_postscaler_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)340 static int sma1303_postscaler_get(struct snd_kcontrol *kcontrol,
341 struct snd_ctl_elem_value *ucontrol)
342 {
343 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
344 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
345 int val, ret;
346
347 ret = sma1303_regmap_read(sma1303, SMA1303_90_POSTSCALER, &val);
348 if (ret < 0)
349 return -EINVAL;
350
351 ucontrol->value.integer.value[0] = (val & 0x7E) >> 1;
352
353 return 0;
354 }
355
sma1303_postscaler_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)356 static int sma1303_postscaler_put(struct snd_kcontrol *kcontrol,
357 struct snd_ctl_elem_value *ucontrol)
358 {
359 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
360 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
361 int ret, val = (int)ucontrol->value.integer.value[0];
362 bool change;
363
364 ret = sma1303_regmap_update_bits(sma1303,
365 SMA1303_90_POSTSCALER, 0x7E, (val << 1), &change);
366 if (ret < 0)
367 return -EINVAL;
368
369 return change;
370 }
371
sma1303_tdm_slot_rx_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)372 static int sma1303_tdm_slot_rx_get(struct snd_kcontrol *kcontrol,
373 struct snd_ctl_elem_value *ucontrol)
374 {
375 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
376 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
377 int val, ret;
378
379 ret = sma1303_regmap_read(sma1303, SMA1303_A5_TDM1, &val);
380 if (ret < 0)
381 return -EINVAL;
382
383 ucontrol->value.integer.value[0] = (val & 0x38) >> 3;
384 sma1303->tdm_slot_rx = ucontrol->value.integer.value[0];
385
386 return 0;
387 }
388
sma1303_tdm_slot_rx_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)389 static int sma1303_tdm_slot_rx_put(struct snd_kcontrol *kcontrol,
390 struct snd_ctl_elem_value *ucontrol)
391 {
392 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
393 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
394 int ret, val = (int)ucontrol->value.integer.value[0];
395 bool change;
396
397 ret = sma1303_regmap_update_bits(sma1303,
398 SMA1303_A5_TDM1, 0x38, (val << 3), &change);
399 if (ret < 0)
400 return -EINVAL;
401
402 return change;
403 }
404
sma1303_tdm_slot_tx_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)405 static int sma1303_tdm_slot_tx_get(struct snd_kcontrol *kcontrol,
406 struct snd_ctl_elem_value *ucontrol)
407 {
408 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
409 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
410 int val, ret;
411
412 ret = sma1303_regmap_read(sma1303, SMA1303_A6_TDM2, &val);
413 if (ret < 0)
414 return -EINVAL;
415
416 ucontrol->value.integer.value[0] = (val & 0x38) >> 3;
417 sma1303->tdm_slot_tx = ucontrol->value.integer.value[0];
418
419 return 0;
420 }
421
sma1303_tdm_slot_tx_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)422 static int sma1303_tdm_slot_tx_put(struct snd_kcontrol *kcontrol,
423 struct snd_ctl_elem_value *ucontrol)
424 {
425 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
426 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
427 int ret, val = (int)ucontrol->value.integer.value[0];
428 bool change;
429
430 ret = sma1303_regmap_update_bits(sma1303,
431 SMA1303_A6_TDM2, 0x38, (val << 3), &change);
432 if (ret < 0)
433 return -EINVAL;
434
435 return change;
436 }
437
sma1303_startup(struct snd_soc_component * component)438 static int sma1303_startup(struct snd_soc_component *component)
439 {
440 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
441 bool change = false, temp = false;
442
443 sma1303_regmap_update_bits(sma1303, SMA1303_8E_PLL_CTRL,
444 SMA1303_PLL_PD2_MASK, SMA1303_PLL_OPERATION2, &temp);
445 if (temp == true)
446 change = true;
447
448 sma1303_regmap_update_bits(sma1303, SMA1303_00_SYSTEM_CTRL,
449 SMA1303_POWER_MASK, SMA1303_POWER_ON, &temp);
450 if (temp == true)
451 change = true;
452
453 if (sma1303->amp_mode == SMA1303_MONO) {
454 sma1303_regmap_update_bits(sma1303,
455 SMA1303_10_SYSTEM_CTRL1,
456 SMA1303_SPK_MODE_MASK,
457 SMA1303_SPK_MONO,
458 &temp);
459 if (temp == true)
460 change = true;
461
462 } else {
463 sma1303_regmap_update_bits(sma1303,
464 SMA1303_10_SYSTEM_CTRL1,
465 SMA1303_SPK_MODE_MASK,
466 SMA1303_SPK_STEREO,
467 &temp);
468 if (temp == true)
469 change = true;
470 }
471
472 if (sma1303->check_fault_status) {
473 if (sma1303->check_fault_period > 0)
474 queue_delayed_work(system_freezable_wq,
475 &sma1303->check_fault_work,
476 sma1303->check_fault_period * HZ);
477 else
478 queue_delayed_work(system_freezable_wq,
479 &sma1303->check_fault_work,
480 CHECK_PERIOD_TIME * HZ);
481 }
482
483 sma1303->amp_power_status = true;
484
485 return change;
486 }
487
sma1303_shutdown(struct snd_soc_component * component)488 static int sma1303_shutdown(struct snd_soc_component *component)
489 {
490 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
491 bool change = false, temp = false;
492
493 cancel_delayed_work_sync(&sma1303->check_fault_work);
494
495 sma1303_regmap_update_bits(sma1303, SMA1303_10_SYSTEM_CTRL1,
496 SMA1303_SPK_MODE_MASK, SMA1303_SPK_OFF, &temp);
497 if (temp == true)
498 change = true;
499
500 sma1303_regmap_update_bits(sma1303, SMA1303_00_SYSTEM_CTRL,
501 SMA1303_POWER_MASK, SMA1303_POWER_OFF, &temp);
502 if (temp == true)
503 change = true;
504 sma1303_regmap_update_bits(sma1303, SMA1303_8E_PLL_CTRL,
505 SMA1303_PLL_PD2_MASK, SMA1303_PLL_PD2, &temp);
506 if (temp == true)
507 change = true;
508
509 sma1303->amp_power_status = false;
510
511 return change;
512 }
513
sma1303_aif_in_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)514 static int sma1303_aif_in_event(struct snd_soc_dapm_widget *w,
515 struct snd_kcontrol *kcontrol, int event)
516 {
517 struct snd_soc_component *component =
518 snd_soc_dapm_to_component(w->dapm);
519 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
520 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]);
521 int ret = 0;
522 bool change = false, temp = false;
523
524 switch (event) {
525 case SND_SOC_DAPM_PRE_PMU:
526 switch (mux) {
527 case 0:
528 ret += sma1303_regmap_update_bits(sma1303,
529 SMA1303_11_SYSTEM_CTRL2,
530 SMA1303_MONOMIX_MASK,
531 SMA1303_MONOMIX_ON,
532 &change);
533 sma1303->amp_mode = SMA1303_MONO;
534 break;
535 case 1:
536 ret += sma1303_regmap_update_bits(sma1303,
537 SMA1303_11_SYSTEM_CTRL2,
538 SMA1303_MONOMIX_MASK,
539 SMA1303_MONOMIX_OFF,
540 &temp);
541 if (temp == true)
542 change = true;
543 ret += sma1303_regmap_update_bits(sma1303,
544 SMA1303_11_SYSTEM_CTRL2,
545 SMA1303_LR_DATA_SW_MASK,
546 SMA1303_LR_DATA_SW_NORMAL,
547 &temp);
548 if (temp == true)
549 change = true;
550 sma1303->amp_mode = SMA1303_STEREO;
551 break;
552 case 2:
553 ret += sma1303_regmap_update_bits(sma1303,
554 SMA1303_11_SYSTEM_CTRL2,
555 SMA1303_MONOMIX_MASK,
556 SMA1303_MONOMIX_OFF,
557 &temp);
558 if (temp == true)
559 change = true;
560 ret += sma1303_regmap_update_bits(sma1303,
561 SMA1303_11_SYSTEM_CTRL2,
562 SMA1303_LR_DATA_SW_MASK,
563 SMA1303_LR_DATA_SW_SWAP,
564 &temp);
565 if (temp == true)
566 change = true;
567 sma1303->amp_mode = SMA1303_STEREO;
568 break;
569 default:
570 dev_err(sma1303->dev, "%s : Invalid value (%d)\n",
571 __func__, mux);
572 return -EINVAL;
573 }
574
575 dev_dbg(sma1303->dev, "%s : Source : %s\n", __func__,
576 sma1303_aif_in_source_text[mux]);
577 break;
578 }
579 if (ret < 0)
580 return -EINVAL;
581 return change;
582 }
583
sma1303_aif_out_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)584 static int sma1303_aif_out_event(struct snd_soc_dapm_widget *w,
585 struct snd_kcontrol *kcontrol, int event)
586 {
587 struct snd_soc_component *component =
588 snd_soc_dapm_to_component(w->dapm);
589 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
590 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]);
591 int ret = 0;
592 bool change = false, temp = false;
593
594 switch (event) {
595 case SND_SOC_DAPM_PRE_PMU:
596 switch (mux) {
597 case 0:
598 ret += sma1303_regmap_update_bits(sma1303,
599 SMA1303_A3_TOP_MAN2,
600 SMA1303_TEST_CLKO_EN_MASK,
601 SMA1303_NORMAL_SDO,
602 &temp);
603 if (temp == true)
604 change = true;
605 ret += sma1303_regmap_update_bits(sma1303,
606 SMA1303_09_OUTPUT_CTRL,
607 SMA1303_PORT_OUT_SEL_MASK,
608 SMA1303_OUT_SEL_DISABLE,
609 &temp);
610 if (temp == true)
611 change = true;
612 break;
613 case 1:
614 ret += sma1303_regmap_update_bits(sma1303,
615 SMA1303_A3_TOP_MAN2,
616 SMA1303_TEST_CLKO_EN_MASK,
617 SMA1303_NORMAL_SDO,
618 &temp);
619 if (temp == true)
620 change = true;
621 ret += sma1303_regmap_update_bits(sma1303,
622 SMA1303_09_OUTPUT_CTRL,
623 SMA1303_PORT_OUT_SEL_MASK,
624 SMA1303_FORMAT_CONVERTER,
625 &temp);
626 if (temp == true)
627 change = true;
628 break;
629 case 2:
630 ret += sma1303_regmap_update_bits(sma1303,
631 SMA1303_A3_TOP_MAN2,
632 SMA1303_TEST_CLKO_EN_MASK,
633 SMA1303_NORMAL_SDO,
634 &temp);
635 if (temp == true)
636 change = true;
637 ret += sma1303_regmap_update_bits(sma1303,
638 SMA1303_09_OUTPUT_CTRL,
639 SMA1303_PORT_OUT_SEL_MASK,
640 SMA1303_MIXER_OUTPUT,
641 &temp);
642 if (temp == true)
643 change = true;
644 break;
645 case 3:
646 ret += sma1303_regmap_update_bits(sma1303,
647 SMA1303_A3_TOP_MAN2,
648 SMA1303_TEST_CLKO_EN_MASK,
649 SMA1303_NORMAL_SDO,
650 &temp);
651 if (temp == true)
652 change = true;
653 ret += sma1303_regmap_update_bits(sma1303,
654 SMA1303_09_OUTPUT_CTRL,
655 SMA1303_PORT_OUT_SEL_MASK,
656 SMA1303_SPEAKER_PATH,
657 &temp);
658 if (temp == true)
659 change = true;
660 break;
661 case 4:
662 ret += sma1303_regmap_update_bits(sma1303,
663 SMA1303_A3_TOP_MAN2,
664 SMA1303_TEST_CLKO_EN_MASK,
665 SMA1303_NORMAL_SDO,
666 &temp);
667 if (temp == true)
668 change = true;
669 ret += sma1303_regmap_update_bits(sma1303,
670 SMA1303_09_OUTPUT_CTRL,
671 SMA1303_PORT_OUT_SEL_MASK,
672 SMA1303_POSTSCALER_OUTPUT,
673 &temp);
674 if (temp == true)
675 change = true;
676 break;
677 case 5:
678 ret += sma1303_regmap_update_bits(sma1303,
679 SMA1303_A3_TOP_MAN2,
680 SMA1303_TEST_CLKO_EN_MASK,
681 SMA1303_CLK_OUT_SDO,
682 &temp);
683 if (temp == true)
684 change = true;
685 ret += sma1303_regmap_update_bits(sma1303,
686 SMA1303_A3_TOP_MAN2,
687 SMA1303_MON_OSC_PLL_MASK,
688 SMA1303_PLL_SDO,
689 &temp);
690 if (temp == true)
691 change = true;
692 break;
693 case 6:
694 ret += sma1303_regmap_update_bits(sma1303,
695 SMA1303_A3_TOP_MAN2,
696 SMA1303_TEST_CLKO_EN_MASK,
697 SMA1303_CLK_OUT_SDO,
698 &temp);
699 if (temp == true)
700 change = true;
701 ret += sma1303_regmap_update_bits(sma1303,
702 SMA1303_A3_TOP_MAN2,
703 SMA1303_MON_OSC_PLL_MASK,
704 SMA1303_OSC_SDO,
705 &temp);
706 if (temp == true)
707 change = true;
708 break;
709 default:
710 dev_err(sma1303->dev, "%s : Invalid value (%d)\n",
711 __func__, mux);
712 return -EINVAL;
713 }
714
715 dev_dbg(sma1303->dev, "%s : Source : %s\n", __func__,
716 sma1303_aif_out_source_text[mux]);
717 break;
718 }
719 if (ret < 0)
720 return -EINVAL;
721 return change;
722 }
723
sma1303_sdo_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)724 static int sma1303_sdo_event(struct snd_soc_dapm_widget *w,
725 struct snd_kcontrol *kcontrol, int event)
726 {
727 struct snd_soc_component *component =
728 snd_soc_dapm_to_component(w->dapm);
729 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
730 int ret = 0;
731 bool change = false, temp = false;
732
733 switch (event) {
734 case SND_SOC_DAPM_PRE_PMU:
735 dev_dbg(sma1303->dev,
736 "%s : SND_SOC_DAPM_PRE_PMU\n", __func__);
737 ret += sma1303_regmap_update_bits(sma1303,
738 SMA1303_09_OUTPUT_CTRL,
739 SMA1303_PORT_CONFIG_MASK,
740 SMA1303_OUTPUT_PORT_ENABLE,
741 &temp);
742 if (temp == true)
743 change = true;
744 ret += sma1303_regmap_update_bits(sma1303,
745 SMA1303_A3_TOP_MAN2,
746 SMA1303_SDO_OUTPUT_MASK,
747 SMA1303_NORMAL_OUT,
748 &temp);
749 if (temp == true)
750 change = true;
751 break;
752 case SND_SOC_DAPM_POST_PMD:
753 dev_dbg(sma1303->dev,
754 "%s : SND_SOC_DAPM_POST_PMD\n", __func__);
755 ret += sma1303_regmap_update_bits(sma1303,
756 SMA1303_09_OUTPUT_CTRL,
757 SMA1303_PORT_CONFIG_MASK,
758 SMA1303_INPUT_PORT_ONLY,
759 &temp);
760 if (temp == true)
761 change = true;
762 ret += sma1303_regmap_update_bits(sma1303,
763 SMA1303_A3_TOP_MAN2,
764 SMA1303_SDO_OUTPUT_MASK,
765 SMA1303_HIGH_Z_OUT,
766 &temp);
767 if (temp == true)
768 change = true;
769 break;
770 }
771 if (ret < 0)
772 return -EINVAL;
773 return change;
774 }
775
sma1303_post_scaler_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)776 static int sma1303_post_scaler_event(struct snd_soc_dapm_widget *w,
777 struct snd_kcontrol *kcontrol, int event)
778 {
779 struct snd_soc_component *component =
780 snd_soc_dapm_to_component(w->dapm);
781 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
782 int ret = 0;
783 bool change = false;
784
785 switch (event) {
786 case SND_SOC_DAPM_PRE_PMU:
787 dev_dbg(sma1303->dev,
788 "%s : SND_SOC_DAPM_PRE_PMU\n", __func__);
789 ret += sma1303_regmap_update_bits(sma1303,
790 SMA1303_90_POSTSCALER,
791 SMA1303_BYP_POST_MASK,
792 SMA1303_EN_POST_SCALER,
793 &change);
794 break;
795 case SND_SOC_DAPM_POST_PMD:
796 dev_dbg(sma1303->dev,
797 "%s : SND_SOC_DAPM_POST_PMD\n", __func__);
798 ret += sma1303_regmap_update_bits(sma1303,
799 SMA1303_90_POSTSCALER,
800 SMA1303_BYP_POST_MASK,
801 SMA1303_BYP_POST_SCALER,
802 &change);
803 break;
804 }
805 if (ret < 0)
806 return -EINVAL;
807 return change;
808 }
809
sma1303_power_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)810 static int sma1303_power_event(struct snd_soc_dapm_widget *w,
811 struct snd_kcontrol *kcontrol, int event)
812 {
813 struct snd_soc_component *component =
814 snd_soc_dapm_to_component(w->dapm);
815 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
816 int ret = 0;
817
818 switch (event) {
819 case SND_SOC_DAPM_POST_PMU:
820 dev_dbg(sma1303->dev,
821 "%s : SND_SOC_DAPM_POST_PMU\n", __func__);
822 ret = sma1303_startup(component);
823 break;
824 case SND_SOC_DAPM_PRE_PMD:
825 dev_dbg(sma1303->dev,
826 "%s : SND_SOC_DAPM_PRE_PMD\n", __func__);
827 ret = sma1303_shutdown(component);
828 break;
829 }
830 return ret;
831 }
832
833 static const struct snd_kcontrol_new sma1303_aif_in_source_control =
834 SOC_DAPM_ENUM("AIF IN Source", sma1303_aif_in_source_enum);
835 static const struct snd_kcontrol_new sma1303_aif_out_source_control =
836 SOC_DAPM_ENUM("AIF OUT Source", sma1303_aif_out_source_enum);
837 static const struct snd_kcontrol_new sma1303_sdo_control =
838 SOC_DAPM_SINGLE_VIRT("Switch", 1);
839 static const struct snd_kcontrol_new sma1303_post_scaler_control =
840 SOC_DAPM_SINGLE_VIRT("Switch", 1);
841 static const struct snd_kcontrol_new sma1303_enable_control =
842 SOC_DAPM_SINGLE_VIRT("Switch", 1);
843
844 static const struct snd_kcontrol_new sma1303_snd_controls[] = {
845 SOC_SINGLE_TLV("Speaker Volume", SMA1303_0A_SPK_VOL,
846 0, 167, 1, sma1303_spk_tlv),
847 SOC_SINGLE_BOOL_EXT("Force Mute Switch", 0,
848 sma1303_force_mute_get, sma1303_force_mute_put),
849 SOC_SINGLE_EXT("Postscaler Gain", SMA1303_90_POSTSCALER, 1, 0x30, 0,
850 sma1303_postscaler_get, sma1303_postscaler_put),
851 SOC_ENUM_EXT("TDM RX Slot Position", sma1303_tdm_slot_enum,
852 sma1303_tdm_slot_rx_get, sma1303_tdm_slot_rx_put),
853 SOC_ENUM_EXT("TDM TX Slot Position", sma1303_tdm_slot_enum,
854 sma1303_tdm_slot_tx_get, sma1303_tdm_slot_tx_put),
855 };
856
857 static const struct snd_soc_dapm_widget sma1303_dapm_widgets[] = {
858 /* platform domain */
859 SND_SOC_DAPM_OUTPUT("SPK"),
860 SND_SOC_DAPM_INPUT("SDO"),
861
862 /* path domain */
863 SND_SOC_DAPM_MUX_E("AIF IN Source", SND_SOC_NOPM, 0, 0,
864 &sma1303_aif_in_source_control,
865 sma1303_aif_in_event,
866 SND_SOC_DAPM_PRE_PMU),
867 SND_SOC_DAPM_MUX_E("AIF OUT Source", SND_SOC_NOPM, 0, 0,
868 &sma1303_aif_out_source_control,
869 sma1303_aif_out_event,
870 SND_SOC_DAPM_PRE_PMU),
871 SND_SOC_DAPM_SWITCH_E("SDO Enable", SND_SOC_NOPM, 0, 0,
872 &sma1303_sdo_control,
873 sma1303_sdo_event,
874 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
875 SND_SOC_DAPM_MIXER("Entry", SND_SOC_NOPM, 0, 0, NULL, 0),
876 SND_SOC_DAPM_SWITCH_E("Post Scaler", SND_SOC_NOPM, 0, 1,
877 &sma1303_post_scaler_control,
878 sma1303_post_scaler_event,
879 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
880 SND_SOC_DAPM_OUT_DRV_E("AMP Power", SND_SOC_NOPM, 0, 0, NULL, 0,
881 sma1303_power_event,
882 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
883 SND_SOC_DAPM_SWITCH("AMP Enable", SND_SOC_NOPM, 0, 1,
884 &sma1303_enable_control),
885
886 /* stream domain */
887 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0),
888 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0),
889 };
890
891 static const struct snd_soc_dapm_route sma1303_audio_map[] = {
892 /* Playback */
893 {"AIF IN Source", "Mono", "AIF IN"},
894 {"AIF IN Source", "Left", "AIF IN"},
895 {"AIF IN Source", "Right", "AIF IN"},
896
897 {"SDO Enable", "Switch", "AIF IN"},
898 {"AIF OUT Source", "Disable", "SDO Enable"},
899 {"AIF OUT Source", "After_FmtC", "SDO Enable"},
900 {"AIF OUT Source", "After_Mixer", "SDO Enable"},
901 {"AIF OUT Source", "After_DSP", "SDO Enable"},
902 {"AIF OUT Source", "After_Post", "SDO Enable"},
903 {"AIF OUT Source", "Clk_PLL", "SDO Enable"},
904 {"AIF OUT Source", "Clk_OSC", "SDO Enable"},
905
906 {"Entry", NULL, "AIF OUT Source"},
907 {"Entry", NULL, "AIF IN Source"},
908
909 {"Post Scaler", "Switch", "Entry"},
910 {"AMP Power", NULL, "Entry"},
911 {"AMP Power", NULL, "Entry"},
912
913 {"AMP Enable", "Switch", "AMP Power"},
914 {"SPK", NULL, "AMP Enable"},
915
916 /* Capture */
917 {"AIF OUT", NULL, "AMP Enable"},
918 };
919
sma1303_setup_pll(struct snd_soc_component * component,unsigned int bclk)920 static int sma1303_setup_pll(struct snd_soc_component *component,
921 unsigned int bclk)
922 {
923 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
924
925 int i = 0, ret = 0;
926
927 dev_dbg(component->dev, "%s : BCLK = %dHz\n",
928 __func__, bclk);
929
930 if (sma1303->sys_clk_id == SMA1303_PLL_CLKIN_MCLK) {
931 dev_dbg(component->dev, "%s : MCLK is not supported\n",
932 __func__);
933 } else if (sma1303->sys_clk_id == SMA1303_PLL_CLKIN_BCLK) {
934 for (i = 0; i < sma1303->num_of_pll_matches; i++) {
935 if (sma1303->pll_matches[i].input_clk == bclk)
936 break;
937 }
938 if (i == sma1303->num_of_pll_matches) {
939 dev_dbg(component->dev, "%s : No matching value between pll table and SCK\n",
940 __func__);
941 return -EINVAL;
942 }
943
944 ret += sma1303_regmap_update_bits(sma1303,
945 SMA1303_A2_TOP_MAN1,
946 SMA1303_PLL_PD_MASK|SMA1303_PLL_REF_CLK_MASK,
947 SMA1303_PLL_OPERATION|SMA1303_PLL_SCK,
948 NULL);
949 }
950
951 ret += sma1303_regmap_write(sma1303,
952 SMA1303_8B_PLL_POST_N,
953 sma1303->pll_matches[i].post_n);
954
955 ret += sma1303_regmap_write(sma1303,
956 SMA1303_8C_PLL_N,
957 sma1303->pll_matches[i].n);
958
959 ret += sma1303_regmap_write(sma1303,
960 SMA1303_8D_PLL_A_SETTING,
961 sma1303->pll_matches[i].vco);
962
963 ret += sma1303_regmap_write(sma1303,
964 SMA1303_8F_PLL_P_CP,
965 sma1303->pll_matches[i].p_cp);
966 if (ret < 0)
967 return -EINVAL;
968
969 return 0;
970 }
971
sma1303_dai_hw_params_amp(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)972 static int sma1303_dai_hw_params_amp(struct snd_pcm_substream *substream,
973 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
974 {
975 struct snd_soc_component *component = dai->component;
976 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
977 unsigned int bclk = 0;
978 int ret = 0;
979
980 if (sma1303->format == SND_SOC_DAIFMT_DSP_A)
981 bclk = params_rate(params) * sma1303->frame_size;
982 else
983 bclk = params_rate(params) * params_physical_width(params)
984 * params_channels(params);
985
986 dev_dbg(component->dev,
987 "%s : rate = %d : bit size = %d : channel = %d\n",
988 __func__, params_rate(params), params_width(params),
989 params_channels(params));
990
991 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
992 if (sma1303->sys_clk_id == SMA1303_PLL_CLKIN_BCLK) {
993 if (sma1303->last_bclk != bclk) {
994 sma1303_setup_pll(component, bclk);
995 sma1303->last_bclk = bclk;
996 }
997 }
998
999 switch (params_rate(params)) {
1000 case 8000:
1001 case 12000:
1002 case 16000:
1003 case 24000:
1004 case 32000:
1005 case 44100:
1006 case 48000:
1007 case 96000:
1008 ret += sma1303_regmap_update_bits(sma1303,
1009 SMA1303_A2_TOP_MAN1,
1010 SMA1303_DAC_DN_CONV_MASK,
1011 SMA1303_DAC_DN_CONV_DISABLE,
1012 NULL);
1013
1014 ret += sma1303_regmap_update_bits(sma1303,
1015 SMA1303_01_INPUT1_CTRL1,
1016 SMA1303_LEFTPOL_MASK,
1017 SMA1303_LOW_FIRST_CH,
1018 NULL);
1019 break;
1020
1021 case 192000:
1022 ret += sma1303_regmap_update_bits(sma1303,
1023 SMA1303_A2_TOP_MAN1,
1024 SMA1303_DAC_DN_CONV_MASK,
1025 SMA1303_DAC_DN_CONV_ENABLE,
1026 NULL);
1027
1028 ret += sma1303_regmap_update_bits(sma1303,
1029 SMA1303_01_INPUT1_CTRL1,
1030 SMA1303_LEFTPOL_MASK,
1031 SMA1303_HIGH_FIRST_CH,
1032 NULL);
1033 break;
1034
1035 default:
1036 dev_err(component->dev, "%s not support rate : %d\n",
1037 __func__, params_rate(params));
1038
1039 return -EINVAL;
1040 }
1041
1042 } else {
1043
1044 switch (params_format(params)) {
1045
1046 case SNDRV_PCM_FORMAT_S16_LE:
1047 dev_dbg(component->dev,
1048 "%s set format SNDRV_PCM_FORMAT_S16_LE\n",
1049 __func__);
1050 ret += sma1303_regmap_update_bits(sma1303,
1051 SMA1303_A4_TOP_MAN3,
1052 SMA1303_SCK_RATE_MASK,
1053 SMA1303_SCK_32FS,
1054 NULL);
1055 break;
1056
1057 case SNDRV_PCM_FORMAT_S24_LE:
1058 dev_dbg(component->dev,
1059 "%s set format SNDRV_PCM_FORMAT_S24_LE\n",
1060 __func__);
1061 ret += sma1303_regmap_update_bits(sma1303,
1062 SMA1303_A4_TOP_MAN3,
1063 SMA1303_SCK_RATE_MASK,
1064 SMA1303_SCK_64FS,
1065 NULL);
1066 break;
1067 case SNDRV_PCM_FORMAT_S32_LE:
1068 dev_dbg(component->dev,
1069 "%s set format SNDRV_PCM_FORMAT_S32_LE\n",
1070 __func__);
1071 ret += sma1303_regmap_update_bits(sma1303,
1072 SMA1303_A4_TOP_MAN3,
1073 SMA1303_SCK_RATE_MASK,
1074 SMA1303_SCK_64FS,
1075 NULL);
1076 break;
1077 default:
1078 dev_err(component->dev,
1079 "%s not support data bit : %d\n", __func__,
1080 params_format(params));
1081 return -EINVAL;
1082 }
1083 }
1084
1085 switch (sma1303->format) {
1086 case SND_SOC_DAIFMT_I2S:
1087 ret += sma1303_regmap_update_bits(sma1303,
1088 SMA1303_01_INPUT1_CTRL1,
1089 SMA1303_I2S_MODE_MASK,
1090 SMA1303_STANDARD_I2S,
1091 NULL);
1092 ret += sma1303_regmap_update_bits(sma1303,
1093 SMA1303_A4_TOP_MAN3,
1094 SMA1303_O_FORMAT_MASK,
1095 SMA1303_O_FMT_I2S,
1096 NULL);
1097 break;
1098 case SND_SOC_DAIFMT_LEFT_J:
1099 ret += sma1303_regmap_update_bits(sma1303,
1100 SMA1303_01_INPUT1_CTRL1,
1101 SMA1303_I2S_MODE_MASK,
1102 SMA1303_LJ,
1103 NULL);
1104 ret += sma1303_regmap_update_bits(sma1303,
1105 SMA1303_A4_TOP_MAN3,
1106 SMA1303_O_FORMAT_MASK,
1107 SMA1303_O_FMT_LJ,
1108 NULL);
1109 break;
1110 case SND_SOC_DAIFMT_RIGHT_J:
1111 switch (params_width(params)) {
1112 case 16:
1113 ret += sma1303_regmap_update_bits(sma1303,
1114 SMA1303_01_INPUT1_CTRL1,
1115 SMA1303_I2S_MODE_MASK,
1116 SMA1303_RJ_16BIT,
1117 NULL);
1118 break;
1119 case 24:
1120 case 32:
1121 ret += sma1303_regmap_update_bits(sma1303,
1122 SMA1303_01_INPUT1_CTRL1,
1123 SMA1303_I2S_MODE_MASK,
1124 SMA1303_RJ_24BIT,
1125 NULL);
1126 break;
1127 }
1128 break;
1129 case SND_SOC_DAIFMT_DSP_A:
1130 ret += sma1303_regmap_update_bits(sma1303,
1131 SMA1303_01_INPUT1_CTRL1,
1132 SMA1303_I2S_MODE_MASK,
1133 SMA1303_STANDARD_I2S,
1134 NULL);
1135 ret += sma1303_regmap_update_bits(sma1303,
1136 SMA1303_A4_TOP_MAN3,
1137 SMA1303_O_FORMAT_MASK,
1138 SMA1303_O_FMT_TDM,
1139 NULL);
1140 break;
1141 }
1142
1143 switch (params_width(params)) {
1144 case 16:
1145 case 24:
1146 case 32:
1147 break;
1148 default:
1149 dev_err(component->dev,
1150 "%s not support data bit : %d\n", __func__,
1151 params_format(params));
1152 return -EINVAL;
1153 }
1154 if (ret < 0)
1155 return -EINVAL;
1156
1157 return 0;
1158 }
1159
sma1303_dai_set_sysclk_amp(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)1160 static int sma1303_dai_set_sysclk_amp(struct snd_soc_dai *dai,
1161 int clk_id, unsigned int freq, int dir)
1162 {
1163 struct snd_soc_component *component = dai->component;
1164 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
1165
1166 switch (clk_id) {
1167 case SMA1303_EXTERNAL_CLOCK_19_2:
1168 break;
1169 case SMA1303_EXTERNAL_CLOCK_24_576:
1170 break;
1171 case SMA1303_PLL_CLKIN_MCLK:
1172 break;
1173 case SMA1303_PLL_CLKIN_BCLK:
1174 break;
1175 default:
1176 dev_err(component->dev, "Invalid clk id: %d\n", clk_id);
1177 return -EINVAL;
1178 }
1179 sma1303->sys_clk_id = clk_id;
1180 return 0;
1181 }
1182
sma1303_dai_mute(struct snd_soc_dai * dai,int mute,int stream)1183 static int sma1303_dai_mute(struct snd_soc_dai *dai, int mute, int stream)
1184 {
1185 struct snd_soc_component *component = dai->component;
1186 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
1187 int ret = 0;
1188
1189 if (stream == SNDRV_PCM_STREAM_CAPTURE)
1190 return ret;
1191
1192 if (mute) {
1193 dev_dbg(component->dev, "%s : %s\n", __func__, "MUTE");
1194
1195 ret += sma1303_regmap_update_bits(sma1303,
1196 SMA1303_0E_MUTE_VOL_CTRL,
1197 SMA1303_SPK_MUTE_MASK,
1198 SMA1303_SPK_MUTE,
1199 NULL);
1200
1201 /* Need to wait time for mute slope */
1202 msleep(55);
1203 } else {
1204 if (!sma1303->force_mute_status) {
1205 dev_dbg(component->dev, "%s : %s\n",
1206 __func__, "UNMUTE");
1207 ret += sma1303_regmap_update_bits(sma1303,
1208 SMA1303_0E_MUTE_VOL_CTRL,
1209 SMA1303_SPK_MUTE_MASK,
1210 SMA1303_SPK_UNMUTE,
1211 NULL);
1212 } else {
1213 dev_dbg(sma1303->dev,
1214 "%s : FORCE MUTE!!!\n", __func__);
1215 }
1216 }
1217
1218 if (ret < 0)
1219 return -EINVAL;
1220 return 0;
1221 }
1222
sma1303_dai_set_fmt_amp(struct snd_soc_dai * dai,unsigned int fmt)1223 static int sma1303_dai_set_fmt_amp(struct snd_soc_dai *dai,
1224 unsigned int fmt)
1225 {
1226 struct snd_soc_component *component = dai->component;
1227 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
1228 int ret = 0;
1229
1230 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1231
1232 case SND_SOC_DAIFMT_CBC_CFC:
1233 dev_dbg(component->dev,
1234 "%s : %s\n", __func__, "I2S/TDM Device mode");
1235 ret += sma1303_regmap_update_bits(sma1303,
1236 SMA1303_01_INPUT1_CTRL1,
1237 SMA1303_CONTROLLER_DEVICE_MASK,
1238 SMA1303_DEVICE_MODE,
1239 NULL);
1240 break;
1241
1242 case SND_SOC_DAIFMT_CBP_CFP:
1243 dev_dbg(component->dev,
1244 "%s : %s\n", __func__, "I2S/TDM Controller mode");
1245 ret += sma1303_regmap_update_bits(sma1303,
1246 SMA1303_01_INPUT1_CTRL1,
1247 SMA1303_CONTROLLER_DEVICE_MASK,
1248 SMA1303_CONTROLLER_MODE,
1249 NULL);
1250 break;
1251
1252 default:
1253 dev_err(component->dev,
1254 "Unsupported Controller/Device : 0x%x\n", fmt);
1255 return -EINVAL;
1256 }
1257
1258 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1259
1260 case SND_SOC_DAIFMT_I2S:
1261 case SND_SOC_DAIFMT_RIGHT_J:
1262 case SND_SOC_DAIFMT_LEFT_J:
1263 case SND_SOC_DAIFMT_DSP_A:
1264 case SND_SOC_DAIFMT_DSP_B:
1265 sma1303->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1266 break;
1267 default:
1268 dev_err(component->dev,
1269 "Unsupported Audio Interface Format : 0x%x\n", fmt);
1270 return -EINVAL;
1271 }
1272
1273 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1274
1275 case SND_SOC_DAIFMT_IB_NF:
1276 dev_dbg(component->dev, "%s : %s\n",
1277 __func__, "Invert BCLK + Normal Frame");
1278 ret += sma1303_regmap_update_bits(sma1303,
1279 SMA1303_01_INPUT1_CTRL1,
1280 SMA1303_SCK_RISING_MASK,
1281 SMA1303_SCK_RISING_EDGE,
1282 NULL);
1283 break;
1284 case SND_SOC_DAIFMT_IB_IF:
1285 dev_dbg(component->dev, "%s : %s\n",
1286 __func__, "Invert BCLK + Invert Frame");
1287 ret += sma1303_regmap_update_bits(sma1303,
1288 SMA1303_01_INPUT1_CTRL1,
1289 SMA1303_LEFTPOL_MASK|SMA1303_SCK_RISING_MASK,
1290 SMA1303_HIGH_FIRST_CH|SMA1303_SCK_RISING_EDGE,
1291 NULL);
1292 break;
1293 case SND_SOC_DAIFMT_NB_IF:
1294 dev_dbg(component->dev, "%s : %s\n",
1295 __func__, "Normal BCLK + Invert Frame");
1296 ret += sma1303_regmap_update_bits(sma1303,
1297 SMA1303_01_INPUT1_CTRL1,
1298 SMA1303_LEFTPOL_MASK,
1299 SMA1303_HIGH_FIRST_CH,
1300 NULL);
1301 break;
1302 case SND_SOC_DAIFMT_NB_NF:
1303 dev_dbg(component->dev, "%s : %s\n",
1304 __func__, "Normal BCLK + Normal Frame");
1305 break;
1306 default:
1307 dev_err(component->dev,
1308 "Unsupported Bit & Frameclock : 0x%x\n", fmt);
1309 return -EINVAL;
1310 }
1311
1312 if (ret < 0)
1313 return -EINVAL;
1314 return 0;
1315 }
1316
sma1303_dai_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1317 static int sma1303_dai_set_tdm_slot(struct snd_soc_dai *dai,
1318 unsigned int tx_mask, unsigned int rx_mask,
1319 int slots, int slot_width)
1320 {
1321 struct snd_soc_component *component = dai->component;
1322 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
1323 int ret = 0;
1324
1325 dev_dbg(component->dev, "%s : slots = %d, slot_width - %d\n",
1326 __func__, slots, slot_width);
1327
1328 sma1303->frame_size = slot_width * slots;
1329
1330 ret += sma1303_regmap_update_bits(sma1303,
1331 SMA1303_A4_TOP_MAN3,
1332 SMA1303_O_FORMAT_MASK,
1333 SMA1303_O_FMT_TDM,
1334 NULL);
1335
1336 switch (slot_width) {
1337 case 16:
1338 ret += sma1303_regmap_update_bits(sma1303,
1339 SMA1303_A6_TDM2,
1340 SMA1303_TDM_DL_MASK,
1341 SMA1303_TDM_DL_16,
1342 NULL);
1343 break;
1344 case 32:
1345 ret += sma1303_regmap_update_bits(sma1303,
1346 SMA1303_A6_TDM2,
1347 SMA1303_TDM_DL_MASK,
1348 SMA1303_TDM_DL_32,
1349 NULL);
1350 break;
1351 default:
1352 dev_err(component->dev, "%s not support TDM %d slot_width\n",
1353 __func__, slot_width);
1354 break;
1355 }
1356
1357 switch (slots) {
1358 case 4:
1359 ret += sma1303_regmap_update_bits(sma1303,
1360 SMA1303_A6_TDM2,
1361 SMA1303_TDM_N_SLOT_MASK,
1362 SMA1303_TDM_N_SLOT_4,
1363 NULL);
1364 break;
1365 case 8:
1366 ret += sma1303_regmap_update_bits(sma1303,
1367 SMA1303_A6_TDM2,
1368 SMA1303_TDM_N_SLOT_MASK,
1369 SMA1303_TDM_N_SLOT_8,
1370 NULL);
1371 break;
1372 default:
1373 dev_err(component->dev, "%s not support TDM %d slots\n",
1374 __func__, slots);
1375 break;
1376 }
1377
1378 if (sma1303->tdm_slot_rx < slots)
1379 ret += sma1303_regmap_update_bits(sma1303,
1380 SMA1303_A5_TDM1,
1381 SMA1303_TDM_SLOT1_RX_POS_MASK,
1382 (sma1303->tdm_slot_rx) << 3,
1383 NULL);
1384 else
1385 dev_err(component->dev, "%s Incorrect tdm-slot-rx %d set\n",
1386 __func__, sma1303->tdm_slot_rx);
1387
1388 ret += sma1303_regmap_update_bits(sma1303,
1389 SMA1303_A5_TDM1,
1390 SMA1303_TDM_CLK_POL_MASK,
1391 SMA1303_TDM_CLK_POL_RISE,
1392 NULL);
1393
1394 ret += sma1303_regmap_update_bits(sma1303,
1395 SMA1303_A5_TDM1,
1396 SMA1303_TDM_TX_MODE_MASK,
1397 SMA1303_TDM_TX_MONO,
1398 NULL);
1399
1400 if (sma1303->tdm_slot_tx < slots)
1401 ret += sma1303_regmap_update_bits(sma1303,
1402 SMA1303_A6_TDM2,
1403 SMA1303_TDM_SLOT1_TX_POS_MASK,
1404 (sma1303->tdm_slot_tx) << 3,
1405 NULL);
1406 else
1407 dev_err(component->dev, "%s Incorrect tdm-slot-tx %d set\n",
1408 __func__, sma1303->tdm_slot_tx);
1409
1410 if (ret < 0)
1411 return -EINVAL;
1412 return 0;
1413 }
1414
1415 static const struct snd_soc_dai_ops sma1303_dai_ops_amp = {
1416 .set_sysclk = sma1303_dai_set_sysclk_amp,
1417 .set_fmt = sma1303_dai_set_fmt_amp,
1418 .hw_params = sma1303_dai_hw_params_amp,
1419 .mute_stream = sma1303_dai_mute,
1420 .set_tdm_slot = sma1303_dai_set_tdm_slot,
1421 };
1422
1423 #define SMA1303_RATES SNDRV_PCM_RATE_8000_192000
1424 #define SMA1303_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
1425 SNDRV_PCM_FMTBIT_S32_LE)
1426
1427 static struct snd_soc_dai_driver sma1303_dai[] = {
1428 {
1429 .name = "sma1303-amplifier",
1430 .id = 0,
1431 .playback = {
1432 .stream_name = "Playback",
1433 .channels_min = 1,
1434 .channels_max = 2,
1435 .rates = SMA1303_RATES,
1436 .formats = SMA1303_FORMATS,
1437 },
1438 .capture = {
1439 .stream_name = "Capture",
1440 .channels_min = 1,
1441 .channels_max = 2,
1442 .rates = SMA1303_RATES,
1443 .formats = SMA1303_FORMATS,
1444 },
1445 .ops = &sma1303_dai_ops_amp,
1446 },
1447 };
1448
sma1303_check_fault_worker(struct work_struct * work)1449 static void sma1303_check_fault_worker(struct work_struct *work)
1450 {
1451 struct sma1303_priv *sma1303 =
1452 container_of(work, struct sma1303_priv, check_fault_work.work);
1453 int ret = 0;
1454 unsigned int over_temp, ocp_val, uvlo_val;
1455
1456 if (sma1303->tsdw_cnt)
1457 ret = sma1303_regmap_read(sma1303,
1458 SMA1303_0A_SPK_VOL, &sma1303->cur_vol);
1459 else
1460 ret = sma1303_regmap_read(sma1303,
1461 SMA1303_0A_SPK_VOL, &sma1303->init_vol);
1462
1463 if (ret != 0) {
1464 dev_err(sma1303->dev,
1465 "failed to read SMA1303_0A_SPK_VOL : %d\n", ret);
1466 return;
1467 }
1468
1469 ret = sma1303_regmap_read(sma1303, SMA1303_FA_STATUS1, &over_temp);
1470 if (ret != 0) {
1471 dev_err(sma1303->dev,
1472 "failed to read SMA1303_FA_STATUS1 : %d\n", ret);
1473 return;
1474 }
1475
1476 ret = sma1303_regmap_read(sma1303, SMA1303_FB_STATUS2, &ocp_val);
1477 if (ret != 0) {
1478 dev_err(sma1303->dev,
1479 "failed to read SMA1303_FB_STATUS2 : %d\n", ret);
1480 return;
1481 }
1482
1483 ret = sma1303_regmap_read(sma1303, SMA1303_FF_DEVICE_INDEX, &uvlo_val);
1484 if (ret != 0) {
1485 dev_err(sma1303->dev,
1486 "failed to read SMA1303_FF_DEVICE_INDEX : %d\n", ret);
1487 return;
1488 }
1489
1490 if (~over_temp & SMA1303_OT1_OK_STATUS) {
1491 dev_crit(sma1303->dev,
1492 "%s : OT1(Over Temperature Level 1)\n", __func__);
1493
1494 if ((sma1303->cur_vol + 6) <= 0xFF)
1495 sma1303_regmap_write(sma1303,
1496 SMA1303_0A_SPK_VOL, sma1303->cur_vol + 6);
1497
1498 sma1303->tsdw_cnt++;
1499 } else if (sma1303->tsdw_cnt) {
1500 sma1303_regmap_write(sma1303,
1501 SMA1303_0A_SPK_VOL, sma1303->init_vol);
1502 sma1303->tsdw_cnt = 0;
1503 sma1303->cur_vol = sma1303->init_vol;
1504 }
1505
1506 if (~over_temp & SMA1303_OT2_OK_STATUS) {
1507 dev_crit(sma1303->dev,
1508 "%s : OT2(Over Temperature Level 2)\n", __func__);
1509 }
1510 if (ocp_val & SMA1303_OCP_SPK_STATUS) {
1511 dev_crit(sma1303->dev,
1512 "%s : OCP_SPK(Over Current Protect SPK)\n", __func__);
1513 }
1514 if (ocp_val & SMA1303_OCP_BST_STATUS) {
1515 dev_crit(sma1303->dev,
1516 "%s : OCP_BST(Over Current Protect Boost)\n", __func__);
1517 }
1518 if ((ocp_val & SMA1303_CLK_MON_STATUS) && (sma1303->amp_power_status)) {
1519 dev_crit(sma1303->dev,
1520 "%s : CLK_FAULT(No clock input)\n", __func__);
1521 }
1522 if (uvlo_val & SMA1303_UVLO_BST_STATUS) {
1523 dev_crit(sma1303->dev,
1524 "%s : UVLO(Under Voltage Lock Out)\n", __func__);
1525 }
1526
1527 if ((over_temp != sma1303->last_over_temp) ||
1528 (ocp_val != sma1303->last_ocp_val)) {
1529
1530 dev_crit(sma1303->dev, "Please check AMP status");
1531 dev_dbg(sma1303->dev, "STATUS1=0x%02X : STATUS2=0x%02X\n",
1532 over_temp, ocp_val);
1533 sma1303->last_over_temp = over_temp;
1534 sma1303->last_ocp_val = ocp_val;
1535 }
1536
1537 if (sma1303->check_fault_status) {
1538 if (sma1303->check_fault_period > 0)
1539 queue_delayed_work(system_freezable_wq,
1540 &sma1303->check_fault_work,
1541 sma1303->check_fault_period * HZ);
1542 else
1543 queue_delayed_work(system_freezable_wq,
1544 &sma1303->check_fault_work,
1545 CHECK_PERIOD_TIME * HZ);
1546 }
1547
1548 if (!(~over_temp & SMA1303_OT1_OK_STATUS)
1549 && !(~over_temp & SMA1303_OT2_OK_STATUS)
1550 && !(ocp_val & SMA1303_OCP_SPK_STATUS)
1551 && !(ocp_val & SMA1303_OCP_BST_STATUS)
1552 && !(ocp_val & SMA1303_CLK_MON_STATUS)
1553 && !(uvlo_val & SMA1303_UVLO_BST_STATUS)) {
1554 }
1555 }
1556
sma1303_probe(struct snd_soc_component * component)1557 static int sma1303_probe(struct snd_soc_component *component)
1558 {
1559 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1560
1561 snd_soc_dapm_sync(dapm);
1562
1563 return 0;
1564 }
1565
sma1303_remove(struct snd_soc_component * component)1566 static void sma1303_remove(struct snd_soc_component *component)
1567 {
1568 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component);
1569
1570 cancel_delayed_work_sync(&sma1303->check_fault_work);
1571 }
1572
1573 static const struct snd_soc_component_driver sma1303_component = {
1574 .probe = sma1303_probe,
1575 .remove = sma1303_remove,
1576 .controls = sma1303_snd_controls,
1577 .num_controls = ARRAY_SIZE(sma1303_snd_controls),
1578 .dapm_widgets = sma1303_dapm_widgets,
1579 .num_dapm_widgets = ARRAY_SIZE(sma1303_dapm_widgets),
1580 .dapm_routes = sma1303_audio_map,
1581 .num_dapm_routes = ARRAY_SIZE(sma1303_audio_map),
1582 };
1583
1584 static const struct regmap_config sma_i2c_regmap = {
1585 .reg_bits = 8,
1586 .val_bits = 8,
1587
1588 .max_register = SMA1303_FF_DEVICE_INDEX,
1589 .readable_reg = sma1303_readable_register,
1590 .writeable_reg = sma1303_writeable_register,
1591 .volatile_reg = sma1303_volatile_register,
1592
1593 .cache_type = REGCACHE_NONE,
1594 .reg_defaults = sma1303_reg_def,
1595 .num_reg_defaults = ARRAY_SIZE(sma1303_reg_def),
1596 };
1597
check_fault_period_show(struct device * dev,struct device_attribute * devattr,char * buf)1598 static ssize_t check_fault_period_show(struct device *dev,
1599 struct device_attribute *devattr, char *buf)
1600 {
1601 struct sma1303_priv *sma1303 = dev_get_drvdata(dev);
1602
1603 return sysfs_emit(buf, "%ld\n", sma1303->check_fault_period);
1604 }
1605
check_fault_period_store(struct device * dev,struct device_attribute * devattr,const char * buf,size_t count)1606 static ssize_t check_fault_period_store(struct device *dev,
1607 struct device_attribute *devattr, const char *buf, size_t count)
1608 {
1609 struct sma1303_priv *sma1303 = dev_get_drvdata(dev);
1610 int ret;
1611
1612 ret = kstrtol(buf, 10, &sma1303->check_fault_period);
1613
1614 if (ret)
1615 return -EINVAL;
1616
1617 return (ssize_t)count;
1618 }
1619
1620 static DEVICE_ATTR_RW(check_fault_period);
1621
check_fault_status_show(struct device * dev,struct device_attribute * devattr,char * buf)1622 static ssize_t check_fault_status_show(struct device *dev,
1623 struct device_attribute *devattr, char *buf)
1624 {
1625 struct sma1303_priv *sma1303 = dev_get_drvdata(dev);
1626
1627 return sysfs_emit(buf, "%ld\n", sma1303->check_fault_status);
1628 }
1629
check_fault_status_store(struct device * dev,struct device_attribute * devattr,const char * buf,size_t count)1630 static ssize_t check_fault_status_store(struct device *dev,
1631 struct device_attribute *devattr, const char *buf, size_t count)
1632 {
1633 struct sma1303_priv *sma1303 = dev_get_drvdata(dev);
1634 int ret;
1635
1636 ret = kstrtol(buf, 10, &sma1303->check_fault_status);
1637
1638 if (ret)
1639 return -EINVAL;
1640
1641 if (sma1303->check_fault_status) {
1642 if (sma1303->check_fault_period > 0)
1643 queue_delayed_work(system_freezable_wq,
1644 &sma1303->check_fault_work,
1645 sma1303->check_fault_period * HZ);
1646 else
1647 queue_delayed_work(system_freezable_wq,
1648 &sma1303->check_fault_work,
1649 CHECK_PERIOD_TIME * HZ);
1650 }
1651
1652 return (ssize_t)count;
1653 }
1654
1655 static DEVICE_ATTR_RW(check_fault_status);
1656
1657 static struct attribute *sma1303_attr[] = {
1658 &dev_attr_check_fault_period.attr,
1659 &dev_attr_check_fault_status.attr,
1660 NULL,
1661 };
1662
1663 static struct attribute_group sma1303_attr_group = {
1664 .attrs = sma1303_attr,
1665 };
1666
sma1303_i2c_probe(struct i2c_client * client)1667 static int sma1303_i2c_probe(struct i2c_client *client)
1668 {
1669 struct sma1303_priv *sma1303;
1670 int ret, i = 0;
1671 unsigned int device_info, status, otp_stat;
1672
1673 sma1303 = devm_kzalloc(&client->dev,
1674 sizeof(struct sma1303_priv), GFP_KERNEL);
1675 if (!sma1303)
1676 return -ENOMEM;
1677 sma1303->dev = &client->dev;
1678
1679 sma1303->regmap = devm_regmap_init_i2c(client, &sma_i2c_regmap);
1680 if (IS_ERR(sma1303->regmap)) {
1681 ret = PTR_ERR(sma1303->regmap);
1682 dev_err(&client->dev,
1683 "Failed to allocate register map: %d\n", ret);
1684
1685 return ret;
1686 }
1687
1688 ret = sma1303_regmap_read(sma1303,
1689 SMA1303_FF_DEVICE_INDEX, &device_info);
1690
1691 if ((ret != 0) || ((device_info & 0xF8) != SMA1303_DEVICE_ID)) {
1692 dev_err(&client->dev, "device initialization error (%d 0x%02X)",
1693 ret, device_info);
1694 }
1695 dev_dbg(&client->dev, "chip version 0x%02X\n", device_info);
1696
1697 ret += sma1303_regmap_update_bits(sma1303,
1698 SMA1303_00_SYSTEM_CTRL,
1699 SMA1303_RESETBYI2C_MASK, SMA1303_RESETBYI2C_RESET,
1700 NULL);
1701
1702 ret += sma1303_regmap_read(sma1303, SMA1303_FF_DEVICE_INDEX, &status);
1703 sma1303->rev_num = status & SMA1303_REV_NUM_STATUS;
1704 if (sma1303->rev_num == SMA1303_REV_NUM_TV0)
1705 dev_dbg(&client->dev, "SMA1303 Trimming Version 0\n");
1706 else if (sma1303->rev_num == SMA1303_REV_NUM_TV1)
1707 dev_dbg(&client->dev, "SMA1303 Trimming Version 1\n");
1708
1709 ret += sma1303_regmap_read(sma1303, SMA1303_FB_STATUS2, &otp_stat);
1710 if (ret < 0)
1711 dev_err(&client->dev,
1712 "failed to read, register: %02X, ret: %d\n",
1713 SMA1303_FF_DEVICE_INDEX, ret);
1714
1715 if (((sma1303->rev_num == SMA1303_REV_NUM_TV0) &&
1716 ((otp_stat & 0x0E) == SMA1303_OTP_STAT_OK_0)) ||
1717 ((sma1303->rev_num != SMA1303_REV_NUM_TV0) &&
1718 ((otp_stat & 0x0C) == SMA1303_OTP_STAT_OK_1)))
1719 dev_dbg(&client->dev, "SMA1303 OTP Status Successful\n");
1720 else
1721 dev_dbg(&client->dev, "SMA1303 OTP Status Fail\n");
1722
1723 for (i = 0; i < (unsigned int)ARRAY_SIZE(sma1303_reg_def); i++)
1724 ret += sma1303_regmap_write(sma1303,
1725 sma1303_reg_def[i].reg,
1726 sma1303_reg_def[i].def);
1727
1728 sma1303->amp_mode = SMA1303_MONO;
1729 sma1303->amp_power_status = false;
1730 sma1303->check_fault_period = CHECK_PERIOD_TIME;
1731 sma1303->check_fault_status = true;
1732 sma1303->force_mute_status = false;
1733 sma1303->init_vol = 0x31;
1734 sma1303->cur_vol = sma1303->init_vol;
1735 sma1303->last_bclk = 0;
1736 sma1303->last_ocp_val = 0x08;
1737 sma1303->last_over_temp = 0xC0;
1738 sma1303->tsdw_cnt = 0;
1739 sma1303->retry_cnt = SMA1303_I2C_RETRY_COUNT;
1740 sma1303->tdm_slot_rx = 0;
1741 sma1303->tdm_slot_tx = 0;
1742 sma1303->sys_clk_id = SMA1303_PLL_CLKIN_BCLK;
1743
1744 sma1303->dev = &client->dev;
1745 sma1303->kobj = &client->dev.kobj;
1746
1747 INIT_DELAYED_WORK(&sma1303->check_fault_work,
1748 sma1303_check_fault_worker);
1749
1750 i2c_set_clientdata(client, sma1303);
1751
1752 sma1303->pll_matches = sma1303_pll_matches;
1753 sma1303->num_of_pll_matches =
1754 ARRAY_SIZE(sma1303_pll_matches);
1755
1756 ret = devm_snd_soc_register_component(&client->dev,
1757 &sma1303_component, sma1303_dai, 1);
1758 if (ret) {
1759 dev_err(&client->dev, "Failed to register component");
1760
1761 return ret;
1762 }
1763
1764 sma1303->attr_grp = &sma1303_attr_group;
1765 ret = sysfs_create_group(sma1303->kobj, sma1303->attr_grp);
1766 if (ret) {
1767 dev_err(&client->dev,
1768 "failed to create attribute group [%d]\n", ret);
1769 sma1303->attr_grp = NULL;
1770 }
1771
1772 return ret;
1773 }
1774
sma1303_i2c_remove(struct i2c_client * client)1775 static void sma1303_i2c_remove(struct i2c_client *client)
1776 {
1777 struct sma1303_priv *sma1303 =
1778 (struct sma1303_priv *) i2c_get_clientdata(client);
1779
1780 if (sma1303->attr_grp)
1781 sysfs_remove_group(sma1303->kobj, sma1303->attr_grp);
1782 cancel_delayed_work_sync(&sma1303->check_fault_work);
1783 }
1784
1785 static const struct i2c_device_id sma1303_i2c_id[] = {
1786 { .name = "sma1303" },
1787 { }
1788 };
1789 MODULE_DEVICE_TABLE(i2c, sma1303_i2c_id);
1790
1791 static const struct of_device_id sma1303_of_match[] = {
1792 { .compatible = "irondevice,sma1303", },
1793 { }
1794 };
1795 MODULE_DEVICE_TABLE(of, sma1303_of_match);
1796
1797 static struct i2c_driver sma1303_i2c_driver = {
1798 .driver = {
1799 .name = "sma1303",
1800 .of_match_table = sma1303_of_match,
1801 },
1802 .probe = sma1303_i2c_probe,
1803 .remove = sma1303_i2c_remove,
1804 .id_table = sma1303_i2c_id,
1805 };
1806
1807 module_i2c_driver(sma1303_i2c_driver);
1808
1809 MODULE_DESCRIPTION("ALSA SoC SMA1303 driver");
1810 MODULE_AUTHOR("Gyuhwa Park, <gyuhwa.park@irondevice.com>");
1811 MODULE_AUTHOR("Kiseok Jo, <kiseok.jo@irondevice.com>");
1812 MODULE_LICENSE("GPL v2");
1813