xref: /linux/sound/soc/fsl/fsl_asrc.c (revision d006330be3f782ff3fb7c3ed51e617e01f29a465)
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver
4 //
5 // Copyright (C) 2014 Freescale Semiconductor, Inc.
6 //
7 // Author: Nicolin Chen <nicoleotsuka@gmail.com>
8 
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/module.h>
13 #include <linux/of_platform.h>
14 #include <linux/dma/imx-dma.h>
15 #include <linux/pm_runtime.h>
16 #include <sound/dmaengine_pcm.h>
17 #include <sound/pcm_params.h>
18 
19 #include "fsl_asrc.h"
20 
21 #define IDEAL_RATIO_DECIMAL_DEPTH 26
22 #define DIVIDER_NUM  64
23 #define INIT_RETRY_NUM 50
24 
25 #define pair_err(fmt, ...) \
26 	dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
27 
28 #define pair_dbg(fmt, ...) \
29 	dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
30 
31 #define pair_warn(fmt, ...) \
32 	dev_warn(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
33 
34 /* Corresponding to process_option */
35 static unsigned int supported_asrc_rate[] = {
36 	5512, 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000,
37 	64000, 88200, 96000, 128000, 176400, 192000,
38 };
39 
40 static struct snd_pcm_hw_constraint_list fsl_asrc_rate_constraints = {
41 	.count = ARRAY_SIZE(supported_asrc_rate),
42 	.list = supported_asrc_rate,
43 };
44 
45 /*
46  * The following tables map the relationship between asrc_inclk/asrc_outclk in
47  * fsl_asrc.h and the registers of ASRCSR
48  */
49 static unsigned char input_clk_map_imx35[ASRC_CLK_MAP_LEN] = {
50 	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
51 	3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
52 	3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
53 };
54 
55 static unsigned char output_clk_map_imx35[ASRC_CLK_MAP_LEN] = {
56 	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
57 	3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
58 	3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
59 };
60 
61 /* i.MX53 uses the same map for input and output */
62 static unsigned char input_clk_map_imx53[ASRC_CLK_MAP_LEN] = {
63 /*	0x0  0x1  0x2  0x3  0x4  0x5  0x6  0x7  0x8  0x9  0xa  0xb  0xc  0xd  0xe  0xf */
64 	0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
65 	0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
66 	0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
67 };
68 
69 static unsigned char output_clk_map_imx53[ASRC_CLK_MAP_LEN] = {
70 /*	0x0  0x1  0x2  0x3  0x4  0x5  0x6  0x7  0x8  0x9  0xa  0xb  0xc  0xd  0xe  0xf */
71 	0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
72 	0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
73 	0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
74 };
75 
76 /*
77  * i.MX8QM/i.MX8QXP uses the same map for input and output.
78  * clk_map_imx8qm[0] is for i.MX8QM asrc0
79  * clk_map_imx8qm[1] is for i.MX8QM asrc1
80  * clk_map_imx8qxp[0] is for i.MX8QXP asrc0
81  * clk_map_imx8qxp[1] is for i.MX8QXP asrc1
82  */
83 static unsigned char clk_map_imx8qm[2][ASRC_CLK_MAP_LEN] = {
84 	{
85 	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
86 	0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
87 	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
88 	},
89 	{
90 	0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
91 	0x0, 0x1, 0x2, 0x3, 0xb, 0xc, 0xf, 0xf, 0xd, 0xe, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
92 	0x4, 0x5, 0x6, 0xf, 0x8, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
93 	},
94 };
95 
96 static unsigned char clk_map_imx8qxp[2][ASRC_CLK_MAP_LEN] = {
97 	{
98 	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
99 	0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0xf, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xf,
100 	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
101 	},
102 	{
103 	0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
104 	0x0, 0x1, 0x2, 0x3, 0x7, 0x8, 0xf, 0xf, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
105 	0xf, 0xf, 0x6, 0xf, 0xf, 0xf, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
106 	},
107 };
108 
109 /*
110  * According to RM, the divider range is 1 ~ 8,
111  * prescaler is power of 2 from 1 ~ 128.
112  */
113 static int asrc_clk_divider[DIVIDER_NUM] = {
114 	1,  2,  4,  8,  16,  32,  64,  128,  /* divider = 1 */
115 	2,  4,  8, 16,  32,  64, 128,  256,  /* divider = 2 */
116 	3,  6, 12, 24,  48,  96, 192,  384,  /* divider = 3 */
117 	4,  8, 16, 32,  64, 128, 256,  512,  /* divider = 4 */
118 	5, 10, 20, 40,  80, 160, 320,  640,  /* divider = 5 */
119 	6, 12, 24, 48,  96, 192, 384,  768,  /* divider = 6 */
120 	7, 14, 28, 56, 112, 224, 448,  896,  /* divider = 7 */
121 	8, 16, 32, 64, 128, 256, 512, 1024,  /* divider = 8 */
122 };
123 
124 /*
125  * Check if the divider is available for internal ratio mode
126  */
fsl_asrc_divider_avail(int clk_rate,int rate,int * div)127 static bool fsl_asrc_divider_avail(int clk_rate, int rate, int *div)
128 {
129 	u32 rem, i;
130 	u64 n;
131 
132 	if (div)
133 		*div = 0;
134 
135 	if (clk_rate == 0 || rate == 0)
136 		return false;
137 
138 	n = clk_rate;
139 	rem = do_div(n, rate);
140 
141 	if (div)
142 		*div = n;
143 
144 	if (rem != 0)
145 		return false;
146 
147 	for (i = 0; i < DIVIDER_NUM; i++) {
148 		if (n == asrc_clk_divider[i])
149 			break;
150 	}
151 
152 	if (i == DIVIDER_NUM)
153 		return false;
154 
155 	return true;
156 }
157 
158 /**
159  * fsl_asrc_sel_proc - Select the pre-processing and post-processing options
160  * @inrate: input sample rate
161  * @outrate: output sample rate
162  * @pre_proc: return value for pre-processing option
163  * @post_proc: return value for post-processing option
164  *
165  * Make sure to exclude following unsupported cases before
166  * calling this function:
167  * 1) inrate > 8.125 * outrate
168  * 2) inrate > 16.125 * outrate
169  *
170  */
fsl_asrc_sel_proc(int inrate,int outrate,int * pre_proc,int * post_proc)171 static void fsl_asrc_sel_proc(int inrate, int outrate,
172 			     int *pre_proc, int *post_proc)
173 {
174 	bool post_proc_cond2;
175 	bool post_proc_cond0;
176 
177 	/* select pre_proc between [0, 2] */
178 	if (inrate * 8 > 33 * outrate)
179 		*pre_proc = 2;
180 	else if (inrate * 8 > 15 * outrate) {
181 		if (inrate > 152000)
182 			*pre_proc = 2;
183 		else
184 			*pre_proc = 1;
185 	} else if (inrate < 76000)
186 		*pre_proc = 0;
187 	else if (inrate > 152000)
188 		*pre_proc = 2;
189 	else
190 		*pre_proc = 1;
191 
192 	/* Condition for selection of post-processing */
193 	post_proc_cond2 = (inrate * 15 > outrate * 16 && outrate < 56000) ||
194 			  (inrate > 56000 && outrate < 56000);
195 	post_proc_cond0 = inrate * 23 < outrate * 8;
196 
197 	if (post_proc_cond2)
198 		*post_proc = 2;
199 	else if (post_proc_cond0)
200 		*post_proc = 0;
201 	else
202 		*post_proc = 1;
203 }
204 
205 /**
206  * fsl_asrc_request_pair - Request ASRC pair
207  * @channels: number of channels
208  * @pair: pointer to pair
209  *
210  * It assigns pair by the order of A->C->B because allocation of pair B,
211  * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A
212  * while pair A and pair C are comparatively independent.
213  */
fsl_asrc_request_pair(int channels,struct fsl_asrc_pair * pair)214 static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
215 {
216 	enum asrc_pair_index index = ASRC_INVALID_PAIR;
217 	struct fsl_asrc *asrc = pair->asrc;
218 	struct device *dev = &asrc->pdev->dev;
219 	unsigned long lock_flags;
220 	int i, ret = 0;
221 
222 	spin_lock_irqsave(&asrc->lock, lock_flags);
223 
224 	for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
225 		if (asrc->pair[i] != NULL)
226 			continue;
227 
228 		index = i;
229 
230 		if (i != ASRC_PAIR_B)
231 			break;
232 	}
233 
234 	if (index == ASRC_INVALID_PAIR) {
235 		dev_err(dev, "all pairs are busy now\n");
236 		ret = -EBUSY;
237 	} else if (asrc->channel_avail < channels) {
238 		dev_err(dev, "can't afford required channels: %d\n", channels);
239 		ret = -EINVAL;
240 	} else {
241 		asrc->channel_avail -= channels;
242 		asrc->pair[index] = pair;
243 		pair->channels = channels;
244 		pair->index = index;
245 	}
246 
247 	spin_unlock_irqrestore(&asrc->lock, lock_flags);
248 
249 	return ret;
250 }
251 
252 /**
253  * fsl_asrc_release_pair - Release ASRC pair
254  * @pair: pair to release
255  *
256  * It clears the resource from asrc and releases the occupied channels.
257  */
fsl_asrc_release_pair(struct fsl_asrc_pair * pair)258 static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair)
259 {
260 	struct fsl_asrc *asrc = pair->asrc;
261 	enum asrc_pair_index index = pair->index;
262 	unsigned long lock_flags;
263 
264 	/* Make sure the pair is disabled */
265 	regmap_update_bits(asrc->regmap, REG_ASRCTR,
266 			   ASRCTR_ASRCEi_MASK(index), 0);
267 
268 	spin_lock_irqsave(&asrc->lock, lock_flags);
269 
270 	asrc->channel_avail += pair->channels;
271 	asrc->pair[index] = NULL;
272 	pair->error = 0;
273 
274 	spin_unlock_irqrestore(&asrc->lock, lock_flags);
275 }
276 
277 /**
278  * fsl_asrc_set_watermarks- configure input and output thresholds
279  * @pair: pointer to pair
280  * @in: input threshold
281  * @out: output threshold
282  */
fsl_asrc_set_watermarks(struct fsl_asrc_pair * pair,u32 in,u32 out)283 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out)
284 {
285 	struct fsl_asrc *asrc = pair->asrc;
286 	enum asrc_pair_index index = pair->index;
287 
288 	regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
289 			   ASRMCRi_EXTTHRSHi_MASK |
290 			   ASRMCRi_INFIFO_THRESHOLD_MASK |
291 			   ASRMCRi_OUTFIFO_THRESHOLD_MASK,
292 			   ASRMCRi_EXTTHRSHi |
293 			   ASRMCRi_INFIFO_THRESHOLD(in) |
294 			   ASRMCRi_OUTFIFO_THRESHOLD(out));
295 }
296 
297 /**
298  * fsl_asrc_cal_asrck_divisor - Calculate the total divisor between asrck clock rate and sample rate
299  * @pair: pointer to pair
300  * @div: divider
301  *
302  * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider
303  */
fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair * pair,u32 div)304 static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div)
305 {
306 	u32 ps;
307 
308 	/* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */
309 	for (ps = 0; div > 8; ps++)
310 		div >>= 1;
311 
312 	return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps;
313 }
314 
315 /**
316  * fsl_asrc_set_ideal_ratio - Calculate and set the ratio for Ideal Ratio mode only
317  * @pair: pointer to pair
318  * @inrate: input rate
319  * @outrate: output rate
320  *
321  * The ratio is a 32-bit fixed point value with 26 fractional bits.
322  */
fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair * pair,int inrate,int outrate)323 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
324 				    int inrate, int outrate)
325 {
326 	struct fsl_asrc *asrc = pair->asrc;
327 	enum asrc_pair_index index = pair->index;
328 	unsigned long ratio;
329 	int i;
330 
331 	if (!outrate) {
332 		pair_err("output rate should not be zero\n");
333 		return -EINVAL;
334 	}
335 
336 	/* Calculate the intergal part of the ratio */
337 	ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH;
338 
339 	/* ... and then the 26 depth decimal part */
340 	inrate %= outrate;
341 
342 	for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) {
343 		inrate <<= 1;
344 
345 		if (inrate < outrate)
346 			continue;
347 
348 		ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i);
349 		inrate -= outrate;
350 
351 		if (!inrate)
352 			break;
353 	}
354 
355 	regmap_write(asrc->regmap, REG_ASRIDRL(index), ratio);
356 	regmap_write(asrc->regmap, REG_ASRIDRH(index), ratio >> 24);
357 
358 	return 0;
359 }
360 
361 /**
362  * fsl_asrc_config_pair - Configure the assigned ASRC pair
363  * @pair: pointer to pair
364  * @use_ideal_rate: boolean configuration
365  *
366  * It configures those ASRC registers according to a configuration instance
367  * of struct asrc_config which includes in/output sample rate, width, channel
368  * and clock settings.
369  *
370  * Note:
371  * The ideal ratio configuration can work with a flexible clock rate setting.
372  * Using IDEAL_RATIO_RATE gives a faster converting speed but overloads ASRC.
373  * For a regular audio playback, the clock rate should not be slower than an
374  * clock rate aligning with the output sample rate; For a use case requiring
375  * faster conversion, set use_ideal_rate to have the faster speed.
376  */
fsl_asrc_config_pair(struct fsl_asrc_pair * pair,bool use_ideal_rate)377 static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate)
378 {
379 	struct fsl_asrc_pair_priv *pair_priv = pair->private;
380 	struct asrc_config *config = pair_priv->config;
381 	struct fsl_asrc *asrc = pair->asrc;
382 	struct fsl_asrc_priv *asrc_priv = asrc->private;
383 	enum asrc_pair_index index = pair->index;
384 	enum asrc_word_width input_word_width;
385 	enum asrc_word_width output_word_width;
386 	u32 inrate, outrate, indiv, outdiv;
387 	u32 clk_index[2], div[2];
388 	u64 clk_rate;
389 	int in, out, channels;
390 	int pre_proc, post_proc;
391 	struct clk *clk;
392 	bool ideal, div_avail;
393 
394 	if (!config) {
395 		pair_err("invalid pair config\n");
396 		return -EINVAL;
397 	}
398 
399 	/* Validate channels */
400 	if (config->channel_num < 1 || config->channel_num > 10) {
401 		pair_err("does not support %d channels\n", config->channel_num);
402 		return -EINVAL;
403 	}
404 
405 	switch (snd_pcm_format_width(config->input_format)) {
406 	case 8:
407 		input_word_width = ASRC_WIDTH_8_BIT;
408 		break;
409 	case 16:
410 		input_word_width = ASRC_WIDTH_16_BIT;
411 		break;
412 	case 24:
413 		input_word_width = ASRC_WIDTH_24_BIT;
414 		break;
415 	default:
416 		pair_err("does not support this input format, %d\n",
417 			 config->input_format);
418 		return -EINVAL;
419 	}
420 
421 	switch (snd_pcm_format_width(config->output_format)) {
422 	case 16:
423 		output_word_width = ASRC_WIDTH_16_BIT;
424 		break;
425 	case 24:
426 		output_word_width = ASRC_WIDTH_24_BIT;
427 		break;
428 	default:
429 		pair_err("does not support this output format, %d\n",
430 			 config->output_format);
431 		return -EINVAL;
432 	}
433 
434 	inrate = config->input_sample_rate;
435 	outrate = config->output_sample_rate;
436 	ideal = config->inclk == INCLK_NONE;
437 
438 	/* Validate input and output sample rates */
439 	for (in = 0; in < ARRAY_SIZE(supported_asrc_rate); in++)
440 		if (inrate == supported_asrc_rate[in])
441 			break;
442 
443 	if (in == ARRAY_SIZE(supported_asrc_rate)) {
444 		pair_err("unsupported input sample rate: %dHz\n", inrate);
445 		return -EINVAL;
446 	}
447 
448 	for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++)
449 		if (outrate == supported_asrc_rate[out])
450 			break;
451 
452 	if (out == ARRAY_SIZE(supported_asrc_rate)) {
453 		pair_err("unsupported output sample rate: %dHz\n", outrate);
454 		return -EINVAL;
455 	}
456 
457 	if ((outrate >= 5512 && outrate <= 30000) &&
458 	    (outrate > 24 * inrate || inrate > 8 * outrate)) {
459 		pair_err("exceed supported ratio range [1/24, 8] for \
460 				inrate/outrate: %d/%d\n", inrate, outrate);
461 		return -EINVAL;
462 	}
463 
464 	/* Validate input and output clock sources */
465 	clk_index[IN] = asrc_priv->clk_map[IN][config->inclk];
466 	clk_index[OUT] = asrc_priv->clk_map[OUT][config->outclk];
467 
468 	/* We only have output clock for ideal ratio mode */
469 	clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
470 
471 	clk_rate = clk_get_rate(clk);
472 	div_avail = fsl_asrc_divider_avail(clk_rate, inrate, &div[IN]);
473 
474 	/*
475 	 * The divider range is [1, 1024], defined by the hardware. For non-
476 	 * ideal ratio configuration, clock rate has to be strictly aligned
477 	 * with the sample rate. For ideal ratio configuration, clock rates
478 	 * only result in different converting speeds. So remainder does not
479 	 * matter, as long as we keep the divider within its valid range.
480 	 */
481 	if (div[IN] == 0 || (!ideal && !div_avail)) {
482 		pair_err("failed to support input sample rate %dHz by asrck_%x\n",
483 				inrate, clk_index[ideal ? OUT : IN]);
484 		return -EINVAL;
485 	}
486 
487 	div[IN] = min_t(u32, 1024, div[IN]);
488 
489 	clk = asrc_priv->asrck_clk[clk_index[OUT]];
490 	clk_rate = clk_get_rate(clk);
491 	if (ideal && use_ideal_rate)
492 		div_avail = fsl_asrc_divider_avail(clk_rate, IDEAL_RATIO_RATE, &div[OUT]);
493 	else
494 		div_avail = fsl_asrc_divider_avail(clk_rate, outrate, &div[OUT]);
495 
496 	/* Output divider has the same limitation as the input one */
497 	if (div[OUT] == 0 || (!ideal && !div_avail)) {
498 		pair_err("failed to support output sample rate %dHz by asrck_%x\n",
499 				outrate, clk_index[OUT]);
500 		return -EINVAL;
501 	}
502 
503 	div[OUT] = min_t(u32, 1024, div[OUT]);
504 
505 	/* Set the channel number */
506 	channels = config->channel_num;
507 
508 	if (asrc_priv->soc->channel_bits < 4)
509 		channels /= 2;
510 
511 	/* Update channels for current pair */
512 	regmap_update_bits(asrc->regmap, REG_ASRCNCR,
513 			   ASRCNCR_ANCi_MASK(index, asrc_priv->soc->channel_bits),
514 			   ASRCNCR_ANCi(index, channels, asrc_priv->soc->channel_bits));
515 
516 	/* Default setting: Automatic selection for processing mode */
517 	regmap_update_bits(asrc->regmap, REG_ASRCTR,
518 			   ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index));
519 	regmap_update_bits(asrc->regmap, REG_ASRCTR,
520 			   ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
521 			   ASRCTR_USR(index));
522 
523 	/* Set the input and output clock sources */
524 	regmap_update_bits(asrc->regmap, REG_ASRCSR,
525 			   ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index),
526 			   ASRCSR_AICS(index, clk_index[IN]) |
527 			   ASRCSR_AOCS(index, clk_index[OUT]));
528 
529 	/* Calculate the input clock divisors */
530 	indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]);
531 	outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]);
532 
533 	/* Suppose indiv and outdiv includes prescaler, so add its MASK too */
534 	regmap_update_bits(asrc->regmap, REG_ASRCDR(index),
535 			   ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) |
536 			   ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index),
537 			   ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv));
538 
539 	/* Implement word_width configurations */
540 	regmap_update_bits(asrc->regmap, REG_ASRMCR1(index),
541 			   ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK,
542 			   ASRMCR1i_OW16(output_word_width) |
543 			   ASRMCR1i_IWD(input_word_width));
544 
545 	/* Enable BUFFER STALL */
546 	regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
547 			   ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi);
548 
549 	/* Set default thresholds for input and output FIFO */
550 	fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD,
551 				ASRC_INPUTFIFO_THRESHOLD);
552 
553 	/* Configure the following only for Ideal Ratio mode */
554 	if (!ideal)
555 		return 0;
556 
557 	/* Clear ASTSx bit to use Ideal Ratio mode */
558 	regmap_update_bits(asrc->regmap, REG_ASRCTR,
559 			   ASRCTR_ATSi_MASK(index), 0);
560 
561 	/* Enable Ideal Ratio mode */
562 	regmap_update_bits(asrc->regmap, REG_ASRCTR,
563 			   ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
564 			   ASRCTR_IDR(index) | ASRCTR_USR(index));
565 
566 	fsl_asrc_sel_proc(inrate, outrate, &pre_proc, &post_proc);
567 
568 	/* Apply configurations for pre- and post-processing */
569 	regmap_update_bits(asrc->regmap, REG_ASRCFG,
570 			   ASRCFG_PREMODi_MASK(index) |	ASRCFG_POSTMODi_MASK(index),
571 			   ASRCFG_PREMOD(index, pre_proc) |
572 			   ASRCFG_POSTMOD(index, post_proc));
573 
574 	return fsl_asrc_set_ideal_ratio(pair, inrate, outrate);
575 }
576 
577 /**
578  * fsl_asrc_start_pair - Start the assigned ASRC pair
579  * @pair: pointer to pair
580  *
581  * It enables the assigned pair and makes it stopped at the stall level.
582  */
fsl_asrc_start_pair(struct fsl_asrc_pair * pair)583 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair)
584 {
585 	struct fsl_asrc *asrc = pair->asrc;
586 	enum asrc_pair_index index = pair->index;
587 	int reg, retry = INIT_RETRY_NUM, i;
588 
589 	/* Enable the current pair */
590 	regmap_update_bits(asrc->regmap, REG_ASRCTR,
591 			   ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index));
592 
593 	/* Wait for status of initialization */
594 	do {
595 		udelay(5);
596 		regmap_read(asrc->regmap, REG_ASRCFG, &reg);
597 		reg &= ASRCFG_INIRQi_MASK(index);
598 	} while (!reg && --retry);
599 
600 	/* NOTE: Doesn't treat initialization timeout as an error */
601 	if (!retry)
602 		pair_warn("initialization isn't finished\n");
603 
604 	/* Make the input fifo to ASRC STALL level */
605 	regmap_read(asrc->regmap, REG_ASRCNCR, &reg);
606 	for (i = 0; i < pair->channels * 4; i++)
607 		regmap_write(asrc->regmap, REG_ASRDI(index), 0);
608 
609 	/* Enable overload interrupt */
610 	regmap_write(asrc->regmap, REG_ASRIER, ASRIER_AOLIE);
611 }
612 
613 /**
614  * fsl_asrc_stop_pair - Stop the assigned ASRC pair
615  * @pair: pointer to pair
616  */
fsl_asrc_stop_pair(struct fsl_asrc_pair * pair)617 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair)
618 {
619 	struct fsl_asrc *asrc = pair->asrc;
620 	enum asrc_pair_index index = pair->index;
621 
622 	/* Stop the current pair */
623 	regmap_update_bits(asrc->regmap, REG_ASRCTR,
624 			   ASRCTR_ASRCEi_MASK(index), 0);
625 }
626 
627 /**
628  * fsl_asrc_get_dma_channel- Get DMA channel according to the pair and direction.
629  * @pair: pointer to pair
630  * @dir: DMA direction
631  */
fsl_asrc_get_dma_channel(struct fsl_asrc_pair * pair,bool dir)632 static struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair,
633 						 bool dir)
634 {
635 	struct fsl_asrc *asrc = pair->asrc;
636 	enum asrc_pair_index index = pair->index;
637 	char name[4];
638 
639 	sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a');
640 
641 	return dma_request_slave_channel(&asrc->pdev->dev, name);
642 }
643 
fsl_asrc_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)644 static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream,
645 				struct snd_soc_dai *dai)
646 {
647 	struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
648 	struct fsl_asrc_priv *asrc_priv = asrc->private;
649 
650 	/* Odd channel number is not valid for older ASRC (channel_bits==3) */
651 	if (asrc_priv->soc->channel_bits == 3)
652 		snd_pcm_hw_constraint_step(substream->runtime, 0,
653 					   SNDRV_PCM_HW_PARAM_CHANNELS, 2);
654 
655 
656 	return snd_pcm_hw_constraint_list(substream->runtime, 0,
657 			SNDRV_PCM_HW_PARAM_RATE, &fsl_asrc_rate_constraints);
658 }
659 
660 /* Select proper clock source for internal ratio mode */
fsl_asrc_select_clk(struct fsl_asrc_priv * asrc_priv,struct fsl_asrc_pair * pair,int in_rate,int out_rate)661 static void fsl_asrc_select_clk(struct fsl_asrc_priv *asrc_priv,
662 				struct fsl_asrc_pair *pair,
663 				int in_rate,
664 				int out_rate)
665 {
666 	struct fsl_asrc_pair_priv *pair_priv = pair->private;
667 	struct asrc_config *config = pair_priv->config;
668 	int rate[2], select_clk[2]; /* Array size 2 means IN and OUT */
669 	int clk_rate, clk_index;
670 	int i, j;
671 
672 	rate[IN] = in_rate;
673 	rate[OUT] = out_rate;
674 
675 	/* Select proper clock source for internal ratio mode */
676 	for (j = 0; j < 2; j++) {
677 		for (i = 0; i < ASRC_CLK_MAP_LEN; i++) {
678 			clk_index = asrc_priv->clk_map[j][i];
679 			clk_rate = clk_get_rate(asrc_priv->asrck_clk[clk_index]);
680 			/* Only match a perfect clock source with no remainder */
681 			if (fsl_asrc_divider_avail(clk_rate, rate[j], NULL))
682 				break;
683 		}
684 
685 		select_clk[j] = i;
686 	}
687 
688 	/* Switch to ideal ratio mode if there is no proper clock source */
689 	if (select_clk[IN] == ASRC_CLK_MAP_LEN || select_clk[OUT] == ASRC_CLK_MAP_LEN) {
690 		select_clk[IN] = INCLK_NONE;
691 		select_clk[OUT] = OUTCLK_ASRCK1_CLK;
692 	}
693 
694 	config->inclk = select_clk[IN];
695 	config->outclk = select_clk[OUT];
696 }
697 
fsl_asrc_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)698 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
699 				  struct snd_pcm_hw_params *params,
700 				  struct snd_soc_dai *dai)
701 {
702 	struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
703 	struct fsl_asrc_priv *asrc_priv = asrc->private;
704 	struct snd_pcm_runtime *runtime = substream->runtime;
705 	struct fsl_asrc_pair *pair = runtime->private_data;
706 	struct fsl_asrc_pair_priv *pair_priv = pair->private;
707 	unsigned int channels = params_channels(params);
708 	unsigned int rate = params_rate(params);
709 	struct asrc_config config;
710 	int ret;
711 
712 	ret = fsl_asrc_request_pair(channels, pair);
713 	if (ret) {
714 		dev_err(dai->dev, "fail to request asrc pair\n");
715 		return ret;
716 	}
717 
718 	pair_priv->config = &config;
719 
720 	config.pair = pair->index;
721 	config.channel_num = channels;
722 
723 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
724 		config.input_format   = params_format(params);
725 		config.output_format  = asrc->asrc_format;
726 		config.input_sample_rate  = rate;
727 		config.output_sample_rate = asrc->asrc_rate;
728 	} else {
729 		config.input_format   = asrc->asrc_format;
730 		config.output_format  = params_format(params);
731 		config.input_sample_rate  = asrc->asrc_rate;
732 		config.output_sample_rate = rate;
733 	}
734 
735 	fsl_asrc_select_clk(asrc_priv, pair,
736 			    config.input_sample_rate,
737 			    config.output_sample_rate);
738 
739 	ret = fsl_asrc_config_pair(pair, false);
740 	if (ret) {
741 		dev_err(dai->dev, "fail to config asrc pair\n");
742 		return ret;
743 	}
744 
745 	return 0;
746 }
747 
fsl_asrc_dai_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)748 static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream,
749 				struct snd_soc_dai *dai)
750 {
751 	struct snd_pcm_runtime *runtime = substream->runtime;
752 	struct fsl_asrc_pair *pair = runtime->private_data;
753 
754 	if (pair)
755 		fsl_asrc_release_pair(pair);
756 
757 	return 0;
758 }
759 
fsl_asrc_dai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)760 static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
761 				struct snd_soc_dai *dai)
762 {
763 	struct snd_pcm_runtime *runtime = substream->runtime;
764 	struct fsl_asrc_pair *pair = runtime->private_data;
765 
766 	switch (cmd) {
767 	case SNDRV_PCM_TRIGGER_START:
768 	case SNDRV_PCM_TRIGGER_RESUME:
769 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
770 		fsl_asrc_start_pair(pair);
771 		break;
772 	case SNDRV_PCM_TRIGGER_STOP:
773 	case SNDRV_PCM_TRIGGER_SUSPEND:
774 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
775 		fsl_asrc_stop_pair(pair);
776 		break;
777 	default:
778 		return -EINVAL;
779 	}
780 
781 	return 0;
782 }
783 
fsl_asrc_dai_probe(struct snd_soc_dai * dai)784 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai)
785 {
786 	struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
787 
788 	snd_soc_dai_init_dma_data(dai, &asrc->dma_params_tx,
789 				  &asrc->dma_params_rx);
790 
791 	return 0;
792 }
793 
794 static const struct snd_soc_dai_ops fsl_asrc_dai_ops = {
795 	.probe		= fsl_asrc_dai_probe,
796 	.startup	= fsl_asrc_dai_startup,
797 	.hw_params	= fsl_asrc_dai_hw_params,
798 	.hw_free	= fsl_asrc_dai_hw_free,
799 	.trigger	= fsl_asrc_dai_trigger,
800 };
801 
802 #define FSL_ASRC_FORMATS	(SNDRV_PCM_FMTBIT_S24_LE | \
803 				 SNDRV_PCM_FMTBIT_S16_LE | \
804 				 SNDRV_PCM_FMTBIT_S24_3LE)
805 
806 static struct snd_soc_dai_driver fsl_asrc_dai = {
807 	.playback = {
808 		.stream_name = "ASRC-Playback",
809 		.channels_min = 1,
810 		.channels_max = 10,
811 		.rate_min = 5512,
812 		.rate_max = 192000,
813 		.rates = SNDRV_PCM_RATE_KNOT,
814 		.formats = FSL_ASRC_FORMATS |
815 			   SNDRV_PCM_FMTBIT_S8,
816 	},
817 	.capture = {
818 		.stream_name = "ASRC-Capture",
819 		.channels_min = 1,
820 		.channels_max = 10,
821 		.rate_min = 5512,
822 		.rate_max = 192000,
823 		.rates = SNDRV_PCM_RATE_KNOT,
824 		.formats = FSL_ASRC_FORMATS,
825 	},
826 	.ops = &fsl_asrc_dai_ops,
827 };
828 
fsl_asrc_readable_reg(struct device * dev,unsigned int reg)829 static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg)
830 {
831 	switch (reg) {
832 	case REG_ASRCTR:
833 	case REG_ASRIER:
834 	case REG_ASRCNCR:
835 	case REG_ASRCFG:
836 	case REG_ASRCSR:
837 	case REG_ASRCDR1:
838 	case REG_ASRCDR2:
839 	case REG_ASRSTR:
840 	case REG_ASRPM1:
841 	case REG_ASRPM2:
842 	case REG_ASRPM3:
843 	case REG_ASRPM4:
844 	case REG_ASRPM5:
845 	case REG_ASRTFR1:
846 	case REG_ASRCCR:
847 	case REG_ASRDOA:
848 	case REG_ASRDOB:
849 	case REG_ASRDOC:
850 	case REG_ASRIDRHA:
851 	case REG_ASRIDRLA:
852 	case REG_ASRIDRHB:
853 	case REG_ASRIDRLB:
854 	case REG_ASRIDRHC:
855 	case REG_ASRIDRLC:
856 	case REG_ASR76K:
857 	case REG_ASR56K:
858 	case REG_ASRMCRA:
859 	case REG_ASRFSTA:
860 	case REG_ASRMCRB:
861 	case REG_ASRFSTB:
862 	case REG_ASRMCRC:
863 	case REG_ASRFSTC:
864 	case REG_ASRMCR1A:
865 	case REG_ASRMCR1B:
866 	case REG_ASRMCR1C:
867 		return true;
868 	default:
869 		return false;
870 	}
871 }
872 
fsl_asrc_volatile_reg(struct device * dev,unsigned int reg)873 static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg)
874 {
875 	switch (reg) {
876 	case REG_ASRSTR:
877 	case REG_ASRDIA:
878 	case REG_ASRDIB:
879 	case REG_ASRDIC:
880 	case REG_ASRDOA:
881 	case REG_ASRDOB:
882 	case REG_ASRDOC:
883 	case REG_ASRFSTA:
884 	case REG_ASRFSTB:
885 	case REG_ASRFSTC:
886 	case REG_ASRCFG:
887 		return true;
888 	default:
889 		return false;
890 	}
891 }
892 
fsl_asrc_writeable_reg(struct device * dev,unsigned int reg)893 static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg)
894 {
895 	switch (reg) {
896 	case REG_ASRCTR:
897 	case REG_ASRIER:
898 	case REG_ASRCNCR:
899 	case REG_ASRCFG:
900 	case REG_ASRCSR:
901 	case REG_ASRCDR1:
902 	case REG_ASRCDR2:
903 	case REG_ASRSTR:
904 	case REG_ASRPM1:
905 	case REG_ASRPM2:
906 	case REG_ASRPM3:
907 	case REG_ASRPM4:
908 	case REG_ASRPM5:
909 	case REG_ASRTFR1:
910 	case REG_ASRCCR:
911 	case REG_ASRDIA:
912 	case REG_ASRDIB:
913 	case REG_ASRDIC:
914 	case REG_ASRIDRHA:
915 	case REG_ASRIDRLA:
916 	case REG_ASRIDRHB:
917 	case REG_ASRIDRLB:
918 	case REG_ASRIDRHC:
919 	case REG_ASRIDRLC:
920 	case REG_ASR76K:
921 	case REG_ASR56K:
922 	case REG_ASRMCRA:
923 	case REG_ASRMCRB:
924 	case REG_ASRMCRC:
925 	case REG_ASRMCR1A:
926 	case REG_ASRMCR1B:
927 	case REG_ASRMCR1C:
928 		return true;
929 	default:
930 		return false;
931 	}
932 }
933 
934 static struct reg_default fsl_asrc_reg[] = {
935 	{ REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 },
936 	{ REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 },
937 	{ REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 },
938 	{ REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 },
939 	{ REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 },
940 	{ REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 },
941 	{ REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 },
942 	{ REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 },
943 	{ REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 },
944 	{ REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 },
945 	{ REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 },
946 	{ REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 },
947 	{ REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 },
948 	{ REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 },
949 	{ REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 },
950 	{ REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 },
951 	{ REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 },
952 	{ REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 },
953 	{ REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 },
954 	{ REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 },
955 	{ REG_ASRMCR1C, 0x0000 },
956 };
957 
958 static const struct regmap_config fsl_asrc_regmap_config = {
959 	.reg_bits = 32,
960 	.reg_stride = 4,
961 	.val_bits = 32,
962 
963 	.max_register = REG_ASRMCR1C,
964 	.reg_defaults = fsl_asrc_reg,
965 	.num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg),
966 	.readable_reg = fsl_asrc_readable_reg,
967 	.volatile_reg = fsl_asrc_volatile_reg,
968 	.writeable_reg = fsl_asrc_writeable_reg,
969 	.cache_type = REGCACHE_FLAT,
970 };
971 
972 /**
973  * fsl_asrc_init - Initialize ASRC registers with a default configuration
974  * @asrc: ASRC context
975  */
fsl_asrc_init(struct fsl_asrc * asrc)976 static int fsl_asrc_init(struct fsl_asrc *asrc)
977 {
978 	unsigned long ipg_rate;
979 
980 	/* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
981 	regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
982 
983 	/* Disable interrupt by default */
984 	regmap_write(asrc->regmap, REG_ASRIER, 0x0);
985 
986 	/* Apply recommended settings for parameters from Reference Manual */
987 	regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff);
988 	regmap_write(asrc->regmap, REG_ASRPM2, 0x255555);
989 	regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280);
990 	regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280);
991 	regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280);
992 
993 	/* Base address for task queue FIFO. Set to 0x7C */
994 	regmap_update_bits(asrc->regmap, REG_ASRTFR1,
995 			   ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
996 
997 	/*
998 	 * Set the period of the 76KHz and 56KHz sampling clocks based on
999 	 * the ASRC processing clock.
1000 	 * On iMX6, ipg_clk = 133MHz, REG_ASR76K = 0x06D6, REG_ASR56K = 0x0947
1001 	 */
1002 	ipg_rate = clk_get_rate(asrc->ipg_clk);
1003 	regmap_write(asrc->regmap, REG_ASR76K, ipg_rate / 76000);
1004 	return regmap_write(asrc->regmap, REG_ASR56K, ipg_rate / 56000);
1005 }
1006 
1007 /**
1008  * fsl_asrc_isr- Interrupt handler for ASRC
1009  * @irq: irq number
1010  * @dev_id: ASRC context
1011  */
fsl_asrc_isr(int irq,void * dev_id)1012 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
1013 {
1014 	struct fsl_asrc *asrc = (struct fsl_asrc *)dev_id;
1015 	struct device *dev = &asrc->pdev->dev;
1016 	enum asrc_pair_index index;
1017 	u32 status;
1018 
1019 	regmap_read(asrc->regmap, REG_ASRSTR, &status);
1020 
1021 	/* Clean overload error */
1022 	regmap_write(asrc->regmap, REG_ASRSTR, ASRSTR_AOLE);
1023 
1024 	/*
1025 	 * We here use dev_dbg() for all exceptions because ASRC itself does
1026 	 * not care if FIFO overflowed or underrun while a warning in the
1027 	 * interrupt would result a ridged conversion.
1028 	 */
1029 	for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
1030 		if (!asrc->pair[index])
1031 			continue;
1032 
1033 		if (status & ASRSTR_ATQOL) {
1034 			asrc->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
1035 			dev_dbg(dev, "ASRC Task Queue FIFO overload\n");
1036 		}
1037 
1038 		if (status & ASRSTR_AOOL(index)) {
1039 			asrc->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
1040 			pair_dbg("Output Task Overload\n");
1041 		}
1042 
1043 		if (status & ASRSTR_AIOL(index)) {
1044 			asrc->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
1045 			pair_dbg("Input Task Overload\n");
1046 		}
1047 
1048 		if (status & ASRSTR_AODO(index)) {
1049 			asrc->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
1050 			pair_dbg("Output Data Buffer has overflowed\n");
1051 		}
1052 
1053 		if (status & ASRSTR_AIDU(index)) {
1054 			asrc->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
1055 			pair_dbg("Input Data Buffer has underflowed\n");
1056 		}
1057 	}
1058 
1059 	return IRQ_HANDLED;
1060 }
1061 
fsl_asrc_get_fifo_addr(u8 dir,enum asrc_pair_index index)1062 static int fsl_asrc_get_fifo_addr(u8 dir, enum asrc_pair_index index)
1063 {
1064 	return REG_ASRDx(dir, index);
1065 }
1066 
1067 /* Get sample numbers in FIFO */
fsl_asrc_get_output_fifo_size(struct fsl_asrc_pair * pair)1068 static unsigned int fsl_asrc_get_output_fifo_size(struct fsl_asrc_pair *pair)
1069 {
1070 	struct fsl_asrc *asrc = pair->asrc;
1071 	enum asrc_pair_index index = pair->index;
1072 	u32 val;
1073 
1074 	regmap_read(asrc->regmap, REG_ASRFST(index), &val);
1075 
1076 	val &= ASRFSTi_OUTPUT_FIFO_MASK;
1077 
1078 	return val >> ASRFSTi_OUTPUT_FIFO_SHIFT;
1079 }
1080 
fsl_asrc_m2m_prepare(struct fsl_asrc_pair * pair)1081 static int fsl_asrc_m2m_prepare(struct fsl_asrc_pair *pair)
1082 {
1083 	struct fsl_asrc_pair_priv *pair_priv = pair->private;
1084 	struct fsl_asrc *asrc = pair->asrc;
1085 	struct device *dev = &asrc->pdev->dev;
1086 	struct asrc_config config;
1087 	int ret;
1088 
1089 	/* fill config */
1090 	config.pair = pair->index;
1091 	config.channel_num = pair->channels;
1092 	config.input_sample_rate = pair->rate[IN];
1093 	config.output_sample_rate = pair->rate[OUT];
1094 	config.input_format = pair->sample_format[IN];
1095 	config.output_format = pair->sample_format[OUT];
1096 	config.inclk = INCLK_NONE;
1097 	config.outclk = OUTCLK_ASRCK1_CLK;
1098 
1099 	pair_priv->config = &config;
1100 	ret = fsl_asrc_config_pair(pair, true);
1101 	if (ret) {
1102 		dev_err(dev, "failed to config pair: %d\n", ret);
1103 		return ret;
1104 	}
1105 
1106 	pair->first_convert = 1;
1107 
1108 	return 0;
1109 }
1110 
fsl_asrc_m2m_start(struct fsl_asrc_pair * pair)1111 static int fsl_asrc_m2m_start(struct fsl_asrc_pair *pair)
1112 {
1113 	if (pair->first_convert) {
1114 		fsl_asrc_start_pair(pair);
1115 		pair->first_convert = 0;
1116 	}
1117 	/*
1118 	 * Clear DMA request during the stall state of ASRC:
1119 	 * During STALL state, the remaining in input fifo would never be
1120 	 * smaller than the input threshold while the output fifo would not
1121 	 * be bigger than output one. Thus the DMA request would be cleared.
1122 	 */
1123 	fsl_asrc_set_watermarks(pair, ASRC_FIFO_THRESHOLD_MIN,
1124 				ASRC_FIFO_THRESHOLD_MAX);
1125 
1126 	/* Update the real input threshold to raise DMA request */
1127 	fsl_asrc_set_watermarks(pair, ASRC_M2M_INPUTFIFO_WML,
1128 				ASRC_M2M_OUTPUTFIFO_WML);
1129 
1130 	return 0;
1131 }
1132 
fsl_asrc_m2m_stop(struct fsl_asrc_pair * pair)1133 static int fsl_asrc_m2m_stop(struct fsl_asrc_pair *pair)
1134 {
1135 	if (!pair->first_convert) {
1136 		fsl_asrc_stop_pair(pair);
1137 		pair->first_convert = 1;
1138 	}
1139 
1140 	return 0;
1141 }
1142 
1143 /* calculate capture data length according to output data length and sample rate */
fsl_asrc_m2m_calc_out_len(struct fsl_asrc_pair * pair,int input_buffer_length)1144 static int fsl_asrc_m2m_calc_out_len(struct fsl_asrc_pair *pair, int input_buffer_length)
1145 {
1146 	unsigned int in_width, out_width;
1147 	unsigned int channels = pair->channels;
1148 	unsigned int in_samples, out_samples;
1149 	unsigned int out_length;
1150 
1151 	in_width = snd_pcm_format_physical_width(pair->sample_format[IN]) / 8;
1152 	out_width = snd_pcm_format_physical_width(pair->sample_format[OUT]) / 8;
1153 
1154 	in_samples = input_buffer_length / in_width / channels;
1155 	out_samples = pair->rate[OUT] * in_samples / pair->rate[IN];
1156 	out_length = (out_samples - ASRC_OUTPUT_LAST_SAMPLE) * out_width * channels;
1157 
1158 	return out_length;
1159 }
1160 
fsl_asrc_m2m_get_maxburst(u8 dir,struct fsl_asrc_pair * pair)1161 static int fsl_asrc_m2m_get_maxburst(u8 dir, struct fsl_asrc_pair *pair)
1162 {
1163 	struct fsl_asrc *asrc = pair->asrc;
1164 	struct fsl_asrc_priv *asrc_priv = asrc->private;
1165 	int wml = (dir == IN) ? ASRC_M2M_INPUTFIFO_WML : ASRC_M2M_OUTPUTFIFO_WML;
1166 
1167 	if (!asrc_priv->soc->use_edma)
1168 		return wml * pair->channels;
1169 	else
1170 		return 1;
1171 }
1172 
fsl_asrc_m2m_get_cap(struct fsl_asrc_m2m_cap * cap)1173 static int fsl_asrc_m2m_get_cap(struct fsl_asrc_m2m_cap *cap)
1174 {
1175 	cap->fmt_in = FSL_ASRC_FORMATS;
1176 	cap->fmt_out = FSL_ASRC_FORMATS | SNDRV_PCM_FMTBIT_S8;
1177 
1178 	cap->rate_in = supported_asrc_rate;
1179 	cap->rate_in_count = ARRAY_SIZE(supported_asrc_rate);
1180 	cap->rate_out = supported_asrc_rate;
1181 	cap->rate_out_count = ARRAY_SIZE(supported_asrc_rate);
1182 	cap->chan_min = 1;
1183 	cap->chan_max = 10;
1184 
1185 	return 0;
1186 }
1187 
fsl_asrc_m2m_pair_resume(struct fsl_asrc_pair * pair)1188 static int fsl_asrc_m2m_pair_resume(struct fsl_asrc_pair *pair)
1189 {
1190 	struct fsl_asrc *asrc = pair->asrc;
1191 	int i;
1192 
1193 	for (i = 0; i < pair->channels * 4; i++)
1194 		regmap_write(asrc->regmap, REG_ASRDI(pair->index), 0);
1195 
1196 	pair->first_convert = 1;
1197 	return 0;
1198 }
1199 
1200 static int fsl_asrc_runtime_resume(struct device *dev);
1201 static int fsl_asrc_runtime_suspend(struct device *dev);
1202 
fsl_asrc_probe(struct platform_device * pdev)1203 static int fsl_asrc_probe(struct platform_device *pdev)
1204 {
1205 	struct device_node *np = pdev->dev.of_node;
1206 	struct fsl_asrc_priv *asrc_priv;
1207 	struct fsl_asrc *asrc;
1208 	struct resource *res;
1209 	void __iomem *regs;
1210 	int irq, ret, i;
1211 	u32 asrc_fmt = 0;
1212 	u32 map_idx;
1213 	char tmp[16];
1214 	u32 width;
1215 
1216 	asrc = devm_kzalloc(&pdev->dev, sizeof(*asrc), GFP_KERNEL);
1217 	if (!asrc)
1218 		return -ENOMEM;
1219 
1220 	asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL);
1221 	if (!asrc_priv)
1222 		return -ENOMEM;
1223 
1224 	asrc->pdev = pdev;
1225 	asrc->private = asrc_priv;
1226 
1227 	/* Get the addresses and IRQ */
1228 	regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1229 	if (IS_ERR(regs))
1230 		return PTR_ERR(regs);
1231 
1232 	asrc->paddr = res->start;
1233 
1234 	asrc->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_asrc_regmap_config);
1235 	if (IS_ERR(asrc->regmap)) {
1236 		dev_err(&pdev->dev, "failed to init regmap\n");
1237 		return PTR_ERR(asrc->regmap);
1238 	}
1239 
1240 	irq = platform_get_irq(pdev, 0);
1241 	if (irq < 0)
1242 		return irq;
1243 
1244 	ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,
1245 			       dev_name(&pdev->dev), asrc);
1246 	if (ret) {
1247 		dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
1248 		return ret;
1249 	}
1250 
1251 	asrc->mem_clk = devm_clk_get(&pdev->dev, "mem");
1252 	if (IS_ERR(asrc->mem_clk)) {
1253 		dev_err(&pdev->dev, "failed to get mem clock\n");
1254 		return PTR_ERR(asrc->mem_clk);
1255 	}
1256 
1257 	asrc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
1258 	if (IS_ERR(asrc->ipg_clk)) {
1259 		dev_err(&pdev->dev, "failed to get ipg clock\n");
1260 		return PTR_ERR(asrc->ipg_clk);
1261 	}
1262 
1263 	asrc->spba_clk = devm_clk_get(&pdev->dev, "spba");
1264 	if (IS_ERR(asrc->spba_clk))
1265 		dev_warn(&pdev->dev, "failed to get spba clock\n");
1266 
1267 	for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
1268 		sprintf(tmp, "asrck_%x", i);
1269 		asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
1270 		if (IS_ERR(asrc_priv->asrck_clk[i])) {
1271 			dev_err(&pdev->dev, "failed to get %s clock\n", tmp);
1272 			return PTR_ERR(asrc_priv->asrck_clk[i]);
1273 		}
1274 	}
1275 
1276 	asrc_priv->soc = of_device_get_match_data(&pdev->dev);
1277 	asrc->use_edma = asrc_priv->soc->use_edma;
1278 	asrc->get_dma_channel = fsl_asrc_get_dma_channel;
1279 	asrc->request_pair = fsl_asrc_request_pair;
1280 	asrc->release_pair = fsl_asrc_release_pair;
1281 	asrc->get_fifo_addr = fsl_asrc_get_fifo_addr;
1282 	asrc->pair_priv_size = sizeof(struct fsl_asrc_pair_priv);
1283 
1284 	asrc->m2m_prepare = fsl_asrc_m2m_prepare;
1285 	asrc->m2m_start = fsl_asrc_m2m_start;
1286 	asrc->m2m_stop = fsl_asrc_m2m_stop;
1287 	asrc->get_output_fifo_size = fsl_asrc_get_output_fifo_size;
1288 	asrc->m2m_calc_out_len = fsl_asrc_m2m_calc_out_len;
1289 	asrc->m2m_get_maxburst = fsl_asrc_m2m_get_maxburst;
1290 	asrc->m2m_pair_resume = fsl_asrc_m2m_pair_resume;
1291 	asrc->m2m_get_cap = fsl_asrc_m2m_get_cap;
1292 
1293 	if (of_device_is_compatible(np, "fsl,imx35-asrc")) {
1294 		asrc_priv->clk_map[IN] = input_clk_map_imx35;
1295 		asrc_priv->clk_map[OUT] = output_clk_map_imx35;
1296 	} else if (of_device_is_compatible(np, "fsl,imx53-asrc")) {
1297 		asrc_priv->clk_map[IN] = input_clk_map_imx53;
1298 		asrc_priv->clk_map[OUT] = output_clk_map_imx53;
1299 	} else if (of_device_is_compatible(np, "fsl,imx8qm-asrc") ||
1300 		   of_device_is_compatible(np, "fsl,imx8qxp-asrc")) {
1301 		ret = of_property_read_u32(np, "fsl,asrc-clk-map", &map_idx);
1302 		if (ret) {
1303 			dev_err(&pdev->dev, "failed to get clk map index\n");
1304 			return ret;
1305 		}
1306 
1307 		if (map_idx > 1) {
1308 			dev_err(&pdev->dev, "unsupported clk map index\n");
1309 			return -EINVAL;
1310 		}
1311 		if (of_device_is_compatible(np, "fsl,imx8qm-asrc")) {
1312 			asrc_priv->clk_map[IN] = clk_map_imx8qm[map_idx];
1313 			asrc_priv->clk_map[OUT] = clk_map_imx8qm[map_idx];
1314 		} else {
1315 			asrc_priv->clk_map[IN] = clk_map_imx8qxp[map_idx];
1316 			asrc_priv->clk_map[OUT] = clk_map_imx8qxp[map_idx];
1317 		}
1318 	}
1319 
1320 	asrc->channel_avail = 10;
1321 
1322 	ret = of_property_read_u32(np, "fsl,asrc-rate",
1323 				   &asrc->asrc_rate);
1324 	if (ret) {
1325 		dev_err(&pdev->dev, "failed to get output rate\n");
1326 		return ret;
1327 	}
1328 
1329 	ret = of_property_read_u32(np, "fsl,asrc-format", &asrc_fmt);
1330 	asrc->asrc_format = (__force snd_pcm_format_t)asrc_fmt;
1331 	if (ret) {
1332 		ret = of_property_read_u32(np, "fsl,asrc-width", &width);
1333 		if (ret) {
1334 			dev_err(&pdev->dev, "failed to decide output format\n");
1335 			return ret;
1336 		}
1337 
1338 		switch (width) {
1339 		case 16:
1340 			asrc->asrc_format = SNDRV_PCM_FORMAT_S16_LE;
1341 			break;
1342 		case 24:
1343 			asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
1344 			break;
1345 		default:
1346 			dev_warn(&pdev->dev,
1347 				 "unsupported width, use default S24_LE\n");
1348 			asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
1349 			break;
1350 		}
1351 	}
1352 
1353 	if (!(FSL_ASRC_FORMATS & pcm_format_to_bits(asrc->asrc_format))) {
1354 		dev_warn(&pdev->dev, "unsupported width, use default S24_LE\n");
1355 		asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
1356 	}
1357 
1358 	platform_set_drvdata(pdev, asrc);
1359 	spin_lock_init(&asrc->lock);
1360 	pm_runtime_enable(&pdev->dev);
1361 	if (!pm_runtime_enabled(&pdev->dev)) {
1362 		ret = fsl_asrc_runtime_resume(&pdev->dev);
1363 		if (ret)
1364 			goto err_pm_disable;
1365 	}
1366 
1367 	ret = pm_runtime_resume_and_get(&pdev->dev);
1368 	if (ret < 0)
1369 		goto err_pm_get_sync;
1370 
1371 	ret = fsl_asrc_init(asrc);
1372 	if (ret) {
1373 		dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
1374 		goto err_pm_get_sync;
1375 	}
1376 
1377 	ret = pm_runtime_put_sync(&pdev->dev);
1378 	if (ret < 0 && ret != -ENOSYS)
1379 		goto err_pm_get_sync;
1380 
1381 	ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component,
1382 					      &fsl_asrc_dai, 1);
1383 	if (ret) {
1384 		dev_err(&pdev->dev, "failed to register ASoC DAI\n");
1385 		goto err_pm_get_sync;
1386 	}
1387 
1388 	ret = fsl_asrc_m2m_init(asrc);
1389 	if (ret) {
1390 		dev_err(&pdev->dev, "failed to init m2m device %d\n", ret);
1391 		return ret;
1392 	}
1393 
1394 	return 0;
1395 
1396 err_pm_get_sync:
1397 	if (!pm_runtime_status_suspended(&pdev->dev))
1398 		fsl_asrc_runtime_suspend(&pdev->dev);
1399 err_pm_disable:
1400 	pm_runtime_disable(&pdev->dev);
1401 	return ret;
1402 }
1403 
fsl_asrc_remove(struct platform_device * pdev)1404 static void fsl_asrc_remove(struct platform_device *pdev)
1405 {
1406 	struct fsl_asrc *asrc = dev_get_drvdata(&pdev->dev);
1407 
1408 	fsl_asrc_m2m_exit(asrc);
1409 
1410 	pm_runtime_disable(&pdev->dev);
1411 	if (!pm_runtime_status_suspended(&pdev->dev))
1412 		fsl_asrc_runtime_suspend(&pdev->dev);
1413 }
1414 
fsl_asrc_runtime_resume(struct device * dev)1415 static int fsl_asrc_runtime_resume(struct device *dev)
1416 {
1417 	struct fsl_asrc *asrc = dev_get_drvdata(dev);
1418 	struct fsl_asrc_priv *asrc_priv = asrc->private;
1419 	int reg, retry = INIT_RETRY_NUM;
1420 	int i, ret;
1421 	u32 asrctr;
1422 
1423 	ret = clk_prepare_enable(asrc->mem_clk);
1424 	if (ret)
1425 		return ret;
1426 	ret = clk_prepare_enable(asrc->ipg_clk);
1427 	if (ret)
1428 		goto disable_mem_clk;
1429 	if (!IS_ERR(asrc->spba_clk)) {
1430 		ret = clk_prepare_enable(asrc->spba_clk);
1431 		if (ret)
1432 			goto disable_ipg_clk;
1433 	}
1434 	for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
1435 		ret = clk_prepare_enable(asrc_priv->asrck_clk[i]);
1436 		if (ret)
1437 			goto disable_asrck_clk;
1438 	}
1439 
1440 	/* Stop all pairs provisionally */
1441 	regmap_read(asrc->regmap, REG_ASRCTR, &asrctr);
1442 	regmap_update_bits(asrc->regmap, REG_ASRCTR,
1443 			   ASRCTR_ASRCEi_ALL_MASK, 0);
1444 
1445 	/* Restore all registers */
1446 	regcache_cache_only(asrc->regmap, false);
1447 	regcache_mark_dirty(asrc->regmap);
1448 	regcache_sync(asrc->regmap);
1449 
1450 	regmap_update_bits(asrc->regmap, REG_ASRCFG,
1451 			   ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK |
1452 			   ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg);
1453 
1454 	/* Restart enabled pairs */
1455 	regmap_update_bits(asrc->regmap, REG_ASRCTR,
1456 			   ASRCTR_ASRCEi_ALL_MASK, asrctr);
1457 
1458 	/* Wait for status of initialization for all enabled pairs */
1459 	do {
1460 		udelay(5);
1461 		regmap_read(asrc->regmap, REG_ASRCFG, &reg);
1462 		reg = (reg >> ASRCFG_INIRQi_SHIFT(0)) & 0x7;
1463 	} while ((reg != ((asrctr >> ASRCTR_ASRCEi_SHIFT(0)) & 0x7)) && --retry);
1464 
1465 	/*
1466 	 * NOTE: Doesn't treat initialization timeout as an error
1467 	 * Some of the pairs may success, then still can continue.
1468 	 */
1469 	if (!retry) {
1470 		for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
1471 			if ((asrctr & ASRCTR_ASRCEi_MASK(i)) && !(reg & (1 << i)))
1472 				dev_warn(dev, "Pair %c initialization isn't finished\n", 'A' + i);
1473 		}
1474 	}
1475 
1476 	return 0;
1477 
1478 disable_asrck_clk:
1479 	for (i--; i >= 0; i--)
1480 		clk_disable_unprepare(asrc_priv->asrck_clk[i]);
1481 	if (!IS_ERR(asrc->spba_clk))
1482 		clk_disable_unprepare(asrc->spba_clk);
1483 disable_ipg_clk:
1484 	clk_disable_unprepare(asrc->ipg_clk);
1485 disable_mem_clk:
1486 	clk_disable_unprepare(asrc->mem_clk);
1487 	return ret;
1488 }
1489 
fsl_asrc_runtime_suspend(struct device * dev)1490 static int fsl_asrc_runtime_suspend(struct device *dev)
1491 {
1492 	struct fsl_asrc *asrc = dev_get_drvdata(dev);
1493 	struct fsl_asrc_priv *asrc_priv = asrc->private;
1494 	int i;
1495 
1496 	regmap_read(asrc->regmap, REG_ASRCFG,
1497 		    &asrc_priv->regcache_cfg);
1498 
1499 	regcache_cache_only(asrc->regmap, true);
1500 
1501 	for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
1502 		clk_disable_unprepare(asrc_priv->asrck_clk[i]);
1503 	if (!IS_ERR(asrc->spba_clk))
1504 		clk_disable_unprepare(asrc->spba_clk);
1505 	clk_disable_unprepare(asrc->ipg_clk);
1506 	clk_disable_unprepare(asrc->mem_clk);
1507 
1508 	return 0;
1509 }
1510 
fsl_asrc_suspend(struct device * dev)1511 static int fsl_asrc_suspend(struct device *dev)
1512 {
1513 	struct fsl_asrc *asrc = dev_get_drvdata(dev);
1514 	int ret;
1515 
1516 	fsl_asrc_m2m_suspend(asrc);
1517 	ret = pm_runtime_force_suspend(dev);
1518 	return ret;
1519 }
1520 
fsl_asrc_resume(struct device * dev)1521 static int fsl_asrc_resume(struct device *dev)
1522 {
1523 	struct fsl_asrc *asrc = dev_get_drvdata(dev);
1524 	int ret;
1525 
1526 	ret = pm_runtime_force_resume(dev);
1527 	fsl_asrc_m2m_resume(asrc);
1528 	return ret;
1529 }
1530 
1531 static const struct dev_pm_ops fsl_asrc_pm = {
1532 	RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL)
1533 	SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume)
1534 };
1535 
1536 static const struct fsl_asrc_soc_data fsl_asrc_imx35_data = {
1537 	.use_edma = false,
1538 	.channel_bits = 3,
1539 };
1540 
1541 static const struct fsl_asrc_soc_data fsl_asrc_imx53_data = {
1542 	.use_edma = false,
1543 	.channel_bits = 4,
1544 };
1545 
1546 static const struct fsl_asrc_soc_data fsl_asrc_imx8qm_data = {
1547 	.use_edma = true,
1548 	.channel_bits = 4,
1549 };
1550 
1551 static const struct fsl_asrc_soc_data fsl_asrc_imx8qxp_data = {
1552 	.use_edma = true,
1553 	.channel_bits = 4,
1554 };
1555 
1556 static const struct of_device_id fsl_asrc_ids[] = {
1557 	{ .compatible = "fsl,imx35-asrc", .data = &fsl_asrc_imx35_data },
1558 	{ .compatible = "fsl,imx53-asrc", .data = &fsl_asrc_imx53_data },
1559 	{ .compatible = "fsl,imx8qm-asrc", .data = &fsl_asrc_imx8qm_data },
1560 	{ .compatible = "fsl,imx8qxp-asrc", .data = &fsl_asrc_imx8qxp_data },
1561 	{}
1562 };
1563 MODULE_DEVICE_TABLE(of, fsl_asrc_ids);
1564 
1565 static struct platform_driver fsl_asrc_driver = {
1566 	.probe = fsl_asrc_probe,
1567 	.remove = fsl_asrc_remove,
1568 	.driver = {
1569 		.name = "fsl-asrc",
1570 		.of_match_table = fsl_asrc_ids,
1571 		.pm = pm_ptr(&fsl_asrc_pm),
1572 	},
1573 };
1574 module_platform_driver(fsl_asrc_driver);
1575 
1576 MODULE_DESCRIPTION("Freescale ASRC ASoC driver");
1577 MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>");
1578 MODULE_ALIAS("platform:fsl-asrc");
1579 MODULE_LICENSE("GPL v2");
1580