1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright 2019 NXP
3
4 #include <linux/atomic.h>
5 #include <linux/clk.h>
6 #include <linux/device.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/firmware.h>
9 #include <linux/interrupt.h>
10 #include <linux/kobject.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/miscdevice.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/of_platform.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/sched/signal.h>
21 #include <linux/sysfs.h>
22 #include <linux/types.h>
23 #include <linux/gcd.h>
24 #include <sound/dmaengine_pcm.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/tlv.h>
29 #include <sound/core.h>
30
31 #include "fsl_easrc.h"
32 #include "imx-pcm.h"
33
34 #define FSL_EASRC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
35 SNDRV_PCM_FMTBIT_U16_LE | \
36 SNDRV_PCM_FMTBIT_S24_LE | \
37 SNDRV_PCM_FMTBIT_S24_3LE | \
38 SNDRV_PCM_FMTBIT_U24_LE | \
39 SNDRV_PCM_FMTBIT_U24_3LE | \
40 SNDRV_PCM_FMTBIT_S32_LE | \
41 SNDRV_PCM_FMTBIT_U32_LE | \
42 SNDRV_PCM_FMTBIT_S20_3LE | \
43 SNDRV_PCM_FMTBIT_U20_3LE | \
44 SNDRV_PCM_FMTBIT_FLOAT_LE)
45
fsl_easrc_iec958_put_bits(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)46 static int fsl_easrc_iec958_put_bits(struct snd_kcontrol *kcontrol,
47 struct snd_ctl_elem_value *ucontrol)
48 {
49 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
50 struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp);
51 struct fsl_easrc_priv *easrc_priv = easrc->private;
52 struct soc_mreg_control *mc =
53 (struct soc_mreg_control *)kcontrol->private_value;
54 unsigned int regval = ucontrol->value.integer.value[0];
55 int ret;
56
57 ret = (easrc_priv->bps_iec958[mc->regbase] != regval);
58
59 easrc_priv->bps_iec958[mc->regbase] = regval;
60
61 return ret;
62 }
63
fsl_easrc_iec958_get_bits(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)64 static int fsl_easrc_iec958_get_bits(struct snd_kcontrol *kcontrol,
65 struct snd_ctl_elem_value *ucontrol)
66 {
67 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
68 struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp);
69 struct fsl_easrc_priv *easrc_priv = easrc->private;
70 struct soc_mreg_control *mc =
71 (struct soc_mreg_control *)kcontrol->private_value;
72
73 ucontrol->value.enumerated.item[0] = easrc_priv->bps_iec958[mc->regbase];
74
75 return 0;
76 }
77
fsl_easrc_get_reg(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)78 static int fsl_easrc_get_reg(struct snd_kcontrol *kcontrol,
79 struct snd_ctl_elem_value *ucontrol)
80 {
81 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
82 struct soc_mreg_control *mc =
83 (struct soc_mreg_control *)kcontrol->private_value;
84 unsigned int regval;
85
86 regval = snd_soc_component_read(component, mc->regbase);
87
88 ucontrol->value.integer.value[0] = regval;
89
90 return 0;
91 }
92
fsl_easrc_set_reg(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)93 static int fsl_easrc_set_reg(struct snd_kcontrol *kcontrol,
94 struct snd_ctl_elem_value *ucontrol)
95 {
96 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
97 struct soc_mreg_control *mc =
98 (struct soc_mreg_control *)kcontrol->private_value;
99 struct fsl_asrc *easrc = snd_soc_component_get_drvdata(component);
100 unsigned int regval = ucontrol->value.integer.value[0];
101 bool changed;
102 int ret;
103
104 ret = regmap_update_bits_check(easrc->regmap, mc->regbase,
105 GENMASK(31, 0), regval, &changed);
106 if (ret != 0)
107 return ret;
108
109 return changed;
110 }
111
112 #define SOC_SINGLE_REG_RW(xname, xreg) \
113 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \
114 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
115 .info = snd_soc_info_xr_sx, .get = fsl_easrc_get_reg, \
116 .put = fsl_easrc_set_reg, \
117 .private_value = (unsigned long)&(struct soc_mreg_control) \
118 { .regbase = xreg, .regcount = 1, .nbits = 32, \
119 .invert = 0, .min = 0, .max = 0xffffffff, } }
120
121 #define SOC_SINGLE_VAL_RW(xname, xreg) \
122 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \
123 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
124 .info = snd_soc_info_xr_sx, .get = fsl_easrc_iec958_get_bits, \
125 .put = fsl_easrc_iec958_put_bits, \
126 .private_value = (unsigned long)&(struct soc_mreg_control) \
127 { .regbase = xreg, .regcount = 1, .nbits = 32, \
128 .invert = 0, .min = 0, .max = 2, } }
129
130 static const struct snd_kcontrol_new fsl_easrc_snd_controls[] = {
131 SOC_SINGLE("Context 0 Dither Switch", REG_EASRC_COC(0), 0, 1, 0),
132 SOC_SINGLE("Context 1 Dither Switch", REG_EASRC_COC(1), 0, 1, 0),
133 SOC_SINGLE("Context 2 Dither Switch", REG_EASRC_COC(2), 0, 1, 0),
134 SOC_SINGLE("Context 3 Dither Switch", REG_EASRC_COC(3), 0, 1, 0),
135
136 SOC_SINGLE("Context 0 IEC958 Validity", REG_EASRC_COC(0), 2, 1, 0),
137 SOC_SINGLE("Context 1 IEC958 Validity", REG_EASRC_COC(1), 2, 1, 0),
138 SOC_SINGLE("Context 2 IEC958 Validity", REG_EASRC_COC(2), 2, 1, 0),
139 SOC_SINGLE("Context 3 IEC958 Validity", REG_EASRC_COC(3), 2, 1, 0),
140
141 SOC_SINGLE_VAL_RW("Context 0 IEC958 Bits Per Sample", 0),
142 SOC_SINGLE_VAL_RW("Context 1 IEC958 Bits Per Sample", 1),
143 SOC_SINGLE_VAL_RW("Context 2 IEC958 Bits Per Sample", 2),
144 SOC_SINGLE_VAL_RW("Context 3 IEC958 Bits Per Sample", 3),
145
146 SOC_SINGLE_REG_RW("Context 0 IEC958 CS0", REG_EASRC_CS0(0)),
147 SOC_SINGLE_REG_RW("Context 1 IEC958 CS0", REG_EASRC_CS0(1)),
148 SOC_SINGLE_REG_RW("Context 2 IEC958 CS0", REG_EASRC_CS0(2)),
149 SOC_SINGLE_REG_RW("Context 3 IEC958 CS0", REG_EASRC_CS0(3)),
150 SOC_SINGLE_REG_RW("Context 0 IEC958 CS1", REG_EASRC_CS1(0)),
151 SOC_SINGLE_REG_RW("Context 1 IEC958 CS1", REG_EASRC_CS1(1)),
152 SOC_SINGLE_REG_RW("Context 2 IEC958 CS1", REG_EASRC_CS1(2)),
153 SOC_SINGLE_REG_RW("Context 3 IEC958 CS1", REG_EASRC_CS1(3)),
154 SOC_SINGLE_REG_RW("Context 0 IEC958 CS2", REG_EASRC_CS2(0)),
155 SOC_SINGLE_REG_RW("Context 1 IEC958 CS2", REG_EASRC_CS2(1)),
156 SOC_SINGLE_REG_RW("Context 2 IEC958 CS2", REG_EASRC_CS2(2)),
157 SOC_SINGLE_REG_RW("Context 3 IEC958 CS2", REG_EASRC_CS2(3)),
158 SOC_SINGLE_REG_RW("Context 0 IEC958 CS3", REG_EASRC_CS3(0)),
159 SOC_SINGLE_REG_RW("Context 1 IEC958 CS3", REG_EASRC_CS3(1)),
160 SOC_SINGLE_REG_RW("Context 2 IEC958 CS3", REG_EASRC_CS3(2)),
161 SOC_SINGLE_REG_RW("Context 3 IEC958 CS3", REG_EASRC_CS3(3)),
162 SOC_SINGLE_REG_RW("Context 0 IEC958 CS4", REG_EASRC_CS4(0)),
163 SOC_SINGLE_REG_RW("Context 1 IEC958 CS4", REG_EASRC_CS4(1)),
164 SOC_SINGLE_REG_RW("Context 2 IEC958 CS4", REG_EASRC_CS4(2)),
165 SOC_SINGLE_REG_RW("Context 3 IEC958 CS4", REG_EASRC_CS4(3)),
166 SOC_SINGLE_REG_RW("Context 0 IEC958 CS5", REG_EASRC_CS5(0)),
167 SOC_SINGLE_REG_RW("Context 1 IEC958 CS5", REG_EASRC_CS5(1)),
168 SOC_SINGLE_REG_RW("Context 2 IEC958 CS5", REG_EASRC_CS5(2)),
169 SOC_SINGLE_REG_RW("Context 3 IEC958 CS5", REG_EASRC_CS5(3)),
170 };
171
172 /*
173 * fsl_easrc_set_rs_ratio
174 *
175 * According to the resample taps, calculate the resample ratio
176 * ratio = in_rate / out_rate
177 */
fsl_easrc_set_rs_ratio(struct fsl_asrc_pair * ctx)178 static int fsl_easrc_set_rs_ratio(struct fsl_asrc_pair *ctx)
179 {
180 struct fsl_asrc *easrc = ctx->asrc;
181 struct fsl_easrc_priv *easrc_priv = easrc->private;
182 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
183 unsigned int in_rate = ctx_priv->in_params.norm_rate;
184 unsigned int out_rate = ctx_priv->out_params.norm_rate;
185 unsigned int frac_bits;
186 u64 val;
187 u32 *r;
188
189 switch (easrc_priv->rs_num_taps) {
190 case EASRC_RS_32_TAPS:
191 /* integer bits = 5; */
192 frac_bits = 39;
193 break;
194 case EASRC_RS_64_TAPS:
195 /* integer bits = 6; */
196 frac_bits = 38;
197 break;
198 case EASRC_RS_128_TAPS:
199 /* integer bits = 7; */
200 frac_bits = 37;
201 break;
202 default:
203 return -EINVAL;
204 }
205
206 val = (u64)in_rate << frac_bits;
207 do_div(val, out_rate);
208 r = (uint32_t *)&val;
209
210 if (r[1] & 0xFFFFF000) {
211 dev_err(&easrc->pdev->dev, "ratio exceed range\n");
212 return -EINVAL;
213 }
214
215 regmap_write(easrc->regmap, REG_EASRC_RRL(ctx->index),
216 EASRC_RRL_RS_RL(r[0]));
217 regmap_write(easrc->regmap, REG_EASRC_RRH(ctx->index),
218 EASRC_RRH_RS_RH(r[1]));
219
220 return 0;
221 }
222
223 /* Normalize input and output sample rates */
fsl_easrc_normalize_rates(struct fsl_asrc_pair * ctx)224 static void fsl_easrc_normalize_rates(struct fsl_asrc_pair *ctx)
225 {
226 struct fsl_easrc_ctx_priv *ctx_priv;
227 int a, b;
228
229 if (!ctx)
230 return;
231
232 ctx_priv = ctx->private;
233
234 a = ctx_priv->in_params.sample_rate;
235 b = ctx_priv->out_params.sample_rate;
236
237 a = gcd(a, b);
238
239 /* Divide by gcd to normalize the rate */
240 ctx_priv->in_params.norm_rate = ctx_priv->in_params.sample_rate / a;
241 ctx_priv->out_params.norm_rate = ctx_priv->out_params.sample_rate / a;
242 }
243
244 /* Resets the pointer of the coeff memory pointers */
fsl_easrc_coeff_mem_ptr_reset(struct fsl_asrc * easrc,unsigned int ctx_id,int mem_type)245 static int fsl_easrc_coeff_mem_ptr_reset(struct fsl_asrc *easrc,
246 unsigned int ctx_id, int mem_type)
247 {
248 struct device *dev;
249 u32 reg, mask, val;
250
251 if (!easrc)
252 return -ENODEV;
253
254 dev = &easrc->pdev->dev;
255
256 switch (mem_type) {
257 case EASRC_PF_COEFF_MEM:
258 /* This resets the prefilter memory pointer addr */
259 if (ctx_id >= EASRC_CTX_MAX_NUM) {
260 dev_err(dev, "Invalid context id[%d]\n", ctx_id);
261 return -EINVAL;
262 }
263
264 reg = REG_EASRC_CCE1(ctx_id);
265 mask = EASRC_CCE1_COEF_MEM_RST_MASK;
266 val = EASRC_CCE1_COEF_MEM_RST;
267 break;
268 case EASRC_RS_COEFF_MEM:
269 /* This resets the resampling memory pointer addr */
270 reg = REG_EASRC_CRCC;
271 mask = EASRC_CRCC_RS_CPR_MASK;
272 val = EASRC_CRCC_RS_CPR;
273 break;
274 default:
275 dev_err(dev, "Unknown memory type\n");
276 return -EINVAL;
277 }
278
279 /*
280 * To reset the write pointer back to zero, the register field
281 * ASRC_CTX_CTRL_EXT1x[PF_COEFF_MEM_RST] can be toggled from
282 * 0x0 to 0x1 to 0x0.
283 */
284 regmap_update_bits(easrc->regmap, reg, mask, 0);
285 regmap_update_bits(easrc->regmap, reg, mask, val);
286 regmap_update_bits(easrc->regmap, reg, mask, 0);
287
288 return 0;
289 }
290
bits_taps_to_val(unsigned int t)291 static inline uint32_t bits_taps_to_val(unsigned int t)
292 {
293 switch (t) {
294 case EASRC_RS_32_TAPS:
295 return 32;
296 case EASRC_RS_64_TAPS:
297 return 64;
298 case EASRC_RS_128_TAPS:
299 return 128;
300 }
301
302 return 0;
303 }
304
fsl_easrc_resampler_config(struct fsl_asrc * easrc)305 static int fsl_easrc_resampler_config(struct fsl_asrc *easrc)
306 {
307 struct device *dev = &easrc->pdev->dev;
308 struct fsl_easrc_priv *easrc_priv = easrc->private;
309 struct asrc_firmware_hdr *hdr = easrc_priv->firmware_hdr;
310 struct interp_params *interp = easrc_priv->interp;
311 struct interp_params *selected_interp = NULL;
312 unsigned int num_coeff;
313 unsigned int i;
314 u64 *coef;
315 u32 *r;
316 int ret;
317
318 if (!hdr) {
319 dev_err(dev, "firmware not loaded!\n");
320 return -ENODEV;
321 }
322
323 for (i = 0; i < hdr->interp_scen; i++) {
324 if ((interp[i].num_taps - 1) !=
325 bits_taps_to_val(easrc_priv->rs_num_taps))
326 continue;
327
328 coef = interp[i].coeff;
329 selected_interp = &interp[i];
330 dev_dbg(dev, "Selected interp_filter: %u taps - %u phases\n",
331 selected_interp->num_taps,
332 selected_interp->num_phases);
333 break;
334 }
335
336 if (!selected_interp) {
337 dev_err(dev, "failed to get interpreter configuration\n");
338 return -EINVAL;
339 }
340
341 /*
342 * RS_LOW - first half of center tap of the sinc function
343 * RS_HIGH - second half of center tap of the sinc function
344 * This is due to the fact the resampling function must be
345 * symetrical - i.e. odd number of taps
346 */
347 r = (uint32_t *)&selected_interp->center_tap;
348 regmap_write(easrc->regmap, REG_EASRC_RCTCL, EASRC_RCTCL_RS_CL(r[0]));
349 regmap_write(easrc->regmap, REG_EASRC_RCTCH, EASRC_RCTCH_RS_CH(r[1]));
350
351 /*
352 * Write Number of Resampling Coefficient Taps
353 * 00b - 32-Tap Resampling Filter
354 * 01b - 64-Tap Resampling Filter
355 * 10b - 128-Tap Resampling Filter
356 * 11b - N/A
357 */
358 regmap_update_bits(easrc->regmap, REG_EASRC_CRCC,
359 EASRC_CRCC_RS_TAPS_MASK,
360 EASRC_CRCC_RS_TAPS(easrc_priv->rs_num_taps));
361
362 /* Reset prefilter coefficient pointer back to 0 */
363 ret = fsl_easrc_coeff_mem_ptr_reset(easrc, 0, EASRC_RS_COEFF_MEM);
364 if (ret)
365 return ret;
366
367 /*
368 * When the filter is programmed to run in:
369 * 32-tap mode, 16-taps, 128-phases 4-coefficients per phase
370 * 64-tap mode, 32-taps, 64-phases 4-coefficients per phase
371 * 128-tap mode, 64-taps, 32-phases 4-coefficients per phase
372 * This means the number of writes is constant no matter
373 * the mode we are using
374 */
375 num_coeff = 16 * 128 * 4;
376
377 for (i = 0; i < num_coeff; i++) {
378 r = (uint32_t *)&coef[i];
379 regmap_write(easrc->regmap, REG_EASRC_CRCM,
380 EASRC_CRCM_RS_CWD(r[0]));
381 regmap_write(easrc->regmap, REG_EASRC_CRCM,
382 EASRC_CRCM_RS_CWD(r[1]));
383 }
384
385 return 0;
386 }
387
388 /**
389 * fsl_easrc_normalize_filter - Scale filter coefficients (64 bits float)
390 * For input float32 normalized range (1.0,-1.0) -> output int[16,24,32]:
391 * scale it by multiplying filter coefficients by 2^31
392 * For input int[16, 24, 32] -> output float32
393 * scale it by multiplying filter coefficients by 2^-15, 2^-23, 2^-31
394 * input:
395 * @easrc: Structure pointer of fsl_asrc
396 * @infilter : Pointer to non-scaled input filter
397 * @shift: The multiply factor
398 * output:
399 * @outfilter: scaled filter
400 */
fsl_easrc_normalize_filter(struct fsl_asrc * easrc,u64 * infilter,u64 * outfilter,int shift)401 static int fsl_easrc_normalize_filter(struct fsl_asrc *easrc,
402 u64 *infilter,
403 u64 *outfilter,
404 int shift)
405 {
406 struct device *dev = &easrc->pdev->dev;
407 u64 coef = *infilter;
408 s64 exp = (coef & 0x7ff0000000000000ll) >> 52;
409 u64 outcoef;
410
411 /*
412 * If exponent is zero (value == 0), or 7ff (value == NaNs)
413 * dont touch the content
414 */
415 if (exp == 0 || exp == 0x7ff) {
416 *outfilter = coef;
417 return 0;
418 }
419
420 /* coef * 2^shift ==> exp + shift */
421 exp += shift;
422
423 if ((shift > 0 && exp >= 0x7ff) || (shift < 0 && exp <= 0)) {
424 dev_err(dev, "coef out of range\n");
425 return -EINVAL;
426 }
427
428 outcoef = (u64)(coef & 0x800FFFFFFFFFFFFFll) + ((u64)exp << 52);
429 *outfilter = outcoef;
430
431 return 0;
432 }
433
fsl_easrc_write_pf_coeff_mem(struct fsl_asrc * easrc,int ctx_id,u64 * coef,int n_taps,int shift)434 static int fsl_easrc_write_pf_coeff_mem(struct fsl_asrc *easrc, int ctx_id,
435 u64 *coef, int n_taps, int shift)
436 {
437 struct device *dev = &easrc->pdev->dev;
438 int ret = 0;
439 int i;
440 u32 *r;
441 u64 tmp;
442
443 /* If STx_NUM_TAPS is set to 0x0 then return */
444 if (!n_taps)
445 return 0;
446
447 if (!coef) {
448 dev_err(dev, "coef table is NULL\n");
449 return -EINVAL;
450 }
451
452 /*
453 * When switching between stages, the address pointer
454 * should be reset back to 0x0 before performing a write
455 */
456 ret = fsl_easrc_coeff_mem_ptr_reset(easrc, ctx_id, EASRC_PF_COEFF_MEM);
457 if (ret)
458 return ret;
459
460 for (i = 0; i < (n_taps + 1) / 2; i++) {
461 ret = fsl_easrc_normalize_filter(easrc, &coef[i], &tmp, shift);
462 if (ret)
463 return ret;
464
465 r = (uint32_t *)&tmp;
466 regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id),
467 EASRC_PCF_CD(r[0]));
468 regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id),
469 EASRC_PCF_CD(r[1]));
470 }
471
472 return 0;
473 }
474
fsl_easrc_prefilter_config(struct fsl_asrc * easrc,unsigned int ctx_id)475 static int fsl_easrc_prefilter_config(struct fsl_asrc *easrc,
476 unsigned int ctx_id)
477 {
478 struct prefil_params *prefil, *selected_prefil = NULL;
479 struct fsl_easrc_ctx_priv *ctx_priv;
480 struct fsl_easrc_priv *easrc_priv;
481 struct asrc_firmware_hdr *hdr;
482 struct fsl_asrc_pair *ctx;
483 struct device *dev;
484 u32 inrate, outrate, offset = 0;
485 u32 in_s_rate, out_s_rate;
486 snd_pcm_format_t in_s_fmt, out_s_fmt;
487 int ret, i;
488
489 if (!easrc)
490 return -ENODEV;
491
492 dev = &easrc->pdev->dev;
493
494 if (ctx_id >= EASRC_CTX_MAX_NUM) {
495 dev_err(dev, "Invalid context id[%d]\n", ctx_id);
496 return -EINVAL;
497 }
498
499 easrc_priv = easrc->private;
500
501 ctx = easrc->pair[ctx_id];
502 ctx_priv = ctx->private;
503
504 in_s_rate = ctx_priv->in_params.sample_rate;
505 out_s_rate = ctx_priv->out_params.sample_rate;
506 in_s_fmt = ctx_priv->in_params.sample_format;
507 out_s_fmt = ctx_priv->out_params.sample_format;
508
509 ctx_priv->in_filled_sample = bits_taps_to_val(easrc_priv->rs_num_taps) / 2;
510 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate;
511
512 ctx_priv->st1_num_taps = 0;
513 ctx_priv->st2_num_taps = 0;
514
515 regmap_write(easrc->regmap, REG_EASRC_CCE1(ctx_id), 0);
516 regmap_write(easrc->regmap, REG_EASRC_CCE2(ctx_id), 0);
517
518 /*
519 * The audio float point data range is (-1, 1), the asrc would output
520 * all zero for float point input and integer output case, that is to
521 * drop the fractional part of the data directly.
522 *
523 * In order to support float to int conversion or int to float
524 * conversion we need to do special operation on the coefficient to
525 * enlarge/reduce the data to the expected range.
526 *
527 * For float to int case:
528 * Up sampling:
529 * 1. Create a 1 tap filter with center tap (only tap) of 2^31
530 * in 64 bits floating point.
531 * double value = (double)(((uint64_t)1) << 31)
532 * 2. Program 1 tap prefilter with center tap above.
533 *
534 * Down sampling,
535 * 1. If the filter is single stage filter, add "shift" to the exponent
536 * of stage 1 coefficients.
537 * 2. If the filter is two stage filter , add "shift" to the exponent
538 * of stage 2 coefficients.
539 *
540 * The "shift" is 31, same for int16, int24, int32 case.
541 *
542 * For int to float case:
543 * Up sampling:
544 * 1. Create a 1 tap filter with center tap (only tap) of 2^-31
545 * in 64 bits floating point.
546 * 2. Program 1 tap prefilter with center tap above.
547 *
548 * Down sampling,
549 * 1. If the filter is single stage filter, subtract "shift" to the
550 * exponent of stage 1 coefficients.
551 * 2. If the filter is two stage filter , subtract "shift" to the
552 * exponent of stage 2 coefficients.
553 *
554 * The "shift" is 15,23,31, different for int16, int24, int32 case.
555 *
556 */
557 if (out_s_rate >= in_s_rate) {
558 if (out_s_rate == in_s_rate)
559 regmap_update_bits(easrc->regmap,
560 REG_EASRC_CCE1(ctx_id),
561 EASRC_CCE1_RS_BYPASS_MASK,
562 EASRC_CCE1_RS_BYPASS);
563
564 ctx_priv->st1_num_taps = 1;
565 ctx_priv->st1_coeff = &easrc_priv->const_coeff;
566 ctx_priv->st1_num_exp = 1;
567 ctx_priv->st2_num_taps = 0;
568
569 if (in_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE &&
570 out_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE)
571 ctx_priv->st1_addexp = 31;
572 else if (in_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE &&
573 out_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE)
574 ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp;
575 } else {
576 inrate = ctx_priv->in_params.norm_rate;
577 outrate = ctx_priv->out_params.norm_rate;
578
579 hdr = easrc_priv->firmware_hdr;
580 prefil = easrc_priv->prefil;
581
582 for (i = 0; i < hdr->prefil_scen; i++) {
583 if (inrate == prefil[i].insr &&
584 outrate == prefil[i].outsr) {
585 selected_prefil = &prefil[i];
586 dev_dbg(dev, "Selected prefilter: %u insr, %u outsr, %u st1_taps, %u st2_taps\n",
587 selected_prefil->insr,
588 selected_prefil->outsr,
589 selected_prefil->st1_taps,
590 selected_prefil->st2_taps);
591 break;
592 }
593 }
594
595 if (!selected_prefil) {
596 dev_err(dev, "Conversion from in ratio %u(%u) to out ratio %u(%u) is not supported\n",
597 in_s_rate, inrate,
598 out_s_rate, outrate);
599 return -EINVAL;
600 }
601
602 /*
603 * In prefilter coeff array, first st1_num_taps represent the
604 * stage1 prefilter coefficients followed by next st2_num_taps
605 * representing stage 2 coefficients
606 */
607 ctx_priv->st1_num_taps = selected_prefil->st1_taps;
608 ctx_priv->st1_coeff = selected_prefil->coeff;
609 ctx_priv->st1_num_exp = selected_prefil->st1_exp;
610
611 offset = ((selected_prefil->st1_taps + 1) / 2);
612 ctx_priv->st2_num_taps = selected_prefil->st2_taps;
613 ctx_priv->st2_coeff = selected_prefil->coeff + offset;
614
615 if (in_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE &&
616 out_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE) {
617 /* only change stage2 coefficient for 2 stage case */
618 if (ctx_priv->st2_num_taps > 0)
619 ctx_priv->st2_addexp = 31;
620 else
621 ctx_priv->st1_addexp = 31;
622 } else if (in_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE &&
623 out_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE) {
624 if (ctx_priv->st2_num_taps > 0)
625 ctx_priv->st2_addexp -= ctx_priv->in_params.fmt.addexp;
626 else
627 ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp;
628 }
629 }
630
631 ctx_priv->in_filled_sample += (ctx_priv->st1_num_taps / 2) * ctx_priv->st1_num_exp +
632 ctx_priv->st2_num_taps / 2;
633 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate;
634
635 if (ctx_priv->in_filled_sample * out_s_rate % in_s_rate != 0)
636 ctx_priv->out_missed_sample += 1;
637 /*
638 * To modify the value of a prefilter coefficient, the user must
639 * perform a write to the register ASRC_PRE_COEFF_FIFOn[COEFF_DATA]
640 * while the respective context RUN_EN bit is set to 0b0
641 */
642 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
643 EASRC_CC_EN_MASK, 0);
644
645 if (ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) {
646 dev_err(dev, "ST1 taps [%d] mus be lower than %d\n",
647 ctx_priv->st1_num_taps, EASRC_MAX_PF_TAPS);
648 ret = -EINVAL;
649 goto ctx_error;
650 }
651
652 /* Update ctx ST1_NUM_TAPS in Context Control Extended 2 register */
653 regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id),
654 EASRC_CCE2_ST1_TAPS_MASK,
655 EASRC_CCE2_ST1_TAPS(ctx_priv->st1_num_taps - 1));
656
657 /* Prefilter Coefficient Write Select to write in ST1 coeff */
658 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
659 EASRC_CCE1_COEF_WS_MASK,
660 EASRC_PF_ST1_COEFF_WR << EASRC_CCE1_COEF_WS_SHIFT);
661
662 ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id,
663 ctx_priv->st1_coeff,
664 ctx_priv->st1_num_taps,
665 ctx_priv->st1_addexp);
666 if (ret)
667 goto ctx_error;
668
669 if (ctx_priv->st2_num_taps > 0) {
670 if (ctx_priv->st2_num_taps + ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) {
671 dev_err(dev, "ST2 taps [%d] mus be lower than %d\n",
672 ctx_priv->st2_num_taps, EASRC_MAX_PF_TAPS);
673 ret = -EINVAL;
674 goto ctx_error;
675 }
676
677 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
678 EASRC_CCE1_PF_TSEN_MASK,
679 EASRC_CCE1_PF_TSEN);
680 /*
681 * Enable prefilter stage1 writeback floating point
682 * which is used for FLOAT_LE case
683 */
684 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
685 EASRC_CCE1_PF_ST1_WBFP_MASK,
686 EASRC_CCE1_PF_ST1_WBFP);
687
688 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
689 EASRC_CCE1_PF_EXP_MASK,
690 EASRC_CCE1_PF_EXP(ctx_priv->st1_num_exp - 1));
691
692 /* Update ctx ST2_NUM_TAPS in Context Control Extended 2 reg */
693 regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id),
694 EASRC_CCE2_ST2_TAPS_MASK,
695 EASRC_CCE2_ST2_TAPS(ctx_priv->st2_num_taps - 1));
696
697 /* Prefilter Coefficient Write Select to write in ST2 coeff */
698 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
699 EASRC_CCE1_COEF_WS_MASK,
700 EASRC_PF_ST2_COEFF_WR << EASRC_CCE1_COEF_WS_SHIFT);
701
702 ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id,
703 ctx_priv->st2_coeff,
704 ctx_priv->st2_num_taps,
705 ctx_priv->st2_addexp);
706 if (ret)
707 goto ctx_error;
708 }
709
710 return 0;
711
712 ctx_error:
713 return ret;
714 }
715
fsl_easrc_max_ch_for_slot(struct fsl_asrc_pair * ctx,struct fsl_easrc_slot * slot)716 static int fsl_easrc_max_ch_for_slot(struct fsl_asrc_pair *ctx,
717 struct fsl_easrc_slot *slot)
718 {
719 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
720 int st1_mem_alloc = 0, st2_mem_alloc = 0;
721 int pf_mem_alloc = 0;
722 int max_channels = 8 - slot->num_channel;
723 int channels = 0;
724
725 if (ctx_priv->st1_num_taps > 0) {
726 if (ctx_priv->st2_num_taps > 0)
727 st1_mem_alloc =
728 (ctx_priv->st1_num_taps - 1) * ctx_priv->st1_num_exp + 1;
729 else
730 st1_mem_alloc = ctx_priv->st1_num_taps;
731 }
732
733 if (ctx_priv->st2_num_taps > 0)
734 st2_mem_alloc = ctx_priv->st2_num_taps;
735
736 pf_mem_alloc = st1_mem_alloc + st2_mem_alloc;
737
738 if (pf_mem_alloc != 0)
739 channels = (6144 - slot->pf_mem_used) / pf_mem_alloc;
740 else
741 channels = 8;
742
743 if (channels < max_channels)
744 max_channels = channels;
745
746 return max_channels;
747 }
748
fsl_easrc_config_one_slot(struct fsl_asrc_pair * ctx,struct fsl_easrc_slot * slot,unsigned int slot_ctx_idx,unsigned int * req_channels,unsigned int * start_channel,unsigned int * avail_channel)749 static int fsl_easrc_config_one_slot(struct fsl_asrc_pair *ctx,
750 struct fsl_easrc_slot *slot,
751 unsigned int slot_ctx_idx,
752 unsigned int *req_channels,
753 unsigned int *start_channel,
754 unsigned int *avail_channel)
755 {
756 struct fsl_asrc *easrc = ctx->asrc;
757 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
758 int st1_chanxexp, st1_mem_alloc = 0, st2_mem_alloc;
759 unsigned int reg0, reg1, reg2, reg3;
760 unsigned int addr;
761
762 if (slot->slot_index == 0) {
763 reg0 = REG_EASRC_DPCS0R0(slot_ctx_idx);
764 reg1 = REG_EASRC_DPCS0R1(slot_ctx_idx);
765 reg2 = REG_EASRC_DPCS0R2(slot_ctx_idx);
766 reg3 = REG_EASRC_DPCS0R3(slot_ctx_idx);
767 } else {
768 reg0 = REG_EASRC_DPCS1R0(slot_ctx_idx);
769 reg1 = REG_EASRC_DPCS1R1(slot_ctx_idx);
770 reg2 = REG_EASRC_DPCS1R2(slot_ctx_idx);
771 reg3 = REG_EASRC_DPCS1R3(slot_ctx_idx);
772 }
773
774 if (*req_channels <= *avail_channel) {
775 slot->num_channel = *req_channels;
776 *req_channels = 0;
777 } else {
778 slot->num_channel = *avail_channel;
779 *req_channels -= *avail_channel;
780 }
781
782 slot->min_channel = *start_channel;
783 slot->max_channel = *start_channel + slot->num_channel - 1;
784 slot->ctx_index = ctx->index;
785 slot->busy = true;
786 *start_channel += slot->num_channel;
787
788 regmap_update_bits(easrc->regmap, reg0,
789 EASRC_DPCS0R0_MAXCH_MASK,
790 EASRC_DPCS0R0_MAXCH(slot->max_channel));
791
792 regmap_update_bits(easrc->regmap, reg0,
793 EASRC_DPCS0R0_MINCH_MASK,
794 EASRC_DPCS0R0_MINCH(slot->min_channel));
795
796 regmap_update_bits(easrc->regmap, reg0,
797 EASRC_DPCS0R0_NUMCH_MASK,
798 EASRC_DPCS0R0_NUMCH(slot->num_channel - 1));
799
800 regmap_update_bits(easrc->regmap, reg0,
801 EASRC_DPCS0R0_CTXNUM_MASK,
802 EASRC_DPCS0R0_CTXNUM(slot->ctx_index));
803
804 if (ctx_priv->st1_num_taps > 0) {
805 if (ctx_priv->st2_num_taps > 0)
806 st1_mem_alloc =
807 (ctx_priv->st1_num_taps - 1) * slot->num_channel *
808 ctx_priv->st1_num_exp + slot->num_channel;
809 else
810 st1_mem_alloc = ctx_priv->st1_num_taps * slot->num_channel;
811
812 slot->pf_mem_used = st1_mem_alloc;
813 regmap_update_bits(easrc->regmap, reg2,
814 EASRC_DPCS0R2_ST1_MA_MASK,
815 EASRC_DPCS0R2_ST1_MA(st1_mem_alloc));
816
817 if (slot->slot_index == 1)
818 addr = PREFILTER_MEM_LEN - st1_mem_alloc;
819 else
820 addr = 0;
821
822 regmap_update_bits(easrc->regmap, reg2,
823 EASRC_DPCS0R2_ST1_SA_MASK,
824 EASRC_DPCS0R2_ST1_SA(addr));
825 }
826
827 if (ctx_priv->st2_num_taps > 0) {
828 st1_chanxexp = slot->num_channel * (ctx_priv->st1_num_exp - 1);
829
830 regmap_update_bits(easrc->regmap, reg1,
831 EASRC_DPCS0R1_ST1_EXP_MASK,
832 EASRC_DPCS0R1_ST1_EXP(st1_chanxexp));
833
834 st2_mem_alloc = slot->num_channel * ctx_priv->st2_num_taps;
835 slot->pf_mem_used += st2_mem_alloc;
836 regmap_update_bits(easrc->regmap, reg3,
837 EASRC_DPCS0R3_ST2_MA_MASK,
838 EASRC_DPCS0R3_ST2_MA(st2_mem_alloc));
839
840 if (slot->slot_index == 1)
841 addr = PREFILTER_MEM_LEN - st1_mem_alloc - st2_mem_alloc;
842 else
843 addr = st1_mem_alloc;
844
845 regmap_update_bits(easrc->regmap, reg3,
846 EASRC_DPCS0R3_ST2_SA_MASK,
847 EASRC_DPCS0R3_ST2_SA(addr));
848 }
849
850 regmap_update_bits(easrc->regmap, reg0,
851 EASRC_DPCS0R0_EN_MASK, EASRC_DPCS0R0_EN);
852
853 return 0;
854 }
855
856 /*
857 * fsl_easrc_config_slot
858 *
859 * A single context can be split amongst any of the 4 context processing pipes
860 * in the design.
861 * The total number of channels consumed within the context processor must be
862 * less than or equal to 8. if a single context is configured to contain more
863 * than 8 channels then it must be distributed across multiple context
864 * processing pipe slots.
865 *
866 */
fsl_easrc_config_slot(struct fsl_asrc * easrc,unsigned int ctx_id)867 static int fsl_easrc_config_slot(struct fsl_asrc *easrc, unsigned int ctx_id)
868 {
869 struct fsl_easrc_priv *easrc_priv = easrc->private;
870 struct fsl_asrc_pair *ctx = easrc->pair[ctx_id];
871 int req_channels = ctx->channels;
872 int start_channel = 0, avail_channel;
873 struct fsl_easrc_slot *slot0, *slot1;
874 struct fsl_easrc_slot *slota, *slotb;
875 int i, ret;
876
877 if (req_channels <= 0)
878 return -EINVAL;
879
880 for (i = 0; i < EASRC_CTX_MAX_NUM; i++) {
881 slot0 = &easrc_priv->slot[i][0];
882 slot1 = &easrc_priv->slot[i][1];
883
884 if (slot0->busy && slot1->busy) {
885 continue;
886 } else if ((slot0->busy && slot0->ctx_index == ctx->index) ||
887 (slot1->busy && slot1->ctx_index == ctx->index)) {
888 continue;
889 } else if (!slot0->busy) {
890 slota = slot0;
891 slotb = slot1;
892 slota->slot_index = 0;
893 } else if (!slot1->busy) {
894 slota = slot1;
895 slotb = slot0;
896 slota->slot_index = 1;
897 }
898
899 if (!slota || !slotb)
900 continue;
901
902 avail_channel = fsl_easrc_max_ch_for_slot(ctx, slotb);
903 if (avail_channel <= 0)
904 continue;
905
906 ret = fsl_easrc_config_one_slot(ctx, slota, i, &req_channels,
907 &start_channel, &avail_channel);
908 if (ret)
909 return ret;
910
911 if (req_channels > 0)
912 continue;
913 else
914 break;
915 }
916
917 if (req_channels > 0) {
918 dev_err(&easrc->pdev->dev, "no avail slot.\n");
919 return -EINVAL;
920 }
921
922 return 0;
923 }
924
925 /*
926 * fsl_easrc_release_slot
927 *
928 * Clear the slot configuration
929 */
fsl_easrc_release_slot(struct fsl_asrc * easrc,unsigned int ctx_id)930 static int fsl_easrc_release_slot(struct fsl_asrc *easrc, unsigned int ctx_id)
931 {
932 struct fsl_easrc_priv *easrc_priv = easrc->private;
933 struct fsl_asrc_pair *ctx = easrc->pair[ctx_id];
934 int i;
935
936 for (i = 0; i < EASRC_CTX_MAX_NUM; i++) {
937 if (easrc_priv->slot[i][0].busy &&
938 easrc_priv->slot[i][0].ctx_index == ctx->index) {
939 easrc_priv->slot[i][0].busy = false;
940 easrc_priv->slot[i][0].num_channel = 0;
941 easrc_priv->slot[i][0].pf_mem_used = 0;
942 /* set registers */
943 regmap_write(easrc->regmap, REG_EASRC_DPCS0R0(i), 0);
944 regmap_write(easrc->regmap, REG_EASRC_DPCS0R1(i), 0);
945 regmap_write(easrc->regmap, REG_EASRC_DPCS0R2(i), 0);
946 regmap_write(easrc->regmap, REG_EASRC_DPCS0R3(i), 0);
947 }
948
949 if (easrc_priv->slot[i][1].busy &&
950 easrc_priv->slot[i][1].ctx_index == ctx->index) {
951 easrc_priv->slot[i][1].busy = false;
952 easrc_priv->slot[i][1].num_channel = 0;
953 easrc_priv->slot[i][1].pf_mem_used = 0;
954 /* set registers */
955 regmap_write(easrc->regmap, REG_EASRC_DPCS1R0(i), 0);
956 regmap_write(easrc->regmap, REG_EASRC_DPCS1R1(i), 0);
957 regmap_write(easrc->regmap, REG_EASRC_DPCS1R2(i), 0);
958 regmap_write(easrc->regmap, REG_EASRC_DPCS1R3(i), 0);
959 }
960 }
961
962 return 0;
963 }
964
965 /*
966 * fsl_easrc_config_context
967 *
968 * Configure the register relate with context.
969 */
fsl_easrc_config_context(struct fsl_asrc * easrc,unsigned int ctx_id)970 static int fsl_easrc_config_context(struct fsl_asrc *easrc, unsigned int ctx_id)
971 {
972 struct fsl_easrc_ctx_priv *ctx_priv;
973 struct fsl_asrc_pair *ctx;
974 struct device *dev;
975 unsigned long lock_flags;
976 int ret;
977
978 if (!easrc)
979 return -ENODEV;
980
981 dev = &easrc->pdev->dev;
982
983 if (ctx_id >= EASRC_CTX_MAX_NUM) {
984 dev_err(dev, "Invalid context id[%d]\n", ctx_id);
985 return -EINVAL;
986 }
987
988 ctx = easrc->pair[ctx_id];
989
990 ctx_priv = ctx->private;
991
992 fsl_easrc_normalize_rates(ctx);
993
994 ret = fsl_easrc_set_rs_ratio(ctx);
995 if (ret)
996 return ret;
997
998 /* Initialize the context coeficients */
999 ret = fsl_easrc_prefilter_config(easrc, ctx->index);
1000 if (ret)
1001 return ret;
1002
1003 spin_lock_irqsave(&easrc->lock, lock_flags);
1004 ret = fsl_easrc_config_slot(easrc, ctx->index);
1005 spin_unlock_irqrestore(&easrc->lock, lock_flags);
1006 if (ret)
1007 return ret;
1008
1009 /*
1010 * Both prefilter and resampling filters can use following
1011 * initialization modes:
1012 * 2 - zero-fil mode
1013 * 1 - replication mode
1014 * 0 - software control
1015 */
1016 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
1017 EASRC_CCE1_RS_INIT_MASK,
1018 EASRC_CCE1_RS_INIT(ctx_priv->rs_init_mode));
1019
1020 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
1021 EASRC_CCE1_PF_INIT_MASK,
1022 EASRC_CCE1_PF_INIT(ctx_priv->pf_init_mode));
1023
1024 /*
1025 * Context Input FIFO Watermark
1026 * DMA request is generated when input FIFO < FIFO_WTMK
1027 */
1028 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
1029 EASRC_CC_FIFO_WTMK_MASK,
1030 EASRC_CC_FIFO_WTMK(ctx_priv->in_params.fifo_wtmk));
1031
1032 /*
1033 * Context Output FIFO Watermark
1034 * DMA request is generated when output FIFO > FIFO_WTMK
1035 * So we set fifo_wtmk -1 to register.
1036 */
1037 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx_id),
1038 EASRC_COC_FIFO_WTMK_MASK,
1039 EASRC_COC_FIFO_WTMK(ctx_priv->out_params.fifo_wtmk - 1));
1040
1041 /* Number of channels */
1042 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
1043 EASRC_CC_CHEN_MASK,
1044 EASRC_CC_CHEN(ctx->channels - 1));
1045 return 0;
1046 }
1047
fsl_easrc_process_format(struct fsl_asrc_pair * ctx,struct fsl_easrc_data_fmt * fmt,snd_pcm_format_t raw_fmt)1048 static int fsl_easrc_process_format(struct fsl_asrc_pair *ctx,
1049 struct fsl_easrc_data_fmt *fmt,
1050 snd_pcm_format_t raw_fmt)
1051 {
1052 struct fsl_asrc *easrc = ctx->asrc;
1053 struct fsl_easrc_priv *easrc_priv = easrc->private;
1054 int ret;
1055
1056 if (!fmt)
1057 return -EINVAL;
1058
1059 /*
1060 * Context Input Floating Point Format
1061 * 0 - Integer Format
1062 * 1 - Single Precision FP Format
1063 */
1064 fmt->floating_point = !snd_pcm_format_linear(raw_fmt);
1065 fmt->sample_pos = 0;
1066 fmt->iec958 = 0;
1067
1068 /* Get the data width */
1069 switch (snd_pcm_format_width(raw_fmt)) {
1070 case 16:
1071 fmt->width = EASRC_WIDTH_16_BIT;
1072 fmt->addexp = 15;
1073 break;
1074 case 20:
1075 fmt->width = EASRC_WIDTH_20_BIT;
1076 fmt->addexp = 19;
1077 break;
1078 case 24:
1079 fmt->width = EASRC_WIDTH_24_BIT;
1080 fmt->addexp = 23;
1081 break;
1082 case 32:
1083 fmt->width = EASRC_WIDTH_32_BIT;
1084 fmt->addexp = 31;
1085 break;
1086 default:
1087 return -EINVAL;
1088 }
1089
1090 switch (raw_fmt) {
1091 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
1092 fmt->width = easrc_priv->bps_iec958[ctx->index];
1093 fmt->iec958 = 1;
1094 fmt->floating_point = 0;
1095 if (fmt->width == EASRC_WIDTH_16_BIT) {
1096 fmt->sample_pos = 12;
1097 fmt->addexp = 15;
1098 } else if (fmt->width == EASRC_WIDTH_20_BIT) {
1099 fmt->sample_pos = 8;
1100 fmt->addexp = 19;
1101 } else if (fmt->width == EASRC_WIDTH_24_BIT) {
1102 fmt->sample_pos = 4;
1103 fmt->addexp = 23;
1104 }
1105 break;
1106 default:
1107 break;
1108 }
1109
1110 /*
1111 * Data Endianness
1112 * 0 - Little-Endian
1113 * 1 - Big-Endian
1114 */
1115 ret = snd_pcm_format_big_endian(raw_fmt);
1116 if (ret < 0)
1117 return ret;
1118
1119 fmt->endianness = ret;
1120
1121 /*
1122 * Input Data sign
1123 * 0b - Signed Format
1124 * 1b - Unsigned Format
1125 */
1126 fmt->unsign = snd_pcm_format_unsigned(raw_fmt) > 0 ? 1 : 0;
1127
1128 return 0;
1129 }
1130
fsl_easrc_set_ctx_format(struct fsl_asrc_pair * ctx,snd_pcm_format_t * in_raw_format,snd_pcm_format_t * out_raw_format)1131 static int fsl_easrc_set_ctx_format(struct fsl_asrc_pair *ctx,
1132 snd_pcm_format_t *in_raw_format,
1133 snd_pcm_format_t *out_raw_format)
1134 {
1135 struct fsl_asrc *easrc = ctx->asrc;
1136 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
1137 struct fsl_easrc_data_fmt *in_fmt = &ctx_priv->in_params.fmt;
1138 struct fsl_easrc_data_fmt *out_fmt = &ctx_priv->out_params.fmt;
1139 int ret = 0;
1140
1141 /* Get the bitfield values for input data format */
1142 if (in_raw_format && out_raw_format) {
1143 ret = fsl_easrc_process_format(ctx, in_fmt, *in_raw_format);
1144 if (ret)
1145 return ret;
1146 }
1147
1148 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1149 EASRC_CC_BPS_MASK,
1150 EASRC_CC_BPS(in_fmt->width));
1151 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1152 EASRC_CC_ENDIANNESS_MASK,
1153 in_fmt->endianness << EASRC_CC_ENDIANNESS_SHIFT);
1154 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1155 EASRC_CC_FMT_MASK,
1156 in_fmt->floating_point << EASRC_CC_FMT_SHIFT);
1157 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1158 EASRC_CC_INSIGN_MASK,
1159 in_fmt->unsign << EASRC_CC_INSIGN_SHIFT);
1160
1161 /* In Sample Position */
1162 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1163 EASRC_CC_SAMPLE_POS_MASK,
1164 EASRC_CC_SAMPLE_POS(in_fmt->sample_pos));
1165
1166 /* Get the bitfield values for input data format */
1167 if (in_raw_format && out_raw_format) {
1168 ret = fsl_easrc_process_format(ctx, out_fmt, *out_raw_format);
1169 if (ret)
1170 return ret;
1171 }
1172
1173 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1174 EASRC_COC_BPS_MASK,
1175 EASRC_COC_BPS(out_fmt->width));
1176 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1177 EASRC_COC_ENDIANNESS_MASK,
1178 out_fmt->endianness << EASRC_COC_ENDIANNESS_SHIFT);
1179 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1180 EASRC_COC_FMT_MASK,
1181 out_fmt->floating_point << EASRC_COC_FMT_SHIFT);
1182 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1183 EASRC_COC_OUTSIGN_MASK,
1184 out_fmt->unsign << EASRC_COC_OUTSIGN_SHIFT);
1185
1186 /* Out Sample Position */
1187 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1188 EASRC_COC_SAMPLE_POS_MASK,
1189 EASRC_COC_SAMPLE_POS(out_fmt->sample_pos));
1190
1191 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1192 EASRC_COC_IEC_EN_MASK,
1193 out_fmt->iec958 << EASRC_COC_IEC_EN_SHIFT);
1194
1195 return ret;
1196 }
1197
1198 /*
1199 * The ASRC provides interleaving support in hardware to ensure that a
1200 * variety of sample sources can be internally combined
1201 * to conform with this format. Interleaving parameters are accessed
1202 * through the ASRC_CTRL_IN_ACCESSa and ASRC_CTRL_OUT_ACCESSa registers
1203 */
fsl_easrc_set_ctx_organziation(struct fsl_asrc_pair * ctx)1204 static int fsl_easrc_set_ctx_organziation(struct fsl_asrc_pair *ctx)
1205 {
1206 struct fsl_easrc_ctx_priv *ctx_priv;
1207 struct fsl_asrc *easrc;
1208
1209 if (!ctx)
1210 return -ENODEV;
1211
1212 easrc = ctx->asrc;
1213 ctx_priv = ctx->private;
1214
1215 /* input interleaving parameters */
1216 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
1217 EASRC_CIA_ITER_MASK,
1218 EASRC_CIA_ITER(ctx_priv->in_params.iterations));
1219 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
1220 EASRC_CIA_GRLEN_MASK,
1221 EASRC_CIA_GRLEN(ctx_priv->in_params.group_len));
1222 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
1223 EASRC_CIA_ACCLEN_MASK,
1224 EASRC_CIA_ACCLEN(ctx_priv->in_params.access_len));
1225
1226 /* output interleaving parameters */
1227 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
1228 EASRC_COA_ITER_MASK,
1229 EASRC_COA_ITER(ctx_priv->out_params.iterations));
1230 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
1231 EASRC_COA_GRLEN_MASK,
1232 EASRC_COA_GRLEN(ctx_priv->out_params.group_len));
1233 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
1234 EASRC_COA_ACCLEN_MASK,
1235 EASRC_COA_ACCLEN(ctx_priv->out_params.access_len));
1236
1237 return 0;
1238 }
1239
1240 /*
1241 * Request one of the available contexts
1242 *
1243 * Returns a negative number on error and >=0 as context id
1244 * on success
1245 */
fsl_easrc_request_context(int channels,struct fsl_asrc_pair * ctx)1246 static int fsl_easrc_request_context(int channels, struct fsl_asrc_pair *ctx)
1247 {
1248 enum asrc_pair_index index = ASRC_INVALID_PAIR;
1249 struct fsl_asrc *easrc = ctx->asrc;
1250 struct device *dev;
1251 unsigned long lock_flags;
1252 int ret = 0;
1253 int i;
1254
1255 dev = &easrc->pdev->dev;
1256
1257 spin_lock_irqsave(&easrc->lock, lock_flags);
1258
1259 for (i = ASRC_PAIR_A; i < EASRC_CTX_MAX_NUM; i++) {
1260 if (easrc->pair[i])
1261 continue;
1262
1263 index = i;
1264 break;
1265 }
1266
1267 if (index == ASRC_INVALID_PAIR) {
1268 dev_err(dev, "all contexts are busy\n");
1269 ret = -EBUSY;
1270 } else if (channels > easrc->channel_avail) {
1271 dev_err(dev, "can't give the required channels: %d\n",
1272 channels);
1273 ret = -EINVAL;
1274 } else {
1275 ctx->index = index;
1276 ctx->channels = channels;
1277 easrc->pair[index] = ctx;
1278 easrc->channel_avail -= channels;
1279 }
1280
1281 spin_unlock_irqrestore(&easrc->lock, lock_flags);
1282
1283 return ret;
1284 }
1285
1286 /*
1287 * Release the context
1288 *
1289 * This funciton is mainly doing the revert thing in request context
1290 */
fsl_easrc_release_context(struct fsl_asrc_pair * ctx)1291 static void fsl_easrc_release_context(struct fsl_asrc_pair *ctx)
1292 {
1293 unsigned long lock_flags;
1294 struct fsl_asrc *easrc;
1295
1296 if (!ctx)
1297 return;
1298
1299 easrc = ctx->asrc;
1300
1301 spin_lock_irqsave(&easrc->lock, lock_flags);
1302
1303 fsl_easrc_release_slot(easrc, ctx->index);
1304
1305 easrc->channel_avail += ctx->channels;
1306 easrc->pair[ctx->index] = NULL;
1307
1308 spin_unlock_irqrestore(&easrc->lock, lock_flags);
1309 }
1310
1311 /*
1312 * Start the context
1313 *
1314 * Enable the DMA request and context
1315 */
fsl_easrc_start_context(struct fsl_asrc_pair * ctx)1316 static int fsl_easrc_start_context(struct fsl_asrc_pair *ctx)
1317 {
1318 struct fsl_asrc *easrc = ctx->asrc;
1319
1320 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1321 EASRC_CC_FWMDE_MASK, EASRC_CC_FWMDE);
1322 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1323 EASRC_COC_FWMDE_MASK, EASRC_COC_FWMDE);
1324 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1325 EASRC_CC_EN_MASK, EASRC_CC_EN);
1326 return 0;
1327 }
1328
1329 /*
1330 * Stop the context
1331 *
1332 * Disable the DMA request and context
1333 */
fsl_easrc_stop_context(struct fsl_asrc_pair * ctx)1334 static int fsl_easrc_stop_context(struct fsl_asrc_pair *ctx)
1335 {
1336 struct fsl_asrc *easrc = ctx->asrc;
1337 int val, i;
1338 int size;
1339 int retry = 200;
1340
1341 regmap_read(easrc->regmap, REG_EASRC_CC(ctx->index), &val);
1342
1343 if (val & EASRC_CC_EN_MASK) {
1344 regmap_update_bits(easrc->regmap,
1345 REG_EASRC_CC(ctx->index),
1346 EASRC_CC_STOP_MASK, EASRC_CC_STOP);
1347 do {
1348 regmap_read(easrc->regmap, REG_EASRC_SFS(ctx->index), &val);
1349 val &= EASRC_SFS_NSGO_MASK;
1350 size = val >> EASRC_SFS_NSGO_SHIFT;
1351
1352 /* Read FIFO, drop the data */
1353 for (i = 0; i < size * ctx->channels; i++)
1354 regmap_read(easrc->regmap, REG_EASRC_RDFIFO(ctx->index), &val);
1355 /* Check RUN_STOP_DONE */
1356 regmap_read(easrc->regmap, REG_EASRC_IRQF, &val);
1357 if (val & EASRC_IRQF_RSD(1 << ctx->index)) {
1358 /*Clear RUN_STOP_DONE*/
1359 regmap_write_bits(easrc->regmap,
1360 REG_EASRC_IRQF,
1361 EASRC_IRQF_RSD(1 << ctx->index),
1362 EASRC_IRQF_RSD(1 << ctx->index));
1363 break;
1364 }
1365 udelay(100);
1366 } while (--retry);
1367
1368 if (retry == 0)
1369 dev_warn(&easrc->pdev->dev, "RUN STOP fail\n");
1370 }
1371
1372 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1373 EASRC_CC_EN_MASK | EASRC_CC_STOP_MASK, 0);
1374 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
1375 EASRC_CC_FWMDE_MASK, 0);
1376 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
1377 EASRC_COC_FWMDE_MASK, 0);
1378 return 0;
1379 }
1380
fsl_easrc_get_dma_channel(struct fsl_asrc_pair * ctx,bool dir)1381 static struct dma_chan *fsl_easrc_get_dma_channel(struct fsl_asrc_pair *ctx,
1382 bool dir)
1383 {
1384 struct fsl_asrc *easrc = ctx->asrc;
1385 enum asrc_pair_index index = ctx->index;
1386 char name[8];
1387
1388 /* Example of dma name: ctx0_rx */
1389 sprintf(name, "ctx%c_%cx", index + '0', dir == IN ? 'r' : 't');
1390
1391 return dma_request_slave_channel(&easrc->pdev->dev, name);
1392 };
1393
1394 static const unsigned int easrc_rates[] = {
1395 8000, 11025, 12000, 16000,
1396 22050, 24000, 32000, 44100,
1397 48000, 64000, 88200, 96000,
1398 128000, 176400, 192000, 256000,
1399 352800, 384000, 705600, 768000,
1400 };
1401
1402 static const struct snd_pcm_hw_constraint_list easrc_rate_constraints = {
1403 .count = ARRAY_SIZE(easrc_rates),
1404 .list = easrc_rates,
1405 };
1406
fsl_easrc_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1407 static int fsl_easrc_startup(struct snd_pcm_substream *substream,
1408 struct snd_soc_dai *dai)
1409 {
1410 return snd_pcm_hw_constraint_list(substream->runtime, 0,
1411 SNDRV_PCM_HW_PARAM_RATE,
1412 &easrc_rate_constraints);
1413 }
1414
fsl_easrc_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1415 static int fsl_easrc_trigger(struct snd_pcm_substream *substream,
1416 int cmd, struct snd_soc_dai *dai)
1417 {
1418 struct snd_pcm_runtime *runtime = substream->runtime;
1419 struct fsl_asrc_pair *ctx = runtime->private_data;
1420 int ret;
1421
1422 switch (cmd) {
1423 case SNDRV_PCM_TRIGGER_START:
1424 case SNDRV_PCM_TRIGGER_RESUME:
1425 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1426 ret = fsl_easrc_start_context(ctx);
1427 if (ret)
1428 return ret;
1429 break;
1430 case SNDRV_PCM_TRIGGER_STOP:
1431 case SNDRV_PCM_TRIGGER_SUSPEND:
1432 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1433 ret = fsl_easrc_stop_context(ctx);
1434 if (ret)
1435 return ret;
1436 break;
1437 default:
1438 return -EINVAL;
1439 }
1440
1441 return 0;
1442 }
1443
fsl_easrc_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1444 static int fsl_easrc_hw_params(struct snd_pcm_substream *substream,
1445 struct snd_pcm_hw_params *params,
1446 struct snd_soc_dai *dai)
1447 {
1448 struct fsl_asrc *easrc = snd_soc_dai_get_drvdata(dai);
1449 struct snd_pcm_runtime *runtime = substream->runtime;
1450 struct device *dev = &easrc->pdev->dev;
1451 struct fsl_asrc_pair *ctx = runtime->private_data;
1452 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
1453 unsigned int channels = params_channels(params);
1454 unsigned int rate = params_rate(params);
1455 snd_pcm_format_t format = params_format(params);
1456 int ret;
1457
1458 ret = fsl_easrc_request_context(channels, ctx);
1459 if (ret) {
1460 dev_err(dev, "failed to request context\n");
1461 return ret;
1462 }
1463
1464 ctx_priv->ctx_streams |= BIT(substream->stream);
1465
1466 /*
1467 * Set the input and output ratio so we can compute
1468 * the resampling ratio in RS_LOW/HIGH
1469 */
1470 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1471 ctx_priv->in_params.sample_rate = rate;
1472 ctx_priv->in_params.sample_format = format;
1473 ctx_priv->out_params.sample_rate = easrc->asrc_rate;
1474 ctx_priv->out_params.sample_format = easrc->asrc_format;
1475 } else {
1476 ctx_priv->out_params.sample_rate = rate;
1477 ctx_priv->out_params.sample_format = format;
1478 ctx_priv->in_params.sample_rate = easrc->asrc_rate;
1479 ctx_priv->in_params.sample_format = easrc->asrc_format;
1480 }
1481
1482 ctx->channels = channels;
1483 ctx_priv->in_params.fifo_wtmk = 0x20;
1484 ctx_priv->out_params.fifo_wtmk = 0x20;
1485
1486 /*
1487 * Do only rate conversion and keep the same format for input
1488 * and output data
1489 */
1490 ret = fsl_easrc_set_ctx_format(ctx,
1491 &ctx_priv->in_params.sample_format,
1492 &ctx_priv->out_params.sample_format);
1493 if (ret) {
1494 dev_err(dev, "failed to set format %d", ret);
1495 return ret;
1496 }
1497
1498 ret = fsl_easrc_config_context(easrc, ctx->index);
1499 if (ret) {
1500 dev_err(dev, "failed to config context\n");
1501 return ret;
1502 }
1503
1504 ctx_priv->in_params.iterations = 1;
1505 ctx_priv->in_params.group_len = ctx->channels;
1506 ctx_priv->in_params.access_len = ctx->channels;
1507 ctx_priv->out_params.iterations = 1;
1508 ctx_priv->out_params.group_len = ctx->channels;
1509 ctx_priv->out_params.access_len = ctx->channels;
1510
1511 ret = fsl_easrc_set_ctx_organziation(ctx);
1512 if (ret) {
1513 dev_err(dev, "failed to set fifo organization\n");
1514 return ret;
1515 }
1516
1517 return 0;
1518 }
1519
fsl_easrc_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1520 static int fsl_easrc_hw_free(struct snd_pcm_substream *substream,
1521 struct snd_soc_dai *dai)
1522 {
1523 struct snd_pcm_runtime *runtime = substream->runtime;
1524 struct fsl_asrc_pair *ctx = runtime->private_data;
1525 struct fsl_easrc_ctx_priv *ctx_priv;
1526
1527 if (!ctx)
1528 return -EINVAL;
1529
1530 ctx_priv = ctx->private;
1531
1532 if (ctx_priv->ctx_streams & BIT(substream->stream)) {
1533 ctx_priv->ctx_streams &= ~BIT(substream->stream);
1534 fsl_easrc_release_context(ctx);
1535 }
1536
1537 return 0;
1538 }
1539
fsl_easrc_dai_probe(struct snd_soc_dai * cpu_dai)1540 static int fsl_easrc_dai_probe(struct snd_soc_dai *cpu_dai)
1541 {
1542 struct fsl_asrc *easrc = dev_get_drvdata(cpu_dai->dev);
1543
1544 snd_soc_dai_init_dma_data(cpu_dai,
1545 &easrc->dma_params_tx,
1546 &easrc->dma_params_rx);
1547 return 0;
1548 }
1549
1550 static const struct snd_soc_dai_ops fsl_easrc_dai_ops = {
1551 .probe = fsl_easrc_dai_probe,
1552 .startup = fsl_easrc_startup,
1553 .trigger = fsl_easrc_trigger,
1554 .hw_params = fsl_easrc_hw_params,
1555 .hw_free = fsl_easrc_hw_free,
1556 };
1557
1558 static struct snd_soc_dai_driver fsl_easrc_dai = {
1559 .playback = {
1560 .stream_name = "ASRC-Playback",
1561 .channels_min = 1,
1562 .channels_max = 32,
1563 .rate_min = 8000,
1564 .rate_max = 768000,
1565 .rates = SNDRV_PCM_RATE_KNOT,
1566 .formats = FSL_EASRC_FORMATS,
1567 },
1568 .capture = {
1569 .stream_name = "ASRC-Capture",
1570 .channels_min = 1,
1571 .channels_max = 32,
1572 .rate_min = 8000,
1573 .rate_max = 768000,
1574 .rates = SNDRV_PCM_RATE_KNOT,
1575 .formats = FSL_EASRC_FORMATS |
1576 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1577 },
1578 .ops = &fsl_easrc_dai_ops,
1579 };
1580
1581 static const struct snd_soc_component_driver fsl_easrc_component = {
1582 .name = "fsl-easrc-dai",
1583 .controls = fsl_easrc_snd_controls,
1584 .num_controls = ARRAY_SIZE(fsl_easrc_snd_controls),
1585 .legacy_dai_naming = 1,
1586 #ifdef CONFIG_DEBUG_FS
1587 .debugfs_prefix = "easrc",
1588 #endif
1589 };
1590
1591 static const struct reg_default fsl_easrc_reg_defaults[] = {
1592 {REG_EASRC_WRFIFO(0), 0x00000000},
1593 {REG_EASRC_WRFIFO(1), 0x00000000},
1594 {REG_EASRC_WRFIFO(2), 0x00000000},
1595 {REG_EASRC_WRFIFO(3), 0x00000000},
1596 {REG_EASRC_RDFIFO(0), 0x00000000},
1597 {REG_EASRC_RDFIFO(1), 0x00000000},
1598 {REG_EASRC_RDFIFO(2), 0x00000000},
1599 {REG_EASRC_RDFIFO(3), 0x00000000},
1600 {REG_EASRC_CC(0), 0x00000000},
1601 {REG_EASRC_CC(1), 0x00000000},
1602 {REG_EASRC_CC(2), 0x00000000},
1603 {REG_EASRC_CC(3), 0x00000000},
1604 {REG_EASRC_CCE1(0), 0x00000000},
1605 {REG_EASRC_CCE1(1), 0x00000000},
1606 {REG_EASRC_CCE1(2), 0x00000000},
1607 {REG_EASRC_CCE1(3), 0x00000000},
1608 {REG_EASRC_CCE2(0), 0x00000000},
1609 {REG_EASRC_CCE2(1), 0x00000000},
1610 {REG_EASRC_CCE2(2), 0x00000000},
1611 {REG_EASRC_CCE2(3), 0x00000000},
1612 {REG_EASRC_CIA(0), 0x00000000},
1613 {REG_EASRC_CIA(1), 0x00000000},
1614 {REG_EASRC_CIA(2), 0x00000000},
1615 {REG_EASRC_CIA(3), 0x00000000},
1616 {REG_EASRC_DPCS0R0(0), 0x00000000},
1617 {REG_EASRC_DPCS0R0(1), 0x00000000},
1618 {REG_EASRC_DPCS0R0(2), 0x00000000},
1619 {REG_EASRC_DPCS0R0(3), 0x00000000},
1620 {REG_EASRC_DPCS0R1(0), 0x00000000},
1621 {REG_EASRC_DPCS0R1(1), 0x00000000},
1622 {REG_EASRC_DPCS0R1(2), 0x00000000},
1623 {REG_EASRC_DPCS0R1(3), 0x00000000},
1624 {REG_EASRC_DPCS0R2(0), 0x00000000},
1625 {REG_EASRC_DPCS0R2(1), 0x00000000},
1626 {REG_EASRC_DPCS0R2(2), 0x00000000},
1627 {REG_EASRC_DPCS0R2(3), 0x00000000},
1628 {REG_EASRC_DPCS0R3(0), 0x00000000},
1629 {REG_EASRC_DPCS0R3(1), 0x00000000},
1630 {REG_EASRC_DPCS0R3(2), 0x00000000},
1631 {REG_EASRC_DPCS0R3(3), 0x00000000},
1632 {REG_EASRC_DPCS1R0(0), 0x00000000},
1633 {REG_EASRC_DPCS1R0(1), 0x00000000},
1634 {REG_EASRC_DPCS1R0(2), 0x00000000},
1635 {REG_EASRC_DPCS1R0(3), 0x00000000},
1636 {REG_EASRC_DPCS1R1(0), 0x00000000},
1637 {REG_EASRC_DPCS1R1(1), 0x00000000},
1638 {REG_EASRC_DPCS1R1(2), 0x00000000},
1639 {REG_EASRC_DPCS1R1(3), 0x00000000},
1640 {REG_EASRC_DPCS1R2(0), 0x00000000},
1641 {REG_EASRC_DPCS1R2(1), 0x00000000},
1642 {REG_EASRC_DPCS1R2(2), 0x00000000},
1643 {REG_EASRC_DPCS1R2(3), 0x00000000},
1644 {REG_EASRC_DPCS1R3(0), 0x00000000},
1645 {REG_EASRC_DPCS1R3(1), 0x00000000},
1646 {REG_EASRC_DPCS1R3(2), 0x00000000},
1647 {REG_EASRC_DPCS1R3(3), 0x00000000},
1648 {REG_EASRC_COC(0), 0x00000000},
1649 {REG_EASRC_COC(1), 0x00000000},
1650 {REG_EASRC_COC(2), 0x00000000},
1651 {REG_EASRC_COC(3), 0x00000000},
1652 {REG_EASRC_COA(0), 0x00000000},
1653 {REG_EASRC_COA(1), 0x00000000},
1654 {REG_EASRC_COA(2), 0x00000000},
1655 {REG_EASRC_COA(3), 0x00000000},
1656 {REG_EASRC_SFS(0), 0x00000000},
1657 {REG_EASRC_SFS(1), 0x00000000},
1658 {REG_EASRC_SFS(2), 0x00000000},
1659 {REG_EASRC_SFS(3), 0x00000000},
1660 {REG_EASRC_RRL(0), 0x00000000},
1661 {REG_EASRC_RRL(1), 0x00000000},
1662 {REG_EASRC_RRL(2), 0x00000000},
1663 {REG_EASRC_RRL(3), 0x00000000},
1664 {REG_EASRC_RRH(0), 0x00000000},
1665 {REG_EASRC_RRH(1), 0x00000000},
1666 {REG_EASRC_RRH(2), 0x00000000},
1667 {REG_EASRC_RRH(3), 0x00000000},
1668 {REG_EASRC_RUC(0), 0x00000000},
1669 {REG_EASRC_RUC(1), 0x00000000},
1670 {REG_EASRC_RUC(2), 0x00000000},
1671 {REG_EASRC_RUC(3), 0x00000000},
1672 {REG_EASRC_RUR(0), 0x7FFFFFFF},
1673 {REG_EASRC_RUR(1), 0x7FFFFFFF},
1674 {REG_EASRC_RUR(2), 0x7FFFFFFF},
1675 {REG_EASRC_RUR(3), 0x7FFFFFFF},
1676 {REG_EASRC_RCTCL, 0x00000000},
1677 {REG_EASRC_RCTCH, 0x00000000},
1678 {REG_EASRC_PCF(0), 0x00000000},
1679 {REG_EASRC_PCF(1), 0x00000000},
1680 {REG_EASRC_PCF(2), 0x00000000},
1681 {REG_EASRC_PCF(3), 0x00000000},
1682 {REG_EASRC_CRCM, 0x00000000},
1683 {REG_EASRC_CRCC, 0x00000000},
1684 {REG_EASRC_IRQC, 0x00000FFF},
1685 {REG_EASRC_IRQF, 0x00000000},
1686 {REG_EASRC_CS0(0), 0x00000000},
1687 {REG_EASRC_CS0(1), 0x00000000},
1688 {REG_EASRC_CS0(2), 0x00000000},
1689 {REG_EASRC_CS0(3), 0x00000000},
1690 {REG_EASRC_CS1(0), 0x00000000},
1691 {REG_EASRC_CS1(1), 0x00000000},
1692 {REG_EASRC_CS1(2), 0x00000000},
1693 {REG_EASRC_CS1(3), 0x00000000},
1694 {REG_EASRC_CS2(0), 0x00000000},
1695 {REG_EASRC_CS2(1), 0x00000000},
1696 {REG_EASRC_CS2(2), 0x00000000},
1697 {REG_EASRC_CS2(3), 0x00000000},
1698 {REG_EASRC_CS3(0), 0x00000000},
1699 {REG_EASRC_CS3(1), 0x00000000},
1700 {REG_EASRC_CS3(2), 0x00000000},
1701 {REG_EASRC_CS3(3), 0x00000000},
1702 {REG_EASRC_CS4(0), 0x00000000},
1703 {REG_EASRC_CS4(1), 0x00000000},
1704 {REG_EASRC_CS4(2), 0x00000000},
1705 {REG_EASRC_CS4(3), 0x00000000},
1706 {REG_EASRC_CS5(0), 0x00000000},
1707 {REG_EASRC_CS5(1), 0x00000000},
1708 {REG_EASRC_CS5(2), 0x00000000},
1709 {REG_EASRC_CS5(3), 0x00000000},
1710 {REG_EASRC_DBGC, 0x00000000},
1711 {REG_EASRC_DBGS, 0x00000000},
1712 };
1713
1714 static const struct regmap_range fsl_easrc_readable_ranges[] = {
1715 regmap_reg_range(REG_EASRC_RDFIFO(0), REG_EASRC_RCTCH),
1716 regmap_reg_range(REG_EASRC_PCF(0), REG_EASRC_PCF(3)),
1717 regmap_reg_range(REG_EASRC_CRCC, REG_EASRC_DBGS),
1718 };
1719
1720 static const struct regmap_access_table fsl_easrc_readable_table = {
1721 .yes_ranges = fsl_easrc_readable_ranges,
1722 .n_yes_ranges = ARRAY_SIZE(fsl_easrc_readable_ranges),
1723 };
1724
1725 static const struct regmap_range fsl_easrc_writeable_ranges[] = {
1726 regmap_reg_range(REG_EASRC_WRFIFO(0), REG_EASRC_WRFIFO(3)),
1727 regmap_reg_range(REG_EASRC_CC(0), REG_EASRC_COA(3)),
1728 regmap_reg_range(REG_EASRC_RRL(0), REG_EASRC_RCTCH),
1729 regmap_reg_range(REG_EASRC_PCF(0), REG_EASRC_DBGC),
1730 };
1731
1732 static const struct regmap_access_table fsl_easrc_writeable_table = {
1733 .yes_ranges = fsl_easrc_writeable_ranges,
1734 .n_yes_ranges = ARRAY_SIZE(fsl_easrc_writeable_ranges),
1735 };
1736
1737 static const struct regmap_range fsl_easrc_volatileable_ranges[] = {
1738 regmap_reg_range(REG_EASRC_RDFIFO(0), REG_EASRC_RDFIFO(3)),
1739 regmap_reg_range(REG_EASRC_SFS(0), REG_EASRC_SFS(3)),
1740 regmap_reg_range(REG_EASRC_IRQF, REG_EASRC_IRQF),
1741 regmap_reg_range(REG_EASRC_DBGS, REG_EASRC_DBGS),
1742 };
1743
1744 static const struct regmap_access_table fsl_easrc_volatileable_table = {
1745 .yes_ranges = fsl_easrc_volatileable_ranges,
1746 .n_yes_ranges = ARRAY_SIZE(fsl_easrc_volatileable_ranges),
1747 };
1748
1749 static const struct regmap_config fsl_easrc_regmap_config = {
1750 .reg_bits = 32,
1751 .reg_stride = 4,
1752 .val_bits = 32,
1753
1754 .max_register = REG_EASRC_DBGS,
1755 .reg_defaults = fsl_easrc_reg_defaults,
1756 .num_reg_defaults = ARRAY_SIZE(fsl_easrc_reg_defaults),
1757 .rd_table = &fsl_easrc_readable_table,
1758 .wr_table = &fsl_easrc_writeable_table,
1759 .volatile_table = &fsl_easrc_volatileable_table,
1760 .cache_type = REGCACHE_MAPLE,
1761 };
1762
1763 #ifdef DEBUG
fsl_easrc_dump_firmware(struct fsl_asrc * easrc)1764 static void fsl_easrc_dump_firmware(struct fsl_asrc *easrc)
1765 {
1766 struct fsl_easrc_priv *easrc_priv = easrc->private;
1767 struct asrc_firmware_hdr *firm = easrc_priv->firmware_hdr;
1768 struct interp_params *interp = easrc_priv->interp;
1769 struct prefil_params *prefil = easrc_priv->prefil;
1770 struct device *dev = &easrc->pdev->dev;
1771 int i;
1772
1773 if (firm->magic != FIRMWARE_MAGIC) {
1774 dev_err(dev, "Wrong magic. Something went wrong!");
1775 return;
1776 }
1777
1778 dev_dbg(dev, "Firmware v%u dump:\n", firm->firmware_version);
1779 dev_dbg(dev, "Num prefilter scenarios: %u\n", firm->prefil_scen);
1780 dev_dbg(dev, "Num interpolation scenarios: %u\n", firm->interp_scen);
1781 dev_dbg(dev, "\nInterpolation scenarios:\n");
1782
1783 for (i = 0; i < firm->interp_scen; i++) {
1784 if (interp[i].magic != FIRMWARE_MAGIC) {
1785 dev_dbg(dev, "%d. wrong interp magic: %x\n",
1786 i, interp[i].magic);
1787 continue;
1788 }
1789 dev_dbg(dev, "%d. taps: %u, phases: %u, center: %llu\n", i,
1790 interp[i].num_taps, interp[i].num_phases,
1791 interp[i].center_tap);
1792 }
1793
1794 for (i = 0; i < firm->prefil_scen; i++) {
1795 if (prefil[i].magic != FIRMWARE_MAGIC) {
1796 dev_dbg(dev, "%d. wrong prefil magic: %x\n",
1797 i, prefil[i].magic);
1798 continue;
1799 }
1800 dev_dbg(dev, "%d. insr: %u, outsr: %u, st1: %u, st2: %u\n", i,
1801 prefil[i].insr, prefil[i].outsr,
1802 prefil[i].st1_taps, prefil[i].st2_taps);
1803 }
1804
1805 dev_dbg(dev, "end of firmware dump\n");
1806 }
1807 #endif
1808
fsl_easrc_get_firmware(struct fsl_asrc * easrc)1809 static int fsl_easrc_get_firmware(struct fsl_asrc *easrc)
1810 {
1811 struct fsl_easrc_priv *easrc_priv;
1812 const struct firmware **fw_p;
1813 u32 pnum, inum, offset;
1814 const u8 *data;
1815 int ret;
1816
1817 if (!easrc)
1818 return -EINVAL;
1819
1820 easrc_priv = easrc->private;
1821 fw_p = &easrc_priv->fw;
1822
1823 ret = request_firmware(fw_p, easrc_priv->fw_name, &easrc->pdev->dev);
1824 if (ret)
1825 return ret;
1826
1827 data = easrc_priv->fw->data;
1828
1829 easrc_priv->firmware_hdr = (struct asrc_firmware_hdr *)data;
1830 pnum = easrc_priv->firmware_hdr->prefil_scen;
1831 inum = easrc_priv->firmware_hdr->interp_scen;
1832
1833 if (inum) {
1834 offset = sizeof(struct asrc_firmware_hdr);
1835 easrc_priv->interp = (struct interp_params *)(data + offset);
1836 }
1837
1838 if (pnum) {
1839 offset = sizeof(struct asrc_firmware_hdr) +
1840 inum * sizeof(struct interp_params);
1841 easrc_priv->prefil = (struct prefil_params *)(data + offset);
1842 }
1843
1844 #ifdef DEBUG
1845 fsl_easrc_dump_firmware(easrc);
1846 #endif
1847
1848 return 0;
1849 }
1850
fsl_easrc_isr(int irq,void * dev_id)1851 static irqreturn_t fsl_easrc_isr(int irq, void *dev_id)
1852 {
1853 struct fsl_asrc *easrc = (struct fsl_asrc *)dev_id;
1854 struct device *dev = &easrc->pdev->dev;
1855 int val;
1856
1857 regmap_read(easrc->regmap, REG_EASRC_IRQF, &val);
1858
1859 if (val & EASRC_IRQF_OER_MASK)
1860 dev_dbg(dev, "output FIFO underflow\n");
1861
1862 if (val & EASRC_IRQF_IFO_MASK)
1863 dev_dbg(dev, "input FIFO overflow\n");
1864
1865 return IRQ_HANDLED;
1866 }
1867
fsl_easrc_get_fifo_addr(u8 dir,enum asrc_pair_index index)1868 static int fsl_easrc_get_fifo_addr(u8 dir, enum asrc_pair_index index)
1869 {
1870 return REG_EASRC_FIFO(dir, index);
1871 }
1872
1873 /* Get sample numbers in FIFO */
fsl_easrc_get_output_fifo_size(struct fsl_asrc_pair * pair)1874 static unsigned int fsl_easrc_get_output_fifo_size(struct fsl_asrc_pair *pair)
1875 {
1876 struct fsl_asrc *asrc = pair->asrc;
1877 enum asrc_pair_index index = pair->index;
1878 u32 val;
1879
1880 regmap_read(asrc->regmap, REG_EASRC_SFS(index), &val);
1881 val &= EASRC_SFS_NSGO_MASK;
1882
1883 return val >> EASRC_SFS_NSGO_SHIFT;
1884 }
1885
fsl_easrc_m2m_prepare(struct fsl_asrc_pair * pair)1886 static int fsl_easrc_m2m_prepare(struct fsl_asrc_pair *pair)
1887 {
1888 struct fsl_easrc_ctx_priv *ctx_priv = pair->private;
1889 struct fsl_asrc *asrc = pair->asrc;
1890 struct device *dev = &asrc->pdev->dev;
1891 int ret;
1892
1893 ctx_priv->in_params.sample_rate = pair->rate[IN];
1894 ctx_priv->in_params.sample_format = pair->sample_format[IN];
1895 ctx_priv->out_params.sample_rate = pair->rate[OUT];
1896 ctx_priv->out_params.sample_format = pair->sample_format[OUT];
1897
1898 ctx_priv->in_params.fifo_wtmk = FSL_EASRC_INPUTFIFO_WML;
1899 ctx_priv->out_params.fifo_wtmk = FSL_EASRC_OUTPUTFIFO_WML;
1900 /* Fill the right half of the re-sampler with zeros */
1901 ctx_priv->rs_init_mode = 0x2;
1902 /* Zero fill the right half of the prefilter */
1903 ctx_priv->pf_init_mode = 0x2;
1904
1905 ret = fsl_easrc_set_ctx_format(pair,
1906 &ctx_priv->in_params.sample_format,
1907 &ctx_priv->out_params.sample_format);
1908 if (ret) {
1909 dev_err(dev, "failed to set context format: %d\n", ret);
1910 return ret;
1911 }
1912
1913 ret = fsl_easrc_config_context(asrc, pair->index);
1914 if (ret) {
1915 dev_err(dev, "failed to config context %d\n", ret);
1916 return ret;
1917 }
1918
1919 ctx_priv->in_params.iterations = 1;
1920 ctx_priv->in_params.group_len = pair->channels;
1921 ctx_priv->in_params.access_len = pair->channels;
1922 ctx_priv->out_params.iterations = 1;
1923 ctx_priv->out_params.group_len = pair->channels;
1924 ctx_priv->out_params.access_len = pair->channels;
1925
1926 ret = fsl_easrc_set_ctx_organziation(pair);
1927 if (ret) {
1928 dev_err(dev, "failed to set fifo organization\n");
1929 return ret;
1930 }
1931
1932 /* The context start flag */
1933 pair->first_convert = 1;
1934 return 0;
1935 }
1936
fsl_easrc_m2m_start(struct fsl_asrc_pair * pair)1937 static int fsl_easrc_m2m_start(struct fsl_asrc_pair *pair)
1938 {
1939 /* start context once */
1940 if (pair->first_convert) {
1941 fsl_easrc_start_context(pair);
1942 pair->first_convert = 0;
1943 }
1944
1945 return 0;
1946 }
1947
fsl_easrc_m2m_stop(struct fsl_asrc_pair * pair)1948 static int fsl_easrc_m2m_stop(struct fsl_asrc_pair *pair)
1949 {
1950 /* Stop pair/context */
1951 if (!pair->first_convert) {
1952 fsl_easrc_stop_context(pair);
1953 pair->first_convert = 1;
1954 }
1955
1956 return 0;
1957 }
1958
1959 /* calculate capture data length according to output data length and sample rate */
fsl_easrc_m2m_calc_out_len(struct fsl_asrc_pair * pair,int input_buffer_length)1960 static int fsl_easrc_m2m_calc_out_len(struct fsl_asrc_pair *pair, int input_buffer_length)
1961 {
1962 struct fsl_asrc *easrc = pair->asrc;
1963 struct fsl_easrc_priv *easrc_priv = easrc->private;
1964 struct fsl_easrc_ctx_priv *ctx_priv = pair->private;
1965 unsigned int in_rate = ctx_priv->in_params.norm_rate;
1966 unsigned int out_rate = ctx_priv->out_params.norm_rate;
1967 unsigned int channels = pair->channels;
1968 unsigned int in_samples, out_samples;
1969 unsigned int in_width, out_width;
1970 unsigned int out_length;
1971 unsigned int frac_bits;
1972 u64 val1, val2;
1973
1974 switch (easrc_priv->rs_num_taps) {
1975 case EASRC_RS_32_TAPS:
1976 /* integer bits = 5; */
1977 frac_bits = 39;
1978 break;
1979 case EASRC_RS_64_TAPS:
1980 /* integer bits = 6; */
1981 frac_bits = 38;
1982 break;
1983 case EASRC_RS_128_TAPS:
1984 /* integer bits = 7; */
1985 frac_bits = 37;
1986 break;
1987 default:
1988 return -EINVAL;
1989 }
1990
1991 val1 = (u64)in_rate << frac_bits;
1992 do_div(val1, out_rate);
1993 val1 += (s64)ctx_priv->ratio_mod << (frac_bits - 31);
1994
1995 in_width = snd_pcm_format_physical_width(ctx_priv->in_params.sample_format) / 8;
1996 out_width = snd_pcm_format_physical_width(ctx_priv->out_params.sample_format) / 8;
1997
1998 ctx_priv->in_filled_len += input_buffer_length;
1999 if (ctx_priv->in_filled_len <= ctx_priv->in_filled_sample * in_width * channels) {
2000 out_length = 0;
2001 } else {
2002 in_samples = ctx_priv->in_filled_len / (in_width * channels) -
2003 ctx_priv->in_filled_sample;
2004
2005 /* right shift 12 bit to make ratio in 32bit space */
2006 val2 = (u64)in_samples << (frac_bits - 12);
2007 val1 = val1 >> 12;
2008 do_div(val2, val1);
2009 out_samples = val2;
2010
2011 out_length = out_samples * out_width * channels;
2012 ctx_priv->in_filled_len = ctx_priv->in_filled_sample * in_width * channels;
2013 }
2014
2015 return out_length;
2016 }
2017
fsl_easrc_m2m_get_maxburst(u8 dir,struct fsl_asrc_pair * pair)2018 static int fsl_easrc_m2m_get_maxburst(u8 dir, struct fsl_asrc_pair *pair)
2019 {
2020 struct fsl_easrc_ctx_priv *ctx_priv = pair->private;
2021
2022 if (dir == IN)
2023 return ctx_priv->in_params.fifo_wtmk * pair->channels;
2024 else
2025 return ctx_priv->out_params.fifo_wtmk * pair->channels;
2026 }
2027
fsl_easrc_m2m_pair_suspend(struct fsl_asrc_pair * pair)2028 static int fsl_easrc_m2m_pair_suspend(struct fsl_asrc_pair *pair)
2029 {
2030 fsl_easrc_stop_context(pair);
2031
2032 return 0;
2033 }
2034
fsl_easrc_m2m_pair_resume(struct fsl_asrc_pair * pair)2035 static int fsl_easrc_m2m_pair_resume(struct fsl_asrc_pair *pair)
2036 {
2037 struct fsl_easrc_ctx_priv *ctx_priv = pair->private;
2038
2039 pair->first_convert = 1;
2040 ctx_priv->in_filled_len = 0;
2041
2042 return 0;
2043 }
2044
2045 /* val is Q31 */
fsl_easrc_m2m_set_ratio_mod(struct fsl_asrc_pair * pair,int val)2046 static int fsl_easrc_m2m_set_ratio_mod(struct fsl_asrc_pair *pair, int val)
2047 {
2048 struct fsl_easrc_ctx_priv *ctx_priv = pair->private;
2049 struct fsl_asrc *easrc = pair->asrc;
2050 struct fsl_easrc_priv *easrc_priv = easrc->private;
2051 unsigned int frac_bits;
2052
2053 ctx_priv->ratio_mod += val;
2054
2055 switch (easrc_priv->rs_num_taps) {
2056 case EASRC_RS_32_TAPS:
2057 /* integer bits = 5; */
2058 frac_bits = 39;
2059 break;
2060 case EASRC_RS_64_TAPS:
2061 /* integer bits = 6; */
2062 frac_bits = 38;
2063 break;
2064 case EASRC_RS_128_TAPS:
2065 /* integer bits = 7; */
2066 frac_bits = 37;
2067 break;
2068 default:
2069 return -EINVAL;
2070 }
2071
2072 val <<= (frac_bits - 31);
2073 regmap_write(easrc->regmap, REG_EASRC_RUC(pair->index), EASRC_RSUC_RS_RM(val));
2074
2075 return 0;
2076 }
2077
fsl_easrc_m2m_get_cap(struct fsl_asrc_m2m_cap * cap)2078 static int fsl_easrc_m2m_get_cap(struct fsl_asrc_m2m_cap *cap)
2079 {
2080 cap->fmt_in = FSL_EASRC_FORMATS;
2081 cap->fmt_out = FSL_EASRC_FORMATS | SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
2082 cap->rate_in = easrc_rates;
2083 cap->rate_in_count = ARRAY_SIZE(easrc_rates);
2084 cap->rate_out = easrc_rates;
2085 cap->rate_out_count = ARRAY_SIZE(easrc_rates);
2086 cap->chan_min = 1;
2087 cap->chan_max = 32;
2088 return 0;
2089 }
2090
2091 static const struct of_device_id fsl_easrc_dt_ids[] = {
2092 { .compatible = "fsl,imx8mn-easrc",},
2093 {}
2094 };
2095 MODULE_DEVICE_TABLE(of, fsl_easrc_dt_ids);
2096
fsl_easrc_probe(struct platform_device * pdev)2097 static int fsl_easrc_probe(struct platform_device *pdev)
2098 {
2099 struct fsl_easrc_priv *easrc_priv;
2100 struct device *dev = &pdev->dev;
2101 struct fsl_asrc *easrc;
2102 struct resource *res;
2103 struct device_node *np;
2104 void __iomem *regs;
2105 u32 asrc_fmt = 0;
2106 int ret, irq;
2107
2108 easrc = devm_kzalloc(dev, sizeof(*easrc), GFP_KERNEL);
2109 if (!easrc)
2110 return -ENOMEM;
2111
2112 easrc_priv = devm_kzalloc(dev, sizeof(*easrc_priv), GFP_KERNEL);
2113 if (!easrc_priv)
2114 return -ENOMEM;
2115
2116 easrc->pdev = pdev;
2117 easrc->private = easrc_priv;
2118 np = dev->of_node;
2119
2120 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2121 if (IS_ERR(regs))
2122 return PTR_ERR(regs);
2123
2124 easrc->paddr = res->start;
2125
2126 easrc->regmap = devm_regmap_init_mmio(dev, regs, &fsl_easrc_regmap_config);
2127 if (IS_ERR(easrc->regmap)) {
2128 dev_err(dev, "failed to init regmap");
2129 return PTR_ERR(easrc->regmap);
2130 }
2131
2132 irq = platform_get_irq(pdev, 0);
2133 if (irq < 0)
2134 return irq;
2135
2136 ret = devm_request_irq(&pdev->dev, irq, fsl_easrc_isr, 0,
2137 dev_name(dev), easrc);
2138 if (ret) {
2139 dev_err(dev, "failed to claim irq %u: %d\n", irq, ret);
2140 return ret;
2141 }
2142
2143 easrc->mem_clk = devm_clk_get(dev, "mem");
2144 if (IS_ERR(easrc->mem_clk)) {
2145 dev_err(dev, "failed to get mem clock\n");
2146 return PTR_ERR(easrc->mem_clk);
2147 }
2148
2149 /* Set default value */
2150 easrc->channel_avail = 32;
2151 easrc->get_dma_channel = fsl_easrc_get_dma_channel;
2152 easrc->request_pair = fsl_easrc_request_context;
2153 easrc->release_pair = fsl_easrc_release_context;
2154 easrc->get_fifo_addr = fsl_easrc_get_fifo_addr;
2155 easrc->pair_priv_size = sizeof(struct fsl_easrc_ctx_priv);
2156 easrc->m2m_prepare = fsl_easrc_m2m_prepare;
2157 easrc->m2m_start = fsl_easrc_m2m_start;
2158 easrc->m2m_stop = fsl_easrc_m2m_stop;
2159 easrc->get_output_fifo_size = fsl_easrc_get_output_fifo_size;
2160 easrc->m2m_calc_out_len = fsl_easrc_m2m_calc_out_len;
2161 easrc->m2m_get_maxburst = fsl_easrc_m2m_get_maxburst;
2162 easrc->m2m_pair_suspend = fsl_easrc_m2m_pair_suspend;
2163 easrc->m2m_pair_resume = fsl_easrc_m2m_pair_resume;
2164 easrc->m2m_set_ratio_mod = fsl_easrc_m2m_set_ratio_mod;
2165 easrc->m2m_get_cap = fsl_easrc_m2m_get_cap;
2166
2167 easrc_priv->rs_num_taps = EASRC_RS_32_TAPS;
2168 easrc_priv->const_coeff = 0x3FF0000000000000;
2169
2170 ret = of_property_read_u32(np, "fsl,asrc-rate", &easrc->asrc_rate);
2171 if (ret) {
2172 dev_err(dev, "failed to asrc rate\n");
2173 return ret;
2174 }
2175
2176 ret = of_property_read_u32(np, "fsl,asrc-format", &asrc_fmt);
2177 easrc->asrc_format = (__force snd_pcm_format_t)asrc_fmt;
2178 if (ret) {
2179 dev_err(dev, "failed to asrc format\n");
2180 return ret;
2181 }
2182
2183 if (!(FSL_EASRC_FORMATS & (pcm_format_to_bits(easrc->asrc_format)))) {
2184 dev_warn(dev, "unsupported format, switching to S24_LE\n");
2185 easrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
2186 }
2187
2188 ret = of_property_read_string(np, "firmware-name",
2189 &easrc_priv->fw_name);
2190 if (ret) {
2191 dev_err(dev, "failed to get firmware name\n");
2192 return ret;
2193 }
2194
2195 platform_set_drvdata(pdev, easrc);
2196 pm_runtime_enable(dev);
2197
2198 spin_lock_init(&easrc->lock);
2199
2200 regcache_cache_only(easrc->regmap, true);
2201
2202 ret = devm_snd_soc_register_component(dev, &fsl_easrc_component,
2203 &fsl_easrc_dai, 1);
2204 if (ret) {
2205 dev_err(dev, "failed to register ASoC DAI\n");
2206 goto err_pm_disable;
2207 }
2208
2209 ret = devm_snd_soc_register_component(dev, &fsl_asrc_component,
2210 NULL, 0);
2211 if (ret) {
2212 dev_err(&pdev->dev, "failed to register ASoC platform\n");
2213 goto err_pm_disable;
2214 }
2215
2216 ret = fsl_asrc_m2m_init(easrc);
2217 if (ret) {
2218 dev_err(&pdev->dev, "failed to init m2m device %d\n", ret);
2219 return ret;
2220 }
2221
2222 return 0;
2223
2224 err_pm_disable:
2225 pm_runtime_disable(&pdev->dev);
2226 return ret;
2227 }
2228
fsl_easrc_remove(struct platform_device * pdev)2229 static void fsl_easrc_remove(struct platform_device *pdev)
2230 {
2231 struct fsl_asrc *easrc = dev_get_drvdata(&pdev->dev);
2232
2233 fsl_asrc_m2m_exit(easrc);
2234
2235 pm_runtime_disable(&pdev->dev);
2236 }
2237
fsl_easrc_runtime_suspend(struct device * dev)2238 static int fsl_easrc_runtime_suspend(struct device *dev)
2239 {
2240 struct fsl_asrc *easrc = dev_get_drvdata(dev);
2241 struct fsl_easrc_priv *easrc_priv = easrc->private;
2242 unsigned long lock_flags;
2243
2244 regcache_cache_only(easrc->regmap, true);
2245
2246 clk_disable_unprepare(easrc->mem_clk);
2247
2248 spin_lock_irqsave(&easrc->lock, lock_flags);
2249 easrc_priv->firmware_loaded = 0;
2250 spin_unlock_irqrestore(&easrc->lock, lock_flags);
2251
2252 return 0;
2253 }
2254
fsl_easrc_runtime_resume(struct device * dev)2255 static int fsl_easrc_runtime_resume(struct device *dev)
2256 {
2257 struct fsl_asrc *easrc = dev_get_drvdata(dev);
2258 struct fsl_easrc_priv *easrc_priv = easrc->private;
2259 struct fsl_easrc_ctx_priv *ctx_priv;
2260 struct fsl_asrc_pair *ctx;
2261 unsigned long lock_flags;
2262 int ret;
2263 int i;
2264
2265 ret = clk_prepare_enable(easrc->mem_clk);
2266 if (ret)
2267 return ret;
2268
2269 regcache_cache_only(easrc->regmap, false);
2270 regcache_mark_dirty(easrc->regmap);
2271 regcache_sync(easrc->regmap);
2272
2273 spin_lock_irqsave(&easrc->lock, lock_flags);
2274 if (easrc_priv->firmware_loaded) {
2275 spin_unlock_irqrestore(&easrc->lock, lock_flags);
2276 goto skip_load;
2277 }
2278 easrc_priv->firmware_loaded = 1;
2279 spin_unlock_irqrestore(&easrc->lock, lock_flags);
2280
2281 ret = fsl_easrc_get_firmware(easrc);
2282 if (ret) {
2283 dev_err(dev, "failed to get firmware\n");
2284 goto disable_mem_clk;
2285 }
2286
2287 /*
2288 * Write Resampling Coefficients
2289 * The coefficient RAM must be configured prior to beginning of
2290 * any context processing within the ASRC
2291 */
2292 ret = fsl_easrc_resampler_config(easrc);
2293 if (ret) {
2294 dev_err(dev, "resampler config failed\n");
2295 goto disable_mem_clk;
2296 }
2297
2298 for (i = ASRC_PAIR_A; i < EASRC_CTX_MAX_NUM; i++) {
2299 ctx = easrc->pair[i];
2300 if (!ctx)
2301 continue;
2302
2303 ctx_priv = ctx->private;
2304 fsl_easrc_set_rs_ratio(ctx);
2305 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample *
2306 ctx_priv->out_params.sample_rate /
2307 ctx_priv->in_params.sample_rate;
2308 if (ctx_priv->in_filled_sample * ctx_priv->out_params.sample_rate
2309 % ctx_priv->in_params.sample_rate != 0)
2310 ctx_priv->out_missed_sample += 1;
2311
2312 ret = fsl_easrc_write_pf_coeff_mem(easrc, i,
2313 ctx_priv->st1_coeff,
2314 ctx_priv->st1_num_taps,
2315 ctx_priv->st1_addexp);
2316 if (ret)
2317 goto disable_mem_clk;
2318
2319 ret = fsl_easrc_write_pf_coeff_mem(easrc, i,
2320 ctx_priv->st2_coeff,
2321 ctx_priv->st2_num_taps,
2322 ctx_priv->st2_addexp);
2323 if (ret)
2324 goto disable_mem_clk;
2325 }
2326
2327 skip_load:
2328 return 0;
2329
2330 disable_mem_clk:
2331 clk_disable_unprepare(easrc->mem_clk);
2332 return ret;
2333 }
2334
fsl_easrc_suspend(struct device * dev)2335 static int fsl_easrc_suspend(struct device *dev)
2336 {
2337 struct fsl_asrc *easrc = dev_get_drvdata(dev);
2338 int ret;
2339
2340 fsl_asrc_m2m_suspend(easrc);
2341 ret = pm_runtime_force_suspend(dev);
2342 return ret;
2343 }
2344
fsl_easrc_resume(struct device * dev)2345 static int fsl_easrc_resume(struct device *dev)
2346 {
2347 struct fsl_asrc *easrc = dev_get_drvdata(dev);
2348 int ret;
2349
2350 ret = pm_runtime_force_resume(dev);
2351 fsl_asrc_m2m_resume(easrc);
2352 return ret;
2353 }
2354
2355 static const struct dev_pm_ops fsl_easrc_pm_ops = {
2356 RUNTIME_PM_OPS(fsl_easrc_runtime_suspend, fsl_easrc_runtime_resume, NULL)
2357 SYSTEM_SLEEP_PM_OPS(fsl_easrc_suspend, fsl_easrc_resume)
2358 };
2359
2360 static struct platform_driver fsl_easrc_driver = {
2361 .probe = fsl_easrc_probe,
2362 .remove = fsl_easrc_remove,
2363 .driver = {
2364 .name = "fsl-easrc",
2365 .pm = pm_ptr(&fsl_easrc_pm_ops),
2366 .of_match_table = fsl_easrc_dt_ids,
2367 },
2368 };
2369 module_platform_driver(fsl_easrc_driver);
2370
2371 MODULE_DESCRIPTION("NXP Enhanced Asynchronous Sample Rate (eASRC) driver");
2372 MODULE_LICENSE("GPL v2");
2373