xref: /linux/drivers/gpu/drm/v3d/v3d_drv.h (revision 3fd6c59042dbba50391e30862beac979491145fe)
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2015-2018 Broadcom */
3 
4 #include <linux/delay.h>
5 #include <linux/mutex.h>
6 #include <linux/spinlock_types.h>
7 #include <linux/workqueue.h>
8 
9 #include <drm/drm_encoder.h>
10 #include <drm/drm_gem.h>
11 #include <drm/drm_gem_shmem_helper.h>
12 #include <drm/gpu_scheduler.h>
13 
14 #include "v3d_performance_counters.h"
15 
16 #include "uapi/drm/v3d_drm.h"
17 
18 struct clk;
19 struct platform_device;
20 struct reset_control;
21 
22 #define V3D_MMU_PAGE_SHIFT 12
23 #define V3D_PAGE_FACTOR (PAGE_SIZE >> V3D_MMU_PAGE_SHIFT)
24 
25 #define V3D_MAX_QUEUES (V3D_CPU + 1)
26 
v3d_queue_to_string(enum v3d_queue queue)27 static inline char *v3d_queue_to_string(enum v3d_queue queue)
28 {
29 	switch (queue) {
30 	case V3D_BIN: return "bin";
31 	case V3D_RENDER: return "render";
32 	case V3D_TFU: return "tfu";
33 	case V3D_CSD: return "csd";
34 	case V3D_CACHE_CLEAN: return "cache_clean";
35 	case V3D_CPU: return "cpu";
36 	}
37 	return "UNKNOWN";
38 }
39 
40 struct v3d_stats {
41 	u64 start_ns;
42 	u64 enabled_ns;
43 	u64 jobs_completed;
44 
45 	/*
46 	 * This seqcount is used to protect the access to the GPU stats
47 	 * variables. It must be used as, while we are reading the stats,
48 	 * IRQs can happen and the stats can be updated.
49 	 */
50 	seqcount_t lock;
51 };
52 
53 struct v3d_queue_state {
54 	struct drm_gpu_scheduler sched;
55 
56 	u64 fence_context;
57 	u64 emit_seqno;
58 
59 	/* Stores the GPU stats for this queue in the global context. */
60 	struct v3d_stats stats;
61 };
62 
63 /* Performance monitor object. The perform lifetime is controlled by userspace
64  * using perfmon related ioctls. A perfmon can be attached to a submit_cl
65  * request, and when this is the case, HW perf counters will be activated just
66  * before the submit_cl is submitted to the GPU and disabled when the job is
67  * done. This way, only events related to a specific job will be counted.
68  */
69 struct v3d_perfmon {
70 	/* Tracks the number of users of the perfmon, when this counter reaches
71 	 * zero the perfmon is destroyed.
72 	 */
73 	refcount_t refcnt;
74 
75 	/* Protects perfmon stop, as it can be invoked from multiple places. */
76 	struct mutex lock;
77 
78 	/* Number of counters activated in this perfmon instance
79 	 * (should be less than DRM_V3D_MAX_PERF_COUNTERS).
80 	 */
81 	u8 ncounters;
82 
83 	/* Events counted by the HW perf counters. */
84 	u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
85 
86 	/* Storage for counter values. Counters are incremented by the
87 	 * HW perf counter values every time the perfmon is attached
88 	 * to a GPU job.  This way, perfmon users don't have to
89 	 * retrieve the results after each job if they want to track
90 	 * events covering several submissions.  Note that counter
91 	 * values can't be reset, but you can fake a reset by
92 	 * destroying the perfmon and creating a new one.
93 	 */
94 	u64 values[] __counted_by(ncounters);
95 };
96 
97 struct v3d_dev {
98 	struct drm_device drm;
99 
100 	/* Short representation (e.g. 33, 41) of the V3D tech version */
101 	int ver;
102 
103 	/* Short representation (e.g. 5, 6) of the V3D tech revision */
104 	int rev;
105 
106 	bool single_irq_line;
107 
108 	struct v3d_perfmon_info perfmon_info;
109 
110 	void __iomem *hub_regs;
111 	void __iomem *core_regs[3];
112 	void __iomem *bridge_regs;
113 	void __iomem *gca_regs;
114 	struct clk *clk;
115 	struct reset_control *reset;
116 
117 	/* Virtual and DMA addresses of the single shared page table. */
118 	volatile u32 *pt;
119 	dma_addr_t pt_paddr;
120 
121 	/* Virtual and DMA addresses of the MMU's scratch page.  When
122 	 * a read or write is invalid in the MMU, it will be
123 	 * redirected here.
124 	 */
125 	void *mmu_scratch;
126 	dma_addr_t mmu_scratch_paddr;
127 	/* virtual address bits from V3D to the MMU. */
128 	int va_width;
129 
130 	/* Number of V3D cores. */
131 	u32 cores;
132 
133 	/* Allocator managing the address space.  All units are in
134 	 * number of pages.
135 	 */
136 	struct drm_mm mm;
137 	spinlock_t mm_lock;
138 
139 	/*
140 	 * tmpfs instance used for shmem backed objects
141 	 */
142 	struct vfsmount *gemfs;
143 
144 	struct work_struct overflow_mem_work;
145 
146 	struct v3d_bin_job *bin_job;
147 	struct v3d_render_job *render_job;
148 	struct v3d_tfu_job *tfu_job;
149 	struct v3d_csd_job *csd_job;
150 	struct v3d_cpu_job *cpu_job;
151 
152 	struct v3d_queue_state queue[V3D_MAX_QUEUES];
153 
154 	/* Spinlock used to synchronize the overflow memory
155 	 * management against bin job submission.
156 	 */
157 	spinlock_t job_lock;
158 
159 	/* Used to track the active perfmon if any. */
160 	struct v3d_perfmon *active_perfmon;
161 
162 	/* Protects bo_stats */
163 	struct mutex bo_lock;
164 
165 	/* Lock taken when resetting the GPU, to keep multiple
166 	 * processes from trying to park the scheduler threads and
167 	 * reset at once.
168 	 */
169 	struct mutex reset_lock;
170 
171 	/* Lock taken when creating and pushing the GPU scheduler
172 	 * jobs, to keep the sched-fence seqnos in order.
173 	 */
174 	struct mutex sched_lock;
175 
176 	/* Lock taken during a cache clean and when initiating an L2
177 	 * flush, to keep L2 flushes from interfering with the
178 	 * synchronous L2 cleans.
179 	 */
180 	struct mutex cache_clean_lock;
181 
182 	struct {
183 		u32 num_allocated;
184 		u32 pages_allocated;
185 	} bo_stats;
186 };
187 
188 static inline struct v3d_dev *
to_v3d_dev(struct drm_device * dev)189 to_v3d_dev(struct drm_device *dev)
190 {
191 	return container_of(dev, struct v3d_dev, drm);
192 }
193 
194 static inline bool
v3d_has_csd(struct v3d_dev * v3d)195 v3d_has_csd(struct v3d_dev *v3d)
196 {
197 	return v3d->ver >= 41;
198 }
199 
200 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev)
201 
202 /* The per-fd struct, which tracks the MMU mappings. */
203 struct v3d_file_priv {
204 	struct v3d_dev *v3d;
205 
206 	struct {
207 		struct idr idr;
208 		struct mutex lock;
209 	} perfmon;
210 
211 	struct drm_sched_entity sched_entity[V3D_MAX_QUEUES];
212 
213 	/* Stores the GPU stats for a specific queue for this fd. */
214 	struct v3d_stats stats[V3D_MAX_QUEUES];
215 };
216 
217 struct v3d_bo {
218 	struct drm_gem_shmem_object base;
219 
220 	struct drm_mm_node node;
221 
222 	/* List entry for the BO's position in
223 	 * v3d_render_job->unref_list
224 	 */
225 	struct list_head unref_head;
226 
227 	void *vaddr;
228 };
229 
230 static inline struct v3d_bo *
to_v3d_bo(struct drm_gem_object * bo)231 to_v3d_bo(struct drm_gem_object *bo)
232 {
233 	return (struct v3d_bo *)bo;
234 }
235 
236 struct v3d_fence {
237 	struct dma_fence base;
238 	struct drm_device *dev;
239 	/* v3d seqno for signaled() test */
240 	u64 seqno;
241 	enum v3d_queue queue;
242 };
243 
244 static inline struct v3d_fence *
to_v3d_fence(struct dma_fence * fence)245 to_v3d_fence(struct dma_fence *fence)
246 {
247 	return (struct v3d_fence *)fence;
248 }
249 
250 #define V3D_READ(offset) readl(v3d->hub_regs + offset)
251 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
252 
253 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
254 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
255 
256 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
257 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
258 
259 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
260 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
261 
262 struct v3d_job {
263 	struct drm_sched_job base;
264 
265 	struct kref refcount;
266 
267 	struct v3d_dev *v3d;
268 
269 	/* This is the array of BOs that were looked up at the start
270 	 * of submission.
271 	 */
272 	struct drm_gem_object **bo;
273 	u32 bo_count;
274 
275 	/* v3d fence to be signaled by IRQ handler when the job is complete. */
276 	struct dma_fence *irq_fence;
277 
278 	/* scheduler fence for when the job is considered complete and
279 	 * the BO reservations can be released.
280 	 */
281 	struct dma_fence *done_fence;
282 
283 	/* Pointer to a performance monitor object if the user requested it,
284 	 * NULL otherwise.
285 	 */
286 	struct v3d_perfmon *perfmon;
287 
288 	/* File descriptor of the process that submitted the job that could be used
289 	 * for collecting stats by process of GPU usage.
290 	 */
291 	struct drm_file *file;
292 
293 	/* Callback for the freeing of the job on refcount going to 0. */
294 	void (*free)(struct kref *ref);
295 };
296 
297 struct v3d_bin_job {
298 	struct v3d_job base;
299 
300 	/* GPU virtual addresses of the start/end of the CL job. */
301 	u32 start, end;
302 
303 	u32 timedout_ctca, timedout_ctra;
304 
305 	/* Corresponding render job, for attaching our overflow memory. */
306 	struct v3d_render_job *render;
307 
308 	/* Submitted tile memory allocation start/size, tile state. */
309 	u32 qma, qms, qts;
310 };
311 
312 struct v3d_render_job {
313 	struct v3d_job base;
314 
315 	/* GPU virtual addresses of the start/end of the CL job. */
316 	u32 start, end;
317 
318 	u32 timedout_ctca, timedout_ctra;
319 
320 	/* List of overflow BOs used in the job that need to be
321 	 * released once the job is complete.
322 	 */
323 	struct list_head unref_list;
324 };
325 
326 struct v3d_tfu_job {
327 	struct v3d_job base;
328 
329 	struct drm_v3d_submit_tfu args;
330 };
331 
332 struct v3d_csd_job {
333 	struct v3d_job base;
334 
335 	u32 timedout_batches;
336 
337 	struct drm_v3d_submit_csd args;
338 };
339 
340 enum v3d_cpu_job_type {
341 	V3D_CPU_JOB_TYPE_INDIRECT_CSD = 1,
342 	V3D_CPU_JOB_TYPE_TIMESTAMP_QUERY,
343 	V3D_CPU_JOB_TYPE_RESET_TIMESTAMP_QUERY,
344 	V3D_CPU_JOB_TYPE_COPY_TIMESTAMP_QUERY,
345 	V3D_CPU_JOB_TYPE_RESET_PERFORMANCE_QUERY,
346 	V3D_CPU_JOB_TYPE_COPY_PERFORMANCE_QUERY,
347 };
348 
349 struct v3d_timestamp_query {
350 	/* Offset of this query in the timestamp BO for its value. */
351 	u32 offset;
352 
353 	/* Syncobj that indicates the timestamp availability */
354 	struct drm_syncobj *syncobj;
355 };
356 
357 struct v3d_performance_query {
358 	/* Performance monitor IDs for this query */
359 	u32 *kperfmon_ids;
360 
361 	/* Syncobj that indicates the query availability */
362 	struct drm_syncobj *syncobj;
363 };
364 
365 struct v3d_indirect_csd_info {
366 	/* Indirect CSD */
367 	struct v3d_csd_job *job;
368 
369 	/* Clean cache job associated to the Indirect CSD job */
370 	struct v3d_job *clean_job;
371 
372 	/* Offset within the BO where the workgroup counts are stored */
373 	u32 offset;
374 
375 	/* Workgroups size */
376 	u32 wg_size;
377 
378 	/* Indices of the uniforms with the workgroup dispatch counts
379 	 * in the uniform stream.
380 	 */
381 	u32 wg_uniform_offsets[3];
382 
383 	/* Indirect BO */
384 	struct drm_gem_object *indirect;
385 
386 	/* Context of the Indirect CSD job */
387 	struct ww_acquire_ctx acquire_ctx;
388 };
389 
390 struct v3d_timestamp_query_info {
391 	struct v3d_timestamp_query *queries;
392 
393 	u32 count;
394 };
395 
396 struct v3d_performance_query_info {
397 	struct v3d_performance_query *queries;
398 
399 	/* Number of performance queries */
400 	u32 count;
401 
402 	/* Number of performance monitors related to that query pool */
403 	u32 nperfmons;
404 
405 	/* Number of performance counters related to that query pool */
406 	u32 ncounters;
407 };
408 
409 struct v3d_copy_query_results_info {
410 	/* Define if should write to buffer using 64 or 32 bits */
411 	bool do_64bit;
412 
413 	/* Define if it can write to buffer even if the query is not available */
414 	bool do_partial;
415 
416 	/* Define if it should write availability bit to buffer */
417 	bool availability_bit;
418 
419 	/* Offset of the copy buffer in the BO */
420 	u32 offset;
421 
422 	/* Stride of the copy buffer in the BO */
423 	u32 stride;
424 };
425 
426 struct v3d_cpu_job {
427 	struct v3d_job base;
428 
429 	enum v3d_cpu_job_type job_type;
430 
431 	struct v3d_indirect_csd_info indirect_csd;
432 
433 	struct v3d_timestamp_query_info timestamp_query;
434 
435 	struct v3d_copy_query_results_info copy;
436 
437 	struct v3d_performance_query_info performance_query;
438 };
439 
440 typedef void (*v3d_cpu_job_fn)(struct v3d_cpu_job *);
441 
442 struct v3d_submit_outsync {
443 	struct drm_syncobj *syncobj;
444 };
445 
446 struct v3d_submit_ext {
447 	u32 flags;
448 	u32 wait_stage;
449 
450 	u32 in_sync_count;
451 	u64 in_syncs;
452 
453 	u32 out_sync_count;
454 	struct v3d_submit_outsync *out_syncs;
455 };
456 
457 /**
458  * __wait_for - magic wait macro
459  *
460  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
461  * important that we check the condition again after having timed out, since the
462  * timeout could be due to preemption or similar and we've never had a chance to
463  * check the condition before the timeout.
464  */
465 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
466 	const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
467 	long wait__ = (Wmin); /* recommended min for usleep is 10 us */	\
468 	int ret__;							\
469 	might_sleep();							\
470 	for (;;) {							\
471 		const bool expired__ = ktime_after(ktime_get_raw(), end__); \
472 		OP;							\
473 		/* Guarantee COND check prior to timeout */		\
474 		barrier();						\
475 		if (COND) {						\
476 			ret__ = 0;					\
477 			break;						\
478 		}							\
479 		if (expired__) {					\
480 			ret__ = -ETIMEDOUT;				\
481 			break;						\
482 		}							\
483 		usleep_range(wait__, wait__ * 2);			\
484 		if (wait__ < (Wmax))					\
485 			wait__ <<= 1;					\
486 	}								\
487 	ret__;								\
488 })
489 
490 #define _wait_for(COND, US, Wmin, Wmax)	__wait_for(, (COND), (US), (Wmin), \
491 						   (Wmax))
492 #define wait_for(COND, MS)		_wait_for((COND), (MS) * 1000, 10, 1000)
493 
nsecs_to_jiffies_timeout(const u64 n)494 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
495 {
496 	/* nsecs_to_jiffies64() does not guard against overflow */
497 	if ((NSEC_PER_SEC % HZ) != 0 &&
498 	    div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
499 		return MAX_JIFFY_OFFSET;
500 
501 	return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
502 }
503 
504 /* v3d_bo.c */
505 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size);
506 void v3d_free_object(struct drm_gem_object *gem_obj);
507 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv,
508 			     size_t size);
509 void v3d_get_bo_vaddr(struct v3d_bo *bo);
510 void v3d_put_bo_vaddr(struct v3d_bo *bo);
511 int v3d_create_bo_ioctl(struct drm_device *dev, void *data,
512 			struct drm_file *file_priv);
513 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data,
514 		      struct drm_file *file_priv);
515 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data,
516 			    struct drm_file *file_priv);
517 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
518 		      struct drm_file *file_priv);
519 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev,
520 						 struct dma_buf_attachment *attach,
521 						 struct sg_table *sgt);
522 
523 /* v3d_debugfs.c */
524 void v3d_debugfs_init(struct drm_minor *minor);
525 
526 /* v3d_drv.c */
527 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp,
528 		   u64 *active_runtime, u64 *jobs_completed);
529 
530 /* v3d_fence.c */
531 extern const struct dma_fence_ops v3d_fence_ops;
532 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
533 
534 /* v3d_gem.c */
535 int v3d_gem_init(struct drm_device *dev);
536 void v3d_gem_destroy(struct drm_device *dev);
537 void v3d_reset(struct v3d_dev *v3d);
538 void v3d_invalidate_caches(struct v3d_dev *v3d);
539 void v3d_clean_caches(struct v3d_dev *v3d);
540 
541 /* v3d_gemfs.c */
542 extern bool super_pages;
543 void v3d_gemfs_init(struct v3d_dev *v3d);
544 void v3d_gemfs_fini(struct v3d_dev *v3d);
545 
546 /* v3d_submit.c */
547 void v3d_job_cleanup(struct v3d_job *job);
548 void v3d_job_put(struct v3d_job *job);
549 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
550 			struct drm_file *file_priv);
551 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data,
552 			 struct drm_file *file_priv);
553 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data,
554 			 struct drm_file *file_priv);
555 int v3d_submit_cpu_ioctl(struct drm_device *dev, void *data,
556 			 struct drm_file *file_priv);
557 
558 /* v3d_irq.c */
559 int v3d_irq_init(struct v3d_dev *v3d);
560 void v3d_irq_enable(struct v3d_dev *v3d);
561 void v3d_irq_disable(struct v3d_dev *v3d);
562 void v3d_irq_reset(struct v3d_dev *v3d);
563 
564 /* v3d_mmu.c */
565 int v3d_mmu_flush_all(struct v3d_dev *v3d);
566 int v3d_mmu_set_page_table(struct v3d_dev *v3d);
567 void v3d_mmu_insert_ptes(struct v3d_bo *bo);
568 void v3d_mmu_remove_ptes(struct v3d_bo *bo);
569 
570 /* v3d_sched.c */
571 void v3d_timestamp_query_info_free(struct v3d_timestamp_query_info *query_info,
572 				   unsigned int count);
573 void v3d_performance_query_info_free(struct v3d_performance_query_info *query_info,
574 				     unsigned int count);
575 void v3d_job_update_stats(struct v3d_job *job, enum v3d_queue queue);
576 int v3d_sched_init(struct v3d_dev *v3d);
577 void v3d_sched_fini(struct v3d_dev *v3d);
578 
579 /* v3d_perfmon.c */
580 void v3d_perfmon_init(struct v3d_dev *v3d);
581 void v3d_perfmon_get(struct v3d_perfmon *perfmon);
582 void v3d_perfmon_put(struct v3d_perfmon *perfmon);
583 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon);
584 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon,
585 		      bool capture);
586 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id);
587 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv);
588 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv);
589 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data,
590 			     struct drm_file *file_priv);
591 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
592 			      struct drm_file *file_priv);
593 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
594 				 struct drm_file *file_priv);
595 int v3d_perfmon_get_counter_ioctl(struct drm_device *dev, void *data,
596 				  struct drm_file *file_priv);
597 
598 /* v3d_sysfs.c */
599 int v3d_sysfs_init(struct device *dev);
600 void v3d_sysfs_destroy(struct device *dev);
601