xref: /linux/sound/soc/fsl/fsl_micfil.c (revision 6537cfb395f352782918d8ee7b7f10ba2cc3cbf2)
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 // Copyright 2018 NXP
3 
4 #include <linux/bitfield.h>
5 #include <linux/clk.h>
6 #include <linux/device.h>
7 #include <linux/interrupt.h>
8 #include <linux/kobject.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/of_irq.h>
14 #include <linux/of_platform.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/sysfs.h>
18 #include <linux/types.h>
19 #include <linux/dma/imx-dma.h>
20 #include <sound/dmaengine_pcm.h>
21 #include <sound/pcm.h>
22 #include <sound/soc.h>
23 #include <sound/tlv.h>
24 #include <sound/core.h>
25 
26 #include "fsl_micfil.h"
27 #include "fsl_utils.h"
28 
29 #define MICFIL_OSR_DEFAULT	16
30 
31 #define MICFIL_NUM_RATES	7
32 #define MICFIL_CLK_SRC_NUM	3
33 /* clock source ids */
34 #define MICFIL_AUDIO_PLL1	0
35 #define MICFIL_AUDIO_PLL2	1
36 #define MICFIL_CLK_EXT3		2
37 
38 static const unsigned int fsl_micfil_rates[] = {
39 	8000, 11025, 16000, 22050, 32000, 44100, 48000,
40 };
41 
42 static const struct snd_pcm_hw_constraint_list fsl_micfil_rate_constraints = {
43 	.count = ARRAY_SIZE(fsl_micfil_rates),
44 	.list = fsl_micfil_rates,
45 };
46 
47 enum quality {
48 	QUALITY_HIGH,
49 	QUALITY_MEDIUM,
50 	QUALITY_LOW,
51 	QUALITY_VLOW0,
52 	QUALITY_VLOW1,
53 	QUALITY_VLOW2,
54 };
55 
56 struct fsl_micfil {
57 	struct platform_device *pdev;
58 	struct regmap *regmap;
59 	const struct fsl_micfil_soc_data *soc;
60 	struct clk *busclk;
61 	struct clk *mclk;
62 	struct clk *pll8k_clk;
63 	struct clk *pll11k_clk;
64 	struct clk *clk_src[MICFIL_CLK_SRC_NUM];
65 	struct snd_dmaengine_dai_dma_data dma_params_rx;
66 	struct sdma_peripheral_config sdmacfg;
67 	struct snd_soc_card *card;
68 	struct snd_pcm_hw_constraint_list constraint_rates;
69 	unsigned int constraint_rates_list[MICFIL_NUM_RATES];
70 	unsigned int dataline;
71 	char name[32];
72 	int irq[MICFIL_IRQ_LINES];
73 	enum quality quality;
74 	int dc_remover;
75 	int vad_init_mode;
76 	int vad_enabled;
77 	int vad_detected;
78 	struct fsl_micfil_verid verid;
79 	struct fsl_micfil_param param;
80 	bool mclk_flag;  /* mclk enable flag */
81 };
82 
83 struct fsl_micfil_soc_data {
84 	unsigned int fifos;
85 	unsigned int fifo_depth;
86 	unsigned int dataline;
87 	bool imx;
88 	bool use_edma;
89 	bool use_verid;
90 	bool volume_sx;
91 	u64  formats;
92 	int  fifo_offset;
93 };
94 
95 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
96 	.imx = true,
97 	.fifos = 8,
98 	.fifo_depth = 8,
99 	.dataline =  0xf,
100 	.formats = SNDRV_PCM_FMTBIT_S16_LE,
101 	.volume_sx = true,
102 	.fifo_offset = 0,
103 };
104 
105 static struct fsl_micfil_soc_data fsl_micfil_imx8mp = {
106 	.imx = true,
107 	.fifos = 8,
108 	.fifo_depth = 32,
109 	.dataline =  0xf,
110 	.formats = SNDRV_PCM_FMTBIT_S32_LE,
111 	.volume_sx = false,
112 	.fifo_offset = 0,
113 };
114 
115 static struct fsl_micfil_soc_data fsl_micfil_imx93 = {
116 	.imx = true,
117 	.fifos = 8,
118 	.fifo_depth = 32,
119 	.dataline =  0xf,
120 	.formats = SNDRV_PCM_FMTBIT_S32_LE,
121 	.use_edma = true,
122 	.use_verid = true,
123 	.volume_sx = false,
124 	.fifo_offset = 0,
125 };
126 
127 static struct fsl_micfil_soc_data fsl_micfil_imx943 = {
128 	.imx = true,
129 	.fifos = 8,
130 	.fifo_depth = 32,
131 	.dataline =  0xf,
132 	.formats = SNDRV_PCM_FMTBIT_S32_LE,
133 	.use_edma = true,
134 	.use_verid = true,
135 	.volume_sx = false,
136 	.fifo_offset = -4,
137 };
138 
139 static const struct of_device_id fsl_micfil_dt_ids[] = {
140 	{ .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
141 	{ .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp },
142 	{ .compatible = "fsl,imx93-micfil", .data = &fsl_micfil_imx93 },
143 	{ .compatible = "fsl,imx943-micfil", .data = &fsl_micfil_imx943 },
144 	{}
145 };
146 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
147 
148 static const char * const micfil_quality_select_texts[] = {
149 	[QUALITY_HIGH] = "High",
150 	[QUALITY_MEDIUM] = "Medium",
151 	[QUALITY_LOW] = "Low",
152 	[QUALITY_VLOW0] = "VLow0",
153 	[QUALITY_VLOW1] = "Vlow1",
154 	[QUALITY_VLOW2] = "Vlow2",
155 };
156 
157 static const struct soc_enum fsl_micfil_quality_enum =
158 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts),
159 			    micfil_quality_select_texts);
160 
161 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
162 
micfil_set_quality(struct fsl_micfil * micfil)163 static int micfil_set_quality(struct fsl_micfil *micfil)
164 {
165 	u32 qsel;
166 
167 	switch (micfil->quality) {
168 	case QUALITY_HIGH:
169 		qsel = MICFIL_QSEL_HIGH_QUALITY;
170 		break;
171 	case QUALITY_MEDIUM:
172 		qsel = MICFIL_QSEL_MEDIUM_QUALITY;
173 		break;
174 	case QUALITY_LOW:
175 		qsel = MICFIL_QSEL_LOW_QUALITY;
176 		break;
177 	case QUALITY_VLOW0:
178 		qsel = MICFIL_QSEL_VLOW0_QUALITY;
179 		break;
180 	case QUALITY_VLOW1:
181 		qsel = MICFIL_QSEL_VLOW1_QUALITY;
182 		break;
183 	case QUALITY_VLOW2:
184 		qsel = MICFIL_QSEL_VLOW2_QUALITY;
185 		break;
186 	default:
187 		return -EINVAL;
188 	}
189 
190 	return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
191 				  MICFIL_CTRL2_QSEL,
192 				  FIELD_PREP(MICFIL_CTRL2_QSEL, qsel));
193 }
194 
micfil_quality_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)195 static int micfil_quality_get(struct snd_kcontrol *kcontrol,
196 			      struct snd_ctl_elem_value *ucontrol)
197 {
198 	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
199 	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
200 
201 	ucontrol->value.integer.value[0] = micfil->quality;
202 
203 	return 0;
204 }
205 
micfil_quality_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)206 static int micfil_quality_set(struct snd_kcontrol *kcontrol,
207 			      struct snd_ctl_elem_value *ucontrol)
208 {
209 	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
210 	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
211 
212 	micfil->quality = ucontrol->value.integer.value[0];
213 
214 	return micfil_set_quality(micfil);
215 }
216 
217 static const char * const micfil_hwvad_enable[] = {
218 	"Disable (Record only)",
219 	"Enable (Record with Vad)",
220 };
221 
222 static const char * const micfil_hwvad_init_mode[] = {
223 	"Envelope mode", "Energy mode",
224 };
225 
226 static const char * const micfil_hwvad_hpf_texts[] = {
227 	"Filter bypass",
228 	"Cut-off @1750Hz",
229 	"Cut-off @215Hz",
230 	"Cut-off @102Hz",
231 };
232 
233 /*
234  * DC Remover Control
235  * Filter Bypassed	1 1
236  * Cut-off @21Hz	0 0
237  * Cut-off @83Hz	0 1
238  * Cut-off @152HZ	1 0
239  */
240 static const char * const micfil_dc_remover_texts[] = {
241 	"Cut-off @21Hz", "Cut-off @83Hz",
242 	"Cut-off @152Hz", "Bypass",
243 };
244 
245 static const struct soc_enum hwvad_enable_enum =
246 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_enable),
247 			    micfil_hwvad_enable);
248 static const struct soc_enum hwvad_init_mode_enum =
249 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_init_mode),
250 			    micfil_hwvad_init_mode);
251 static const struct soc_enum hwvad_hpf_enum =
252 	SOC_ENUM_SINGLE(REG_MICFIL_VAD0_CTRL2, 0,
253 			ARRAY_SIZE(micfil_hwvad_hpf_texts),
254 			micfil_hwvad_hpf_texts);
255 static const struct soc_enum fsl_micfil_dc_remover_enum =
256 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_remover_texts),
257 			    micfil_dc_remover_texts);
258 
micfil_put_dc_remover_state(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)259 static int micfil_put_dc_remover_state(struct snd_kcontrol *kcontrol,
260 				       struct snd_ctl_elem_value *ucontrol)
261 {
262 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
263 	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
264 	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
265 	unsigned int *item = ucontrol->value.enumerated.item;
266 	int val = snd_soc_enum_item_to_val(e, item[0]);
267 	int i = 0, ret = 0;
268 	u32 reg_val = 0;
269 
270 	if (val < 0 || val > 3)
271 		return -EINVAL;
272 
273 	micfil->dc_remover = val;
274 
275 	/* Calculate total value for all channels */
276 	for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
277 		reg_val |= val << MICFIL_DC_CHX_SHIFT(i);
278 
279 	/* Update DC Remover mode for all channels */
280 	ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_CTRL,
281 					    MICFIL_DC_CTRL_CONFIG, reg_val);
282 	if (ret < 0)
283 		return ret;
284 
285 	return 0;
286 }
287 
micfil_get_dc_remover_state(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)288 static int micfil_get_dc_remover_state(struct snd_kcontrol *kcontrol,
289 				       struct snd_ctl_elem_value *ucontrol)
290 {
291 	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
292 	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
293 
294 	ucontrol->value.enumerated.item[0] = micfil->dc_remover;
295 
296 	return 0;
297 }
298 
hwvad_put_enable(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)299 static int hwvad_put_enable(struct snd_kcontrol *kcontrol,
300 			    struct snd_ctl_elem_value *ucontrol)
301 {
302 	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
303 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
304 	unsigned int *item = ucontrol->value.enumerated.item;
305 	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
306 	int val = snd_soc_enum_item_to_val(e, item[0]);
307 
308 	micfil->vad_enabled = val;
309 
310 	return 0;
311 }
312 
hwvad_get_enable(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)313 static int hwvad_get_enable(struct snd_kcontrol *kcontrol,
314 			    struct snd_ctl_elem_value *ucontrol)
315 {
316 	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
317 	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
318 
319 	ucontrol->value.enumerated.item[0] = micfil->vad_enabled;
320 
321 	return 0;
322 }
323 
hwvad_put_init_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)324 static int hwvad_put_init_mode(struct snd_kcontrol *kcontrol,
325 			       struct snd_ctl_elem_value *ucontrol)
326 {
327 	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
328 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
329 	unsigned int *item = ucontrol->value.enumerated.item;
330 	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
331 	int val = snd_soc_enum_item_to_val(e, item[0]);
332 
333 	/* 0 - Envelope-based Mode
334 	 * 1 - Energy-based Mode
335 	 */
336 	micfil->vad_init_mode = val;
337 
338 	return 0;
339 }
340 
hwvad_get_init_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)341 static int hwvad_get_init_mode(struct snd_kcontrol *kcontrol,
342 			       struct snd_ctl_elem_value *ucontrol)
343 {
344 	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
345 	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
346 
347 	ucontrol->value.enumerated.item[0] = micfil->vad_init_mode;
348 
349 	return 0;
350 }
351 
hwvad_detected(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)352 static int hwvad_detected(struct snd_kcontrol *kcontrol,
353 			  struct snd_ctl_elem_value *ucontrol)
354 {
355 	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
356 	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
357 
358 	ucontrol->value.enumerated.item[0] = micfil->vad_detected;
359 
360 	return 0;
361 }
362 
363 static const struct snd_kcontrol_new fsl_micfil_volume_controls[] = {
364 	SOC_SINGLE_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
365 		       MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0, gain_tlv),
366 	SOC_SINGLE_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
367 		       MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0, gain_tlv),
368 	SOC_SINGLE_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
369 		       MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0, gain_tlv),
370 	SOC_SINGLE_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
371 		       MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0, gain_tlv),
372 	SOC_SINGLE_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
373 		       MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0, gain_tlv),
374 	SOC_SINGLE_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
375 		       MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0, gain_tlv),
376 	SOC_SINGLE_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
377 		       MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0, gain_tlv),
378 	SOC_SINGLE_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
379 		       MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0, gain_tlv),
380 };
381 
382 static const struct snd_kcontrol_new fsl_micfil_volume_sx_controls[] = {
383 	SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
384 			  MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv),
385 	SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
386 			  MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv),
387 	SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
388 			  MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv),
389 	SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
390 			  MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv),
391 	SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
392 			  MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv),
393 	SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
394 			  MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv),
395 	SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
396 			  MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv),
397 	SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
398 			  MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv),
399 };
400 
401 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
402 	SOC_ENUM_EXT("MICFIL Quality Select",
403 		     fsl_micfil_quality_enum,
404 		     micfil_quality_get, micfil_quality_set),
405 	SOC_ENUM_EXT("HWVAD Enablement Switch", hwvad_enable_enum,
406 		     hwvad_get_enable, hwvad_put_enable),
407 	SOC_ENUM_EXT("HWVAD Initialization Mode", hwvad_init_mode_enum,
408 		     hwvad_get_init_mode, hwvad_put_init_mode),
409 	SOC_ENUM("HWVAD High-Pass Filter", hwvad_hpf_enum),
410 	SOC_SINGLE("HWVAD ZCD Switch", REG_MICFIL_VAD0_ZCD, 0, 1, 0),
411 	SOC_SINGLE("HWVAD ZCD Auto Threshold Switch",
412 		   REG_MICFIL_VAD0_ZCD, 2, 1, 0),
413 	SOC_ENUM_EXT("MICFIL DC Remover Control", fsl_micfil_dc_remover_enum,
414 		     micfil_get_dc_remover_state, micfil_put_dc_remover_state),
415 	SOC_SINGLE("HWVAD Input Gain", REG_MICFIL_VAD0_CTRL2, 8, 15, 0),
416 	SOC_SINGLE("HWVAD Sound Gain", REG_MICFIL_VAD0_SCONFIG, 0, 15, 0),
417 	SOC_SINGLE("HWVAD Noise Gain", REG_MICFIL_VAD0_NCONFIG, 0, 15, 0),
418 	SOC_SINGLE_RANGE("HWVAD Detector Frame Time", REG_MICFIL_VAD0_CTRL2, 16, 0, 63, 0),
419 	SOC_SINGLE("HWVAD Detector Initialization Time", REG_MICFIL_VAD0_CTRL1, 8, 31, 0),
420 	SOC_SINGLE("HWVAD Noise Filter Adjustment", REG_MICFIL_VAD0_NCONFIG, 8, 31, 0),
421 	SOC_SINGLE("HWVAD ZCD Threshold", REG_MICFIL_VAD0_ZCD, 16, 1023, 0),
422 	SOC_SINGLE("HWVAD ZCD Adjustment", REG_MICFIL_VAD0_ZCD, 8, 15, 0),
423 	SOC_SINGLE("HWVAD ZCD And Behavior Switch",
424 		   REG_MICFIL_VAD0_ZCD, 4, 1, 0),
425 	SOC_SINGLE_BOOL_EXT("VAD Detected", 0, hwvad_detected, NULL),
426 };
427 
fsl_micfil_use_verid(struct device * dev)428 static int fsl_micfil_use_verid(struct device *dev)
429 {
430 	struct fsl_micfil *micfil = dev_get_drvdata(dev);
431 	unsigned int val;
432 	int ret;
433 
434 	if (!micfil->soc->use_verid)
435 		return 0;
436 
437 	ret = regmap_read(micfil->regmap, REG_MICFIL_VERID, &val);
438 	if (ret < 0)
439 		return ret;
440 
441 	dev_dbg(dev, "VERID: 0x%016X\n", val);
442 
443 	micfil->verid.version = val &
444 		(MICFIL_VERID_MAJOR_MASK | MICFIL_VERID_MINOR_MASK);
445 	micfil->verid.version >>= MICFIL_VERID_MINOR_SHIFT;
446 	micfil->verid.feature = val & MICFIL_VERID_FEATURE_MASK;
447 
448 	ret = regmap_read(micfil->regmap, REG_MICFIL_PARAM, &val);
449 	if (ret < 0)
450 		return ret;
451 
452 	dev_dbg(dev, "PARAM: 0x%016X\n", val);
453 
454 	micfil->param.hwvad_num = (val & MICFIL_PARAM_NUM_HWVAD_MASK) >>
455 		MICFIL_PARAM_NUM_HWVAD_SHIFT;
456 	micfil->param.hwvad_zcd = val & MICFIL_PARAM_HWVAD_ZCD;
457 	micfil->param.hwvad_energy_mode = val & MICFIL_PARAM_HWVAD_ENERGY_MODE;
458 	micfil->param.hwvad = val & MICFIL_PARAM_HWVAD;
459 	micfil->param.dc_out_bypass = val & MICFIL_PARAM_DC_OUT_BYPASS;
460 	micfil->param.dc_in_bypass = val & MICFIL_PARAM_DC_IN_BYPASS;
461 	micfil->param.low_power = val & MICFIL_PARAM_LOW_POWER;
462 	micfil->param.fil_out_width = val & MICFIL_PARAM_FIL_OUT_WIDTH;
463 	micfil->param.fifo_ptrwid = (val & MICFIL_PARAM_FIFO_PTRWID_MASK) >>
464 		MICFIL_PARAM_FIFO_PTRWID_SHIFT;
465 	micfil->param.npair = (val & MICFIL_PARAM_NPAIR_MASK) >>
466 		MICFIL_PARAM_NPAIR_SHIFT;
467 
468 	return 0;
469 }
470 
471 /* The SRES is a self-negated bit which provides the CPU with the
472  * capability to initialize the PDM Interface module through the
473  * slave-bus interface. This bit always reads as zero, and this
474  * bit is only effective when MDIS is cleared
475  */
fsl_micfil_reset(struct device * dev)476 static int fsl_micfil_reset(struct device *dev)
477 {
478 	struct fsl_micfil *micfil = dev_get_drvdata(dev);
479 	int ret;
480 
481 	ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
482 				MICFIL_CTRL1_MDIS);
483 	if (ret)
484 		return ret;
485 
486 	ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
487 			      MICFIL_CTRL1_SRES);
488 	if (ret)
489 		return ret;
490 
491 	/*
492 	 * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined
493 	 * as non-volatile register, so SRES still remain in regmap
494 	 * cache after set, that every update of REG_MICFIL_CTRL1,
495 	 * software reset happens. so clear it explicitly.
496 	 */
497 	ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
498 				MICFIL_CTRL1_SRES);
499 	if (ret)
500 		return ret;
501 
502 	/*
503 	 * Set SRES should clear CHnF flags, But even add delay here
504 	 * the CHnF may not be cleared sometimes, so clear CHnF explicitly.
505 	 */
506 	ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF);
507 	if (ret)
508 		return ret;
509 
510 	return 0;
511 }
512 
fsl_micfil_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)513 static int fsl_micfil_startup(struct snd_pcm_substream *substream,
514 			      struct snd_soc_dai *dai)
515 {
516 	struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
517 
518 	if (!micfil) {
519 		dev_err(dai->dev, "micfil dai priv_data not set\n");
520 		return -EINVAL;
521 	}
522 
523 	if (micfil->constraint_rates.count > 0)
524 		snd_pcm_hw_constraint_list(substream->runtime, 0,
525 					   SNDRV_PCM_HW_PARAM_RATE,
526 					   &micfil->constraint_rates);
527 
528 	return 0;
529 }
530 
531 /* Enable/disable hwvad interrupts */
fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil * micfil,int enable)532 static int fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil *micfil, int enable)
533 {
534 	u32 vadie_reg = enable ? MICFIL_VAD0_CTRL1_IE : 0;
535 	u32 vaderie_reg = enable ? MICFIL_VAD0_CTRL1_ERIE : 0;
536 
537 	/* Voice Activity Detector Error Interruption */
538 	regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
539 			   MICFIL_VAD0_CTRL1_ERIE, vaderie_reg);
540 
541 	/* Voice Activity Detector Interruption */
542 	regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
543 			   MICFIL_VAD0_CTRL1_IE, vadie_reg);
544 
545 	return 0;
546 }
547 
548 /* Configuration done only in energy-based initialization mode */
fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil * micfil)549 static int fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil *micfil)
550 {
551 	/* Keep the VADFRENDIS bitfield cleared. */
552 	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
553 			  MICFIL_VAD0_CTRL2_FRENDIS);
554 
555 	/* Keep the VADPREFEN bitfield cleared. */
556 	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
557 			  MICFIL_VAD0_CTRL2_PREFEN);
558 
559 	/* Keep the VADSFILEN bitfield cleared. */
560 	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
561 			  MICFIL_VAD0_SCONFIG_SFILEN);
562 
563 	/* Keep the VADSMAXEN bitfield cleared. */
564 	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
565 			  MICFIL_VAD0_SCONFIG_SMAXEN);
566 
567 	/* Keep the VADNFILAUTO bitfield asserted. */
568 	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
569 			MICFIL_VAD0_NCONFIG_NFILAUT);
570 
571 	/* Keep the VADNMINEN bitfield cleared. */
572 	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
573 			  MICFIL_VAD0_NCONFIG_NMINEN);
574 
575 	/* Keep the VADNDECEN bitfield cleared. */
576 	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
577 			  MICFIL_VAD0_NCONFIG_NDECEN);
578 
579 	/* Keep the VADNOREN bitfield cleared. */
580 	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
581 			  MICFIL_VAD0_NCONFIG_NOREN);
582 
583 	return 0;
584 }
585 
586 /* Configuration done only in envelope-based initialization mode */
fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil * micfil)587 static int fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil *micfil)
588 {
589 	/* Assert the VADFRENDIS bitfield */
590 	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
591 			MICFIL_VAD0_CTRL2_FRENDIS);
592 
593 	/* Assert the VADPREFEN bitfield. */
594 	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
595 			MICFIL_VAD0_CTRL2_PREFEN);
596 
597 	/* Assert the VADSFILEN bitfield. */
598 	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
599 			MICFIL_VAD0_SCONFIG_SFILEN);
600 
601 	/* Assert the VADSMAXEN bitfield. */
602 	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
603 			MICFIL_VAD0_SCONFIG_SMAXEN);
604 
605 	/* Clear the VADNFILAUTO bitfield */
606 	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
607 			  MICFIL_VAD0_NCONFIG_NFILAUT);
608 
609 	/* Assert the VADNMINEN bitfield. */
610 	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
611 			MICFIL_VAD0_NCONFIG_NMINEN);
612 
613 	/* Assert the VADNDECEN bitfield. */
614 	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
615 			MICFIL_VAD0_NCONFIG_NDECEN);
616 
617 	/* Assert VADNOREN bitfield. */
618 	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
619 			MICFIL_VAD0_NCONFIG_NOREN);
620 
621 	return 0;
622 }
623 
624 /*
625  * Hardware Voice Active Detection: The HWVAD takes data from the input
626  * of a selected PDM microphone to detect if there is any
627  * voice activity. When a voice activity is detected, an interrupt could
628  * be delivered to the system. Initialization in section 8.4:
629  * Can work in two modes:
630  *  -> Eneveope-based mode (section 8.4.1)
631  *  -> Energy-based mode (section 8.4.2)
632  *
633  * It is important to remark that the HWVAD detector could be enabled
634  * or reset only when the MICFIL isn't running i.e. when the BSY_FIL
635  * bit in STAT register is cleared
636  */
fsl_micfil_hwvad_enable(struct fsl_micfil * micfil)637 static int fsl_micfil_hwvad_enable(struct fsl_micfil *micfil)
638 {
639 	int ret;
640 
641 	micfil->vad_detected = 0;
642 
643 	/* envelope-based specific initialization */
644 	if (micfil->vad_init_mode == MICFIL_HWVAD_ENVELOPE_MODE)
645 		ret = fsl_micfil_init_hwvad_envelope_mode(micfil);
646 	else
647 		ret = fsl_micfil_init_hwvad_energy_mode(micfil);
648 	if (ret)
649 		return ret;
650 
651 	/* Voice Activity Detector Internal Filters Initialization*/
652 	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
653 			MICFIL_VAD0_CTRL1_ST10);
654 
655 	/* Voice Activity Detector Internal Filter */
656 	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
657 			  MICFIL_VAD0_CTRL1_ST10);
658 
659 	/* Enable Interrupts */
660 	ret = fsl_micfil_configure_hwvad_interrupts(micfil, 1);
661 	if (ret)
662 		return ret;
663 
664 	/* Voice Activity Detector Reset */
665 	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
666 			MICFIL_VAD0_CTRL1_RST);
667 
668 	/* Voice Activity Detector Enabled */
669 	regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
670 			MICFIL_VAD0_CTRL1_EN);
671 
672 	return 0;
673 }
674 
fsl_micfil_hwvad_disable(struct fsl_micfil * micfil)675 static int fsl_micfil_hwvad_disable(struct fsl_micfil *micfil)
676 {
677 	struct device *dev = &micfil->pdev->dev;
678 	int ret = 0;
679 
680 	/* Disable HWVAD */
681 	regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
682 			  MICFIL_VAD0_CTRL1_EN);
683 
684 	/* Disable hwvad interrupts */
685 	ret = fsl_micfil_configure_hwvad_interrupts(micfil, 0);
686 	if (ret)
687 		dev_err(dev, "Failed to disable interrupts\n");
688 
689 	return ret;
690 }
691 
fsl_micfil_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)692 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
693 			      struct snd_soc_dai *dai)
694 {
695 	struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
696 	struct device *dev = &micfil->pdev->dev;
697 	int ret;
698 
699 	switch (cmd) {
700 	case SNDRV_PCM_TRIGGER_START:
701 	case SNDRV_PCM_TRIGGER_RESUME:
702 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
703 		ret = fsl_micfil_reset(dev);
704 		if (ret) {
705 			dev_err(dev, "failed to soft reset\n");
706 			return ret;
707 		}
708 
709 		/* DMA Interrupt Selection - DISEL bits
710 		 * 00 - DMA and IRQ disabled
711 		 * 01 - DMA req enabled
712 		 * 10 - IRQ enabled
713 		 * 11 - reserved
714 		 */
715 		ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
716 				MICFIL_CTRL1_DISEL,
717 				FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
718 		if (ret)
719 			return ret;
720 
721 		/* Enable the module */
722 		ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
723 				      MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN);
724 		if (ret)
725 			return ret;
726 
727 		if (micfil->vad_enabled)
728 			fsl_micfil_hwvad_enable(micfil);
729 
730 		break;
731 	case SNDRV_PCM_TRIGGER_STOP:
732 	case SNDRV_PCM_TRIGGER_SUSPEND:
733 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
734 		if (micfil->vad_enabled)
735 			fsl_micfil_hwvad_disable(micfil);
736 
737 		/* Disable the module */
738 		ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
739 					MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN);
740 		if (ret)
741 			return ret;
742 
743 		ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
744 				MICFIL_CTRL1_DISEL,
745 				FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
746 		if (ret)
747 			return ret;
748 		break;
749 	default:
750 		return -EINVAL;
751 	}
752 	return 0;
753 }
754 
fsl_micfil_reparent_rootclk(struct fsl_micfil * micfil,unsigned int sample_rate)755 static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate)
756 {
757 	struct device *dev = &micfil->pdev->dev;
758 	u64 ratio = sample_rate;
759 	struct clk *clk;
760 	int ret;
761 
762 	/* Get root clock */
763 	clk = micfil->mclk;
764 
765 	/* Disable clock first, for it was enabled by pm_runtime */
766 	fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk,
767 				     micfil->pll11k_clk, ratio);
768 	ret = clk_prepare_enable(clk);
769 	if (ret)
770 		return ret;
771 
772 	return 0;
773 }
774 
fsl_micfil_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)775 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
776 				struct snd_pcm_hw_params *params,
777 				struct snd_soc_dai *dai)
778 {
779 	struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
780 	unsigned int channels = params_channels(params);
781 	unsigned int rate = params_rate(params);
782 	int clk_div = 8;
783 	int osr = MICFIL_OSR_DEFAULT;
784 	int ret;
785 
786 	/* 1. Disable the module */
787 	ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
788 				MICFIL_CTRL1_PDMIEN);
789 	if (ret)
790 		return ret;
791 
792 	/* enable channels */
793 	ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
794 				 0xFF, ((1 << channels) - 1));
795 	if (ret)
796 		return ret;
797 
798 	ret = fsl_micfil_reparent_rootclk(micfil, rate);
799 	if (ret)
800 		return ret;
801 
802 	micfil->mclk_flag = true;
803 
804 	ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);
805 	if (ret)
806 		return ret;
807 
808 	ret = micfil_set_quality(micfil);
809 	if (ret)
810 		return ret;
811 
812 	ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
813 				 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
814 				 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
815 				 FIELD_PREP(MICFIL_CTRL2_CICOSR, 32 - osr));
816 
817 	/* Configure CIC OSR in VADCICOSR */
818 	regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
819 			   MICFIL_VAD0_CTRL1_CICOSR,
820 			   FIELD_PREP(MICFIL_VAD0_CTRL1_CICOSR, 16 - osr));
821 
822 	/* Configure source channel in VADCHSEL */
823 	regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
824 			   MICFIL_VAD0_CTRL1_CHSEL,
825 			   FIELD_PREP(MICFIL_VAD0_CTRL1_CHSEL, (channels - 1)));
826 
827 	micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
828 	micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
829 	micfil->sdmacfg.n_fifos_src = channels;
830 	micfil->sdmacfg.sw_done = true;
831 	micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
832 	if (micfil->soc->use_edma)
833 		micfil->dma_params_rx.maxburst = channels;
834 
835 	return 0;
836 }
837 
fsl_micfil_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)838 static int fsl_micfil_hw_free(struct snd_pcm_substream *substream,
839 			      struct snd_soc_dai *dai)
840 {
841 	struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
842 
843 	clk_disable_unprepare(micfil->mclk);
844 	micfil->mclk_flag = false;
845 
846 	return 0;
847 }
848 
fsl_micfil_dai_probe(struct snd_soc_dai * cpu_dai)849 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
850 {
851 	struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
852 	struct device *dev = cpu_dai->dev;
853 	unsigned int val = 0;
854 	int ret, i;
855 
856 	micfil->quality = QUALITY_VLOW0;
857 	micfil->card = cpu_dai->component->card;
858 
859 	/* set default gain to 2 */
860 	regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222);
861 
862 	/* set DC Remover in bypass mode*/
863 	for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
864 		val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i);
865 	ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL,
866 				 MICFIL_DC_CTRL_CONFIG, val);
867 	if (ret) {
868 		dev_err(dev, "failed to set DC Remover mode bits\n");
869 		return ret;
870 	}
871 	micfil->dc_remover = MICFIL_DC_BYPASS;
872 
873 	snd_soc_dai_init_dma_data(cpu_dai, NULL,
874 				  &micfil->dma_params_rx);
875 
876 	/* FIFO Watermark Control - FIFOWMK*/
877 	ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
878 			MICFIL_FIFO_CTRL_FIFOWMK,
879 			FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
880 	if (ret)
881 		return ret;
882 
883 	return 0;
884 }
885 
fsl_micfil_component_probe(struct snd_soc_component * component)886 static int fsl_micfil_component_probe(struct snd_soc_component *component)
887 {
888 	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(component);
889 
890 	if (micfil->soc->volume_sx)
891 		snd_soc_add_component_controls(component, fsl_micfil_volume_sx_controls,
892 					       ARRAY_SIZE(fsl_micfil_volume_sx_controls));
893 	else
894 		snd_soc_add_component_controls(component, fsl_micfil_volume_controls,
895 					       ARRAY_SIZE(fsl_micfil_volume_controls));
896 
897 	return 0;
898 }
899 
900 static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
901 	.probe		= fsl_micfil_dai_probe,
902 	.startup	= fsl_micfil_startup,
903 	.trigger	= fsl_micfil_trigger,
904 	.hw_params	= fsl_micfil_hw_params,
905 	.hw_free	= fsl_micfil_hw_free,
906 };
907 
908 static struct snd_soc_dai_driver fsl_micfil_dai = {
909 	.capture = {
910 		.stream_name = "CPU-Capture",
911 		.channels_min = 1,
912 		.channels_max = 8,
913 		.rates = SNDRV_PCM_RATE_8000_48000,
914 		.formats = SNDRV_PCM_FMTBIT_S16_LE,
915 	},
916 	.ops = &fsl_micfil_dai_ops,
917 };
918 
919 static const struct snd_soc_component_driver fsl_micfil_component = {
920 	.name		= "fsl-micfil-dai",
921 	.probe		= fsl_micfil_component_probe,
922 	.controls       = fsl_micfil_snd_controls,
923 	.num_controls   = ARRAY_SIZE(fsl_micfil_snd_controls),
924 	.legacy_dai_naming      = 1,
925 };
926 
927 /* REGMAP */
928 static const struct reg_default fsl_micfil_reg_defaults[] = {
929 	{REG_MICFIL_CTRL1,		0x00000000},
930 	{REG_MICFIL_CTRL2,		0x00000000},
931 	{REG_MICFIL_STAT,		0x00000000},
932 	{REG_MICFIL_FIFO_CTRL,		0x0000001F},
933 	{REG_MICFIL_FIFO_STAT,		0x00000000},
934 	{REG_MICFIL_DATACH0,		0x00000000},
935 	{REG_MICFIL_DATACH1,		0x00000000},
936 	{REG_MICFIL_DATACH2,		0x00000000},
937 	{REG_MICFIL_DATACH3,		0x00000000},
938 	{REG_MICFIL_DATACH4,		0x00000000},
939 	{REG_MICFIL_DATACH5,		0x00000000},
940 	{REG_MICFIL_DATACH6,		0x00000000},
941 	{REG_MICFIL_DATACH7,		0x00000000},
942 	{REG_MICFIL_DC_CTRL,		0x00000000},
943 	{REG_MICFIL_OUT_CTRL,		0x00000000},
944 	{REG_MICFIL_OUT_STAT,		0x00000000},
945 	{REG_MICFIL_VAD0_CTRL1,		0x00000000},
946 	{REG_MICFIL_VAD0_CTRL2,		0x000A0000},
947 	{REG_MICFIL_VAD0_STAT,		0x00000000},
948 	{REG_MICFIL_VAD0_SCONFIG,	0x00000000},
949 	{REG_MICFIL_VAD0_NCONFIG,	0x80000000},
950 	{REG_MICFIL_VAD0_NDATA,		0x00000000},
951 	{REG_MICFIL_VAD0_ZCD,		0x00000004},
952 };
953 
954 static const struct reg_default fsl_micfil_reg_defaults_v2[] = {
955 	{REG_MICFIL_CTRL1,		0x00000000},
956 	{REG_MICFIL_CTRL2,		0x00000000},
957 	{REG_MICFIL_STAT,		0x00000000},
958 	{REG_MICFIL_FIFO_CTRL,		0x0000001F},
959 	{REG_MICFIL_FIFO_STAT,		0x00000000},
960 	{REG_MICFIL_DATACH0 - 0x4,	0x00000000},
961 	{REG_MICFIL_DATACH1 - 0x4,	0x00000000},
962 	{REG_MICFIL_DATACH2 - 0x4,	0x00000000},
963 	{REG_MICFIL_DATACH3 - 0x4,	0x00000000},
964 	{REG_MICFIL_DATACH4 - 0x4,	0x00000000},
965 	{REG_MICFIL_DATACH5 - 0x4,	0x00000000},
966 	{REG_MICFIL_DATACH6 - 0x4,	0x00000000},
967 	{REG_MICFIL_DATACH7 - 0x4,	0x00000000},
968 	{REG_MICFIL_DC_CTRL,		0x00000000},
969 	{REG_MICFIL_OUT_CTRL,		0x00000000},
970 	{REG_MICFIL_OUT_STAT,		0x00000000},
971 	{REG_MICFIL_VAD0_CTRL1,		0x00000000},
972 	{REG_MICFIL_VAD0_CTRL2,		0x000A0000},
973 	{REG_MICFIL_VAD0_STAT,		0x00000000},
974 	{REG_MICFIL_VAD0_SCONFIG,	0x00000000},
975 	{REG_MICFIL_VAD0_NCONFIG,	0x80000000},
976 	{REG_MICFIL_VAD0_NDATA,		0x00000000},
977 	{REG_MICFIL_VAD0_ZCD,		0x00000004},
978 };
979 
fsl_micfil_readable_reg(struct device * dev,unsigned int reg)980 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
981 {
982 	struct fsl_micfil *micfil = dev_get_drvdata(dev);
983 	int ofs = micfil->soc->fifo_offset;
984 
985 	if (reg >= (REG_MICFIL_DATACH0 + ofs) && reg <= (REG_MICFIL_DATACH7 + ofs))
986 		return true;
987 
988 	switch (reg) {
989 	case REG_MICFIL_CTRL1:
990 	case REG_MICFIL_CTRL2:
991 	case REG_MICFIL_STAT:
992 	case REG_MICFIL_FIFO_CTRL:
993 	case REG_MICFIL_FIFO_STAT:
994 	case REG_MICFIL_DC_CTRL:
995 	case REG_MICFIL_OUT_CTRL:
996 	case REG_MICFIL_OUT_STAT:
997 	case REG_MICFIL_VAD0_CTRL1:
998 	case REG_MICFIL_VAD0_CTRL2:
999 	case REG_MICFIL_VAD0_STAT:
1000 	case REG_MICFIL_VAD0_SCONFIG:
1001 	case REG_MICFIL_VAD0_NCONFIG:
1002 	case REG_MICFIL_VAD0_NDATA:
1003 	case REG_MICFIL_VAD0_ZCD:
1004 		return true;
1005 	case REG_MICFIL_FSYNC_CTRL:
1006 	case REG_MICFIL_VERID:
1007 	case REG_MICFIL_PARAM:
1008 		if (micfil->soc->use_verid)
1009 			return true;
1010 		fallthrough;
1011 	default:
1012 		return false;
1013 	}
1014 }
1015 
fsl_micfil_writeable_reg(struct device * dev,unsigned int reg)1016 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
1017 {
1018 	struct fsl_micfil *micfil = dev_get_drvdata(dev);
1019 
1020 	switch (reg) {
1021 	case REG_MICFIL_CTRL1:
1022 	case REG_MICFIL_CTRL2:
1023 	case REG_MICFIL_STAT:		/* Write 1 to Clear */
1024 	case REG_MICFIL_FIFO_CTRL:
1025 	case REG_MICFIL_FIFO_STAT:	/* Write 1 to Clear */
1026 	case REG_MICFIL_DC_CTRL:
1027 	case REG_MICFIL_OUT_CTRL:
1028 	case REG_MICFIL_OUT_STAT:	/* Write 1 to Clear */
1029 	case REG_MICFIL_VAD0_CTRL1:
1030 	case REG_MICFIL_VAD0_CTRL2:
1031 	case REG_MICFIL_VAD0_STAT:	/* Write 1 to Clear */
1032 	case REG_MICFIL_VAD0_SCONFIG:
1033 	case REG_MICFIL_VAD0_NCONFIG:
1034 	case REG_MICFIL_VAD0_ZCD:
1035 		return true;
1036 	case REG_MICFIL_FSYNC_CTRL:
1037 		if (micfil->soc->use_verid)
1038 			return true;
1039 		fallthrough;
1040 	default:
1041 		return false;
1042 	}
1043 }
1044 
fsl_micfil_volatile_reg(struct device * dev,unsigned int reg)1045 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
1046 {
1047 	struct fsl_micfil *micfil = dev_get_drvdata(dev);
1048 	int ofs = micfil->soc->fifo_offset;
1049 
1050 	if (reg >= (REG_MICFIL_DATACH0 + ofs) && reg <= (REG_MICFIL_DATACH7 + ofs))
1051 		return true;
1052 
1053 	switch (reg) {
1054 	case REG_MICFIL_STAT:
1055 	case REG_MICFIL_FIFO_STAT:
1056 	case REG_MICFIL_OUT_STAT:
1057 	case REG_MICFIL_VERID:
1058 	case REG_MICFIL_PARAM:
1059 	case REG_MICFIL_VAD0_STAT:
1060 	case REG_MICFIL_VAD0_NDATA:
1061 		return true;
1062 	default:
1063 		return false;
1064 	}
1065 }
1066 
1067 static const struct regmap_config fsl_micfil_regmap_config = {
1068 	.reg_bits = 32,
1069 	.reg_stride = 4,
1070 	.val_bits = 32,
1071 
1072 	.max_register = REG_MICFIL_VAD0_ZCD,
1073 	.reg_defaults = fsl_micfil_reg_defaults,
1074 	.num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
1075 	.readable_reg = fsl_micfil_readable_reg,
1076 	.volatile_reg = fsl_micfil_volatile_reg,
1077 	.writeable_reg = fsl_micfil_writeable_reg,
1078 	.cache_type = REGCACHE_MAPLE,
1079 };
1080 
1081 static const struct regmap_config fsl_micfil_regmap_config_v2 = {
1082 	.reg_bits = 32,
1083 	.reg_stride = 4,
1084 	.val_bits = 32,
1085 
1086 	.max_register = REG_MICFIL_VAD0_ZCD,
1087 	.reg_defaults = fsl_micfil_reg_defaults_v2,
1088 	.num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults_v2),
1089 	.readable_reg = fsl_micfil_readable_reg,
1090 	.volatile_reg = fsl_micfil_volatile_reg,
1091 	.writeable_reg = fsl_micfil_writeable_reg,
1092 	.cache_type = REGCACHE_MAPLE,
1093 };
1094 
1095 /* END OF REGMAP */
1096 
micfil_isr(int irq,void * devid)1097 static irqreturn_t micfil_isr(int irq, void *devid)
1098 {
1099 	struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1100 	struct platform_device *pdev = micfil->pdev;
1101 	u32 stat_reg;
1102 	u32 fifo_stat_reg;
1103 	u32 ctrl1_reg;
1104 	bool dma_enabled;
1105 	int i;
1106 
1107 	regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
1108 	regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
1109 	regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
1110 
1111 	dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;
1112 
1113 	/* Channel 0-7 Output Data Flags */
1114 	for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
1115 		if (stat_reg & MICFIL_STAT_CHXF(i))
1116 			dev_dbg(&pdev->dev,
1117 				"Data available in Data Channel %d\n", i);
1118 		/* if DMA is not enabled, field must be written with 1
1119 		 * to clear
1120 		 */
1121 		if (!dma_enabled)
1122 			regmap_write_bits(micfil->regmap,
1123 					  REG_MICFIL_STAT,
1124 					  MICFIL_STAT_CHXF(i),
1125 					  MICFIL_STAT_CHXF(i));
1126 	}
1127 
1128 	for (i = 0; i < MICFIL_FIFO_NUM; i++) {
1129 		if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))
1130 			dev_dbg(&pdev->dev,
1131 				"FIFO Overflow Exception flag for channel %d\n",
1132 				i);
1133 
1134 		if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))
1135 			dev_dbg(&pdev->dev,
1136 				"FIFO Underflow Exception flag for channel %d\n",
1137 				i);
1138 	}
1139 
1140 	return IRQ_HANDLED;
1141 }
1142 
micfil_err_isr(int irq,void * devid)1143 static irqreturn_t micfil_err_isr(int irq, void *devid)
1144 {
1145 	struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1146 	struct platform_device *pdev = micfil->pdev;
1147 	u32 fifo_stat_reg;
1148 	u32 out_stat_reg;
1149 	u32 stat_reg;
1150 
1151 	regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
1152 
1153 	if (stat_reg & MICFIL_STAT_BSY_FIL)
1154 		dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
1155 
1156 	if (stat_reg & MICFIL_STAT_FIR_RDY)
1157 		dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
1158 
1159 	if (stat_reg & MICFIL_STAT_LOWFREQF) {
1160 		dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
1161 		regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
1162 				  MICFIL_STAT_LOWFREQF, MICFIL_STAT_LOWFREQF);
1163 	}
1164 
1165 	regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
1166 	regmap_write_bits(micfil->regmap, REG_MICFIL_FIFO_STAT,
1167 			  fifo_stat_reg, fifo_stat_reg);
1168 
1169 	regmap_read(micfil->regmap, REG_MICFIL_OUT_STAT, &out_stat_reg);
1170 	regmap_write_bits(micfil->regmap, REG_MICFIL_OUT_STAT,
1171 			  out_stat_reg, out_stat_reg);
1172 
1173 	return IRQ_HANDLED;
1174 }
1175 
voice_detected_fn(int irq,void * devid)1176 static irqreturn_t voice_detected_fn(int irq, void *devid)
1177 {
1178 	struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1179 	struct snd_kcontrol *kctl;
1180 
1181 	if (!micfil->card)
1182 		return IRQ_HANDLED;
1183 
1184 	kctl = snd_soc_card_get_kcontrol(micfil->card, "VAD Detected");
1185 	if (!kctl)
1186 		return IRQ_HANDLED;
1187 
1188 	if (micfil->vad_detected)
1189 		snd_ctl_notify(micfil->card->snd_card,
1190 			       SNDRV_CTL_EVENT_MASK_VALUE,
1191 			       &kctl->id);
1192 
1193 	return IRQ_HANDLED;
1194 }
1195 
hwvad_isr(int irq,void * devid)1196 static irqreturn_t hwvad_isr(int irq, void *devid)
1197 {
1198 	struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1199 	struct device *dev = &micfil->pdev->dev;
1200 	u32 vad0_reg;
1201 	int ret;
1202 
1203 	regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);
1204 
1205 	/*
1206 	 * The only difference between MICFIL_VAD0_STAT_EF and
1207 	 * MICFIL_VAD0_STAT_IF is that the former requires Write
1208 	 * 1 to Clear. Since both flags are set, it is enough
1209 	 * to only read one of them
1210 	 */
1211 	if (vad0_reg & MICFIL_VAD0_STAT_IF) {
1212 		/* Write 1 to clear */
1213 		regmap_write_bits(micfil->regmap, REG_MICFIL_VAD0_STAT,
1214 				  MICFIL_VAD0_STAT_IF,
1215 				  MICFIL_VAD0_STAT_IF);
1216 
1217 		micfil->vad_detected = 1;
1218 	}
1219 
1220 	ret = fsl_micfil_hwvad_disable(micfil);
1221 	if (ret)
1222 		dev_err(dev, "Failed to disable hwvad\n");
1223 
1224 	return IRQ_WAKE_THREAD;
1225 }
1226 
hwvad_err_isr(int irq,void * devid)1227 static irqreturn_t hwvad_err_isr(int irq, void *devid)
1228 {
1229 	struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1230 	struct device *dev = &micfil->pdev->dev;
1231 	u32 vad0_reg;
1232 
1233 	regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);
1234 
1235 	if (vad0_reg & MICFIL_VAD0_STAT_INSATF)
1236 		dev_dbg(dev, "voice activity input overflow/underflow detected\n");
1237 
1238 	return IRQ_HANDLED;
1239 }
1240 
1241 static int fsl_micfil_runtime_suspend(struct device *dev);
1242 static int fsl_micfil_runtime_resume(struct device *dev);
1243 
fsl_micfil_probe(struct platform_device * pdev)1244 static int fsl_micfil_probe(struct platform_device *pdev)
1245 {
1246 	struct device_node *np = pdev->dev.of_node;
1247 	struct fsl_micfil *micfil;
1248 	struct resource *res;
1249 	void __iomem *regs;
1250 	int ret, i;
1251 
1252 	micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
1253 	if (!micfil)
1254 		return -ENOMEM;
1255 
1256 	micfil->pdev = pdev;
1257 	strscpy(micfil->name, np->name, sizeof(micfil->name));
1258 
1259 	micfil->soc = of_device_get_match_data(&pdev->dev);
1260 
1261 	/* ipg_clk is used to control the registers
1262 	 * ipg_clk_app is used to operate the filter
1263 	 */
1264 	micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
1265 	if (IS_ERR(micfil->mclk)) {
1266 		dev_err(&pdev->dev, "failed to get core clock: %ld\n",
1267 			PTR_ERR(micfil->mclk));
1268 		return PTR_ERR(micfil->mclk);
1269 	}
1270 
1271 	micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk");
1272 	if (IS_ERR(micfil->busclk)) {
1273 		dev_err(&pdev->dev, "failed to get ipg clock: %ld\n",
1274 			PTR_ERR(micfil->busclk));
1275 		return PTR_ERR(micfil->busclk);
1276 	}
1277 
1278 	fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk,
1279 				&micfil->pll11k_clk);
1280 
1281 	micfil->clk_src[MICFIL_AUDIO_PLL1] = micfil->pll8k_clk;
1282 	micfil->clk_src[MICFIL_AUDIO_PLL2] = micfil->pll11k_clk;
1283 	micfil->clk_src[MICFIL_CLK_EXT3] = devm_clk_get(&pdev->dev, "clkext3");
1284 	if (IS_ERR(micfil->clk_src[MICFIL_CLK_EXT3]))
1285 		micfil->clk_src[MICFIL_CLK_EXT3] = NULL;
1286 
1287 	fsl_asoc_constrain_rates(&micfil->constraint_rates,
1288 				 &fsl_micfil_rate_constraints,
1289 				 micfil->clk_src[MICFIL_AUDIO_PLL1],
1290 				 micfil->clk_src[MICFIL_AUDIO_PLL2],
1291 				 micfil->clk_src[MICFIL_CLK_EXT3],
1292 				 micfil->constraint_rates_list);
1293 
1294 	/* init regmap */
1295 	regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1296 	if (IS_ERR(regs))
1297 		return PTR_ERR(regs);
1298 
1299 	if (of_device_is_compatible(np, "fsl,imx943-micfil"))
1300 		micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1301 						       regs,
1302 						       &fsl_micfil_regmap_config_v2);
1303 	else
1304 		micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1305 						       regs,
1306 						       &fsl_micfil_regmap_config);
1307 	if (IS_ERR(micfil->regmap)) {
1308 		dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
1309 			PTR_ERR(micfil->regmap));
1310 		return PTR_ERR(micfil->regmap);
1311 	}
1312 
1313 	/* dataline mask for RX */
1314 	ret = of_property_read_u32_index(np,
1315 					 "fsl,dataline",
1316 					 0,
1317 					 &micfil->dataline);
1318 	if (ret)
1319 		micfil->dataline = 1;
1320 
1321 	if (micfil->dataline & ~micfil->soc->dataline) {
1322 		dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
1323 			micfil->soc->dataline);
1324 		return -EINVAL;
1325 	}
1326 
1327 	/* get IRQs */
1328 	for (i = 0; i < MICFIL_IRQ_LINES; i++) {
1329 		micfil->irq[i] = platform_get_irq(pdev, i);
1330 		if (micfil->irq[i] < 0)
1331 			return micfil->irq[i];
1332 	}
1333 
1334 	/* Digital Microphone interface interrupt */
1335 	ret = devm_request_irq(&pdev->dev, micfil->irq[0],
1336 			       micfil_isr, IRQF_SHARED,
1337 			       micfil->name, micfil);
1338 	if (ret) {
1339 		dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
1340 			micfil->irq[0]);
1341 		return ret;
1342 	}
1343 
1344 	/* Digital Microphone interface error interrupt */
1345 	ret = devm_request_irq(&pdev->dev, micfil->irq[1],
1346 			       micfil_err_isr, IRQF_SHARED,
1347 			       micfil->name, micfil);
1348 	if (ret) {
1349 		dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
1350 			micfil->irq[1]);
1351 		return ret;
1352 	}
1353 
1354 	/* Digital Microphone interface voice activity detector event */
1355 	ret = devm_request_threaded_irq(&pdev->dev, micfil->irq[2],
1356 					hwvad_isr, voice_detected_fn,
1357 					IRQF_SHARED, micfil->name, micfil);
1358 	if (ret) {
1359 		dev_err(&pdev->dev, "failed to claim hwvad event irq %u\n",
1360 			micfil->irq[0]);
1361 		return ret;
1362 	}
1363 
1364 	/* Digital Microphone interface voice activity detector error */
1365 	ret = devm_request_irq(&pdev->dev, micfil->irq[3],
1366 			       hwvad_err_isr, IRQF_SHARED,
1367 			       micfil->name, micfil);
1368 	if (ret) {
1369 		dev_err(&pdev->dev, "failed to claim hwvad error irq %u\n",
1370 			micfil->irq[1]);
1371 		return ret;
1372 	}
1373 
1374 	micfil->dma_params_rx.chan_name = "rx";
1375 	micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0 + micfil->soc->fifo_offset;
1376 	micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
1377 
1378 	platform_set_drvdata(pdev, micfil);
1379 
1380 	pm_runtime_enable(&pdev->dev);
1381 	if (!pm_runtime_enabled(&pdev->dev)) {
1382 		ret = fsl_micfil_runtime_resume(&pdev->dev);
1383 		if (ret)
1384 			goto err_pm_disable;
1385 	}
1386 
1387 	ret = pm_runtime_resume_and_get(&pdev->dev);
1388 	if (ret < 0)
1389 		goto err_pm_get_sync;
1390 
1391 	/* Get micfil version */
1392 	ret = fsl_micfil_use_verid(&pdev->dev);
1393 	if (ret < 0)
1394 		dev_warn(&pdev->dev, "Error reading MICFIL version: %d\n", ret);
1395 
1396 	ret = pm_runtime_put_sync(&pdev->dev);
1397 	if (ret < 0 && ret != -ENOSYS)
1398 		goto err_pm_get_sync;
1399 
1400 	regcache_cache_only(micfil->regmap, true);
1401 
1402 	/*
1403 	 * Register platform component before registering cpu dai for there
1404 	 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1405 	 */
1406 	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1407 	if (ret) {
1408 		dev_err(&pdev->dev, "failed to pcm register\n");
1409 		goto err_pm_disable;
1410 	}
1411 
1412 	fsl_micfil_dai.capture.formats = micfil->soc->formats;
1413 
1414 	ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
1415 					      &fsl_micfil_dai, 1);
1416 	if (ret) {
1417 		dev_err(&pdev->dev, "failed to register component %s\n",
1418 			fsl_micfil_component.name);
1419 		goto err_pm_disable;
1420 	}
1421 
1422 	return ret;
1423 
1424 err_pm_get_sync:
1425 	if (!pm_runtime_status_suspended(&pdev->dev))
1426 		fsl_micfil_runtime_suspend(&pdev->dev);
1427 err_pm_disable:
1428 	pm_runtime_disable(&pdev->dev);
1429 
1430 	return ret;
1431 }
1432 
fsl_micfil_remove(struct platform_device * pdev)1433 static void fsl_micfil_remove(struct platform_device *pdev)
1434 {
1435 	pm_runtime_disable(&pdev->dev);
1436 }
1437 
fsl_micfil_runtime_suspend(struct device * dev)1438 static int fsl_micfil_runtime_suspend(struct device *dev)
1439 {
1440 	struct fsl_micfil *micfil = dev_get_drvdata(dev);
1441 
1442 	regcache_cache_only(micfil->regmap, true);
1443 
1444 	if (micfil->mclk_flag)
1445 		clk_disable_unprepare(micfil->mclk);
1446 	clk_disable_unprepare(micfil->busclk);
1447 
1448 	return 0;
1449 }
1450 
fsl_micfil_runtime_resume(struct device * dev)1451 static int fsl_micfil_runtime_resume(struct device *dev)
1452 {
1453 	struct fsl_micfil *micfil = dev_get_drvdata(dev);
1454 	int ret;
1455 
1456 	ret = clk_prepare_enable(micfil->busclk);
1457 	if (ret < 0)
1458 		return ret;
1459 
1460 	if (micfil->mclk_flag) {
1461 		ret = clk_prepare_enable(micfil->mclk);
1462 		if (ret < 0) {
1463 			clk_disable_unprepare(micfil->busclk);
1464 			return ret;
1465 		}
1466 	}
1467 
1468 	regcache_cache_only(micfil->regmap, false);
1469 	regcache_mark_dirty(micfil->regmap);
1470 	regcache_sync(micfil->regmap);
1471 
1472 	return 0;
1473 }
1474 
1475 static const struct dev_pm_ops fsl_micfil_pm_ops = {
1476 	SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
1477 			   fsl_micfil_runtime_resume,
1478 			   NULL)
1479 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1480 				pm_runtime_force_resume)
1481 };
1482 
1483 static struct platform_driver fsl_micfil_driver = {
1484 	.probe = fsl_micfil_probe,
1485 	.remove = fsl_micfil_remove,
1486 	.driver = {
1487 		.name = "fsl-micfil-dai",
1488 		.pm = &fsl_micfil_pm_ops,
1489 		.of_match_table = fsl_micfil_dt_ids,
1490 	},
1491 };
1492 module_platform_driver(fsl_micfil_driver);
1493 
1494 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
1495 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
1496 MODULE_LICENSE("Dual BSD/GPL");
1497