1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27 #include "dcn301_optc.h"
28 #include "dc.h"
29 #include "dcn_calc_math.h"
30 #include "dc_dmub_srv.h"
31
32 #include "dml/dcn30/dcn30_fpu.h"
33 #include "dc_trace.h"
34
35 #define REG(reg)\
36 optc1->tg_regs->reg
37
38 #define CTX \
39 optc1->base.ctx
40
41 #undef FN
42 #define FN(reg_name, field_name) \
43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
44
45
46 /**
47 * optc301_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
48 *
49 * @optc: timing_generator instance.
50 * @params: parameters used for Dynamic Refresh Rate.
51 */
optc301_set_drr(struct timing_generator * optc,const struct drr_params * params)52 void optc301_set_drr(
53 struct timing_generator *optc,
54 const struct drr_params *params)
55 {
56 struct optc *optc1 = DCN10TG_FROM_TG(optc);
57
58 if (params != NULL &&
59 params->vertical_total_max > 0 &&
60 params->vertical_total_min > 0) {
61
62 if (params->vertical_total_mid != 0) {
63
64 REG_SET(OTG_V_TOTAL_MID, 0,
65 OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
66
67 REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
68 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
69 OTG_VTOTAL_MID_FRAME_NUM,
70 (uint8_t)params->vertical_total_mid_frame_num);
71
72 }
73
74 optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
75
76 REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
77 OTG_V_TOTAL_MIN_SEL, 1,
78 OTG_V_TOTAL_MAX_SEL, 1,
79 OTG_FORCE_LOCK_ON_EVENT, 0,
80 OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
81 OTG_SET_V_TOTAL_MIN_MASK, 0);
82 // Setup manual flow control for EOF via TRIG_A
83 optc->funcs->setup_manual_trigger(optc);
84
85 } else {
86 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
87 OTG_SET_V_TOTAL_MIN_MASK, 0,
88 OTG_V_TOTAL_MIN_SEL, 0,
89 OTG_V_TOTAL_MAX_SEL, 0,
90 OTG_FORCE_LOCK_ON_EVENT, 0);
91
92 optc->funcs->set_vtotal_min_max(optc, 0, 0);
93 }
94 }
95
96
optc301_setup_manual_trigger(struct timing_generator * optc)97 void optc301_setup_manual_trigger(struct timing_generator *optc)
98 {
99 struct optc *optc1 = DCN10TG_FROM_TG(optc);
100
101 REG_SET_8(OTG_TRIGA_CNTL, 0,
102 OTG_TRIGA_SOURCE_SELECT, 21,
103 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
104 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
105 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
106 OTG_TRIGA_POLARITY_SELECT, 0,
107 OTG_TRIGA_FREQUENCY_SELECT, 0,
108 OTG_TRIGA_DELAY, 0,
109 OTG_TRIGA_CLEAR, 1);
110 }
111
112 static struct timing_generator_funcs dcn30_tg_funcs = {
113 .validate_timing = optc1_validate_timing,
114 .program_timing = optc1_program_timing,
115 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
116 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
117 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
118 .program_global_sync = optc1_program_global_sync,
119 .enable_crtc = optc2_enable_crtc,
120 .disable_crtc = optc1_disable_crtc,
121 /* used by enable_timing_synchronization. Not need for FPGA */
122 .is_counter_moving = optc1_is_counter_moving,
123 .get_position = optc1_get_position,
124 .get_frame_count = optc1_get_vblank_counter,
125 .get_scanoutpos = optc1_get_crtc_scanoutpos,
126 .get_otg_active_size = optc1_get_otg_active_size,
127 .set_early_control = optc1_set_early_control,
128 /* used by enable_timing_synchronization. Not need for FPGA */
129 .wait_for_state = optc1_wait_for_state,
130 .set_blank_color = optc3_program_blank_color,
131 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
132 .triplebuffer_lock = optc3_triplebuffer_lock,
133 .triplebuffer_unlock = optc2_triplebuffer_unlock,
134 .enable_reset_trigger = optc1_enable_reset_trigger,
135 .enable_crtc_reset = optc1_enable_crtc_reset,
136 .disable_reset_trigger = optc1_disable_reset_trigger,
137 .lock = optc3_lock,
138 .unlock = optc1_unlock,
139 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
140 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
141 .enable_optc_clock = optc1_enable_optc_clock,
142 .set_drr = optc301_set_drr,
143 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
144 .set_vtotal_min_max = optc3_set_vtotal_min_max,
145 .set_static_screen_control = optc1_set_static_screen_control,
146 .program_stereo = optc1_program_stereo,
147 .is_stereo_left_eye = optc1_is_stereo_left_eye,
148 .tg_init = optc3_tg_init,
149 .is_tg_enabled = optc1_is_tg_enabled,
150 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
151 .clear_optc_underflow = optc1_clear_optc_underflow,
152 .setup_global_swap_lock = NULL,
153 .get_crc = optc1_get_crc,
154 .configure_crc = optc2_configure_crc,
155 .set_dsc_config = optc3_set_dsc_config,
156 .get_dsc_status = optc2_get_dsc_status,
157 .set_dwb_source = NULL,
158 .set_odm_bypass = optc3_set_odm_bypass,
159 .set_odm_combine = optc3_set_odm_combine,
160 .get_optc_source = optc2_get_optc_source,
161 .set_out_mux = optc3_set_out_mux,
162 .set_drr_trigger_window = optc3_set_drr_trigger_window,
163 .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
164 .set_gsl = optc2_set_gsl,
165 .set_gsl_source_select = optc2_set_gsl_source_select,
166 .set_vtg_params = optc1_set_vtg_params,
167 .program_manual_trigger = optc2_program_manual_trigger,
168 .setup_manual_trigger = optc301_setup_manual_trigger,
169 .get_hw_timing = optc1_get_hw_timing,
170 .wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear,
171 .is_two_pixels_per_container = optc1_is_two_pixels_per_container,
172 };
173
dcn301_timing_generator_init(struct optc * optc1)174 void dcn301_timing_generator_init(struct optc *optc1)
175 {
176 optc1->base.funcs = &dcn30_tg_funcs;
177
178 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
179 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
180
181 optc1->min_h_blank = 32;
182 optc1->min_v_blank = 3;
183 optc1->min_v_blank_interlace = 5;
184 optc1->min_h_sync_width = 4;
185 optc1->min_v_sync_width = 1;
186 }
187